drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "global1.h"
  36 #include "global2.h"
  37 #include "hwtstamp.h"
  38 #include "phy.h"
  39 #include "port.h"
  40 #include "ptp.h"
  41 #include "serdes.h"
  42 #include "smi.h"
  43
  44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  45 {
  46         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  47                 dev_err(chip->dev, "Switch registers lock not held!\n");
  48                 dump_stack();
  49         }
  50 }
  51
  52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  53 {
  54         int err;
  55
  56         assert_reg_lock(chip);
  57
  58         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  59         if (err)
  60                 return err;
  61
  62         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  63                 addr, reg, *val);
  64
  65         return 0;
  66 }
  67
  68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  69 {
  70         int err;
  71
  72         assert_reg_lock(chip);
  73
  74         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  75         if (err)
  76                 return err;
  77
  78         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  79                 addr, reg, val);
  80
  81         return 0;
  82 }
  83
  84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  85                         u16 mask, u16 val)
  86 {
  87         u16 data;
  88         int err;
  89         int i;
  90
  91         /* There's no bus specific operation to wait for a mask */
  92         for (i = 0; i < 16; i++) {
  93                 err = mv88e6xxx_read(chip, addr, reg, &data);
  94                 if (err)
  95                         return err;
  96
  97                 if ((data & mask) == val)
  98                         return 0;
  99
 100                 usleep_range(1000, 2000);
 101         }
 102
 103         dev_err(chip->dev, "Timeout while waiting for switch\n");
 104         return -ETIMEDOUT;
 105 }
 106
 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 108                        int bit, int val)
 109 {
 110         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 111                                    val ? BIT(bit) : 0x0000);
 112 }
 113
 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 115 {
 116         struct mv88e6xxx_mdio_bus *mdio_bus;
 117
 118         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 119                                     list);
 120         if (!mdio_bus)
 121                 return NULL;
 122
 123         return mdio_bus->bus;
 124 }
 125
 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 127 {
 128         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 129         unsigned int n = d->hwirq;
 130
 131         chip->g1_irq.masked |= (1 << n);
 132 }
 133
 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 135 {
 136         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 137         unsigned int n = d->hwirq;
 138
 139         chip->g1_irq.masked &= ~(1 << n);
 140 }
 141
 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 143 {
 144         unsigned int nhandled = 0;
 145         unsigned int sub_irq;
 146         unsigned int n;
 147         u16 reg;
 148         u16 ctl1;
 149         int err;
 150
 151         mv88e6xxx_reg_lock(chip);
 152         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 153         mv88e6xxx_reg_unlock(chip);
 154
 155         if (err)
 156                 goto out;
 157
 158         do {
 159                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 160                         if (reg & (1 << n)) {
 161                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 162                                                            n);
 163                                 handle_nested_irq(sub_irq);
 164                                 ++nhandled;
 165                         }
 166                 }
 167
 168                 mv88e6xxx_reg_lock(chip);
 169                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 170                 if (err)
 171                         goto unlock;
 172                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 173 unlock:
 174                 mv88e6xxx_reg_unlock(chip);
 175                 if (err)
 176                         goto out;
 177                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 178         } while (reg & ctl1);
 179
 180 out:
 181         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 182 }
 183
 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 185 {
 186         struct mv88e6xxx_chip *chip = dev_id;
 187
 188         return mv88e6xxx_g1_irq_thread_work(chip);
 189 }
 190
 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 192 {
 193         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 194
 195         mv88e6xxx_reg_lock(chip);
 196 }
 197
 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 199 {
 200         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 201         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 202         u16 reg;
 203         int err;
 204
 205         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 206         if (err)
 207                 goto out;
 208
 209         reg &= ~mask;
 210         reg |= (~chip->g1_irq.masked & mask);
 211
 212         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 213         if (err)
 214                 goto out;
 215
 216 out:
 217         mv88e6xxx_reg_unlock(chip);
 218 }
 219
 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 221         .name                   = "mv88e6xxx-g1",
 222         .irq_mask               = mv88e6xxx_g1_irq_mask,
 223         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 224         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 225         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 226 };
 227
 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 229                                        unsigned int irq,
 230                                        irq_hw_number_t hwirq)
 231 {
 232         struct mv88e6xxx_chip *chip = d->host_data;
 233
 234         irq_set_chip_data(irq, d->host_data);
 235         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 236         irq_set_noprobe(irq);
 237
 238         return 0;
 239 }
 240
 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 242         .map    = mv88e6xxx_g1_irq_domain_map,
 243         .xlate  = irq_domain_xlate_twocell,
 244 };
 245
 246 /* To be called with reg_lock held */
 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 248 {
 249         int irq, virq;
 250         u16 mask;
 251
 252         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 253         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 254         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 255
 256         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 257                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 258                 irq_dispose_mapping(virq);
 259         }
 260
 261         irq_domain_remove(chip->g1_irq.domain);
 262 }
 263
 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 265 {
 266         /*
 267          * free_irq must be called without reg_lock taken because the irq
 268          * handler takes this lock, too.
 269          */
 270         free_irq(chip->irq, chip);
 271
 272         mv88e6xxx_reg_lock(chip);
 273         mv88e6xxx_g1_irq_free_common(chip);
 274         mv88e6xxx_reg_unlock(chip);
 275 }
 276
 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 278 {
 279         int err, irq, virq;
 280         u16 reg, mask;
 281
 282         chip->g1_irq.nirqs = chip->info->g1_irqs;
 283         chip->g1_irq.domain = irq_domain_add_simple(
 284                 NULL, chip->g1_irq.nirqs, 0,
 285                 &mv88e6xxx_g1_irq_domain_ops, chip);
 286         if (!chip->g1_irq.domain)
 287                 return -ENOMEM;
 288
 289         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 290                 irq_create_mapping(chip->g1_irq.domain, irq);
 291
 292         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 293         chip->g1_irq.masked = ~0;
 294
 295         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 296         if (err)
 297                 goto out_mapping;
 298
 299         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 300
 301         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 302         if (err)
 303                 goto out_disable;
 304
 305         /* Reading the interrupt status clears (most of) them */
 306         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 307         if (err)
 308                 goto out_disable;
 309
 310         return 0;
 311
 312 out_disable:
 313         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 314         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 315
 316 out_mapping:
 317         for (irq = 0; irq < 16; irq++) {
 318                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 319                 irq_dispose_mapping(virq);
 320         }
 321
 322         irq_domain_remove(chip->g1_irq.domain);
 323
 324         return err;
 325 }
 326
 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 328 {
 329         static struct lock_class_key lock_key;
 330         static struct lock_class_key request_key;
 331         int err;
 332
 333         err = mv88e6xxx_g1_irq_setup_common(chip);
 334         if (err)
 335                 return err;
 336
 337         /* These lock classes tells lockdep that global 1 irqs are in
 338          * a different category than their parent GPIO, so it won't
 339          * report false recursion.
 340          */
 341         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 342
 343         mv88e6xxx_reg_unlock(chip);
 344         err = request_threaded_irq(chip->irq, NULL,
 345                                    mv88e6xxx_g1_irq_thread_fn,
 346                                    IRQF_ONESHOT | IRQF_SHARED,
 347                                    dev_name(chip->dev), chip);
 348         mv88e6xxx_reg_lock(chip);
 349         if (err)
 350                 mv88e6xxx_g1_irq_free_common(chip);
 351
 352         return err;
 353 }
 354
 355 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 356 {
 357         struct mv88e6xxx_chip *chip = container_of(work,
 358                                                    struct mv88e6xxx_chip,
 359                                                    irq_poll_work.work);
 360         mv88e6xxx_g1_irq_thread_work(chip);
 361
 362         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 363                                    msecs_to_jiffies(100));
 364 }
 365
 366 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 367 {
 368         int err;
 369
 370         err = mv88e6xxx_g1_irq_setup_common(chip);
 371         if (err)
 372                 return err;
 373
 374         kthread_init_delayed_work(&chip->irq_poll_work,
 375                                   mv88e6xxx_irq_poll);
 376
 377         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 378         if (IS_ERR(chip->kworker))
 379                 return PTR_ERR(chip->kworker);
 380
 381         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 382                                    msecs_to_jiffies(100));
 383
 384         return 0;
 385 }
 386
 387 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 388 {
 389         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 390         kthread_destroy_worker(chip->kworker);
 391
 392         mv88e6xxx_reg_lock(chip);
 393         mv88e6xxx_g1_irq_free_common(chip);
 394         mv88e6xxx_reg_unlock(chip);
 395 }
 396
 397 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 398                              int speed, int duplex, int pause,
 399                              phy_interface_t mode)
 400 {
 401         struct phylink_link_state state;
 402         int err;
 403
 404         if (!chip->info->ops->port_set_link)
 405                 return 0;
 406
 407         if (!chip->info->ops->port_link_state)
 408                 return 0;
 409
 410         err = chip->info->ops->port_link_state(chip, port, &state);
 411         if (err)
 412                 return err;
 413
 414         /* Has anything actually changed? We don't expect the
 415          * interface mode to change without one of the other
 416          * parameters also changing
 417          */
 418         if (state.link == link &&
 419             state.speed == speed &&
 420             state.duplex == duplex &&
 421             (state.interface == mode ||
 422              state.interface == PHY_INTERFACE_MODE_NA))
 423                 return 0;
 424
 425         /* Port's MAC control must not be changed unless the link is down */
 426         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 427         if (err)
 428                 return err;
 429
 430         if (chip->info->ops->port_set_speed) {
 431                 err = chip->info->ops->port_set_speed(chip, port, speed);
 432                 if (err && err != -EOPNOTSUPP)
 433                         goto restore_link;
 434         }
 435
 436         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 437                 mode = chip->info->ops->port_max_speed_mode(port);
 438
 439         if (chip->info->ops->port_set_pause) {
 440                 err = chip->info->ops->port_set_pause(chip, port, pause);
 441                 if (err)
 442                         goto restore_link;
 443         }
 444
 445         if (chip->info->ops->port_set_duplex) {
 446                 err = chip->info->ops->port_set_duplex(chip, port, duplex);
 447                 if (err && err != -EOPNOTSUPP)
 448                         goto restore_link;
 449         }
 450
 451         if (chip->info->ops->port_set_rgmii_delay) {
 452                 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
 453                 if (err && err != -EOPNOTSUPP)
 454                         goto restore_link;
 455         }
 456
 457         if (chip->info->ops->port_set_cmode) {
 458                 err = chip->info->ops->port_set_cmode(chip, port, mode);
 459                 if (err && err != -EOPNOTSUPP)
 460                         goto restore_link;
 461         }
 462
 463         err = 0;
 464 restore_link:
 465         if (chip->info->ops->port_set_link(chip, port, link))
 466                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 467
 468         return err;
 469 }
 470
 471 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 472 {
 473         struct mv88e6xxx_chip *chip = ds->priv;
 474
 475         return port < chip->info->num_internal_phys;
 476 }
 477
 478 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 479                                        unsigned long *mask,
 480                                        struct phylink_link_state *state)
 481 {
 482         if (!phy_interface_mode_is_8023z(state->interface)) {
 483                 /* 10M and 100M are only supported in non-802.3z mode */
 484                 phylink_set(mask, 10baseT_Half);
 485                 phylink_set(mask, 10baseT_Full);
 486                 phylink_set(mask, 100baseT_Half);
 487                 phylink_set(mask, 100baseT_Full);
 488         }
 489 }
 490
 491 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 492                                        unsigned long *mask,
 493                                        struct phylink_link_state *state)
 494 {
 495         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 496          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 497          */
 498         phylink_set(mask, 1000baseT_Full);
 499         phylink_set(mask, 1000baseX_Full);
 500
 501         mv88e6065_phylink_validate(chip, port, mask, state);
 502 }
 503
 504 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 505                                        unsigned long *mask,
 506                                        struct phylink_link_state *state)
 507 {
 508         if (port >= 5)
 509                 phylink_set(mask, 2500baseX_Full);
 510
 511         /* No ethtool bits for 200Mbps */
 512         phylink_set(mask, 1000baseT_Full);
 513         phylink_set(mask, 1000baseX_Full);
 514
 515         mv88e6065_phylink_validate(chip, port, mask, state);
 516 }
 517
 518 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 519                                        unsigned long *mask,
 520                                        struct phylink_link_state *state)
 521 {
 522         /* No ethtool bits for 200Mbps */
 523         phylink_set(mask, 1000baseT_Full);
 524         phylink_set(mask, 1000baseX_Full);
 525
 526         mv88e6065_phylink_validate(chip, port, mask, state);
 527 }
 528
 529 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 530                                        unsigned long *mask,
 531                                        struct phylink_link_state *state)
 532 {
 533         if (port >= 9) {
 534                 phylink_set(mask, 2500baseX_Full);
 535                 phylink_set(mask, 2500baseT_Full);
 536         }
 537
 538         /* No ethtool bits for 200Mbps */
 539         phylink_set(mask, 1000baseT_Full);
 540         phylink_set(mask, 1000baseX_Full);
 541
 542         mv88e6065_phylink_validate(chip, port, mask, state);
 543 }
 544
 545 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 546                                         unsigned long *mask,
 547                                         struct phylink_link_state *state)
 548 {
 549         if (port >= 9) {
 550                 phylink_set(mask, 10000baseT_Full);
 551                 phylink_set(mask, 10000baseKR_Full);
 552         }
 553
 554         mv88e6390_phylink_validate(chip, port, mask, state);
 555 }
 556
 557 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 558                                unsigned long *supported,
 559                                struct phylink_link_state *state)
 560 {
 561         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 562         struct mv88e6xxx_chip *chip = ds->priv;
 563
 564         /* Allow all the expected bits */
 565         phylink_set(mask, Autoneg);
 566         phylink_set(mask, Pause);
 567         phylink_set_port_modes(mask);
 568
 569         if (chip->info->ops->phylink_validate)
 570                 chip->info->ops->phylink_validate(chip, port, mask, state);
 571
 572         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 573         bitmap_and(state->advertising, state->advertising, mask,
 574                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 575
 576         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 577          * to advertise both, only report advertising at 2500BaseX.
 578          */
 579         phylink_helper_basex_speed(state);
 580 }
 581
 582 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
 583                                 struct phylink_link_state *state)
 584 {
 585         struct mv88e6xxx_chip *chip = ds->priv;
 586         int err;
 587
 588         mv88e6xxx_reg_lock(chip);
 589         if (chip->info->ops->port_link_state)
 590                 err = chip->info->ops->port_link_state(chip, port, state);
 591         else
 592                 err = -EOPNOTSUPP;
 593         mv88e6xxx_reg_unlock(chip);
 594
 595         return err;
 596 }
 597
 598 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 599                                  unsigned int mode,
 600                                  const struct phylink_link_state *state)
 601 {
 602         struct mv88e6xxx_chip *chip = ds->priv;
 603         int speed, duplex, link, pause, err;
 604
 605         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 606                 return;
 607
 608         if (mode == MLO_AN_FIXED) {
 609                 link = LINK_FORCED_UP;
 610                 speed = state->speed;
 611                 duplex = state->duplex;
 612         } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
 613                 link = state->link;
 614                 speed = state->speed;
 615                 duplex = state->duplex;
 616         } else {
 617                 speed = SPEED_UNFORCED;
 618                 duplex = DUPLEX_UNFORCED;
 619                 link = LINK_UNFORCED;
 620         }
 621         pause = !!phylink_test(state->advertising, Pause);
 622
 623         mv88e6xxx_reg_lock(chip);
 624         err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
 625                                        state->interface);
 626         mv88e6xxx_reg_unlock(chip);
 627
 628         if (err && err != -EOPNOTSUPP)
 629                 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
 630 }
 631
 632 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
 633 {
 634         struct mv88e6xxx_chip *chip = ds->priv;
 635         int err;
 636
 637         mv88e6xxx_reg_lock(chip);
 638         err = chip->info->ops->port_set_link(chip, port, link);
 639         mv88e6xxx_reg_unlock(chip);
 640
 641         if (err)
 642                 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
 643 }
 644
 645 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 646                                     unsigned int mode,
 647                                     phy_interface_t interface)
 648 {
 649         if (mode == MLO_AN_FIXED)
 650                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
 651 }
 652
 653 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 654                                   unsigned int mode, phy_interface_t interface,
 655                                   struct phy_device *phydev)
 656 {
 657         if (mode == MLO_AN_FIXED)
 658                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
 659 }
 660
 661 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 662 {
 663         if (!chip->info->ops->stats_snapshot)
 664                 return -EOPNOTSUPP;
 665
 666         return chip->info->ops->stats_snapshot(chip, port);
 667 }
 668
 669 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 670         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 671         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 672         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 673         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 674         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 675         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 676         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 677         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 678         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 679         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 680         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 681         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 682         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 683         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 684         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 685         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 686         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 687         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 688         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 689         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 690         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 691         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 692         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 693         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 694         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 695         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 696         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 697         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 698         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 699         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 700         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 701         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 702         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 703         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 704         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 705         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 706         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 707         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 708         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 709         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 710         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 711         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 712         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 713         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 714         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 715         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 716         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 717         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 718         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 719         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 720         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 721         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 722         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 723         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 724         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 725         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 726         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 727         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 728         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 729 };
 730
 731 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 732                                             struct mv88e6xxx_hw_stat *s,
 733                                             int port, u16 bank1_select,
 734                                             u16 histogram)
 735 {
 736         u32 low;
 737         u32 high = 0;
 738         u16 reg = 0;
 739         int err;
 740         u64 value;
 741
 742         switch (s->type) {
 743         case STATS_TYPE_PORT:
 744                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 745                 if (err)
 746                         return U64_MAX;
 747
 748                 low = reg;
 749                 if (s->size == 4) {
 750                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 751                         if (err)
 752                                 return U64_MAX;
 753                         low |= ((u32)reg) << 16;
 754                 }
 755                 break;
 756         case STATS_TYPE_BANK1:
 757                 reg = bank1_select;
 758                 /* fall through */
 759         case STATS_TYPE_BANK0:
 760                 reg |= s->reg | histogram;
 761                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 762                 if (s->size == 8)
 763                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 764                 break;
 765         default:
 766                 return U64_MAX;
 767         }
 768         value = (((u64)high) << 32) | low;
 769         return value;
 770 }
 771
 772 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 773                                        uint8_t *data, int types)
 774 {
 775         struct mv88e6xxx_hw_stat *stat;
 776         int i, j;
 777
 778         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 779                 stat = &mv88e6xxx_hw_stats[i];
 780                 if (stat->type & types) {
 781                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 782                                ETH_GSTRING_LEN);
 783                         j++;
 784                 }
 785         }
 786
 787         return j;
 788 }
 789
 790 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 791                                        uint8_t *data)
 792 {
 793         return mv88e6xxx_stats_get_strings(chip, data,
 794                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 795 }
 796
 797 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 798                                        uint8_t *data)
 799 {
 800         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 801 }
 802
 803 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 804                                        uint8_t *data)
 805 {
 806         return mv88e6xxx_stats_get_strings(chip, data,
 807                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 808 }
 809
 810 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 811         "atu_member_violation",
 812         "atu_miss_violation",
 813         "atu_full_violation",
 814         "vtu_member_violation",
 815         "vtu_miss_violation",
 816 };
 817
 818 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 819 {
 820         unsigned int i;
 821
 822         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 823                 strlcpy(data + i * ETH_GSTRING_LEN,
 824                         mv88e6xxx_atu_vtu_stats_strings[i],
 825                         ETH_GSTRING_LEN);
 826 }
 827
 828 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 829                                   u32 stringset, uint8_t *data)
 830 {
 831         struct mv88e6xxx_chip *chip = ds->priv;
 832         int count = 0;
 833
 834         if (stringset != ETH_SS_STATS)
 835                 return;
 836
 837         mv88e6xxx_reg_lock(chip);
 838
 839         if (chip->info->ops->stats_get_strings)
 840                 count = chip->info->ops->stats_get_strings(chip, data);
 841
 842         if (chip->info->ops->serdes_get_strings) {
 843                 data += count * ETH_GSTRING_LEN;
 844                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 845         }
 846
 847         data += count * ETH_GSTRING_LEN;
 848         mv88e6xxx_atu_vtu_get_strings(data);
 849
 850         mv88e6xxx_reg_unlock(chip);
 851 }
 852
 853 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 854                                           int types)
 855 {
 856         struct mv88e6xxx_hw_stat *stat;
 857         int i, j;
 858
 859         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 860                 stat = &mv88e6xxx_hw_stats[i];
 861                 if (stat->type & types)
 862                         j++;
 863         }
 864         return j;
 865 }
 866
 867 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 868 {
 869         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 870                                               STATS_TYPE_PORT);
 871 }
 872
 873 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 874 {
 875         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 876 }
 877
 878 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 879 {
 880         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 881                                               STATS_TYPE_BANK1);
 882 }
 883
 884 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
 885 {
 886         struct mv88e6xxx_chip *chip = ds->priv;
 887         int serdes_count = 0;
 888         int count = 0;
 889
 890         if (sset != ETH_SS_STATS)
 891                 return 0;
 892
 893         mv88e6xxx_reg_lock(chip);
 894         if (chip->info->ops->stats_get_sset_count)
 895                 count = chip->info->ops->stats_get_sset_count(chip);
 896         if (count < 0)
 897                 goto out;
 898
 899         if (chip->info->ops->serdes_get_sset_count)
 900                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
 901                                                                       port);
 902         if (serdes_count < 0) {
 903                 count = serdes_count;
 904                 goto out;
 905         }
 906         count += serdes_count;
 907         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
 908
 909 out:
 910         mv88e6xxx_reg_unlock(chip);
 911
 912         return count;
 913 }
 914
 915 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 916                                      uint64_t *data, int types,
 917                                      u16 bank1_select, u16 histogram)
 918 {
 919         struct mv88e6xxx_hw_stat *stat;
 920         int i, j;
 921
 922         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 923                 stat = &mv88e6xxx_hw_stats[i];
 924                 if (stat->type & types) {
 925                         mv88e6xxx_reg_lock(chip);
 926                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
 927                                                               bank1_select,
 928                                                               histogram);
 929                         mv88e6xxx_reg_unlock(chip);
 930
 931                         j++;
 932                 }
 933         }
 934         return j;
 935 }
 936
 937 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 938                                      uint64_t *data)
 939 {
 940         return mv88e6xxx_stats_get_stats(chip, port, data,
 941                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
 942                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 943 }
 944
 945 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 946                                      uint64_t *data)
 947 {
 948         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
 949                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 950 }
 951
 952 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 953                                      uint64_t *data)
 954 {
 955         return mv88e6xxx_stats_get_stats(chip, port, data,
 956                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 957                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
 958                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 959 }
 960
 961 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 962                                      uint64_t *data)
 963 {
 964         return mv88e6xxx_stats_get_stats(chip, port, data,
 965                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 966                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
 967                                          0);
 968 }
 969
 970 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
 971                                         uint64_t *data)
 972 {
 973         *data++ = chip->ports[port].atu_member_violation;
 974         *data++ = chip->ports[port].atu_miss_violation;
 975         *data++ = chip->ports[port].atu_full_violation;
 976         *data++ = chip->ports[port].vtu_member_violation;
 977         *data++ = chip->ports[port].vtu_miss_violation;
 978 }
 979
 980 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
 981                                 uint64_t *data)
 982 {
 983         int count = 0;
 984
 985         if (chip->info->ops->stats_get_stats)
 986                 count = chip->info->ops->stats_get_stats(chip, port, data);
 987
 988         mv88e6xxx_reg_lock(chip);
 989         if (chip->info->ops->serdes_get_stats) {
 990                 data += count;
 991                 count = chip->info->ops->serdes_get_stats(chip, port, data);
 992         }
 993         data += count;
 994         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
 995         mv88e6xxx_reg_unlock(chip);
 996 }
 997
 998 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 999                                         uint64_t *data)
1000 {
1001         struct mv88e6xxx_chip *chip = ds->priv;
1002         int ret;
1003
1004         mv88e6xxx_reg_lock(chip);
1005
1006         ret = mv88e6xxx_stats_snapshot(chip, port);
1007         mv88e6xxx_reg_unlock(chip);
1008
1009         if (ret < 0)
1010                 return;
1011
1012         mv88e6xxx_get_stats(chip, port, data);
1013
1014 }
1015
1016 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1017 {
1018         return 32 * sizeof(u16);
1019 }
1020
1021 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1022                                struct ethtool_regs *regs, void *_p)
1023 {
1024         struct mv88e6xxx_chip *chip = ds->priv;
1025         int err;
1026         u16 reg;
1027         u16 *p = _p;
1028         int i;
1029
1030         regs->version = chip->info->prod_num;
1031
1032         memset(p, 0xff, 32 * sizeof(u16));
1033
1034         mv88e6xxx_reg_lock(chip);
1035
1036         for (i = 0; i < 32; i++) {
1037
1038                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1039                 if (!err)
1040                         p[i] = reg;
1041         }
1042
1043         mv88e6xxx_reg_unlock(chip);
1044 }
1045
1046 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1047                                  struct ethtool_eee *e)
1048 {
1049         /* Nothing to do on the port's MAC */
1050         return 0;
1051 }
1052
1053 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1054                                  struct ethtool_eee *e)
1055 {
1056         /* Nothing to do on the port's MAC */
1057         return 0;
1058 }
1059
1060 /* Mask of the local ports allowed to receive frames from a given fabric port */
1061 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1062 {
1063         struct dsa_switch *ds = chip->ds;
1064         struct dsa_switch_tree *dst = ds->dst;
1065         struct net_device *br;
1066         struct dsa_port *dp;
1067         bool found = false;
1068         u16 pvlan;
1069
1070         list_for_each_entry(dp, &dst->ports, list) {
1071                 if (dp->ds->index == dev && dp->index == port) {
1072                         found = true;
1073                         break;
1074                 }
1075         }
1076
1077         /* Prevent frames from unknown switch or port */
1078         if (!found)
1079                 return 0;
1080
1081         /* Frames from DSA links and CPU ports can egress any local port */
1082         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1083                 return mv88e6xxx_port_mask(chip);
1084
1085         br = dp->bridge_dev;
1086         pvlan = 0;
1087
1088         /* Frames from user ports can egress any local DSA links and CPU ports,
1089          * as well as any local member of their bridge group.
1090          */
1091         list_for_each_entry(dp, &dst->ports, list)
1092                 if (dp->ds == ds &&
1093                     (dp->type == DSA_PORT_TYPE_CPU ||
1094                      dp->type == DSA_PORT_TYPE_DSA ||
1095                      (br && dp->bridge_dev == br)))
1096                         pvlan |= BIT(dp->index);
1097
1098         return pvlan;
1099 }
1100
1101 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1102 {
1103         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1104
1105         /* prevent frames from going back out of the port they came in on */
1106         output_ports &= ~BIT(port);
1107
1108         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1109 }
1110
1111 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1112                                          u8 state)
1113 {
1114         struct mv88e6xxx_chip *chip = ds->priv;
1115         int err;
1116
1117         mv88e6xxx_reg_lock(chip);
1118         err = mv88e6xxx_port_set_state(chip, port, state);
1119         mv88e6xxx_reg_unlock(chip);
1120
1121         if (err)
1122                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1123 }
1124
1125 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1126 {
1127         int err;
1128
1129         if (chip->info->ops->ieee_pri_map) {
1130                 err = chip->info->ops->ieee_pri_map(chip);
1131                 if (err)
1132                         return err;
1133         }
1134
1135         if (chip->info->ops->ip_pri_map) {
1136                 err = chip->info->ops->ip_pri_map(chip);
1137                 if (err)
1138                         return err;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1145 {
1146         struct dsa_switch *ds = chip->ds;
1147         int target, port;
1148         int err;
1149
1150         if (!chip->info->global2_addr)
1151                 return 0;
1152
1153         /* Initialize the routing port to the 32 possible target devices */
1154         for (target = 0; target < 32; target++) {
1155                 port = dsa_routing_port(ds, target);
1156                 if (port == ds->num_ports)
1157                         port = 0x1f;
1158
1159                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1160                 if (err)
1161                         return err;
1162         }
1163
1164         if (chip->info->ops->set_cascade_port) {
1165                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1166                 err = chip->info->ops->set_cascade_port(chip, port);
1167                 if (err)
1168                         return err;
1169         }
1170
1171         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1172         if (err)
1173                 return err;
1174
1175         return 0;
1176 }
1177
1178 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1179 {
1180         /* Clear all trunk masks and mapping */
1181         if (chip->info->global2_addr)
1182                 return mv88e6xxx_g2_trunk_clear(chip);
1183
1184         return 0;
1185 }
1186
1187 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1188 {
1189         if (chip->info->ops->rmu_disable)
1190                 return chip->info->ops->rmu_disable(chip);
1191
1192         return 0;
1193 }
1194
1195 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1196 {
1197         if (chip->info->ops->pot_clear)
1198                 return chip->info->ops->pot_clear(chip);
1199
1200         return 0;
1201 }
1202
1203 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1204 {
1205         if (chip->info->ops->mgmt_rsvd2cpu)
1206                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1207
1208         return 0;
1209 }
1210
1211 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1212 {
1213         int err;
1214
1215         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1216         if (err)
1217                 return err;
1218
1219         err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1220         if (err)
1221                 return err;
1222
1223         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1224 }
1225
1226 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1227 {
1228         int port;
1229         int err;
1230
1231         if (!chip->info->ops->irl_init_all)
1232                 return 0;
1233
1234         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1235                 /* Disable ingress rate limiting by resetting all per port
1236                  * ingress rate limit resources to their initial state.
1237                  */
1238                 err = chip->info->ops->irl_init_all(chip, port);
1239                 if (err)
1240                         return err;
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1247 {
1248         if (chip->info->ops->set_switch_mac) {
1249                 u8 addr[ETH_ALEN];
1250
1251                 eth_random_addr(addr);
1252
1253                 return chip->info->ops->set_switch_mac(chip, addr);
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1260 {
1261         u16 pvlan = 0;
1262
1263         if (!mv88e6xxx_has_pvt(chip))
1264                 return 0;
1265
1266         /* Skip the local source device, which uses in-chip port VLAN */
1267         if (dev != chip->ds->index)
1268                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1269
1270         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1271 }
1272
1273 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1274 {
1275         int dev, port;
1276         int err;
1277
1278         if (!mv88e6xxx_has_pvt(chip))
1279                 return 0;
1280
1281         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1282          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1283          */
1284         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1285         if (err)
1286                 return err;
1287
1288         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1289                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1290                         err = mv88e6xxx_pvt_map(chip, dev, port);
1291                         if (err)
1292                                 return err;
1293                 }
1294         }
1295
1296         return 0;
1297 }
1298
1299 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1300 {
1301         struct mv88e6xxx_chip *chip = ds->priv;
1302         int err;
1303
1304         mv88e6xxx_reg_lock(chip);
1305         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1306         mv88e6xxx_reg_unlock(chip);
1307
1308         if (err)
1309                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1310 }
1311
1312 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1313 {
1314         if (!chip->info->max_vid)
1315                 return 0;
1316
1317         return mv88e6xxx_g1_vtu_flush(chip);
1318 }
1319
1320 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1321                                  struct mv88e6xxx_vtu_entry *entry)
1322 {
1323         if (!chip->info->ops->vtu_getnext)
1324                 return -EOPNOTSUPP;
1325
1326         return chip->info->ops->vtu_getnext(chip, entry);
1327 }
1328
1329 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1330                                    struct mv88e6xxx_vtu_entry *entry)
1331 {
1332         if (!chip->info->ops->vtu_loadpurge)
1333                 return -EOPNOTSUPP;
1334
1335         return chip->info->ops->vtu_loadpurge(chip, entry);
1336 }
1337
1338 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1339 {
1340         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1341         struct mv88e6xxx_vtu_entry vlan;
1342         int i, err;
1343
1344         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1345
1346         /* Set every FID bit used by the (un)bridged ports */
1347         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1348                 err = mv88e6xxx_port_get_fid(chip, i, fid);
1349                 if (err)
1350                         return err;
1351
1352                 set_bit(*fid, fid_bitmap);
1353         }
1354
1355         /* Set every FID bit used by the VLAN entries */
1356         vlan.vid = chip->info->max_vid;
1357         vlan.valid = false;
1358
1359         do {
1360                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1361                 if (err)
1362                         return err;
1363
1364                 if (!vlan.valid)
1365                         break;
1366
1367                 set_bit(vlan.fid, fid_bitmap);
1368         } while (vlan.vid < chip->info->max_vid);
1369
1370         /* The reset value 0x000 is used to indicate that multiple address
1371          * databases are not needed. Return the next positive available.
1372          */
1373         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1374         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1375                 return -ENOSPC;
1376
1377         /* Clear the database */
1378         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1379 }
1380
1381 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
1382 {
1383         if (chip->info->ops->atu_get_hash)
1384                 return chip->info->ops->atu_get_hash(chip, hash);
1385
1386         return -EOPNOTSUPP;
1387 }
1388
1389 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
1390 {
1391         if (chip->info->ops->atu_set_hash)
1392                 return chip->info->ops->atu_set_hash(chip, hash);
1393
1394         return -EOPNOTSUPP;
1395 }
1396
1397 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1398                                         u16 vid_begin, u16 vid_end)
1399 {
1400         struct mv88e6xxx_chip *chip = ds->priv;
1401         struct mv88e6xxx_vtu_entry vlan;
1402         int i, err;
1403
1404         /* DSA and CPU ports have to be members of multiple vlans */
1405         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1406                 return 0;
1407
1408         if (!vid_begin)
1409                 return -EOPNOTSUPP;
1410
1411         vlan.vid = vid_begin - 1;
1412         vlan.valid = false;
1413
1414         do {
1415                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1416                 if (err)
1417                         return err;
1418
1419                 if (!vlan.valid)
1420                         break;
1421
1422                 if (vlan.vid > vid_end)
1423                         break;
1424
1425                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1426                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1427                                 continue;
1428
1429                         if (!dsa_to_port(ds, i)->slave)
1430                                 continue;
1431
1432                         if (vlan.member[i] ==
1433                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1434                                 continue;
1435
1436                         if (dsa_to_port(ds, i)->bridge_dev ==
1437                             dsa_to_port(ds, port)->bridge_dev)
1438                                 break; /* same bridge, check next VLAN */
1439
1440                         if (!dsa_to_port(ds, i)->bridge_dev)
1441                                 continue;
1442
1443                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1444                                 port, vlan.vid, i,
1445                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1446                         return -EOPNOTSUPP;
1447                 }
1448         } while (vlan.vid < vid_end);
1449
1450         return 0;
1451 }
1452
1453 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1454                                          bool vlan_filtering)
1455 {
1456         struct mv88e6xxx_chip *chip = ds->priv;
1457         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1458                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1459         int err;
1460
1461         if (!chip->info->max_vid)
1462                 return -EOPNOTSUPP;
1463
1464         mv88e6xxx_reg_lock(chip);
1465         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1466         mv88e6xxx_reg_unlock(chip);
1467
1468         return err;
1469 }
1470
1471 static int
1472 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1473                             const struct switchdev_obj_port_vlan *vlan)
1474 {
1475         struct mv88e6xxx_chip *chip = ds->priv;
1476         int err;
1477
1478         if (!chip->info->max_vid)
1479                 return -EOPNOTSUPP;
1480
1481         /* If the requested port doesn't belong to the same bridge as the VLAN
1482          * members, do not support it (yet) and fallback to software VLAN.
1483          */
1484         mv88e6xxx_reg_lock(chip);
1485         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1486                                            vlan->vid_end);
1487         mv88e6xxx_reg_unlock(chip);
1488
1489         /* We don't need any dynamic resource from the kernel (yet),
1490          * so skip the prepare phase.
1491          */
1492         return err;
1493 }
1494
1495 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1496                                         const unsigned char *addr, u16 vid,
1497                                         u8 state)
1498 {
1499         struct mv88e6xxx_atu_entry entry;
1500         struct mv88e6xxx_vtu_entry vlan;
1501         u16 fid;
1502         int err;
1503
1504         /* Null VLAN ID corresponds to the port private database */
1505         if (vid == 0) {
1506                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1507                 if (err)
1508                         return err;
1509         } else {
1510                 vlan.vid = vid - 1;
1511                 vlan.valid = false;
1512
1513                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1514                 if (err)
1515                         return err;
1516
1517                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1518                 if (vlan.vid != vid || !vlan.valid)
1519                         return -EOPNOTSUPP;
1520
1521                 fid = vlan.fid;
1522         }
1523
1524         entry.state = 0;
1525         ether_addr_copy(entry.mac, addr);
1526         eth_addr_dec(entry.mac);
1527
1528         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1529         if (err)
1530                 return err;
1531
1532         /* Initialize a fresh ATU entry if it isn't found */
1533         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1534                 memset(&entry, 0, sizeof(entry));
1535                 ether_addr_copy(entry.mac, addr);
1536         }
1537
1538         /* Purge the ATU entry only if no port is using it anymore */
1539         if (!state) {
1540                 entry.portvec &= ~BIT(port);
1541                 if (!entry.portvec)
1542                         entry.state = 0;
1543         } else {
1544                 entry.portvec |= BIT(port);
1545                 entry.state = state;
1546         }
1547
1548         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1549 }
1550
1551 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1552                                   const struct mv88e6xxx_policy *policy)
1553 {
1554         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1555         enum mv88e6xxx_policy_action action = policy->action;
1556         const u8 *addr = policy->addr;
1557         u16 vid = policy->vid;
1558         u8 state;
1559         int err;
1560         int id;
1561
1562         if (!chip->info->ops->port_set_policy)
1563                 return -EOPNOTSUPP;
1564
1565         switch (mapping) {
1566         case MV88E6XXX_POLICY_MAPPING_DA:
1567         case MV88E6XXX_POLICY_MAPPING_SA:
1568                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1569                         state = 0; /* Dissociate the port and address */
1570                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1571                          is_multicast_ether_addr(addr))
1572                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1573                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1574                          is_unicast_ether_addr(addr))
1575                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1576                 else
1577                         return -EOPNOTSUPP;
1578
1579                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1580                                                    state);
1581                 if (err)
1582                         return err;
1583                 break;
1584         default:
1585                 return -EOPNOTSUPP;
1586         }
1587
1588         /* Skip the port's policy clearing if the mapping is still in use */
1589         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1590                 idr_for_each_entry(&chip->policies, policy, id)
1591                         if (policy->port == port &&
1592                             policy->mapping == mapping &&
1593                             policy->action != action)
1594                                 return 0;
1595
1596         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1597 }
1598
1599 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1600                                    struct ethtool_rx_flow_spec *fs)
1601 {
1602         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1603         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1604         enum mv88e6xxx_policy_mapping mapping;
1605         enum mv88e6xxx_policy_action action;
1606         struct mv88e6xxx_policy *policy;
1607         u16 vid = 0;
1608         u8 *addr;
1609         int err;
1610         int id;
1611
1612         if (fs->location != RX_CLS_LOC_ANY)
1613                 return -EINVAL;
1614
1615         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1616                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1617         else
1618                 return -EOPNOTSUPP;
1619
1620         switch (fs->flow_type & ~FLOW_EXT) {
1621         case ETHER_FLOW:
1622                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1623                     is_zero_ether_addr(mac_mask->h_source)) {
1624                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1625                         addr = mac_entry->h_dest;
1626                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1627                     !is_zero_ether_addr(mac_mask->h_source)) {
1628                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1629                         addr = mac_entry->h_source;
1630                 } else {
1631                         /* Cannot support DA and SA mapping in the same rule */
1632                         return -EOPNOTSUPP;
1633                 }
1634                 break;
1635         default:
1636                 return -EOPNOTSUPP;
1637         }
1638
1639         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1640                 if (fs->m_ext.vlan_tci != 0xffff)
1641                         return -EOPNOTSUPP;
1642                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1643         }
1644
1645         idr_for_each_entry(&chip->policies, policy, id) {
1646                 if (policy->port == port && policy->mapping == mapping &&
1647                     policy->action == action && policy->vid == vid &&
1648                     ether_addr_equal(policy->addr, addr))
1649                         return -EEXIST;
1650         }
1651
1652         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1653         if (!policy)
1654                 return -ENOMEM;
1655
1656         fs->location = 0;
1657         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1658                             GFP_KERNEL);
1659         if (err) {
1660                 devm_kfree(chip->dev, policy);
1661                 return err;
1662         }
1663
1664         memcpy(&policy->fs, fs, sizeof(*fs));
1665         ether_addr_copy(policy->addr, addr);
1666         policy->mapping = mapping;
1667         policy->action = action;
1668         policy->port = port;
1669         policy->vid = vid;
1670
1671         err = mv88e6xxx_policy_apply(chip, port, policy);
1672         if (err) {
1673                 idr_remove(&chip->policies, fs->location);
1674                 devm_kfree(chip->dev, policy);
1675                 return err;
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1682                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1683 {
1684         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1685         struct mv88e6xxx_chip *chip = ds->priv;
1686         struct mv88e6xxx_policy *policy;
1687         int err;
1688         int id;
1689
1690         mv88e6xxx_reg_lock(chip);
1691
1692         switch (rxnfc->cmd) {
1693         case ETHTOOL_GRXCLSRLCNT:
1694                 rxnfc->data = 0;
1695                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1696                 rxnfc->rule_cnt = 0;
1697                 idr_for_each_entry(&chip->policies, policy, id)
1698                         if (policy->port == port)
1699                                 rxnfc->rule_cnt++;
1700                 err = 0;
1701                 break;
1702         case ETHTOOL_GRXCLSRULE:
1703                 err = -ENOENT;
1704                 policy = idr_find(&chip->policies, fs->location);
1705                 if (policy) {
1706                         memcpy(fs, &policy->fs, sizeof(*fs));
1707                         err = 0;
1708                 }
1709                 break;
1710         case ETHTOOL_GRXCLSRLALL:
1711                 rxnfc->data = 0;
1712                 rxnfc->rule_cnt = 0;
1713                 idr_for_each_entry(&chip->policies, policy, id)
1714                         if (policy->port == port)
1715                                 rule_locs[rxnfc->rule_cnt++] = id;
1716                 err = 0;
1717                 break;
1718         default:
1719                 err = -EOPNOTSUPP;
1720                 break;
1721         }
1722
1723         mv88e6xxx_reg_unlock(chip);
1724
1725         return err;
1726 }
1727
1728 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1729                                struct ethtool_rxnfc *rxnfc)
1730 {
1731         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1732         struct mv88e6xxx_chip *chip = ds->priv;
1733         struct mv88e6xxx_policy *policy;
1734         int err;
1735
1736         mv88e6xxx_reg_lock(chip);
1737
1738         switch (rxnfc->cmd) {
1739         case ETHTOOL_SRXCLSRLINS:
1740                 err = mv88e6xxx_policy_insert(chip, port, fs);
1741                 break;
1742         case ETHTOOL_SRXCLSRLDEL:
1743                 err = -ENOENT;
1744                 policy = idr_remove(&chip->policies, fs->location);
1745                 if (policy) {
1746                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1747                         err = mv88e6xxx_policy_apply(chip, port, policy);
1748                         devm_kfree(chip->dev, policy);
1749                 }
1750                 break;
1751         default:
1752                 err = -EOPNOTSUPP;
1753                 break;
1754         }
1755
1756         mv88e6xxx_reg_unlock(chip);
1757
1758         return err;
1759 }
1760
1761 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1762                                         u16 vid)
1763 {
1764         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1765         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1766
1767         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1768 }
1769
1770 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1771 {
1772         int port;
1773         int err;
1774
1775         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1776                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1777                 if (err)
1778                         return err;
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1785                                     u16 vid, u8 member)
1786 {
1787         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1788         struct mv88e6xxx_vtu_entry vlan;
1789         int i, err;
1790
1791         if (!vid)
1792                 return -EOPNOTSUPP;
1793
1794         vlan.vid = vid - 1;
1795         vlan.valid = false;
1796
1797         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1798         if (err)
1799                 return err;
1800
1801         if (vlan.vid != vid || !vlan.valid) {
1802                 memset(&vlan, 0, sizeof(vlan));
1803
1804                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1805                 if (err)
1806                         return err;
1807
1808                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1809                         if (i == port)
1810                                 vlan.member[i] = member;
1811                         else
1812                                 vlan.member[i] = non_member;
1813
1814                 vlan.vid = vid;
1815                 vlan.valid = true;
1816
1817                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1818                 if (err)
1819                         return err;
1820
1821                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1822                 if (err)
1823                         return err;
1824         } else if (vlan.member[port] != member) {
1825                 vlan.member[port] = member;
1826
1827                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1828                 if (err)
1829                         return err;
1830         } else {
1831                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1832                          port, vid);
1833         }
1834
1835         return 0;
1836 }
1837
1838 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1839                                     const struct switchdev_obj_port_vlan *vlan)
1840 {
1841         struct mv88e6xxx_chip *chip = ds->priv;
1842         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1843         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1844         u8 member;
1845         u16 vid;
1846
1847         if (!chip->info->max_vid)
1848                 return;
1849
1850         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1851                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1852         else if (untagged)
1853                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1854         else
1855                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1856
1857         mv88e6xxx_reg_lock(chip);
1858
1859         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1860                 if (mv88e6xxx_port_vlan_join(chip, port, vid, member))
1861                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1862                                 vid, untagged ? 'u' : 't');
1863
1864         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1865                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1866                         vlan->vid_end);
1867
1868         mv88e6xxx_reg_unlock(chip);
1869 }
1870
1871 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
1872                                      int port, u16 vid)
1873 {
1874         struct mv88e6xxx_vtu_entry vlan;
1875         int i, err;
1876
1877         if (!vid)
1878                 return -EOPNOTSUPP;
1879
1880         vlan.vid = vid - 1;
1881         vlan.valid = false;
1882
1883         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1884         if (err)
1885                 return err;
1886
1887         /* If the VLAN doesn't exist in hardware or the port isn't a member,
1888          * tell switchdev that this VLAN is likely handled in software.
1889          */
1890         if (vlan.vid != vid || !vlan.valid ||
1891             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1892                 return -EOPNOTSUPP;
1893
1894         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1895
1896         /* keep the VLAN unless all ports are excluded */
1897         vlan.valid = false;
1898         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1899                 if (vlan.member[i] !=
1900                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1901                         vlan.valid = true;
1902                         break;
1903                 }
1904         }
1905
1906         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1907         if (err)
1908                 return err;
1909
1910         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1911 }
1912
1913 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1914                                    const struct switchdev_obj_port_vlan *vlan)
1915 {
1916         struct mv88e6xxx_chip *chip = ds->priv;
1917         u16 pvid, vid;
1918         int err = 0;
1919
1920         if (!chip->info->max_vid)
1921                 return -EOPNOTSUPP;
1922
1923         mv88e6xxx_reg_lock(chip);
1924
1925         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1926         if (err)
1927                 goto unlock;
1928
1929         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1930                 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
1931                 if (err)
1932                         goto unlock;
1933
1934                 if (vid == pvid) {
1935                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
1936                         if (err)
1937                                 goto unlock;
1938                 }
1939         }
1940
1941 unlock:
1942         mv88e6xxx_reg_unlock(chip);
1943
1944         return err;
1945 }
1946
1947 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1948                                   const unsigned char *addr, u16 vid)
1949 {
1950         struct mv88e6xxx_chip *chip = ds->priv;
1951         int err;
1952
1953         mv88e6xxx_reg_lock(chip);
1954         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1955                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1956         mv88e6xxx_reg_unlock(chip);
1957
1958         return err;
1959 }
1960
1961 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1962                                   const unsigned char *addr, u16 vid)
1963 {
1964         struct mv88e6xxx_chip *chip = ds->priv;
1965         int err;
1966
1967         mv88e6xxx_reg_lock(chip);
1968         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
1969         mv88e6xxx_reg_unlock(chip);
1970
1971         return err;
1972 }
1973
1974 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1975                                       u16 fid, u16 vid, int port,
1976                                       dsa_fdb_dump_cb_t *cb, void *data)
1977 {
1978         struct mv88e6xxx_atu_entry addr;
1979         bool is_static;
1980         int err;
1981
1982         addr.state = 0;
1983         eth_broadcast_addr(addr.mac);
1984
1985         do {
1986                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1987                 if (err)
1988                         return err;
1989
1990                 if (!addr.state)
1991                         break;
1992
1993                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1994                         continue;
1995
1996                 if (!is_unicast_ether_addr(addr.mac))
1997                         continue;
1998
1999                 is_static = (addr.state ==
2000                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2001                 err = cb(addr.mac, vid, is_static, data);
2002                 if (err)
2003                         return err;
2004         } while (!is_broadcast_ether_addr(addr.mac));
2005
2006         return err;
2007 }
2008
2009 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2010                                   dsa_fdb_dump_cb_t *cb, void *data)
2011 {
2012         struct mv88e6xxx_vtu_entry vlan;
2013         u16 fid;
2014         int err;
2015
2016         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2017         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2018         if (err)
2019                 return err;
2020
2021         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2022         if (err)
2023                 return err;
2024
2025         /* Dump VLANs' Filtering Information Databases */
2026         vlan.vid = chip->info->max_vid;
2027         vlan.valid = false;
2028
2029         do {
2030                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2031                 if (err)
2032                         return err;
2033
2034                 if (!vlan.valid)
2035                         break;
2036
2037                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2038                                                  cb, data);
2039                 if (err)
2040                         return err;
2041         } while (vlan.vid < chip->info->max_vid);
2042
2043         return err;
2044 }
2045
2046 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2047                                    dsa_fdb_dump_cb_t *cb, void *data)
2048 {
2049         struct mv88e6xxx_chip *chip = ds->priv;
2050         int err;
2051
2052         mv88e6xxx_reg_lock(chip);
2053         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2054         mv88e6xxx_reg_unlock(chip);
2055
2056         return err;
2057 }
2058
2059 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2060                                 struct net_device *br)
2061 {
2062         struct dsa_switch *ds = chip->ds;
2063         struct dsa_switch_tree *dst = ds->dst;
2064         struct dsa_port *dp;
2065         int err;
2066
2067         list_for_each_entry(dp, &dst->ports, list) {
2068                 if (dp->bridge_dev == br) {
2069                         if (dp->ds == ds) {
2070                                 /* This is a local bridge group member,
2071                                  * remap its Port VLAN Map.
2072                                  */
2073                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2074                                 if (err)
2075                                         return err;
2076                         } else {
2077                                 /* This is an external bridge group member,
2078                                  * remap its cross-chip Port VLAN Table entry.
2079                                  */
2080                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2081                                                         dp->index);
2082                                 if (err)
2083                                         return err;
2084                         }
2085                 }
2086         }
2087
2088         return 0;
2089 }
2090
2091 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2092                                       struct net_device *br)
2093 {
2094         struct mv88e6xxx_chip *chip = ds->priv;
2095         int err;
2096
2097         mv88e6xxx_reg_lock(chip);
2098         err = mv88e6xxx_bridge_map(chip, br);
2099         mv88e6xxx_reg_unlock(chip);
2100
2101         return err;
2102 }
2103
2104 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2105                                         struct net_device *br)
2106 {
2107         struct mv88e6xxx_chip *chip = ds->priv;
2108
2109         mv88e6xxx_reg_lock(chip);
2110         if (mv88e6xxx_bridge_map(chip, br) ||
2111             mv88e6xxx_port_vlan_map(chip, port))
2112                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2113         mv88e6xxx_reg_unlock(chip);
2114 }
2115
2116 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2117                                            int port, struct net_device *br)
2118 {
2119         struct mv88e6xxx_chip *chip = ds->priv;
2120         int err;
2121
2122         mv88e6xxx_reg_lock(chip);
2123         err = mv88e6xxx_pvt_map(chip, dev, port);
2124         mv88e6xxx_reg_unlock(chip);
2125
2126         return err;
2127 }
2128
2129 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2130                                              int port, struct net_device *br)
2131 {
2132         struct mv88e6xxx_chip *chip = ds->priv;
2133
2134         mv88e6xxx_reg_lock(chip);
2135         if (mv88e6xxx_pvt_map(chip, dev, port))
2136                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2137         mv88e6xxx_reg_unlock(chip);
2138 }
2139
2140 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2141 {
2142         if (chip->info->ops->reset)
2143                 return chip->info->ops->reset(chip);
2144
2145         return 0;
2146 }
2147
2148 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2149 {
2150         struct gpio_desc *gpiod = chip->reset;
2151
2152         /* If there is a GPIO connected to the reset pin, toggle it */
2153         if (gpiod) {
2154                 gpiod_set_value_cansleep(gpiod, 1);
2155                 usleep_range(10000, 20000);
2156                 gpiod_set_value_cansleep(gpiod, 0);
2157                 usleep_range(10000, 20000);
2158         }
2159 }
2160
2161 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2162 {
2163         int i, err;
2164
2165         /* Set all ports to the Disabled state */
2166         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2167                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2168                 if (err)
2169                         return err;
2170         }
2171
2172         /* Wait for transmit queues to drain,
2173          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2174          */
2175         usleep_range(2000, 4000);
2176
2177         return 0;
2178 }
2179
2180 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2181 {
2182         int err;
2183
2184         err = mv88e6xxx_disable_ports(chip);
2185         if (err)
2186                 return err;
2187
2188         mv88e6xxx_hardware_reset(chip);
2189
2190         return mv88e6xxx_software_reset(chip);
2191 }
2192
2193 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2194                                    enum mv88e6xxx_frame_mode frame,
2195                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2196 {
2197         int err;
2198
2199         if (!chip->info->ops->port_set_frame_mode)
2200                 return -EOPNOTSUPP;
2201
2202         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2203         if (err)
2204                 return err;
2205
2206         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2207         if (err)
2208                 return err;
2209
2210         if (chip->info->ops->port_set_ether_type)
2211                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2212
2213         return 0;
2214 }
2215
2216 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2217 {
2218         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2219                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2220                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2221 }
2222
2223 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2224 {
2225         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2226                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2227                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2228 }
2229
2230 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2231 {
2232         return mv88e6xxx_set_port_mode(chip, port,
2233                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2234                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2235                                        ETH_P_EDSA);
2236 }
2237
2238 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2239 {
2240         if (dsa_is_dsa_port(chip->ds, port))
2241                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2242
2243         if (dsa_is_user_port(chip->ds, port))
2244                 return mv88e6xxx_set_port_mode_normal(chip, port);
2245
2246         /* Setup CPU port mode depending on its supported tag format */
2247         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2248                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2249
2250         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2251                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2252
2253         return -EINVAL;
2254 }
2255
2256 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2257 {
2258         bool message = dsa_is_dsa_port(chip->ds, port);
2259
2260         return mv88e6xxx_port_set_message_port(chip, port, message);
2261 }
2262
2263 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2264 {
2265         struct dsa_switch *ds = chip->ds;
2266         bool flood;
2267
2268         /* Upstream ports flood frames with unknown unicast or multicast DA */
2269         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2270         if (chip->info->ops->port_set_egress_floods)
2271                 return chip->info->ops->port_set_egress_floods(chip, port,
2272                                                                flood, flood);
2273
2274         return 0;
2275 }
2276
2277 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2278 {
2279         struct mv88e6xxx_port *mvp = dev_id;
2280         struct mv88e6xxx_chip *chip = mvp->chip;
2281         irqreturn_t ret = IRQ_NONE;
2282         int port = mvp->port;
2283         u8 lane;
2284
2285         mv88e6xxx_reg_lock(chip);
2286         lane = mv88e6xxx_serdes_get_lane(chip, port);
2287         if (lane)
2288                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2289         mv88e6xxx_reg_unlock(chip);
2290
2291         return ret;
2292 }
2293
2294 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2295                                         u8 lane)
2296 {
2297         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2298         unsigned int irq;
2299         int err;
2300
2301         /* Nothing to request if this SERDES port has no IRQ */
2302         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2303         if (!irq)
2304                 return 0;
2305
2306         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2307         mv88e6xxx_reg_unlock(chip);
2308         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2309                                    IRQF_ONESHOT, "mv88e6xxx-serdes", dev_id);
2310         mv88e6xxx_reg_lock(chip);
2311         if (err)
2312                 return err;
2313
2314         dev_id->serdes_irq = irq;
2315
2316         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2317 }
2318
2319 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2320                                      u8 lane)
2321 {
2322         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2323         unsigned int irq = dev_id->serdes_irq;
2324         int err;
2325
2326         /* Nothing to free if no IRQ has been requested */
2327         if (!irq)
2328                 return 0;
2329
2330         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2331
2332         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2333         mv88e6xxx_reg_unlock(chip);
2334         free_irq(irq, dev_id);
2335         mv88e6xxx_reg_lock(chip);
2336
2337         dev_id->serdes_irq = 0;
2338
2339         return err;
2340 }
2341
2342 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2343                                   bool on)
2344 {
2345         u8 lane;
2346         int err;
2347
2348         lane = mv88e6xxx_serdes_get_lane(chip, port);
2349         if (!lane)
2350                 return 0;
2351
2352         if (on) {
2353                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2354                 if (err)
2355                         return err;
2356
2357                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2358         } else {
2359                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2360                 if (err)
2361                         return err;
2362
2363                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2364         }
2365
2366         return err;
2367 }
2368
2369 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2370 {
2371         struct dsa_switch *ds = chip->ds;
2372         int upstream_port;
2373         int err;
2374
2375         upstream_port = dsa_upstream_port(ds, port);
2376         if (chip->info->ops->port_set_upstream_port) {
2377                 err = chip->info->ops->port_set_upstream_port(chip, port,
2378                                                               upstream_port);
2379                 if (err)
2380                         return err;
2381         }
2382
2383         if (port == upstream_port) {
2384                 if (chip->info->ops->set_cpu_port) {
2385                         err = chip->info->ops->set_cpu_port(chip,
2386                                                             upstream_port);
2387                         if (err)
2388                                 return err;
2389                 }
2390
2391                 if (chip->info->ops->set_egress_port) {
2392                         err = chip->info->ops->set_egress_port(chip,
2393                                                                upstream_port);
2394                         if (err)
2395                                 return err;
2396                 }
2397         }
2398
2399         return 0;
2400 }
2401
2402 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2403 {
2404         struct dsa_switch *ds = chip->ds;
2405         int err;
2406         u16 reg;
2407
2408         chip->ports[port].chip = chip;
2409         chip->ports[port].port = port;
2410
2411         /* MAC Forcing register: don't force link, speed, duplex or flow control
2412          * state to any particular values on physical ports, but force the CPU
2413          * port and all DSA ports to their maximum bandwidth and full duplex.
2414          */
2415         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2416                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2417                                                SPEED_MAX, DUPLEX_FULL,
2418                                                PAUSE_OFF,
2419                                                PHY_INTERFACE_MODE_NA);
2420         else
2421                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2422                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2423                                                PAUSE_ON,
2424                                                PHY_INTERFACE_MODE_NA);
2425         if (err)
2426                 return err;
2427
2428         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2429          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2430          * tunneling, determine priority by looking at 802.1p and IP
2431          * priority fields (IP prio has precedence), and set STP state
2432          * to Forwarding.
2433          *
2434          * If this is the CPU link, use DSA or EDSA tagging depending
2435          * on which tagging mode was configured.
2436          *
2437          * If this is a link to another switch, use DSA tagging mode.
2438          *
2439          * If this is the upstream port for this switch, enable
2440          * forwarding of unknown unicasts and multicasts.
2441          */
2442         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2443                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2444                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2445         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2446         if (err)
2447                 return err;
2448
2449         err = mv88e6xxx_setup_port_mode(chip, port);
2450         if (err)
2451                 return err;
2452
2453         err = mv88e6xxx_setup_egress_floods(chip, port);
2454         if (err)
2455                 return err;
2456
2457         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2458          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2459          * untagged frames on this port, do a destination address lookup on all
2460          * received packets as usual, disable ARP mirroring and don't send a
2461          * copy of all transmitted/received frames on this port to the CPU.
2462          */
2463         err = mv88e6xxx_port_set_map_da(chip, port);
2464         if (err)
2465                 return err;
2466
2467         err = mv88e6xxx_setup_upstream_port(chip, port);
2468         if (err)
2469                 return err;
2470
2471         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2472                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2473         if (err)
2474                 return err;
2475
2476         if (chip->info->ops->port_set_jumbo_size) {
2477                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2478                 if (err)
2479                         return err;
2480         }
2481
2482         /* Port Association Vector: when learning source addresses
2483          * of packets, add the address to the address database using
2484          * a port bitmap that has only the bit for this port set and
2485          * the other bits clear.
2486          */
2487         reg = 1 << port;
2488         /* Disable learning for CPU port */
2489         if (dsa_is_cpu_port(ds, port))
2490                 reg = 0;
2491
2492         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2493                                    reg);
2494         if (err)
2495                 return err;
2496
2497         /* Egress rate control 2: disable egress rate control. */
2498         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2499                                    0x0000);
2500         if (err)
2501                 return err;
2502
2503         if (chip->info->ops->port_pause_limit) {
2504                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2505                 if (err)
2506                         return err;
2507         }
2508
2509         if (chip->info->ops->port_disable_learn_limit) {
2510                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2511                 if (err)
2512                         return err;
2513         }
2514
2515         if (chip->info->ops->port_disable_pri_override) {
2516                 err = chip->info->ops->port_disable_pri_override(chip, port);
2517                 if (err)
2518                         return err;
2519         }
2520
2521         if (chip->info->ops->port_tag_remap) {
2522                 err = chip->info->ops->port_tag_remap(chip, port);
2523                 if (err)
2524                         return err;
2525         }
2526
2527         if (chip->info->ops->port_egress_rate_limiting) {
2528                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2529                 if (err)
2530                         return err;
2531         }
2532
2533         if (chip->info->ops->port_setup_message_port) {
2534                 err = chip->info->ops->port_setup_message_port(chip, port);
2535                 if (err)
2536                         return err;
2537         }
2538
2539         /* Port based VLAN map: give each port the same default address
2540          * database, and allow bidirectional communication between the
2541          * CPU and DSA port(s), and the other ports.
2542          */
2543         err = mv88e6xxx_port_set_fid(chip, port, 0);
2544         if (err)
2545                 return err;
2546
2547         err = mv88e6xxx_port_vlan_map(chip, port);
2548         if (err)
2549                 return err;
2550
2551         /* Default VLAN ID and priority: don't set a default VLAN
2552          * ID, and set the default packet priority to zero.
2553          */
2554         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2555 }
2556
2557 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2558                                  struct phy_device *phydev)
2559 {
2560         struct mv88e6xxx_chip *chip = ds->priv;
2561         int err;
2562
2563         mv88e6xxx_reg_lock(chip);
2564         err = mv88e6xxx_serdes_power(chip, port, true);
2565         mv88e6xxx_reg_unlock(chip);
2566
2567         return err;
2568 }
2569
2570 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2571 {
2572         struct mv88e6xxx_chip *chip = ds->priv;
2573
2574         mv88e6xxx_reg_lock(chip);
2575         if (mv88e6xxx_serdes_power(chip, port, false))
2576                 dev_err(chip->dev, "failed to power off SERDES\n");
2577         mv88e6xxx_reg_unlock(chip);
2578 }
2579
2580 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2581                                      unsigned int ageing_time)
2582 {
2583         struct mv88e6xxx_chip *chip = ds->priv;
2584         int err;
2585
2586         mv88e6xxx_reg_lock(chip);
2587         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2588         mv88e6xxx_reg_unlock(chip);
2589
2590         return err;
2591 }
2592
2593 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2594 {
2595         int err;
2596
2597         /* Initialize the statistics unit */
2598         if (chip->info->ops->stats_set_histogram) {
2599                 err = chip->info->ops->stats_set_histogram(chip);
2600                 if (err)
2601                         return err;
2602         }
2603
2604         return mv88e6xxx_g1_stats_clear(chip);
2605 }
2606
2607 /* Check if the errata has already been applied. */
2608 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2609 {
2610         int port;
2611         int err;
2612         u16 val;
2613
2614         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2615                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2616                 if (err) {
2617                         dev_err(chip->dev,
2618                                 "Error reading hidden register: %d\n", err);
2619                         return false;
2620                 }
2621                 if (val != 0x01c0)
2622                         return false;
2623         }
2624
2625         return true;
2626 }
2627
2628 /* The 6390 copper ports have an errata which require poking magic
2629  * values into undocumented hidden registers and then performing a
2630  * software reset.
2631  */
2632 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2633 {
2634         int port;
2635         int err;
2636
2637         if (mv88e6390_setup_errata_applied(chip))
2638                 return 0;
2639
2640         /* Set the ports into blocking mode */
2641         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2642                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2643                 if (err)
2644                         return err;
2645         }
2646
2647         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2648                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2649                 if (err)
2650                         return err;
2651         }
2652
2653         return mv88e6xxx_software_reset(chip);
2654 }
2655
2656 enum mv88e6xxx_devlink_param_id {
2657         MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
2658         MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2659 };
2660
2661 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
2662                                        struct devlink_param_gset_ctx *ctx)
2663 {
2664         struct mv88e6xxx_chip *chip = ds->priv;
2665         int err;
2666
2667         mv88e6xxx_reg_lock(chip);
2668
2669         switch (id) {
2670         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2671                 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
2672                 break;
2673         default:
2674                 err = -EOPNOTSUPP;
2675                 break;
2676         }
2677
2678         mv88e6xxx_reg_unlock(chip);
2679
2680         return err;
2681 }
2682
2683 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
2684                                        struct devlink_param_gset_ctx *ctx)
2685 {
2686         struct mv88e6xxx_chip *chip = ds->priv;
2687         int err;
2688
2689         mv88e6xxx_reg_lock(chip);
2690
2691         switch (id) {
2692         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2693                 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
2694                 break;
2695         default:
2696                 err = -EOPNOTSUPP;
2697                 break;
2698         }
2699
2700         mv88e6xxx_reg_unlock(chip);
2701
2702         return err;
2703 }
2704
2705 static const struct devlink_param mv88e6xxx_devlink_params[] = {
2706         DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2707                                  "ATU_hash", DEVLINK_PARAM_TYPE_U8,
2708                                  BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
2709 };
2710
2711 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
2712 {
2713         return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
2714                                            ARRAY_SIZE(mv88e6xxx_devlink_params));
2715 }
2716
2717 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
2718 {
2719         dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
2720                                       ARRAY_SIZE(mv88e6xxx_devlink_params));
2721 }
2722
2723 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2724 {
2725         mv88e6xxx_teardown_devlink_params(ds);
2726 }
2727
2728 static int mv88e6xxx_setup(struct dsa_switch *ds)
2729 {
2730         struct mv88e6xxx_chip *chip = ds->priv;
2731         u8 cmode;
2732         int err;
2733         int i;
2734
2735         chip->ds = ds;
2736         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2737
2738         mv88e6xxx_reg_lock(chip);
2739
2740         if (chip->info->ops->setup_errata) {
2741                 err = chip->info->ops->setup_errata(chip);
2742                 if (err)
2743                         goto unlock;
2744         }
2745
2746         /* Cache the cmode of each port. */
2747         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2748                 if (chip->info->ops->port_get_cmode) {
2749                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2750                         if (err)
2751                                 goto unlock;
2752
2753                         chip->ports[i].cmode = cmode;
2754                 }
2755         }
2756
2757         /* Setup Switch Port Registers */
2758         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2759                 if (dsa_is_unused_port(ds, i))
2760                         continue;
2761
2762                 /* Prevent the use of an invalid port. */
2763                 if (mv88e6xxx_is_invalid_port(chip, i)) {
2764                         dev_err(chip->dev, "port %d is invalid\n", i);
2765                         err = -EINVAL;
2766                         goto unlock;
2767                 }
2768
2769                 err = mv88e6xxx_setup_port(chip, i);
2770                 if (err)
2771                         goto unlock;
2772         }
2773
2774         err = mv88e6xxx_irl_setup(chip);
2775         if (err)
2776                 goto unlock;
2777
2778         err = mv88e6xxx_mac_setup(chip);
2779         if (err)
2780                 goto unlock;
2781
2782         err = mv88e6xxx_phy_setup(chip);
2783         if (err)
2784                 goto unlock;
2785
2786         err = mv88e6xxx_vtu_setup(chip);
2787         if (err)
2788                 goto unlock;
2789
2790         err = mv88e6xxx_pvt_setup(chip);
2791         if (err)
2792                 goto unlock;
2793
2794         err = mv88e6xxx_atu_setup(chip);
2795         if (err)
2796                 goto unlock;
2797
2798         err = mv88e6xxx_broadcast_setup(chip, 0);
2799         if (err)
2800                 goto unlock;
2801
2802         err = mv88e6xxx_pot_setup(chip);
2803         if (err)
2804                 goto unlock;
2805
2806         err = mv88e6xxx_rmu_setup(chip);
2807         if (err)
2808                 goto unlock;
2809
2810         err = mv88e6xxx_rsvd2cpu_setup(chip);
2811         if (err)
2812                 goto unlock;
2813
2814         err = mv88e6xxx_trunk_setup(chip);
2815         if (err)
2816                 goto unlock;
2817
2818         err = mv88e6xxx_devmap_setup(chip);
2819         if (err)
2820                 goto unlock;
2821
2822         err = mv88e6xxx_pri_setup(chip);
2823         if (err)
2824                 goto unlock;
2825
2826         /* Setup PTP Hardware Clock and timestamping */
2827         if (chip->info->ptp_support) {
2828                 err = mv88e6xxx_ptp_setup(chip);
2829                 if (err)
2830                         goto unlock;
2831
2832                 err = mv88e6xxx_hwtstamp_setup(chip);
2833                 if (err)
2834                         goto unlock;
2835         }
2836
2837         err = mv88e6xxx_stats_setup(chip);
2838         if (err)
2839                 goto unlock;
2840
2841 unlock:
2842         mv88e6xxx_reg_unlock(chip);
2843
2844         /* Has to be called without holding the register lock, since
2845          * it takes the devlink lock, and we later take the locks in
2846          * the reverse order when getting/setting parameters.
2847          */
2848         return mv88e6xxx_setup_devlink_params(ds);
2849 }
2850
2851 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2852 {
2853         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2854         struct mv88e6xxx_chip *chip = mdio_bus->chip;
2855         u16 val;
2856         int err;
2857
2858         if (!chip->info->ops->phy_read)
2859                 return -EOPNOTSUPP;
2860
2861         mv88e6xxx_reg_lock(chip);
2862         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2863         mv88e6xxx_reg_unlock(chip);
2864
2865         if (reg == MII_PHYSID2) {
2866                 /* Some internal PHYs don't have a model number. */
2867                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
2868                         /* Then there is the 6165 family. It gets is
2869                          * PHYs correct. But it can also have two
2870                          * SERDES interfaces in the PHY address
2871                          * space. And these don't have a model
2872                          * number. But they are not PHYs, so we don't
2873                          * want to give them something a PHY driver
2874                          * will recognise.
2875                          *
2876                          * Use the mv88e6390 family model number
2877                          * instead, for anything which really could be
2878                          * a PHY,
2879                          */
2880                         if (!(val & 0x3f0))
2881                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2882         }
2883
2884         return err ? err : val;
2885 }
2886
2887 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2888 {
2889         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2890         struct mv88e6xxx_chip *chip = mdio_bus->chip;
2891         int err;
2892
2893         if (!chip->info->ops->phy_write)
2894                 return -EOPNOTSUPP;
2895
2896         mv88e6xxx_reg_lock(chip);
2897         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2898         mv88e6xxx_reg_unlock(chip);
2899
2900         return err;
2901 }
2902
2903 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2904                                    struct device_node *np,
2905                                    bool external)
2906 {
2907         static int index;
2908         struct mv88e6xxx_mdio_bus *mdio_bus;
2909         struct mii_bus *bus;
2910         int err;
2911
2912         if (external) {
2913                 mv88e6xxx_reg_lock(chip);
2914                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2915                 mv88e6xxx_reg_unlock(chip);
2916
2917                 if (err)
2918                         return err;
2919         }
2920
2921         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2922         if (!bus)
2923                 return -ENOMEM;
2924
2925         mdio_bus = bus->priv;
2926         mdio_bus->bus = bus;
2927         mdio_bus->chip = chip;
2928         INIT_LIST_HEAD(&mdio_bus->list);
2929         mdio_bus->external = external;
2930
2931         if (np) {
2932                 bus->name = np->full_name;
2933                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2934         } else {
2935                 bus->name = "mv88e6xxx SMI";
2936                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2937         }
2938
2939         bus->read = mv88e6xxx_mdio_read;
2940         bus->write = mv88e6xxx_mdio_write;
2941         bus->parent = chip->dev;
2942
2943         if (!external) {
2944                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2945                 if (err)
2946                         return err;
2947         }
2948
2949         err = of_mdiobus_register(bus, np);
2950         if (err) {
2951                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2952                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2953                 return err;
2954         }
2955
2956         if (external)
2957                 list_add_tail(&mdio_bus->list, &chip->mdios);
2958         else
2959                 list_add(&mdio_bus->list, &chip->mdios);
2960
2961         return 0;
2962 }
2963
2964 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2965         { .compatible = "marvell,mv88e6xxx-mdio-external",
2966           .data = (void *)true },
2967         { },
2968 };
2969
2970 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2971
2972 {
2973         struct mv88e6xxx_mdio_bus *mdio_bus;
2974         struct mii_bus *bus;
2975
2976         list_for_each_entry(mdio_bus, &chip->mdios, list) {
2977                 bus = mdio_bus->bus;
2978
2979                 if (!mdio_bus->external)
2980                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
2981
2982                 mdiobus_unregister(bus);
2983         }
2984 }
2985
2986 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2987                                     struct device_node *np)
2988 {
2989         const struct of_device_id *match;
2990         struct device_node *child;
2991         int err;
2992
2993         /* Always register one mdio bus for the internal/default mdio
2994          * bus. This maybe represented in the device tree, but is
2995          * optional.
2996          */
2997         child = of_get_child_by_name(np, "mdio");
2998         err = mv88e6xxx_mdio_register(chip, child, false);
2999         if (err)
3000                 return err;
3001
3002         /* Walk the device tree, and see if there are any other nodes
3003          * which say they are compatible with the external mdio
3004          * bus.
3005          */
3006         for_each_available_child_of_node(np, child) {
3007                 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3008                 if (match) {
3009                         err = mv88e6xxx_mdio_register(chip, child, true);
3010                         if (err) {
3011                                 mv88e6xxx_mdios_unregister(chip);
3012                                 of_node_put(child);
3013                                 return err;
3014                         }
3015                 }
3016         }
3017
3018         return 0;
3019 }
3020
3021 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3022 {
3023         struct mv88e6xxx_chip *chip = ds->priv;
3024
3025         return chip->eeprom_len;
3026 }
3027
3028 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3029                                 struct ethtool_eeprom *eeprom, u8 *data)
3030 {
3031         struct mv88e6xxx_chip *chip = ds->priv;
3032         int err;
3033
3034         if (!chip->info->ops->get_eeprom)
3035                 return -EOPNOTSUPP;
3036
3037         mv88e6xxx_reg_lock(chip);
3038         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3039         mv88e6xxx_reg_unlock(chip);
3040
3041         if (err)
3042                 return err;
3043
3044         eeprom->magic = 0xc3ec4951;
3045
3046         return 0;
3047 }
3048
3049 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3050                                 struct ethtool_eeprom *eeprom, u8 *data)
3051 {
3052         struct mv88e6xxx_chip *chip = ds->priv;
3053         int err;
3054
3055         if (!chip->info->ops->set_eeprom)
3056                 return -EOPNOTSUPP;
3057
3058         if (eeprom->magic != 0xc3ec4951)
3059                 return -EINVAL;
3060
3061         mv88e6xxx_reg_lock(chip);
3062         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3063         mv88e6xxx_reg_unlock(chip);
3064
3065         return err;
3066 }
3067
3068 static const struct mv88e6xxx_ops mv88e6085_ops = {
3069         /* MV88E6XXX_FAMILY_6097 */
3070         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3071         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3072         .irl_init_all = mv88e6352_g2_irl_init_all,
3073         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3074         .phy_read = mv88e6185_phy_ppu_read,
3075         .phy_write = mv88e6185_phy_ppu_write,
3076         .port_set_link = mv88e6xxx_port_set_link,
3077         .port_set_duplex = mv88e6xxx_port_set_duplex,
3078         .port_set_speed = mv88e6185_port_set_speed,
3079         .port_tag_remap = mv88e6095_port_tag_remap,
3080         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3081         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3082         .port_set_ether_type = mv88e6351_port_set_ether_type,
3083         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3084         .port_pause_limit = mv88e6097_port_pause_limit,
3085         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3086         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3087         .port_link_state = mv88e6352_port_link_state,
3088         .port_get_cmode = mv88e6185_port_get_cmode,
3089         .port_setup_message_port = mv88e6xxx_setup_message_port,
3090         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3091         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3092         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3093         .stats_get_strings = mv88e6095_stats_get_strings,
3094         .stats_get_stats = mv88e6095_stats_get_stats,
3095         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3096         .set_egress_port = mv88e6095_g1_set_egress_port,
3097         .watchdog_ops = &mv88e6097_watchdog_ops,
3098         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3099         .pot_clear = mv88e6xxx_g2_pot_clear,
3100         .ppu_enable = mv88e6185_g1_ppu_enable,
3101         .ppu_disable = mv88e6185_g1_ppu_disable,
3102         .reset = mv88e6185_g1_reset,
3103         .rmu_disable = mv88e6085_g1_rmu_disable,
3104         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3105         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3106         .phylink_validate = mv88e6185_phylink_validate,
3107 };
3108
3109 static const struct mv88e6xxx_ops mv88e6095_ops = {
3110         /* MV88E6XXX_FAMILY_6095 */
3111         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3112         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3113         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3114         .phy_read = mv88e6185_phy_ppu_read,
3115         .phy_write = mv88e6185_phy_ppu_write,
3116         .port_set_link = mv88e6xxx_port_set_link,
3117         .port_set_duplex = mv88e6xxx_port_set_duplex,
3118         .port_set_speed = mv88e6185_port_set_speed,
3119         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3120         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3121         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3122         .port_link_state = mv88e6185_port_link_state,
3123         .port_get_cmode = mv88e6185_port_get_cmode,
3124         .port_setup_message_port = mv88e6xxx_setup_message_port,
3125         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3126         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3127         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3128         .stats_get_strings = mv88e6095_stats_get_strings,
3129         .stats_get_stats = mv88e6095_stats_get_stats,
3130         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3131         .ppu_enable = mv88e6185_g1_ppu_enable,
3132         .ppu_disable = mv88e6185_g1_ppu_disable,
3133         .reset = mv88e6185_g1_reset,
3134         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3135         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3136         .phylink_validate = mv88e6185_phylink_validate,
3137 };
3138
3139 static const struct mv88e6xxx_ops mv88e6097_ops = {
3140         /* MV88E6XXX_FAMILY_6097 */
3141         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3142         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3143         .irl_init_all = mv88e6352_g2_irl_init_all,
3144         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3145         .phy_read = mv88e6xxx_g2_smi_phy_read,
3146         .phy_write = mv88e6xxx_g2_smi_phy_write,
3147         .port_set_link = mv88e6xxx_port_set_link,
3148         .port_set_duplex = mv88e6xxx_port_set_duplex,
3149         .port_set_speed = mv88e6185_port_set_speed,
3150         .port_tag_remap = mv88e6095_port_tag_remap,
3151         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3152         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3153         .port_set_ether_type = mv88e6351_port_set_ether_type,
3154         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3155         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3156         .port_pause_limit = mv88e6097_port_pause_limit,
3157         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3158         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3159         .port_link_state = mv88e6352_port_link_state,
3160         .port_get_cmode = mv88e6185_port_get_cmode,
3161         .port_setup_message_port = mv88e6xxx_setup_message_port,
3162         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3163         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3164         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3165         .stats_get_strings = mv88e6095_stats_get_strings,
3166         .stats_get_stats = mv88e6095_stats_get_stats,
3167         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3168         .set_egress_port = mv88e6095_g1_set_egress_port,
3169         .watchdog_ops = &mv88e6097_watchdog_ops,
3170         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3171         .pot_clear = mv88e6xxx_g2_pot_clear,
3172         .reset = mv88e6352_g1_reset,
3173         .rmu_disable = mv88e6085_g1_rmu_disable,
3174         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3175         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3176         .phylink_validate = mv88e6185_phylink_validate,
3177 };
3178
3179 static const struct mv88e6xxx_ops mv88e6123_ops = {
3180         /* MV88E6XXX_FAMILY_6165 */
3181         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3182         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3183         .irl_init_all = mv88e6352_g2_irl_init_all,
3184         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3185         .phy_read = mv88e6xxx_g2_smi_phy_read,
3186         .phy_write = mv88e6xxx_g2_smi_phy_write,
3187         .port_set_link = mv88e6xxx_port_set_link,
3188         .port_set_duplex = mv88e6xxx_port_set_duplex,
3189         .port_set_speed = mv88e6185_port_set_speed,
3190         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3191         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3192         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3193         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3194         .port_link_state = mv88e6352_port_link_state,
3195         .port_get_cmode = mv88e6185_port_get_cmode,
3196         .port_setup_message_port = mv88e6xxx_setup_message_port,
3197         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3198         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3199         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3200         .stats_get_strings = mv88e6095_stats_get_strings,
3201         .stats_get_stats = mv88e6095_stats_get_stats,
3202         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3203         .set_egress_port = mv88e6095_g1_set_egress_port,
3204         .watchdog_ops = &mv88e6097_watchdog_ops,
3205         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3206         .pot_clear = mv88e6xxx_g2_pot_clear,
3207         .reset = mv88e6352_g1_reset,
3208         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3209         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3210         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3211         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3212         .phylink_validate = mv88e6185_phylink_validate,
3213 };
3214
3215 static const struct mv88e6xxx_ops mv88e6131_ops = {
3216         /* MV88E6XXX_FAMILY_6185 */
3217         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3218         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3219         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3220         .phy_read = mv88e6185_phy_ppu_read,
3221         .phy_write = mv88e6185_phy_ppu_write,
3222         .port_set_link = mv88e6xxx_port_set_link,
3223         .port_set_duplex = mv88e6xxx_port_set_duplex,
3224         .port_set_speed = mv88e6185_port_set_speed,
3225         .port_tag_remap = mv88e6095_port_tag_remap,
3226         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3227         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3228         .port_set_ether_type = mv88e6351_port_set_ether_type,
3229         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3230         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3231         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3232         .port_pause_limit = mv88e6097_port_pause_limit,
3233         .port_set_pause = mv88e6185_port_set_pause,
3234         .port_link_state = mv88e6352_port_link_state,
3235         .port_get_cmode = mv88e6185_port_get_cmode,
3236         .port_setup_message_port = mv88e6xxx_setup_message_port,
3237         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3238         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3239         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3240         .stats_get_strings = mv88e6095_stats_get_strings,
3241         .stats_get_stats = mv88e6095_stats_get_stats,
3242         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3243         .set_egress_port = mv88e6095_g1_set_egress_port,
3244         .watchdog_ops = &mv88e6097_watchdog_ops,
3245         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3246         .ppu_enable = mv88e6185_g1_ppu_enable,
3247         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3248         .ppu_disable = mv88e6185_g1_ppu_disable,
3249         .reset = mv88e6185_g1_reset,
3250         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3251         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3252         .phylink_validate = mv88e6185_phylink_validate,
3253 };
3254
3255 static const struct mv88e6xxx_ops mv88e6141_ops = {
3256         /* MV88E6XXX_FAMILY_6341 */
3257         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3258         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3259         .irl_init_all = mv88e6352_g2_irl_init_all,
3260         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3261         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3262         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3263         .phy_read = mv88e6xxx_g2_smi_phy_read,
3264         .phy_write = mv88e6xxx_g2_smi_phy_write,
3265         .port_set_link = mv88e6xxx_port_set_link,
3266         .port_set_duplex = mv88e6xxx_port_set_duplex,
3267         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3268         .port_set_speed = mv88e6341_port_set_speed,
3269         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3270         .port_tag_remap = mv88e6095_port_tag_remap,
3271         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3272         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3273         .port_set_ether_type = mv88e6351_port_set_ether_type,
3274         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3275         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3276         .port_pause_limit = mv88e6097_port_pause_limit,
3277         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3278         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3279         .port_link_state = mv88e6352_port_link_state,
3280         .port_get_cmode = mv88e6352_port_get_cmode,
3281         .port_set_cmode = mv88e6341_port_set_cmode,
3282         .port_setup_message_port = mv88e6xxx_setup_message_port,
3283         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3284         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3285         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3286         .stats_get_strings = mv88e6320_stats_get_strings,
3287         .stats_get_stats = mv88e6390_stats_get_stats,
3288         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3289         .set_egress_port = mv88e6390_g1_set_egress_port,
3290         .watchdog_ops = &mv88e6390_watchdog_ops,
3291         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3292         .pot_clear = mv88e6xxx_g2_pot_clear,
3293         .reset = mv88e6352_g1_reset,
3294         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3295         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3296         .serdes_power = mv88e6390_serdes_power,
3297         .serdes_get_lane = mv88e6341_serdes_get_lane,
3298         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3299         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3300         .serdes_irq_status = mv88e6390_serdes_irq_status,
3301         .gpio_ops = &mv88e6352_gpio_ops,
3302         .phylink_validate = mv88e6341_phylink_validate,
3303 };
3304
3305 static const struct mv88e6xxx_ops mv88e6161_ops = {
3306         /* MV88E6XXX_FAMILY_6165 */
3307         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3308         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3309         .irl_init_all = mv88e6352_g2_irl_init_all,
3310         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3311         .phy_read = mv88e6xxx_g2_smi_phy_read,
3312         .phy_write = mv88e6xxx_g2_smi_phy_write,
3313         .port_set_link = mv88e6xxx_port_set_link,
3314         .port_set_duplex = mv88e6xxx_port_set_duplex,
3315         .port_set_speed = mv88e6185_port_set_speed,
3316         .port_tag_remap = mv88e6095_port_tag_remap,
3317         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3318         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3319         .port_set_ether_type = mv88e6351_port_set_ether_type,
3320         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3321         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3322         .port_pause_limit = mv88e6097_port_pause_limit,
3323         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3324         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3325         .port_link_state = mv88e6352_port_link_state,
3326         .port_get_cmode = mv88e6185_port_get_cmode,
3327         .port_setup_message_port = mv88e6xxx_setup_message_port,
3328         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3329         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3330         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3331         .stats_get_strings = mv88e6095_stats_get_strings,
3332         .stats_get_stats = mv88e6095_stats_get_stats,
3333         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3334         .set_egress_port = mv88e6095_g1_set_egress_port,
3335         .watchdog_ops = &mv88e6097_watchdog_ops,
3336         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3337         .pot_clear = mv88e6xxx_g2_pot_clear,
3338         .reset = mv88e6352_g1_reset,
3339         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3340         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3341         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3342         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3343         .avb_ops = &mv88e6165_avb_ops,
3344         .ptp_ops = &mv88e6165_ptp_ops,
3345         .phylink_validate = mv88e6185_phylink_validate,
3346 };
3347
3348 static const struct mv88e6xxx_ops mv88e6165_ops = {
3349         /* MV88E6XXX_FAMILY_6165 */
3350         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3351         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3352         .irl_init_all = mv88e6352_g2_irl_init_all,
3353         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3354         .phy_read = mv88e6165_phy_read,
3355         .phy_write = mv88e6165_phy_write,
3356         .port_set_link = mv88e6xxx_port_set_link,
3357         .port_set_duplex = mv88e6xxx_port_set_duplex,
3358         .port_set_speed = mv88e6185_port_set_speed,
3359         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3360         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3361         .port_link_state = mv88e6352_port_link_state,
3362         .port_get_cmode = mv88e6185_port_get_cmode,
3363         .port_setup_message_port = mv88e6xxx_setup_message_port,
3364         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3365         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3366         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3367         .stats_get_strings = mv88e6095_stats_get_strings,
3368         .stats_get_stats = mv88e6095_stats_get_stats,
3369         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3370         .set_egress_port = mv88e6095_g1_set_egress_port,
3371         .watchdog_ops = &mv88e6097_watchdog_ops,
3372         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3373         .pot_clear = mv88e6xxx_g2_pot_clear,
3374         .reset = mv88e6352_g1_reset,
3375         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3376         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3377         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3378         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3379         .avb_ops = &mv88e6165_avb_ops,
3380         .ptp_ops = &mv88e6165_ptp_ops,
3381         .phylink_validate = mv88e6185_phylink_validate,
3382 };
3383
3384 static const struct mv88e6xxx_ops mv88e6171_ops = {
3385         /* MV88E6XXX_FAMILY_6351 */
3386         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3387         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3388         .irl_init_all = mv88e6352_g2_irl_init_all,
3389         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3390         .phy_read = mv88e6xxx_g2_smi_phy_read,
3391         .phy_write = mv88e6xxx_g2_smi_phy_write,
3392         .port_set_link = mv88e6xxx_port_set_link,
3393         .port_set_duplex = mv88e6xxx_port_set_duplex,
3394         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3395         .port_set_speed = mv88e6185_port_set_speed,
3396         .port_tag_remap = mv88e6095_port_tag_remap,
3397         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3398         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3399         .port_set_ether_type = mv88e6351_port_set_ether_type,
3400         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3401         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3402         .port_pause_limit = mv88e6097_port_pause_limit,
3403         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3404         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3405         .port_link_state = mv88e6352_port_link_state,
3406         .port_get_cmode = mv88e6352_port_get_cmode,
3407         .port_setup_message_port = mv88e6xxx_setup_message_port,
3408         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3409         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3410         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3411         .stats_get_strings = mv88e6095_stats_get_strings,
3412         .stats_get_stats = mv88e6095_stats_get_stats,
3413         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3414         .set_egress_port = mv88e6095_g1_set_egress_port,
3415         .watchdog_ops = &mv88e6097_watchdog_ops,
3416         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3417         .pot_clear = mv88e6xxx_g2_pot_clear,
3418         .reset = mv88e6352_g1_reset,
3419         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3420         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3421         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3422         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3423         .phylink_validate = mv88e6185_phylink_validate,
3424 };
3425
3426 static const struct mv88e6xxx_ops mv88e6172_ops = {
3427         /* MV88E6XXX_FAMILY_6352 */
3428         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3429         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3430         .irl_init_all = mv88e6352_g2_irl_init_all,
3431         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3432         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3433         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3434         .phy_read = mv88e6xxx_g2_smi_phy_read,
3435         .phy_write = mv88e6xxx_g2_smi_phy_write,
3436         .port_set_link = mv88e6xxx_port_set_link,
3437         .port_set_duplex = mv88e6xxx_port_set_duplex,
3438         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3439         .port_set_speed = mv88e6352_port_set_speed,
3440         .port_tag_remap = mv88e6095_port_tag_remap,
3441         .port_set_policy = mv88e6352_port_set_policy,
3442         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3443         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3444         .port_set_ether_type = mv88e6351_port_set_ether_type,
3445         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3446         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3447         .port_pause_limit = mv88e6097_port_pause_limit,
3448         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3449         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3450         .port_link_state = mv88e6352_port_link_state,
3451         .port_get_cmode = mv88e6352_port_get_cmode,
3452         .port_setup_message_port = mv88e6xxx_setup_message_port,
3453         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3454         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3455         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3456         .stats_get_strings = mv88e6095_stats_get_strings,
3457         .stats_get_stats = mv88e6095_stats_get_stats,
3458         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3459         .set_egress_port = mv88e6095_g1_set_egress_port,
3460         .watchdog_ops = &mv88e6097_watchdog_ops,
3461         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3462         .pot_clear = mv88e6xxx_g2_pot_clear,
3463         .reset = mv88e6352_g1_reset,
3464         .rmu_disable = mv88e6352_g1_rmu_disable,
3465         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3466         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3467         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3468         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3469         .serdes_get_lane = mv88e6352_serdes_get_lane,
3470         .serdes_power = mv88e6352_serdes_power,
3471         .gpio_ops = &mv88e6352_gpio_ops,
3472         .phylink_validate = mv88e6352_phylink_validate,
3473 };
3474
3475 static const struct mv88e6xxx_ops mv88e6175_ops = {
3476         /* MV88E6XXX_FAMILY_6351 */
3477         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3478         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3479         .irl_init_all = mv88e6352_g2_irl_init_all,
3480         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3481         .phy_read = mv88e6xxx_g2_smi_phy_read,
3482         .phy_write = mv88e6xxx_g2_smi_phy_write,
3483         .port_set_link = mv88e6xxx_port_set_link,
3484         .port_set_duplex = mv88e6xxx_port_set_duplex,
3485         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3486         .port_set_speed = mv88e6185_port_set_speed,
3487         .port_tag_remap = mv88e6095_port_tag_remap,
3488         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3489         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3490         .port_set_ether_type = mv88e6351_port_set_ether_type,
3491         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3492         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3493         .port_pause_limit = mv88e6097_port_pause_limit,
3494         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3495         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3496         .port_link_state = mv88e6352_port_link_state,
3497         .port_get_cmode = mv88e6352_port_get_cmode,
3498         .port_setup_message_port = mv88e6xxx_setup_message_port,
3499         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3500         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3501         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3502         .stats_get_strings = mv88e6095_stats_get_strings,
3503         .stats_get_stats = mv88e6095_stats_get_stats,
3504         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3505         .set_egress_port = mv88e6095_g1_set_egress_port,
3506         .watchdog_ops = &mv88e6097_watchdog_ops,
3507         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3508         .pot_clear = mv88e6xxx_g2_pot_clear,
3509         .reset = mv88e6352_g1_reset,
3510         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3511         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3512         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3513         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3514         .phylink_validate = mv88e6185_phylink_validate,
3515 };
3516
3517 static const struct mv88e6xxx_ops mv88e6176_ops = {
3518         /* MV88E6XXX_FAMILY_6352 */
3519         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3520         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3521         .irl_init_all = mv88e6352_g2_irl_init_all,
3522         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3523         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3524         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3525         .phy_read = mv88e6xxx_g2_smi_phy_read,
3526         .phy_write = mv88e6xxx_g2_smi_phy_write,
3527         .port_set_link = mv88e6xxx_port_set_link,
3528         .port_set_duplex = mv88e6xxx_port_set_duplex,
3529         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3530         .port_set_speed = mv88e6352_port_set_speed,
3531         .port_tag_remap = mv88e6095_port_tag_remap,
3532         .port_set_policy = mv88e6352_port_set_policy,
3533         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3534         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3535         .port_set_ether_type = mv88e6351_port_set_ether_type,
3536         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3537         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3538         .port_pause_limit = mv88e6097_port_pause_limit,
3539         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3540         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3541         .port_link_state = mv88e6352_port_link_state,
3542         .port_get_cmode = mv88e6352_port_get_cmode,
3543         .port_setup_message_port = mv88e6xxx_setup_message_port,
3544         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3545         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3546         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3547         .stats_get_strings = mv88e6095_stats_get_strings,
3548         .stats_get_stats = mv88e6095_stats_get_stats,
3549         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3550         .set_egress_port = mv88e6095_g1_set_egress_port,
3551         .watchdog_ops = &mv88e6097_watchdog_ops,
3552         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3553         .pot_clear = mv88e6xxx_g2_pot_clear,
3554         .reset = mv88e6352_g1_reset,
3555         .rmu_disable = mv88e6352_g1_rmu_disable,
3556         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3557         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3558         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3559         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3560         .serdes_get_lane = mv88e6352_serdes_get_lane,
3561         .serdes_power = mv88e6352_serdes_power,
3562         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3563         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3564         .serdes_irq_status = mv88e6352_serdes_irq_status,
3565         .gpio_ops = &mv88e6352_gpio_ops,
3566         .phylink_validate = mv88e6352_phylink_validate,
3567 };
3568
3569 static const struct mv88e6xxx_ops mv88e6185_ops = {
3570         /* MV88E6XXX_FAMILY_6185 */
3571         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3572         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3573         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3574         .phy_read = mv88e6185_phy_ppu_read,
3575         .phy_write = mv88e6185_phy_ppu_write,
3576         .port_set_link = mv88e6xxx_port_set_link,
3577         .port_set_duplex = mv88e6xxx_port_set_duplex,
3578         .port_set_speed = mv88e6185_port_set_speed,
3579         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3580         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3581         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3582         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3583         .port_set_pause = mv88e6185_port_set_pause,
3584         .port_link_state = mv88e6185_port_link_state,
3585         .port_get_cmode = mv88e6185_port_get_cmode,
3586         .port_setup_message_port = mv88e6xxx_setup_message_port,
3587         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3588         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3589         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3590         .stats_get_strings = mv88e6095_stats_get_strings,
3591         .stats_get_stats = mv88e6095_stats_get_stats,
3592         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3593         .set_egress_port = mv88e6095_g1_set_egress_port,
3594         .watchdog_ops = &mv88e6097_watchdog_ops,
3595         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3596         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3597         .ppu_enable = mv88e6185_g1_ppu_enable,
3598         .ppu_disable = mv88e6185_g1_ppu_disable,
3599         .reset = mv88e6185_g1_reset,
3600         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3601         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3602         .phylink_validate = mv88e6185_phylink_validate,
3603 };
3604
3605 static const struct mv88e6xxx_ops mv88e6190_ops = {
3606         /* MV88E6XXX_FAMILY_6390 */
3607         .setup_errata = mv88e6390_setup_errata,
3608         .irl_init_all = mv88e6390_g2_irl_init_all,
3609         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3610         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3611         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3612         .phy_read = mv88e6xxx_g2_smi_phy_read,
3613         .phy_write = mv88e6xxx_g2_smi_phy_write,
3614         .port_set_link = mv88e6xxx_port_set_link,
3615         .port_set_duplex = mv88e6xxx_port_set_duplex,
3616         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3617         .port_set_speed = mv88e6390_port_set_speed,
3618         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3619         .port_tag_remap = mv88e6390_port_tag_remap,
3620         .port_set_policy = mv88e6352_port_set_policy,
3621         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3622         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3623         .port_set_ether_type = mv88e6351_port_set_ether_type,
3624         .port_pause_limit = mv88e6390_port_pause_limit,
3625         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3626         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3627         .port_link_state = mv88e6352_port_link_state,
3628         .port_get_cmode = mv88e6352_port_get_cmode,
3629         .port_set_cmode = mv88e6390_port_set_cmode,
3630         .port_setup_message_port = mv88e6xxx_setup_message_port,
3631         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3632         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3633         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3634         .stats_get_strings = mv88e6320_stats_get_strings,
3635         .stats_get_stats = mv88e6390_stats_get_stats,
3636         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3637         .set_egress_port = mv88e6390_g1_set_egress_port,
3638         .watchdog_ops = &mv88e6390_watchdog_ops,
3639         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3640         .pot_clear = mv88e6xxx_g2_pot_clear,
3641         .reset = mv88e6352_g1_reset,
3642         .rmu_disable = mv88e6390_g1_rmu_disable,
3643         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3644         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3645         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3646         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3647         .serdes_power = mv88e6390_serdes_power,
3648         .serdes_get_lane = mv88e6390_serdes_get_lane,
3649         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3650         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3651         .serdes_irq_status = mv88e6390_serdes_irq_status,
3652         .gpio_ops = &mv88e6352_gpio_ops,
3653         .phylink_validate = mv88e6390_phylink_validate,
3654 };
3655
3656 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3657         /* MV88E6XXX_FAMILY_6390 */
3658         .setup_errata = mv88e6390_setup_errata,
3659         .irl_init_all = mv88e6390_g2_irl_init_all,
3660         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3661         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3662         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3663         .phy_read = mv88e6xxx_g2_smi_phy_read,
3664         .phy_write = mv88e6xxx_g2_smi_phy_write,
3665         .port_set_link = mv88e6xxx_port_set_link,
3666         .port_set_duplex = mv88e6xxx_port_set_duplex,
3667         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3668         .port_set_speed = mv88e6390x_port_set_speed,
3669         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3670         .port_tag_remap = mv88e6390_port_tag_remap,
3671         .port_set_policy = mv88e6352_port_set_policy,
3672         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3673         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3674         .port_set_ether_type = mv88e6351_port_set_ether_type,
3675         .port_pause_limit = mv88e6390_port_pause_limit,
3676         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3677         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3678         .port_link_state = mv88e6352_port_link_state,
3679         .port_get_cmode = mv88e6352_port_get_cmode,
3680         .port_set_cmode = mv88e6390x_port_set_cmode,
3681         .port_setup_message_port = mv88e6xxx_setup_message_port,
3682         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3683         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3684         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3685         .stats_get_strings = mv88e6320_stats_get_strings,
3686         .stats_get_stats = mv88e6390_stats_get_stats,
3687         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3688         .set_egress_port = mv88e6390_g1_set_egress_port,
3689         .watchdog_ops = &mv88e6390_watchdog_ops,
3690         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3691         .pot_clear = mv88e6xxx_g2_pot_clear,
3692         .reset = mv88e6352_g1_reset,
3693         .rmu_disable = mv88e6390_g1_rmu_disable,
3694         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3695         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3696         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3697         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3698         .serdes_power = mv88e6390_serdes_power,
3699         .serdes_get_lane = mv88e6390x_serdes_get_lane,
3700         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3701         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3702         .serdes_irq_status = mv88e6390_serdes_irq_status,
3703         .gpio_ops = &mv88e6352_gpio_ops,
3704         .phylink_validate = mv88e6390x_phylink_validate,
3705 };
3706
3707 static const struct mv88e6xxx_ops mv88e6191_ops = {
3708         /* MV88E6XXX_FAMILY_6390 */
3709         .setup_errata = mv88e6390_setup_errata,
3710         .irl_init_all = mv88e6390_g2_irl_init_all,
3711         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3712         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3713         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3714         .phy_read = mv88e6xxx_g2_smi_phy_read,
3715         .phy_write = mv88e6xxx_g2_smi_phy_write,
3716         .port_set_link = mv88e6xxx_port_set_link,
3717         .port_set_duplex = mv88e6xxx_port_set_duplex,
3718         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3719         .port_set_speed = mv88e6390_port_set_speed,
3720         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3721         .port_tag_remap = mv88e6390_port_tag_remap,
3722         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3723         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3724         .port_set_ether_type = mv88e6351_port_set_ether_type,
3725         .port_pause_limit = mv88e6390_port_pause_limit,
3726         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3727         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3728         .port_link_state = mv88e6352_port_link_state,
3729         .port_get_cmode = mv88e6352_port_get_cmode,
3730         .port_set_cmode = mv88e6390_port_set_cmode,
3731         .port_setup_message_port = mv88e6xxx_setup_message_port,
3732         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3733         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3734         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3735         .stats_get_strings = mv88e6320_stats_get_strings,
3736         .stats_get_stats = mv88e6390_stats_get_stats,
3737         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3738         .set_egress_port = mv88e6390_g1_set_egress_port,
3739         .watchdog_ops = &mv88e6390_watchdog_ops,
3740         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3741         .pot_clear = mv88e6xxx_g2_pot_clear,
3742         .reset = mv88e6352_g1_reset,
3743         .rmu_disable = mv88e6390_g1_rmu_disable,
3744         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3745         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3746         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3747         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3748         .serdes_power = mv88e6390_serdes_power,
3749         .serdes_get_lane = mv88e6390_serdes_get_lane,
3750         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3751         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3752         .serdes_irq_status = mv88e6390_serdes_irq_status,
3753         .avb_ops = &mv88e6390_avb_ops,
3754         .ptp_ops = &mv88e6352_ptp_ops,
3755         .phylink_validate = mv88e6390_phylink_validate,
3756 };
3757
3758 static const struct mv88e6xxx_ops mv88e6240_ops = {
3759         /* MV88E6XXX_FAMILY_6352 */
3760         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3761         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3762         .irl_init_all = mv88e6352_g2_irl_init_all,
3763         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3764         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3765         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3766         .phy_read = mv88e6xxx_g2_smi_phy_read,
3767         .phy_write = mv88e6xxx_g2_smi_phy_write,
3768         .port_set_link = mv88e6xxx_port_set_link,
3769         .port_set_duplex = mv88e6xxx_port_set_duplex,
3770         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3771         .port_set_speed = mv88e6352_port_set_speed,
3772         .port_tag_remap = mv88e6095_port_tag_remap,
3773         .port_set_policy = mv88e6352_port_set_policy,
3774         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3775         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3776         .port_set_ether_type = mv88e6351_port_set_ether_type,
3777         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3778         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3779         .port_pause_limit = mv88e6097_port_pause_limit,
3780         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3781         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3782         .port_link_state = mv88e6352_port_link_state,
3783         .port_get_cmode = mv88e6352_port_get_cmode,
3784         .port_setup_message_port = mv88e6xxx_setup_message_port,
3785         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3786         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3787         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3788         .stats_get_strings = mv88e6095_stats_get_strings,
3789         .stats_get_stats = mv88e6095_stats_get_stats,
3790         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3791         .set_egress_port = mv88e6095_g1_set_egress_port,
3792         .watchdog_ops = &mv88e6097_watchdog_ops,
3793         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3794         .pot_clear = mv88e6xxx_g2_pot_clear,
3795         .reset = mv88e6352_g1_reset,
3796         .rmu_disable = mv88e6352_g1_rmu_disable,
3797         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3798         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3799         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3800         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3801         .serdes_get_lane = mv88e6352_serdes_get_lane,
3802         .serdes_power = mv88e6352_serdes_power,
3803         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3804         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3805         .serdes_irq_status = mv88e6352_serdes_irq_status,
3806         .gpio_ops = &mv88e6352_gpio_ops,
3807         .avb_ops = &mv88e6352_avb_ops,
3808         .ptp_ops = &mv88e6352_ptp_ops,
3809         .phylink_validate = mv88e6352_phylink_validate,
3810 };
3811
3812 static const struct mv88e6xxx_ops mv88e6250_ops = {
3813         /* MV88E6XXX_FAMILY_6250 */
3814         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3815         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3816         .irl_init_all = mv88e6352_g2_irl_init_all,
3817         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3818         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3819         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3820         .phy_read = mv88e6xxx_g2_smi_phy_read,
3821         .phy_write = mv88e6xxx_g2_smi_phy_write,
3822         .port_set_link = mv88e6xxx_port_set_link,
3823         .port_set_duplex = mv88e6xxx_port_set_duplex,
3824         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3825         .port_set_speed = mv88e6250_port_set_speed,
3826         .port_tag_remap = mv88e6095_port_tag_remap,
3827         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3828         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3829         .port_set_ether_type = mv88e6351_port_set_ether_type,
3830         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3831         .port_pause_limit = mv88e6097_port_pause_limit,
3832         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3833         .port_link_state = mv88e6250_port_link_state,
3834         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3835         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3836         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3837         .stats_get_strings = mv88e6250_stats_get_strings,
3838         .stats_get_stats = mv88e6250_stats_get_stats,
3839         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3840         .set_egress_port = mv88e6095_g1_set_egress_port,
3841         .watchdog_ops = &mv88e6250_watchdog_ops,
3842         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3843         .pot_clear = mv88e6xxx_g2_pot_clear,
3844         .reset = mv88e6250_g1_reset,
3845         .vtu_getnext = mv88e6250_g1_vtu_getnext,
3846         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
3847         .avb_ops = &mv88e6352_avb_ops,
3848         .ptp_ops = &mv88e6250_ptp_ops,
3849         .phylink_validate = mv88e6065_phylink_validate,
3850 };
3851
3852 static const struct mv88e6xxx_ops mv88e6290_ops = {
3853         /* MV88E6XXX_FAMILY_6390 */
3854         .setup_errata = mv88e6390_setup_errata,
3855         .irl_init_all = mv88e6390_g2_irl_init_all,
3856         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3857         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3858         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3859         .phy_read = mv88e6xxx_g2_smi_phy_read,
3860         .phy_write = mv88e6xxx_g2_smi_phy_write,
3861         .port_set_link = mv88e6xxx_port_set_link,
3862         .port_set_duplex = mv88e6xxx_port_set_duplex,
3863         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3864         .port_set_speed = mv88e6390_port_set_speed,
3865         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3866         .port_tag_remap = mv88e6390_port_tag_remap,
3867         .port_set_policy = mv88e6352_port_set_policy,
3868         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3869         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3870         .port_set_ether_type = mv88e6351_port_set_ether_type,
3871         .port_pause_limit = mv88e6390_port_pause_limit,
3872         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3873         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3874         .port_link_state = mv88e6352_port_link_state,
3875         .port_get_cmode = mv88e6352_port_get_cmode,
3876         .port_set_cmode = mv88e6390_port_set_cmode,
3877         .port_setup_message_port = mv88e6xxx_setup_message_port,
3878         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3879         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3880         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3881         .stats_get_strings = mv88e6320_stats_get_strings,
3882         .stats_get_stats = mv88e6390_stats_get_stats,
3883         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3884         .set_egress_port = mv88e6390_g1_set_egress_port,
3885         .watchdog_ops = &mv88e6390_watchdog_ops,
3886         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3887         .pot_clear = mv88e6xxx_g2_pot_clear,
3888         .reset = mv88e6352_g1_reset,
3889         .rmu_disable = mv88e6390_g1_rmu_disable,
3890         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3891         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3892         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3893         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3894         .serdes_power = mv88e6390_serdes_power,
3895         .serdes_get_lane = mv88e6390_serdes_get_lane,
3896         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3897         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3898         .serdes_irq_status = mv88e6390_serdes_irq_status,
3899         .gpio_ops = &mv88e6352_gpio_ops,
3900         .avb_ops = &mv88e6390_avb_ops,
3901         .ptp_ops = &mv88e6352_ptp_ops,
3902         .phylink_validate = mv88e6390_phylink_validate,
3903 };
3904
3905 static const struct mv88e6xxx_ops mv88e6320_ops = {
3906         /* MV88E6XXX_FAMILY_6320 */
3907         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3908         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3909         .irl_init_all = mv88e6352_g2_irl_init_all,
3910         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3911         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3912         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3913         .phy_read = mv88e6xxx_g2_smi_phy_read,
3914         .phy_write = mv88e6xxx_g2_smi_phy_write,
3915         .port_set_link = mv88e6xxx_port_set_link,
3916         .port_set_duplex = mv88e6xxx_port_set_duplex,
3917         .port_set_speed = mv88e6185_port_set_speed,
3918         .port_tag_remap = mv88e6095_port_tag_remap,
3919         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3920         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3921         .port_set_ether_type = mv88e6351_port_set_ether_type,
3922         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3923         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3924         .port_pause_limit = mv88e6097_port_pause_limit,
3925         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3926         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3927         .port_link_state = mv88e6352_port_link_state,
3928         .port_get_cmode = mv88e6352_port_get_cmode,
3929         .port_setup_message_port = mv88e6xxx_setup_message_port,
3930         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3931         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3932         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3933         .stats_get_strings = mv88e6320_stats_get_strings,
3934         .stats_get_stats = mv88e6320_stats_get_stats,
3935         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3936         .set_egress_port = mv88e6095_g1_set_egress_port,
3937         .watchdog_ops = &mv88e6390_watchdog_ops,
3938         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3939         .pot_clear = mv88e6xxx_g2_pot_clear,
3940         .reset = mv88e6352_g1_reset,
3941         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3942         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3943         .gpio_ops = &mv88e6352_gpio_ops,
3944         .avb_ops = &mv88e6352_avb_ops,
3945         .ptp_ops = &mv88e6352_ptp_ops,
3946         .phylink_validate = mv88e6185_phylink_validate,
3947 };
3948
3949 static const struct mv88e6xxx_ops mv88e6321_ops = {
3950         /* MV88E6XXX_FAMILY_6320 */
3951         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3952         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3953         .irl_init_all = mv88e6352_g2_irl_init_all,
3954         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3955         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3956         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3957         .phy_read = mv88e6xxx_g2_smi_phy_read,
3958         .phy_write = mv88e6xxx_g2_smi_phy_write,
3959         .port_set_link = mv88e6xxx_port_set_link,
3960         .port_set_duplex = mv88e6xxx_port_set_duplex,
3961         .port_set_speed = mv88e6185_port_set_speed,
3962         .port_tag_remap = mv88e6095_port_tag_remap,
3963         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3964         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3965         .port_set_ether_type = mv88e6351_port_set_ether_type,
3966         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3967         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3968         .port_pause_limit = mv88e6097_port_pause_limit,
3969         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3970         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3971         .port_link_state = mv88e6352_port_link_state,
3972         .port_get_cmode = mv88e6352_port_get_cmode,
3973         .port_setup_message_port = mv88e6xxx_setup_message_port,
3974         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3975         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3976         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3977         .stats_get_strings = mv88e6320_stats_get_strings,
3978         .stats_get_stats = mv88e6320_stats_get_stats,
3979         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3980         .set_egress_port = mv88e6095_g1_set_egress_port,
3981         .watchdog_ops = &mv88e6390_watchdog_ops,
3982         .reset = mv88e6352_g1_reset,
3983         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3984         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3985         .gpio_ops = &mv88e6352_gpio_ops,
3986         .avb_ops = &mv88e6352_avb_ops,
3987         .ptp_ops = &mv88e6352_ptp_ops,
3988         .phylink_validate = mv88e6185_phylink_validate,
3989 };
3990
3991 static const struct mv88e6xxx_ops mv88e6341_ops = {
3992         /* MV88E6XXX_FAMILY_6341 */
3993         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3994         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3995         .irl_init_all = mv88e6352_g2_irl_init_all,
3996         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3997         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3998         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3999         .phy_read = mv88e6xxx_g2_smi_phy_read,
4000         .phy_write = mv88e6xxx_g2_smi_phy_write,
4001         .port_set_link = mv88e6xxx_port_set_link,
4002         .port_set_duplex = mv88e6xxx_port_set_duplex,
4003         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4004         .port_set_speed = mv88e6341_port_set_speed,
4005         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4006         .port_tag_remap = mv88e6095_port_tag_remap,
4007         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4008         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4009         .port_set_ether_type = mv88e6351_port_set_ether_type,
4010         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4011         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4012         .port_pause_limit = mv88e6097_port_pause_limit,
4013         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4014         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4015         .port_link_state = mv88e6352_port_link_state,
4016         .port_get_cmode = mv88e6352_port_get_cmode,
4017         .port_set_cmode = mv88e6341_port_set_cmode,
4018         .port_setup_message_port = mv88e6xxx_setup_message_port,
4019         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4020         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4021         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4022         .stats_get_strings = mv88e6320_stats_get_strings,
4023         .stats_get_stats = mv88e6390_stats_get_stats,
4024         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4025         .set_egress_port = mv88e6390_g1_set_egress_port,
4026         .watchdog_ops = &mv88e6390_watchdog_ops,
4027         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4028         .pot_clear = mv88e6xxx_g2_pot_clear,
4029         .reset = mv88e6352_g1_reset,
4030         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4031         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4032         .serdes_power = mv88e6390_serdes_power,
4033         .serdes_get_lane = mv88e6341_serdes_get_lane,
4034         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4035         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4036         .serdes_irq_status = mv88e6390_serdes_irq_status,
4037         .gpio_ops = &mv88e6352_gpio_ops,
4038         .avb_ops = &mv88e6390_avb_ops,
4039         .ptp_ops = &mv88e6352_ptp_ops,
4040         .phylink_validate = mv88e6341_phylink_validate,
4041 };
4042
4043 static const struct mv88e6xxx_ops mv88e6350_ops = {
4044         /* MV88E6XXX_FAMILY_6351 */
4045         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4046         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4047         .irl_init_all = mv88e6352_g2_irl_init_all,
4048         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4049         .phy_read = mv88e6xxx_g2_smi_phy_read,
4050         .phy_write = mv88e6xxx_g2_smi_phy_write,
4051         .port_set_link = mv88e6xxx_port_set_link,
4052         .port_set_duplex = mv88e6xxx_port_set_duplex,
4053         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4054         .port_set_speed = mv88e6185_port_set_speed,
4055         .port_tag_remap = mv88e6095_port_tag_remap,
4056         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4057         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4058         .port_set_ether_type = mv88e6351_port_set_ether_type,
4059         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4060         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4061         .port_pause_limit = mv88e6097_port_pause_limit,
4062         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4063         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4064         .port_link_state = mv88e6352_port_link_state,
4065         .port_get_cmode = mv88e6352_port_get_cmode,
4066         .port_setup_message_port = mv88e6xxx_setup_message_port,
4067         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4068         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4069         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4070         .stats_get_strings = mv88e6095_stats_get_strings,
4071         .stats_get_stats = mv88e6095_stats_get_stats,
4072         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4073         .set_egress_port = mv88e6095_g1_set_egress_port,
4074         .watchdog_ops = &mv88e6097_watchdog_ops,
4075         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4076         .pot_clear = mv88e6xxx_g2_pot_clear,
4077         .reset = mv88e6352_g1_reset,
4078         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4079         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4080         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4081         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4082         .phylink_validate = mv88e6185_phylink_validate,
4083 };
4084
4085 static const struct mv88e6xxx_ops mv88e6351_ops = {
4086         /* MV88E6XXX_FAMILY_6351 */
4087         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4088         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4089         .irl_init_all = mv88e6352_g2_irl_init_all,
4090         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4091         .phy_read = mv88e6xxx_g2_smi_phy_read,
4092         .phy_write = mv88e6xxx_g2_smi_phy_write,
4093         .port_set_link = mv88e6xxx_port_set_link,
4094         .port_set_duplex = mv88e6xxx_port_set_duplex,
4095         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4096         .port_set_speed = mv88e6185_port_set_speed,
4097         .port_tag_remap = mv88e6095_port_tag_remap,
4098         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4099         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4100         .port_set_ether_type = mv88e6351_port_set_ether_type,
4101         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4102         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4103         .port_pause_limit = mv88e6097_port_pause_limit,
4104         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4105         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4106         .port_link_state = mv88e6352_port_link_state,
4107         .port_get_cmode = mv88e6352_port_get_cmode,
4108         .port_setup_message_port = mv88e6xxx_setup_message_port,
4109         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4110         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4111         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4112         .stats_get_strings = mv88e6095_stats_get_strings,
4113         .stats_get_stats = mv88e6095_stats_get_stats,
4114         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4115         .set_egress_port = mv88e6095_g1_set_egress_port,
4116         .watchdog_ops = &mv88e6097_watchdog_ops,
4117         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4118         .pot_clear = mv88e6xxx_g2_pot_clear,
4119         .reset = mv88e6352_g1_reset,
4120         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4121         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4122         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4123         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4124         .avb_ops = &mv88e6352_avb_ops,
4125         .ptp_ops = &mv88e6352_ptp_ops,
4126         .phylink_validate = mv88e6185_phylink_validate,
4127 };
4128
4129 static const struct mv88e6xxx_ops mv88e6352_ops = {
4130         /* MV88E6XXX_FAMILY_6352 */
4131         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4132         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4133         .irl_init_all = mv88e6352_g2_irl_init_all,
4134         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4135         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4136         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4137         .phy_read = mv88e6xxx_g2_smi_phy_read,
4138         .phy_write = mv88e6xxx_g2_smi_phy_write,
4139         .port_set_link = mv88e6xxx_port_set_link,
4140         .port_set_duplex = mv88e6xxx_port_set_duplex,
4141         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4142         .port_set_speed = mv88e6352_port_set_speed,
4143         .port_tag_remap = mv88e6095_port_tag_remap,
4144         .port_set_policy = mv88e6352_port_set_policy,
4145         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4146         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4147         .port_set_ether_type = mv88e6351_port_set_ether_type,
4148         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4149         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4150         .port_pause_limit = mv88e6097_port_pause_limit,
4151         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4152         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4153         .port_link_state = mv88e6352_port_link_state,
4154         .port_get_cmode = mv88e6352_port_get_cmode,
4155         .port_setup_message_port = mv88e6xxx_setup_message_port,
4156         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4157         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4158         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4159         .stats_get_strings = mv88e6095_stats_get_strings,
4160         .stats_get_stats = mv88e6095_stats_get_stats,
4161         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4162         .set_egress_port = mv88e6095_g1_set_egress_port,
4163         .watchdog_ops = &mv88e6097_watchdog_ops,
4164         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4165         .pot_clear = mv88e6xxx_g2_pot_clear,
4166         .reset = mv88e6352_g1_reset,
4167         .rmu_disable = mv88e6352_g1_rmu_disable,
4168         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4169         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4170         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4171         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4172         .serdes_get_lane = mv88e6352_serdes_get_lane,
4173         .serdes_power = mv88e6352_serdes_power,
4174         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4175         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4176         .serdes_irq_status = mv88e6352_serdes_irq_status,
4177         .gpio_ops = &mv88e6352_gpio_ops,
4178         .avb_ops = &mv88e6352_avb_ops,
4179         .ptp_ops = &mv88e6352_ptp_ops,
4180         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4181         .serdes_get_strings = mv88e6352_serdes_get_strings,
4182         .serdes_get_stats = mv88e6352_serdes_get_stats,
4183         .phylink_validate = mv88e6352_phylink_validate,
4184 };
4185
4186 static const struct mv88e6xxx_ops mv88e6390_ops = {
4187         /* MV88E6XXX_FAMILY_6390 */
4188         .setup_errata = mv88e6390_setup_errata,
4189         .irl_init_all = mv88e6390_g2_irl_init_all,
4190         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4191         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4192         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4193         .phy_read = mv88e6xxx_g2_smi_phy_read,
4194         .phy_write = mv88e6xxx_g2_smi_phy_write,
4195         .port_set_link = mv88e6xxx_port_set_link,
4196         .port_set_duplex = mv88e6xxx_port_set_duplex,
4197         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4198         .port_set_speed = mv88e6390_port_set_speed,
4199         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4200         .port_tag_remap = mv88e6390_port_tag_remap,
4201         .port_set_policy = mv88e6352_port_set_policy,
4202         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4203         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4204         .port_set_ether_type = mv88e6351_port_set_ether_type,
4205         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4206         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4207         .port_pause_limit = mv88e6390_port_pause_limit,
4208         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4209         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4210         .port_link_state = mv88e6352_port_link_state,
4211         .port_get_cmode = mv88e6352_port_get_cmode,
4212         .port_set_cmode = mv88e6390_port_set_cmode,
4213         .port_setup_message_port = mv88e6xxx_setup_message_port,
4214         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4215         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4216         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4217         .stats_get_strings = mv88e6320_stats_get_strings,
4218         .stats_get_stats = mv88e6390_stats_get_stats,
4219         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4220         .set_egress_port = mv88e6390_g1_set_egress_port,
4221         .watchdog_ops = &mv88e6390_watchdog_ops,
4222         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4223         .pot_clear = mv88e6xxx_g2_pot_clear,
4224         .reset = mv88e6352_g1_reset,
4225         .rmu_disable = mv88e6390_g1_rmu_disable,
4226         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4227         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4228         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4229         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4230         .serdes_power = mv88e6390_serdes_power,
4231         .serdes_get_lane = mv88e6390_serdes_get_lane,
4232         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4233         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4234         .serdes_irq_status = mv88e6390_serdes_irq_status,
4235         .gpio_ops = &mv88e6352_gpio_ops,
4236         .avb_ops = &mv88e6390_avb_ops,
4237         .ptp_ops = &mv88e6352_ptp_ops,
4238         .phylink_validate = mv88e6390_phylink_validate,
4239 };
4240
4241 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4242         /* MV88E6XXX_FAMILY_6390 */
4243         .setup_errata = mv88e6390_setup_errata,
4244         .irl_init_all = mv88e6390_g2_irl_init_all,
4245         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4246         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4247         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4248         .phy_read = mv88e6xxx_g2_smi_phy_read,
4249         .phy_write = mv88e6xxx_g2_smi_phy_write,
4250         .port_set_link = mv88e6xxx_port_set_link,
4251         .port_set_duplex = mv88e6xxx_port_set_duplex,
4252         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4253         .port_set_speed = mv88e6390x_port_set_speed,
4254         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4255         .port_tag_remap = mv88e6390_port_tag_remap,
4256         .port_set_policy = mv88e6352_port_set_policy,
4257         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4258         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4259         .port_set_ether_type = mv88e6351_port_set_ether_type,
4260         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4261         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4262         .port_pause_limit = mv88e6390_port_pause_limit,
4263         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4264         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4265         .port_link_state = mv88e6352_port_link_state,
4266         .port_get_cmode = mv88e6352_port_get_cmode,
4267         .port_set_cmode = mv88e6390x_port_set_cmode,
4268         .port_setup_message_port = mv88e6xxx_setup_message_port,
4269         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4270         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4271         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4272         .stats_get_strings = mv88e6320_stats_get_strings,
4273         .stats_get_stats = mv88e6390_stats_get_stats,
4274         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4275         .set_egress_port = mv88e6390_g1_set_egress_port,
4276         .watchdog_ops = &mv88e6390_watchdog_ops,
4277         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4278         .pot_clear = mv88e6xxx_g2_pot_clear,
4279         .reset = mv88e6352_g1_reset,
4280         .rmu_disable = mv88e6390_g1_rmu_disable,
4281         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4282         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4283         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4284         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4285         .serdes_power = mv88e6390_serdes_power,
4286         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4287         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4288         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4289         .serdes_irq_status = mv88e6390_serdes_irq_status,
4290         .gpio_ops = &mv88e6352_gpio_ops,
4291         .avb_ops = &mv88e6390_avb_ops,
4292         .ptp_ops = &mv88e6352_ptp_ops,
4293         .phylink_validate = mv88e6390x_phylink_validate,
4294 };
4295
4296 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4297         [MV88E6085] = {
4298                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4299                 .family = MV88E6XXX_FAMILY_6097,
4300                 .name = "Marvell 88E6085",
4301                 .num_databases = 4096,
4302                 .num_ports = 10,
4303                 .num_internal_phys = 5,
4304                 .max_vid = 4095,
4305                 .port_base_addr = 0x10,
4306                 .phy_base_addr = 0x0,
4307                 .global1_addr = 0x1b,
4308                 .global2_addr = 0x1c,
4309                 .age_time_coeff = 15000,
4310                 .g1_irqs = 8,
4311                 .g2_irqs = 10,
4312                 .atu_move_port_mask = 0xf,
4313                 .pvt = true,
4314                 .multi_chip = true,
4315                 .tag_protocol = DSA_TAG_PROTO_DSA,
4316                 .ops = &mv88e6085_ops,
4317         },
4318
4319         [MV88E6095] = {
4320                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4321                 .family = MV88E6XXX_FAMILY_6095,
4322                 .name = "Marvell 88E6095/88E6095F",
4323                 .num_databases = 256,
4324                 .num_ports = 11,
4325                 .num_internal_phys = 0,
4326                 .max_vid = 4095,
4327                 .port_base_addr = 0x10,
4328                 .phy_base_addr = 0x0,
4329                 .global1_addr = 0x1b,
4330                 .global2_addr = 0x1c,
4331                 .age_time_coeff = 15000,
4332                 .g1_irqs = 8,
4333                 .atu_move_port_mask = 0xf,
4334                 .multi_chip = true,
4335                 .tag_protocol = DSA_TAG_PROTO_DSA,
4336                 .ops = &mv88e6095_ops,
4337         },
4338
4339         [MV88E6097] = {
4340                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4341                 .family = MV88E6XXX_FAMILY_6097,
4342                 .name = "Marvell 88E6097/88E6097F",
4343                 .num_databases = 4096,
4344                 .num_ports = 11,
4345                 .num_internal_phys = 8,
4346                 .max_vid = 4095,
4347                 .port_base_addr = 0x10,
4348                 .phy_base_addr = 0x0,
4349                 .global1_addr = 0x1b,
4350                 .global2_addr = 0x1c,
4351                 .age_time_coeff = 15000,
4352                 .g1_irqs = 8,
4353                 .g2_irqs = 10,
4354                 .atu_move_port_mask = 0xf,
4355                 .pvt = true,
4356                 .multi_chip = true,
4357                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4358                 .ops = &mv88e6097_ops,
4359         },
4360
4361         [MV88E6123] = {
4362                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4363                 .family = MV88E6XXX_FAMILY_6165,
4364                 .name = "Marvell 88E6123",
4365                 .num_databases = 4096,
4366                 .num_ports = 3,
4367                 .num_internal_phys = 5,
4368                 .max_vid = 4095,
4369                 .port_base_addr = 0x10,
4370                 .phy_base_addr = 0x0,
4371                 .global1_addr = 0x1b,
4372                 .global2_addr = 0x1c,
4373                 .age_time_coeff = 15000,
4374                 .g1_irqs = 9,
4375                 .g2_irqs = 10,
4376                 .atu_move_port_mask = 0xf,
4377                 .pvt = true,
4378                 .multi_chip = true,
4379                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4380                 .ops = &mv88e6123_ops,
4381         },
4382
4383         [MV88E6131] = {
4384                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4385                 .family = MV88E6XXX_FAMILY_6185,
4386                 .name = "Marvell 88E6131",
4387                 .num_databases = 256,
4388                 .num_ports = 8,
4389                 .num_internal_phys = 0,
4390                 .max_vid = 4095,
4391                 .port_base_addr = 0x10,
4392                 .phy_base_addr = 0x0,
4393                 .global1_addr = 0x1b,
4394                 .global2_addr = 0x1c,
4395                 .age_time_coeff = 15000,
4396                 .g1_irqs = 9,
4397                 .atu_move_port_mask = 0xf,
4398                 .multi_chip = true,
4399                 .tag_protocol = DSA_TAG_PROTO_DSA,
4400                 .ops = &mv88e6131_ops,
4401         },
4402
4403         [MV88E6141] = {
4404                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4405                 .family = MV88E6XXX_FAMILY_6341,
4406                 .name = "Marvell 88E6141",
4407                 .num_databases = 4096,
4408                 .num_ports = 6,
4409                 .num_internal_phys = 5,
4410                 .num_gpio = 11,
4411                 .max_vid = 4095,
4412                 .port_base_addr = 0x10,
4413                 .phy_base_addr = 0x10,
4414                 .global1_addr = 0x1b,
4415                 .global2_addr = 0x1c,
4416                 .age_time_coeff = 3750,
4417                 .atu_move_port_mask = 0x1f,
4418                 .g1_irqs = 9,
4419                 .g2_irqs = 10,
4420                 .pvt = true,
4421                 .multi_chip = true,
4422                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4423                 .ops = &mv88e6141_ops,
4424         },
4425
4426         [MV88E6161] = {
4427                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4428                 .family = MV88E6XXX_FAMILY_6165,
4429                 .name = "Marvell 88E6161",
4430                 .num_databases = 4096,
4431                 .num_ports = 6,
4432                 .num_internal_phys = 5,
4433                 .max_vid = 4095,
4434                 .port_base_addr = 0x10,
4435                 .phy_base_addr = 0x0,
4436                 .global1_addr = 0x1b,
4437                 .global2_addr = 0x1c,
4438                 .age_time_coeff = 15000,
4439                 .g1_irqs = 9,
4440                 .g2_irqs = 10,
4441                 .atu_move_port_mask = 0xf,
4442                 .pvt = true,
4443                 .multi_chip = true,
4444                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4445                 .ptp_support = true,
4446                 .ops = &mv88e6161_ops,
4447         },
4448
4449         [MV88E6165] = {
4450                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4451                 .family = MV88E6XXX_FAMILY_6165,
4452                 .name = "Marvell 88E6165",
4453                 .num_databases = 4096,
4454                 .num_ports = 6,
4455                 .num_internal_phys = 0,
4456                 .max_vid = 4095,
4457                 .port_base_addr = 0x10,
4458                 .phy_base_addr = 0x0,
4459                 .global1_addr = 0x1b,
4460                 .global2_addr = 0x1c,
4461                 .age_time_coeff = 15000,
4462                 .g1_irqs = 9,
4463                 .g2_irqs = 10,
4464                 .atu_move_port_mask = 0xf,
4465                 .pvt = true,
4466                 .multi_chip = true,
4467                 .tag_protocol = DSA_TAG_PROTO_DSA,
4468                 .ptp_support = true,
4469                 .ops = &mv88e6165_ops,
4470         },
4471
4472         [MV88E6171] = {
4473                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4474                 .family = MV88E6XXX_FAMILY_6351,
4475                 .name = "Marvell 88E6171",
4476                 .num_databases = 4096,
4477                 .num_ports = 7,
4478                 .num_internal_phys = 5,
4479                 .max_vid = 4095,
4480                 .port_base_addr = 0x10,
4481                 .phy_base_addr = 0x0,
4482                 .global1_addr = 0x1b,
4483                 .global2_addr = 0x1c,
4484                 .age_time_coeff = 15000,
4485                 .g1_irqs = 9,
4486                 .g2_irqs = 10,
4487                 .atu_move_port_mask = 0xf,
4488                 .pvt = true,
4489                 .multi_chip = true,
4490                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4491                 .ops = &mv88e6171_ops,
4492         },
4493
4494         [MV88E6172] = {
4495                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4496                 .family = MV88E6XXX_FAMILY_6352,
4497                 .name = "Marvell 88E6172",
4498                 .num_databases = 4096,
4499                 .num_ports = 7,
4500                 .num_internal_phys = 5,
4501                 .num_gpio = 15,
4502                 .max_vid = 4095,
4503                 .port_base_addr = 0x10,
4504                 .phy_base_addr = 0x0,
4505                 .global1_addr = 0x1b,
4506                 .global2_addr = 0x1c,
4507                 .age_time_coeff = 15000,
4508                 .g1_irqs = 9,
4509                 .g2_irqs = 10,
4510                 .atu_move_port_mask = 0xf,
4511                 .pvt = true,
4512                 .multi_chip = true,
4513                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4514                 .ops = &mv88e6172_ops,
4515         },
4516
4517         [MV88E6175] = {
4518                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4519                 .family = MV88E6XXX_FAMILY_6351,
4520                 .name = "Marvell 88E6175",
4521                 .num_databases = 4096,
4522                 .num_ports = 7,
4523                 .num_internal_phys = 5,
4524                 .max_vid = 4095,
4525                 .port_base_addr = 0x10,
4526                 .phy_base_addr = 0x0,
4527                 .global1_addr = 0x1b,
4528                 .global2_addr = 0x1c,
4529                 .age_time_coeff = 15000,
4530                 .g1_irqs = 9,
4531                 .g2_irqs = 10,
4532                 .atu_move_port_mask = 0xf,
4533                 .pvt = true,
4534                 .multi_chip = true,
4535                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4536                 .ops = &mv88e6175_ops,
4537         },
4538
4539         [MV88E6176] = {
4540                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4541                 .family = MV88E6XXX_FAMILY_6352,
4542                 .name = "Marvell 88E6176",
4543                 .num_databases = 4096,
4544                 .num_ports = 7,
4545                 .num_internal_phys = 5,
4546                 .num_gpio = 15,
4547                 .max_vid = 4095,
4548                 .port_base_addr = 0x10,
4549                 .phy_base_addr = 0x0,
4550                 .global1_addr = 0x1b,
4551                 .global2_addr = 0x1c,
4552                 .age_time_coeff = 15000,
4553                 .g1_irqs = 9,
4554                 .g2_irqs = 10,
4555                 .atu_move_port_mask = 0xf,
4556                 .pvt = true,
4557                 .multi_chip = true,
4558                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4559                 .ops = &mv88e6176_ops,
4560         },
4561
4562         [MV88E6185] = {
4563                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4564                 .family = MV88E6XXX_FAMILY_6185,
4565                 .name = "Marvell 88E6185",
4566                 .num_databases = 256,
4567                 .num_ports = 10,
4568                 .num_internal_phys = 0,
4569                 .max_vid = 4095,
4570                 .port_base_addr = 0x10,
4571                 .phy_base_addr = 0x0,
4572                 .global1_addr = 0x1b,
4573                 .global2_addr = 0x1c,
4574                 .age_time_coeff = 15000,
4575                 .g1_irqs = 8,
4576                 .atu_move_port_mask = 0xf,
4577                 .multi_chip = true,
4578                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4579                 .ops = &mv88e6185_ops,
4580         },
4581
4582         [MV88E6190] = {
4583                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4584                 .family = MV88E6XXX_FAMILY_6390,
4585                 .name = "Marvell 88E6190",
4586                 .num_databases = 4096,
4587                 .num_ports = 11,        /* 10 + Z80 */
4588                 .num_internal_phys = 9,
4589                 .num_gpio = 16,
4590                 .max_vid = 8191,
4591                 .port_base_addr = 0x0,
4592                 .phy_base_addr = 0x0,
4593                 .global1_addr = 0x1b,
4594                 .global2_addr = 0x1c,
4595                 .tag_protocol = DSA_TAG_PROTO_DSA,
4596                 .age_time_coeff = 3750,
4597                 .g1_irqs = 9,
4598                 .g2_irqs = 14,
4599                 .pvt = true,
4600                 .multi_chip = true,
4601                 .atu_move_port_mask = 0x1f,
4602                 .ops = &mv88e6190_ops,
4603         },
4604
4605         [MV88E6190X] = {
4606                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4607                 .family = MV88E6XXX_FAMILY_6390,
4608                 .name = "Marvell 88E6190X",
4609                 .num_databases = 4096,
4610                 .num_ports = 11,        /* 10 + Z80 */
4611                 .num_internal_phys = 9,
4612                 .num_gpio = 16,
4613                 .max_vid = 8191,
4614                 .port_base_addr = 0x0,
4615                 .phy_base_addr = 0x0,
4616                 .global1_addr = 0x1b,
4617                 .global2_addr = 0x1c,
4618                 .age_time_coeff = 3750,
4619                 .g1_irqs = 9,
4620                 .g2_irqs = 14,
4621                 .atu_move_port_mask = 0x1f,
4622                 .pvt = true,
4623                 .multi_chip = true,
4624                 .tag_protocol = DSA_TAG_PROTO_DSA,
4625                 .ops = &mv88e6190x_ops,
4626         },
4627
4628         [MV88E6191] = {
4629                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4630                 .family = MV88E6XXX_FAMILY_6390,
4631                 .name = "Marvell 88E6191",
4632                 .num_databases = 4096,
4633                 .num_ports = 11,        /* 10 + Z80 */
4634                 .num_internal_phys = 9,
4635                 .max_vid = 8191,
4636                 .port_base_addr = 0x0,
4637                 .phy_base_addr = 0x0,
4638                 .global1_addr = 0x1b,
4639                 .global2_addr = 0x1c,
4640                 .age_time_coeff = 3750,
4641                 .g1_irqs = 9,
4642                 .g2_irqs = 14,
4643                 .atu_move_port_mask = 0x1f,
4644                 .pvt = true,
4645                 .multi_chip = true,
4646                 .tag_protocol = DSA_TAG_PROTO_DSA,
4647                 .ptp_support = true,
4648                 .ops = &mv88e6191_ops,
4649         },
4650
4651         [MV88E6220] = {
4652                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4653                 .family = MV88E6XXX_FAMILY_6250,
4654                 .name = "Marvell 88E6220",
4655                 .num_databases = 64,
4656
4657                 /* Ports 2-4 are not routed to pins
4658                  * => usable ports 0, 1, 5, 6
4659                  */
4660                 .num_ports = 7,
4661                 .num_internal_phys = 2,
4662                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4663                 .max_vid = 4095,
4664                 .port_base_addr = 0x08,
4665                 .phy_base_addr = 0x00,
4666                 .global1_addr = 0x0f,
4667                 .global2_addr = 0x07,
4668                 .age_time_coeff = 15000,
4669                 .g1_irqs = 9,
4670                 .g2_irqs = 10,
4671                 .atu_move_port_mask = 0xf,
4672                 .dual_chip = true,
4673                 .tag_protocol = DSA_TAG_PROTO_DSA,
4674                 .ptp_support = true,
4675                 .ops = &mv88e6250_ops,
4676         },
4677
4678         [MV88E6240] = {
4679                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4680                 .family = MV88E6XXX_FAMILY_6352,
4681                 .name = "Marvell 88E6240",
4682                 .num_databases = 4096,
4683                 .num_ports = 7,
4684                 .num_internal_phys = 5,
4685                 .num_gpio = 15,
4686                 .max_vid = 4095,
4687                 .port_base_addr = 0x10,
4688                 .phy_base_addr = 0x0,
4689                 .global1_addr = 0x1b,
4690                 .global2_addr = 0x1c,
4691                 .age_time_coeff = 15000,
4692                 .g1_irqs = 9,
4693                 .g2_irqs = 10,
4694                 .atu_move_port_mask = 0xf,
4695                 .pvt = true,
4696                 .multi_chip = true,
4697                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4698                 .ptp_support = true,
4699                 .ops = &mv88e6240_ops,
4700         },
4701
4702         [MV88E6250] = {
4703                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4704                 .family = MV88E6XXX_FAMILY_6250,
4705                 .name = "Marvell 88E6250",
4706                 .num_databases = 64,
4707                 .num_ports = 7,
4708                 .num_internal_phys = 5,
4709                 .max_vid = 4095,
4710                 .port_base_addr = 0x08,
4711                 .phy_base_addr = 0x00,
4712                 .global1_addr = 0x0f,
4713                 .global2_addr = 0x07,
4714                 .age_time_coeff = 15000,
4715                 .g1_irqs = 9,
4716                 .g2_irqs = 10,
4717                 .atu_move_port_mask = 0xf,
4718                 .dual_chip = true,
4719                 .tag_protocol = DSA_TAG_PROTO_DSA,
4720                 .ptp_support = true,
4721                 .ops = &mv88e6250_ops,
4722         },
4723
4724         [MV88E6290] = {
4725                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4726                 .family = MV88E6XXX_FAMILY_6390,
4727                 .name = "Marvell 88E6290",
4728                 .num_databases = 4096,
4729                 .num_ports = 11,        /* 10 + Z80 */
4730                 .num_internal_phys = 9,
4731                 .num_gpio = 16,
4732                 .max_vid = 8191,
4733                 .port_base_addr = 0x0,
4734                 .phy_base_addr = 0x0,
4735                 .global1_addr = 0x1b,
4736                 .global2_addr = 0x1c,
4737                 .age_time_coeff = 3750,
4738                 .g1_irqs = 9,
4739                 .g2_irqs = 14,
4740                 .atu_move_port_mask = 0x1f,
4741                 .pvt = true,
4742                 .multi_chip = true,
4743                 .tag_protocol = DSA_TAG_PROTO_DSA,
4744                 .ptp_support = true,
4745                 .ops = &mv88e6290_ops,
4746         },
4747
4748         [MV88E6320] = {
4749                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4750                 .family = MV88E6XXX_FAMILY_6320,
4751                 .name = "Marvell 88E6320",
4752                 .num_databases = 4096,
4753                 .num_ports = 7,
4754                 .num_internal_phys = 5,
4755                 .num_gpio = 15,
4756                 .max_vid = 4095,
4757                 .port_base_addr = 0x10,
4758                 .phy_base_addr = 0x0,
4759                 .global1_addr = 0x1b,
4760                 .global2_addr = 0x1c,
4761                 .age_time_coeff = 15000,
4762                 .g1_irqs = 8,
4763                 .g2_irqs = 10,
4764                 .atu_move_port_mask = 0xf,
4765                 .pvt = true,
4766                 .multi_chip = true,
4767                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4768                 .ptp_support = true,
4769                 .ops = &mv88e6320_ops,
4770         },
4771
4772         [MV88E6321] = {
4773                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4774                 .family = MV88E6XXX_FAMILY_6320,
4775                 .name = "Marvell 88E6321",
4776                 .num_databases = 4096,
4777                 .num_ports = 7,
4778                 .num_internal_phys = 5,
4779                 .num_gpio = 15,
4780                 .max_vid = 4095,
4781                 .port_base_addr = 0x10,
4782                 .phy_base_addr = 0x0,
4783                 .global1_addr = 0x1b,
4784                 .global2_addr = 0x1c,
4785                 .age_time_coeff = 15000,
4786                 .g1_irqs = 8,
4787                 .g2_irqs = 10,
4788                 .atu_move_port_mask = 0xf,
4789                 .multi_chip = true,
4790                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4791                 .ptp_support = true,
4792                 .ops = &mv88e6321_ops,
4793         },
4794
4795         [MV88E6341] = {
4796                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4797                 .family = MV88E6XXX_FAMILY_6341,
4798                 .name = "Marvell 88E6341",
4799                 .num_databases = 4096,
4800                 .num_internal_phys = 5,
4801                 .num_ports = 6,
4802                 .num_gpio = 11,
4803                 .max_vid = 4095,
4804                 .port_base_addr = 0x10,
4805                 .phy_base_addr = 0x10,
4806                 .global1_addr = 0x1b,
4807                 .global2_addr = 0x1c,
4808                 .age_time_coeff = 3750,
4809                 .atu_move_port_mask = 0x1f,
4810                 .g1_irqs = 9,
4811                 .g2_irqs = 10,
4812                 .pvt = true,
4813                 .multi_chip = true,
4814                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4815                 .ptp_support = true,
4816                 .ops = &mv88e6341_ops,
4817         },
4818
4819         [MV88E6350] = {
4820                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4821                 .family = MV88E6XXX_FAMILY_6351,
4822                 .name = "Marvell 88E6350",
4823                 .num_databases = 4096,
4824                 .num_ports = 7,
4825                 .num_internal_phys = 5,
4826                 .max_vid = 4095,
4827                 .port_base_addr = 0x10,
4828                 .phy_base_addr = 0x0,
4829                 .global1_addr = 0x1b,
4830                 .global2_addr = 0x1c,
4831                 .age_time_coeff = 15000,
4832                 .g1_irqs = 9,
4833                 .g2_irqs = 10,
4834                 .atu_move_port_mask = 0xf,
4835                 .pvt = true,
4836                 .multi_chip = true,
4837                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4838                 .ops = &mv88e6350_ops,
4839         },
4840
4841         [MV88E6351] = {
4842                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4843                 .family = MV88E6XXX_FAMILY_6351,
4844                 .name = "Marvell 88E6351",
4845                 .num_databases = 4096,
4846                 .num_ports = 7,
4847                 .num_internal_phys = 5,
4848                 .max_vid = 4095,
4849                 .port_base_addr = 0x10,
4850                 .phy_base_addr = 0x0,
4851                 .global1_addr = 0x1b,
4852                 .global2_addr = 0x1c,
4853                 .age_time_coeff = 15000,
4854                 .g1_irqs = 9,
4855                 .g2_irqs = 10,
4856                 .atu_move_port_mask = 0xf,
4857                 .pvt = true,
4858                 .multi_chip = true,
4859                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4860                 .ops = &mv88e6351_ops,
4861         },
4862
4863         [MV88E6352] = {
4864                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4865                 .family = MV88E6XXX_FAMILY_6352,
4866                 .name = "Marvell 88E6352",
4867                 .num_databases = 4096,
4868                 .num_ports = 7,
4869                 .num_internal_phys = 5,
4870                 .num_gpio = 15,
4871                 .max_vid = 4095,
4872                 .port_base_addr = 0x10,
4873                 .phy_base_addr = 0x0,
4874                 .global1_addr = 0x1b,
4875                 .global2_addr = 0x1c,
4876                 .age_time_coeff = 15000,
4877                 .g1_irqs = 9,
4878                 .g2_irqs = 10,
4879                 .atu_move_port_mask = 0xf,
4880                 .pvt = true,
4881                 .multi_chip = true,
4882                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4883                 .ptp_support = true,
4884                 .ops = &mv88e6352_ops,
4885         },
4886         [MV88E6390] = {
4887                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4888                 .family = MV88E6XXX_FAMILY_6390,
4889                 .name = "Marvell 88E6390",
4890                 .num_databases = 4096,
4891                 .num_ports = 11,        /* 10 + Z80 */
4892                 .num_internal_phys = 9,
4893                 .num_gpio = 16,
4894                 .max_vid = 8191,
4895                 .port_base_addr = 0x0,
4896                 .phy_base_addr = 0x0,
4897                 .global1_addr = 0x1b,
4898                 .global2_addr = 0x1c,
4899                 .age_time_coeff = 3750,
4900                 .g1_irqs = 9,
4901                 .g2_irqs = 14,
4902                 .atu_move_port_mask = 0x1f,
4903                 .pvt = true,
4904                 .multi_chip = true,
4905                 .tag_protocol = DSA_TAG_PROTO_DSA,
4906                 .ptp_support = true,
4907                 .ops = &mv88e6390_ops,
4908         },
4909         [MV88E6390X] = {
4910                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4911                 .family = MV88E6XXX_FAMILY_6390,
4912                 .name = "Marvell 88E6390X",
4913                 .num_databases = 4096,
4914                 .num_ports = 11,        /* 10 + Z80 */
4915                 .num_internal_phys = 9,
4916                 .num_gpio = 16,
4917                 .max_vid = 8191,
4918                 .port_base_addr = 0x0,
4919                 .phy_base_addr = 0x0,
4920                 .global1_addr = 0x1b,
4921                 .global2_addr = 0x1c,
4922                 .age_time_coeff = 3750,
4923                 .g1_irqs = 9,
4924                 .g2_irqs = 14,
4925                 .atu_move_port_mask = 0x1f,
4926                 .pvt = true,
4927                 .multi_chip = true,
4928                 .tag_protocol = DSA_TAG_PROTO_DSA,
4929                 .ptp_support = true,
4930                 .ops = &mv88e6390x_ops,
4931         },
4932 };
4933
4934 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4935 {
4936         int i;
4937
4938         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4939                 if (mv88e6xxx_table[i].prod_num == prod_num)
4940                         return &mv88e6xxx_table[i];
4941
4942         return NULL;
4943 }
4944
4945 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4946 {
4947         const struct mv88e6xxx_info *info;
4948         unsigned int prod_num, rev;
4949         u16 id;
4950         int err;
4951
4952         mv88e6xxx_reg_lock(chip);
4953         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4954         mv88e6xxx_reg_unlock(chip);
4955         if (err)
4956                 return err;
4957
4958         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4959         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4960
4961         info = mv88e6xxx_lookup_info(prod_num);
4962         if (!info)
4963                 return -ENODEV;
4964
4965         /* Update the compatible info with the probed one */
4966         chip->info = info;
4967
4968         err = mv88e6xxx_g2_require(chip);
4969         if (err)
4970                 return err;
4971
4972         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4973                  chip->info->prod_num, chip->info->name, rev);
4974
4975         return 0;
4976 }
4977
4978 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4979 {
4980         struct mv88e6xxx_chip *chip;
4981
4982         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4983         if (!chip)
4984                 return NULL;
4985
4986         chip->dev = dev;
4987
4988         mutex_init(&chip->reg_lock);
4989         INIT_LIST_HEAD(&chip->mdios);
4990         idr_init(&chip->policies);
4991
4992         return chip;
4993 }
4994
4995 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4996                                                         int port)
4997 {
4998         struct mv88e6xxx_chip *chip = ds->priv;
4999
5000         return chip->info->tag_protocol;
5001 }
5002
5003 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5004                                       const struct switchdev_obj_port_mdb *mdb)
5005 {
5006         /* We don't need any dynamic resource from the kernel (yet),
5007          * so skip the prepare phase.
5008          */
5009
5010         return 0;
5011 }
5012
5013 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5014                                    const struct switchdev_obj_port_mdb *mdb)
5015 {
5016         struct mv88e6xxx_chip *chip = ds->priv;
5017
5018         mv88e6xxx_reg_lock(chip);
5019         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5020                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5021                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5022                         port);
5023         mv88e6xxx_reg_unlock(chip);
5024 }
5025
5026 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5027                                   const struct switchdev_obj_port_mdb *mdb)
5028 {
5029         struct mv88e6xxx_chip *chip = ds->priv;
5030         int err;
5031
5032         mv88e6xxx_reg_lock(chip);
5033         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5034         mv88e6xxx_reg_unlock(chip);
5035
5036         return err;
5037 }
5038
5039 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5040                                          bool unicast, bool multicast)
5041 {
5042         struct mv88e6xxx_chip *chip = ds->priv;
5043         int err = -EOPNOTSUPP;
5044
5045         mv88e6xxx_reg_lock(chip);
5046         if (chip->info->ops->port_set_egress_floods)
5047                 err = chip->info->ops->port_set_egress_floods(chip, port,
5048                                                               unicast,
5049                                                               multicast);
5050         mv88e6xxx_reg_unlock(chip);
5051
5052         return err;
5053 }
5054
5055 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5056         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
5057         .setup                  = mv88e6xxx_setup,
5058         .teardown               = mv88e6xxx_teardown,
5059         .phylink_validate       = mv88e6xxx_validate,
5060         .phylink_mac_link_state = mv88e6xxx_link_state,
5061         .phylink_mac_config     = mv88e6xxx_mac_config,
5062         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
5063         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
5064         .get_strings            = mv88e6xxx_get_strings,
5065         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
5066         .get_sset_count         = mv88e6xxx_get_sset_count,
5067         .port_enable            = mv88e6xxx_port_enable,
5068         .port_disable           = mv88e6xxx_port_disable,
5069         .get_mac_eee            = mv88e6xxx_get_mac_eee,
5070         .set_mac_eee            = mv88e6xxx_set_mac_eee,
5071         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
5072         .get_eeprom             = mv88e6xxx_get_eeprom,
5073         .set_eeprom             = mv88e6xxx_set_eeprom,
5074         .get_regs_len           = mv88e6xxx_get_regs_len,
5075         .get_regs               = mv88e6xxx_get_regs,
5076         .get_rxnfc              = mv88e6xxx_get_rxnfc,
5077         .set_rxnfc              = mv88e6xxx_set_rxnfc,
5078         .set_ageing_time        = mv88e6xxx_set_ageing_time,
5079         .port_bridge_join       = mv88e6xxx_port_bridge_join,
5080         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
5081         .port_egress_floods     = mv88e6xxx_port_egress_floods,
5082         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
5083         .port_fast_age          = mv88e6xxx_port_fast_age,
5084         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
5085         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
5086         .port_vlan_add          = mv88e6xxx_port_vlan_add,
5087         .port_vlan_del          = mv88e6xxx_port_vlan_del,
5088         .port_fdb_add           = mv88e6xxx_port_fdb_add,
5089         .port_fdb_del           = mv88e6xxx_port_fdb_del,
5090         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5091         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5092         .port_mdb_add           = mv88e6xxx_port_mdb_add,
5093         .port_mdb_del           = mv88e6xxx_port_mdb_del,
5094         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
5095         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5096         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
5097         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
5098         .port_txtstamp          = mv88e6xxx_port_txtstamp,
5099         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
5100         .get_ts_info            = mv88e6xxx_get_ts_info,
5101         .devlink_param_get      = mv88e6xxx_devlink_param_get,
5102         .devlink_param_set      = mv88e6xxx_devlink_param_set,
5103 };
5104
5105 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5106 {
5107         struct device *dev = chip->dev;
5108         struct dsa_switch *ds;
5109
5110         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5111         if (!ds)
5112                 return -ENOMEM;
5113
5114         ds->dev = dev;
5115         ds->num_ports = mv88e6xxx_num_ports(chip);
5116         ds->priv = chip;
5117         ds->dev = dev;
5118         ds->ops = &mv88e6xxx_switch_ops;
5119         ds->ageing_time_min = chip->info->age_time_coeff;
5120         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5121
5122         dev_set_drvdata(dev, ds);
5123
5124         return dsa_register_switch(ds);
5125 }
5126
5127 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5128 {
5129         dsa_unregister_switch(chip->ds);
5130 }
5131
5132 static const void *pdata_device_get_match_data(struct device *dev)
5133 {
5134         const struct of_device_id *matches = dev->driver->of_match_table;
5135         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5136
5137         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5138              matches++) {
5139                 if (!strcmp(pdata->compatible, matches->compatible))
5140                         return matches->data;
5141         }
5142         return NULL;
5143 }
5144
5145 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5146  * would be lost after a power cycle so prevent it to be suspended.
5147  */
5148 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5149 {
5150         return -EOPNOTSUPP;
5151 }
5152
5153 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5154 {
5155         return 0;
5156 }
5157
5158 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5159
5160 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5161 {
5162         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5163         const struct mv88e6xxx_info *compat_info = NULL;
5164         struct device *dev = &mdiodev->dev;
5165         struct device_node *np = dev->of_node;
5166         struct mv88e6xxx_chip *chip;
5167         int port;
5168         int err;
5169
5170         if (!np && !pdata)
5171                 return -EINVAL;
5172
5173         if (np)
5174                 compat_info = of_device_get_match_data(dev);
5175
5176         if (pdata) {
5177                 compat_info = pdata_device_get_match_data(dev);
5178
5179                 if (!pdata->netdev)
5180                         return -EINVAL;
5181
5182                 for (port = 0; port < DSA_MAX_PORTS; port++) {
5183                         if (!(pdata->enabled_ports & (1 << port)))
5184                                 continue;
5185                         if (strcmp(pdata->cd.port_names[port], "cpu"))
5186                                 continue;
5187                         pdata->cd.netdev[port] = &pdata->netdev->dev;
5188                         break;
5189                 }
5190         }
5191
5192         if (!compat_info)
5193                 return -EINVAL;
5194
5195         chip = mv88e6xxx_alloc_chip(dev);
5196         if (!chip) {
5197                 err = -ENOMEM;
5198                 goto out;
5199         }
5200
5201         chip->info = compat_info;
5202
5203         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5204         if (err)
5205                 goto out;
5206
5207         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5208         if (IS_ERR(chip->reset)) {
5209                 err = PTR_ERR(chip->reset);
5210                 goto out;
5211         }
5212         if (chip->reset)
5213                 usleep_range(1000, 2000);
5214
5215         err = mv88e6xxx_detect(chip);
5216         if (err)
5217                 goto out;
5218
5219         mv88e6xxx_phy_init(chip);
5220
5221         if (chip->info->ops->get_eeprom) {
5222                 if (np)
5223                         of_property_read_u32(np, "eeprom-length",
5224                                              &chip->eeprom_len);
5225                 else
5226                         chip->eeprom_len = pdata->eeprom_len;
5227         }
5228
5229         mv88e6xxx_reg_lock(chip);
5230         err = mv88e6xxx_switch_reset(chip);
5231         mv88e6xxx_reg_unlock(chip);
5232         if (err)
5233                 goto out;
5234
5235         if (np) {
5236                 chip->irq = of_irq_get(np, 0);
5237                 if (chip->irq == -EPROBE_DEFER) {
5238                         err = chip->irq;
5239                         goto out;
5240                 }
5241         }
5242
5243         if (pdata)
5244                 chip->irq = pdata->irq;
5245
5246         /* Has to be performed before the MDIO bus is created, because
5247          * the PHYs will link their interrupts to these interrupt
5248          * controllers
5249          */
5250         mv88e6xxx_reg_lock(chip);
5251         if (chip->irq > 0)
5252                 err = mv88e6xxx_g1_irq_setup(chip);
5253         else
5254                 err = mv88e6xxx_irq_poll_setup(chip);
5255         mv88e6xxx_reg_unlock(chip);
5256
5257         if (err)
5258                 goto out;
5259
5260         if (chip->info->g2_irqs > 0) {
5261                 err = mv88e6xxx_g2_irq_setup(chip);
5262                 if (err)
5263                         goto out_g1_irq;
5264         }
5265
5266         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5267         if (err)
5268                 goto out_g2_irq;
5269
5270         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5271         if (err)
5272                 goto out_g1_atu_prob_irq;
5273
5274         err = mv88e6xxx_mdios_register(chip, np);
5275         if (err)
5276                 goto out_g1_vtu_prob_irq;
5277
5278         err = mv88e6xxx_register_switch(chip);
5279         if (err)
5280                 goto out_mdio;
5281
5282         return 0;
5283
5284 out_mdio:
5285         mv88e6xxx_mdios_unregister(chip);
5286 out_g1_vtu_prob_irq:
5287         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5288 out_g1_atu_prob_irq:
5289         mv88e6xxx_g1_atu_prob_irq_free(chip);
5290 out_g2_irq:
5291         if (chip->info->g2_irqs > 0)
5292                 mv88e6xxx_g2_irq_free(chip);
5293 out_g1_irq:
5294         if (chip->irq > 0)
5295                 mv88e6xxx_g1_irq_free(chip);
5296         else
5297                 mv88e6xxx_irq_poll_free(chip);
5298 out:
5299         if (pdata)
5300                 dev_put(pdata->netdev);
5301
5302         return err;
5303 }
5304
5305 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5306 {
5307         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5308         struct mv88e6xxx_chip *chip = ds->priv;
5309
5310         if (chip->info->ptp_support) {
5311                 mv88e6xxx_hwtstamp_free(chip);
5312                 mv88e6xxx_ptp_free(chip);
5313         }
5314
5315         mv88e6xxx_phy_destroy(chip);
5316         mv88e6xxx_unregister_switch(chip);
5317         mv88e6xxx_mdios_unregister(chip);
5318
5319         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5320         mv88e6xxx_g1_atu_prob_irq_free(chip);
5321
5322         if (chip->info->g2_irqs > 0)
5323                 mv88e6xxx_g2_irq_free(chip);
5324
5325         if (chip->irq > 0)
5326                 mv88e6xxx_g1_irq_free(chip);
5327         else
5328                 mv88e6xxx_irq_poll_free(chip);
5329 }
5330
5331 static const struct of_device_id mv88e6xxx_of_match[] = {
5332         {
5333                 .compatible = "marvell,mv88e6085",
5334                 .data = &mv88e6xxx_table[MV88E6085],
5335         },
5336         {
5337                 .compatible = "marvell,mv88e6190",
5338                 .data = &mv88e6xxx_table[MV88E6190],
5339         },
5340         {
5341                 .compatible = "marvell,mv88e6250",
5342                 .data = &mv88e6xxx_table[MV88E6250],
5343         },
5344         { /* sentinel */ },
5345 };
5346
5347 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5348
5349 static struct mdio_driver mv88e6xxx_driver = {
5350         .probe  = mv88e6xxx_probe,
5351         .remove = mv88e6xxx_remove,
5352         .mdiodrv.driver = {
5353                 .name = "mv88e6085",
5354                 .of_match_table = mv88e6xxx_of_match,
5355                 .pm = &mv88e6xxx_pm_ops,
5356         },
5357 };
5358
5359 mdio_module_driver(mv88e6xxx_driver);
5360
5361 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5362 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5363 MODULE_LICENSE("GPL");