drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "devlink.h"
  36 #include "global1.h"
  37 #include "global2.h"
  38 #include "hwtstamp.h"
  39 #include "phy.h"
  40 #include "port.h"
  41 #include "ptp.h"
  42 #include "serdes.h"
  43 #include "smi.h"
  44
  45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  46 {
  47         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  48                 dev_err(chip->dev, "Switch registers lock not held!\n");
  49                 dump_stack();
  50         }
  51 }
  52
  53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  54 {
  55         int err;
  56
  57         assert_reg_lock(chip);
  58
  59         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  60         if (err)
  61                 return err;
  62
  63         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  64                 addr, reg, *val);
  65
  66         return 0;
  67 }
  68
  69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  70 {
  71         int err;
  72
  73         assert_reg_lock(chip);
  74
  75         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  76         if (err)
  77                 return err;
  78
  79         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  80                 addr, reg, val);
  81
  82         return 0;
  83 }
  84
  85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  86                         u16 mask, u16 val)
  87 {
  88         u16 data;
  89         int err;
  90         int i;
  91
  92         /* There's no bus specific operation to wait for a mask */
  93         for (i = 0; i < 16; i++) {
  94                 err = mv88e6xxx_read(chip, addr, reg, &data);
  95                 if (err)
  96                         return err;
  97
  98                 if ((data & mask) == val)
  99                         return 0;
 100
 101                 usleep_range(1000, 2000);
 102         }
 103
 104         dev_err(chip->dev, "Timeout while waiting for switch\n");
 105         return -ETIMEDOUT;
 106 }
 107
 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 109                        int bit, int val)
 110 {
 111         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 112                                    val ? BIT(bit) : 0x0000);
 113 }
 114
 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 116 {
 117         struct mv88e6xxx_mdio_bus *mdio_bus;
 118
 119         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 120                                     list);
 121         if (!mdio_bus)
 122                 return NULL;
 123
 124         return mdio_bus->bus;
 125 }
 126
 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 128 {
 129         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 130         unsigned int n = d->hwirq;
 131
 132         chip->g1_irq.masked |= (1 << n);
 133 }
 134
 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 136 {
 137         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 138         unsigned int n = d->hwirq;
 139
 140         chip->g1_irq.masked &= ~(1 << n);
 141 }
 142
 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 144 {
 145         unsigned int nhandled = 0;
 146         unsigned int sub_irq;
 147         unsigned int n;
 148         u16 reg;
 149         u16 ctl1;
 150         int err;
 151
 152         mv88e6xxx_reg_lock(chip);
 153         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 154         mv88e6xxx_reg_unlock(chip);
 155
 156         if (err)
 157                 goto out;
 158
 159         do {
 160                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 161                         if (reg & (1 << n)) {
 162                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 163                                                            n);
 164                                 handle_nested_irq(sub_irq);
 165                                 ++nhandled;
 166                         }
 167                 }
 168
 169                 mv88e6xxx_reg_lock(chip);
 170                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 171                 if (err)
 172                         goto unlock;
 173                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 174 unlock:
 175                 mv88e6xxx_reg_unlock(chip);
 176                 if (err)
 177                         goto out;
 178                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 179         } while (reg & ctl1);
 180
 181 out:
 182         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 183 }
 184
 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 186 {
 187         struct mv88e6xxx_chip *chip = dev_id;
 188
 189         return mv88e6xxx_g1_irq_thread_work(chip);
 190 }
 191
 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 193 {
 194         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 195
 196         mv88e6xxx_reg_lock(chip);
 197 }
 198
 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 200 {
 201         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 202         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 203         u16 reg;
 204         int err;
 205
 206         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 207         if (err)
 208                 goto out;
 209
 210         reg &= ~mask;
 211         reg |= (~chip->g1_irq.masked & mask);
 212
 213         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 214         if (err)
 215                 goto out;
 216
 217 out:
 218         mv88e6xxx_reg_unlock(chip);
 219 }
 220
 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 222         .name                   = "mv88e6xxx-g1",
 223         .irq_mask               = mv88e6xxx_g1_irq_mask,
 224         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 225         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 226         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 227 };
 228
 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 230                                        unsigned int irq,
 231                                        irq_hw_number_t hwirq)
 232 {
 233         struct mv88e6xxx_chip *chip = d->host_data;
 234
 235         irq_set_chip_data(irq, d->host_data);
 236         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 237         irq_set_noprobe(irq);
 238
 239         return 0;
 240 }
 241
 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 243         .map    = mv88e6xxx_g1_irq_domain_map,
 244         .xlate  = irq_domain_xlate_twocell,
 245 };
 246
 247 /* To be called with reg_lock held */
 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 249 {
 250         int irq, virq;
 251         u16 mask;
 252
 253         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 254         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 255         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 256
 257         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 258                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 259                 irq_dispose_mapping(virq);
 260         }
 261
 262         irq_domain_remove(chip->g1_irq.domain);
 263 }
 264
 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 266 {
 267         /*
 268          * free_irq must be called without reg_lock taken because the irq
 269          * handler takes this lock, too.
 270          */
 271         free_irq(chip->irq, chip);
 272
 273         mv88e6xxx_reg_lock(chip);
 274         mv88e6xxx_g1_irq_free_common(chip);
 275         mv88e6xxx_reg_unlock(chip);
 276 }
 277
 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 279 {
 280         int err, irq, virq;
 281         u16 reg, mask;
 282
 283         chip->g1_irq.nirqs = chip->info->g1_irqs;
 284         chip->g1_irq.domain = irq_domain_add_simple(
 285                 NULL, chip->g1_irq.nirqs, 0,
 286                 &mv88e6xxx_g1_irq_domain_ops, chip);
 287         if (!chip->g1_irq.domain)
 288                 return -ENOMEM;
 289
 290         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 291                 irq_create_mapping(chip->g1_irq.domain, irq);
 292
 293         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 294         chip->g1_irq.masked = ~0;
 295
 296         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 297         if (err)
 298                 goto out_mapping;
 299
 300         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 301
 302         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 303         if (err)
 304                 goto out_disable;
 305
 306         /* Reading the interrupt status clears (most of) them */
 307         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 308         if (err)
 309                 goto out_disable;
 310
 311         return 0;
 312
 313 out_disable:
 314         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 315         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 316
 317 out_mapping:
 318         for (irq = 0; irq < 16; irq++) {
 319                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 320                 irq_dispose_mapping(virq);
 321         }
 322
 323         irq_domain_remove(chip->g1_irq.domain);
 324
 325         return err;
 326 }
 327
 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 329 {
 330         static struct lock_class_key lock_key;
 331         static struct lock_class_key request_key;
 332         int err;
 333
 334         err = mv88e6xxx_g1_irq_setup_common(chip);
 335         if (err)
 336                 return err;
 337
 338         /* These lock classes tells lockdep that global 1 irqs are in
 339          * a different category than their parent GPIO, so it won't
 340          * report false recursion.
 341          */
 342         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 343
 344         snprintf(chip->irq_name, sizeof(chip->irq_name),
 345                  "mv88e6xxx-%s", dev_name(chip->dev));
 346
 347         mv88e6xxx_reg_unlock(chip);
 348         err = request_threaded_irq(chip->irq, NULL,
 349                                    mv88e6xxx_g1_irq_thread_fn,
 350                                    IRQF_ONESHOT | IRQF_SHARED,
 351                                    chip->irq_name, chip);
 352         mv88e6xxx_reg_lock(chip);
 353         if (err)
 354                 mv88e6xxx_g1_irq_free_common(chip);
 355
 356         return err;
 357 }
 358
 359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 360 {
 361         struct mv88e6xxx_chip *chip = container_of(work,
 362                                                    struct mv88e6xxx_chip,
 363                                                    irq_poll_work.work);
 364         mv88e6xxx_g1_irq_thread_work(chip);
 365
 366         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 367                                    msecs_to_jiffies(100));
 368 }
 369
 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 371 {
 372         int err;
 373
 374         err = mv88e6xxx_g1_irq_setup_common(chip);
 375         if (err)
 376                 return err;
 377
 378         kthread_init_delayed_work(&chip->irq_poll_work,
 379                                   mv88e6xxx_irq_poll);
 380
 381         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 382         if (IS_ERR(chip->kworker))
 383                 return PTR_ERR(chip->kworker);
 384
 385         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 386                                    msecs_to_jiffies(100));
 387
 388         return 0;
 389 }
 390
 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 392 {
 393         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 394         kthread_destroy_worker(chip->kworker);
 395
 396         mv88e6xxx_reg_lock(chip);
 397         mv88e6xxx_g1_irq_free_common(chip);
 398         mv88e6xxx_reg_unlock(chip);
 399 }
 400
 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 402                                            int port, phy_interface_t interface)
 403 {
 404         int err;
 405
 406         if (chip->info->ops->port_set_rgmii_delay) {
 407                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 408                                                             interface);
 409                 if (err && err != -EOPNOTSUPP)
 410                         return err;
 411         }
 412
 413         if (chip->info->ops->port_set_cmode) {
 414                 err = chip->info->ops->port_set_cmode(chip, port,
 415                                                       interface);
 416                 if (err && err != -EOPNOTSUPP)
 417                         return err;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 424                                     int link, int speed, int duplex, int pause,
 425                                     phy_interface_t mode)
 426 {
 427         int err;
 428
 429         if (!chip->info->ops->port_set_link)
 430                 return 0;
 431
 432         /* Port's MAC control must not be changed unless the link is down */
 433         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 434         if (err)
 435                 return err;
 436
 437         if (chip->info->ops->port_set_speed_duplex) {
 438                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 439                                                              speed, duplex);
 440                 if (err && err != -EOPNOTSUPP)
 441                         goto restore_link;
 442         }
 443
 444         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 445                 mode = chip->info->ops->port_max_speed_mode(port);
 446
 447         if (chip->info->ops->port_set_pause) {
 448                 err = chip->info->ops->port_set_pause(chip, port, pause);
 449                 if (err)
 450                         goto restore_link;
 451         }
 452
 453         err = mv88e6xxx_port_config_interface(chip, port, mode);
 454 restore_link:
 455         if (chip->info->ops->port_set_link(chip, port, link))
 456                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 457
 458         return err;
 459 }
 460
 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 462 {
 463         struct mv88e6xxx_chip *chip = ds->priv;
 464
 465         return port < chip->info->num_internal_phys;
 466 }
 467
 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 469 {
 470         u16 reg;
 471         int err;
 472
 473         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 474         if (err) {
 475                 dev_err(chip->dev,
 476                         "p%d: %s: failed to read port status\n",
 477                         port, __func__);
 478                 return err;
 479         }
 480
 481         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 482 }
 483
 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 485                                           struct phylink_link_state *state)
 486 {
 487         struct mv88e6xxx_chip *chip = ds->priv;
 488         u8 lane;
 489         int err;
 490
 491         mv88e6xxx_reg_lock(chip);
 492         lane = mv88e6xxx_serdes_get_lane(chip, port);
 493         if (lane && chip->info->ops->serdes_pcs_get_state)
 494                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 495                                                             state);
 496         else
 497                 err = -EOPNOTSUPP;
 498         mv88e6xxx_reg_unlock(chip);
 499
 500         return err;
 501 }
 502
 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 504                                        unsigned int mode,
 505                                        phy_interface_t interface,
 506                                        const unsigned long *advertise)
 507 {
 508         const struct mv88e6xxx_ops *ops = chip->info->ops;
 509         u8 lane;
 510
 511         if (ops->serdes_pcs_config) {
 512                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 513                 if (lane)
 514                         return ops->serdes_pcs_config(chip, port, lane, mode,
 515                                                       interface, advertise);
 516         }
 517
 518         return 0;
 519 }
 520
 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 522 {
 523         struct mv88e6xxx_chip *chip = ds->priv;
 524         const struct mv88e6xxx_ops *ops;
 525         int err = 0;
 526         u8 lane;
 527
 528         ops = chip->info->ops;
 529
 530         if (ops->serdes_pcs_an_restart) {
 531                 mv88e6xxx_reg_lock(chip);
 532                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 533                 if (lane)
 534                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 535                 mv88e6xxx_reg_unlock(chip);
 536
 537                 if (err)
 538                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 539         }
 540 }
 541
 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 543                                         unsigned int mode,
 544                                         int speed, int duplex)
 545 {
 546         const struct mv88e6xxx_ops *ops = chip->info->ops;
 547         u8 lane;
 548
 549         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 550                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 551                 if (lane)
 552                         return ops->serdes_pcs_link_up(chip, port, lane,
 553                                                        speed, duplex);
 554         }
 555
 556         return 0;
 557 }
 558
 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 560                                        unsigned long *mask,
 561                                        struct phylink_link_state *state)
 562 {
 563         if (!phy_interface_mode_is_8023z(state->interface)) {
 564                 /* 10M and 100M are only supported in non-802.3z mode */
 565                 phylink_set(mask, 10baseT_Half);
 566                 phylink_set(mask, 10baseT_Full);
 567                 phylink_set(mask, 100baseT_Half);
 568                 phylink_set(mask, 100baseT_Full);
 569         }
 570 }
 571
 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 573                                        unsigned long *mask,
 574                                        struct phylink_link_state *state)
 575 {
 576         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 577          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 578          */
 579         phylink_set(mask, 1000baseT_Full);
 580         phylink_set(mask, 1000baseX_Full);
 581
 582         mv88e6065_phylink_validate(chip, port, mask, state);
 583 }
 584
 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 586                                        unsigned long *mask,
 587                                        struct phylink_link_state *state)
 588 {
 589         if (port >= 5)
 590                 phylink_set(mask, 2500baseX_Full);
 591
 592         /* No ethtool bits for 200Mbps */
 593         phylink_set(mask, 1000baseT_Full);
 594         phylink_set(mask, 1000baseX_Full);
 595
 596         mv88e6065_phylink_validate(chip, port, mask, state);
 597 }
 598
 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 600                                        unsigned long *mask,
 601                                        struct phylink_link_state *state)
 602 {
 603         /* No ethtool bits for 200Mbps */
 604         phylink_set(mask, 1000baseT_Full);
 605         phylink_set(mask, 1000baseX_Full);
 606
 607         mv88e6065_phylink_validate(chip, port, mask, state);
 608 }
 609
 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 611                                        unsigned long *mask,
 612                                        struct phylink_link_state *state)
 613 {
 614         if (port >= 9) {
 615                 phylink_set(mask, 2500baseX_Full);
 616                 phylink_set(mask, 2500baseT_Full);
 617         }
 618
 619         /* No ethtool bits for 200Mbps */
 620         phylink_set(mask, 1000baseT_Full);
 621         phylink_set(mask, 1000baseX_Full);
 622
 623         mv88e6065_phylink_validate(chip, port, mask, state);
 624 }
 625
 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 627                                         unsigned long *mask,
 628                                         struct phylink_link_state *state)
 629 {
 630         if (port >= 9) {
 631                 phylink_set(mask, 10000baseT_Full);
 632                 phylink_set(mask, 10000baseKR_Full);
 633         }
 634
 635         mv88e6390_phylink_validate(chip, port, mask, state);
 636 }
 637
 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 639                                unsigned long *supported,
 640                                struct phylink_link_state *state)
 641 {
 642         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 643         struct mv88e6xxx_chip *chip = ds->priv;
 644
 645         /* Allow all the expected bits */
 646         phylink_set(mask, Autoneg);
 647         phylink_set(mask, Pause);
 648         phylink_set_port_modes(mask);
 649
 650         if (chip->info->ops->phylink_validate)
 651                 chip->info->ops->phylink_validate(chip, port, mask, state);
 652
 653         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 654         bitmap_and(state->advertising, state->advertising, mask,
 655                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 656
 657         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 658          * to advertise both, only report advertising at 2500BaseX.
 659          */
 660         phylink_helper_basex_speed(state);
 661 }
 662
 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 664                                  unsigned int mode,
 665                                  const struct phylink_link_state *state)
 666 {
 667         struct mv88e6xxx_chip *chip = ds->priv;
 668         struct mv88e6xxx_port *p;
 669         int err;
 670
 671         p = &chip->ports[port];
 672
 673         /* FIXME: is this the correct test? If we're in fixed mode on an
 674          * internal port, why should we process this any different from
 675          * PHY mode? On the other hand, the port may be automedia between
 676          * an internal PHY and the serdes...
 677          */
 678         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 679                 return;
 680
 681         mv88e6xxx_reg_lock(chip);
 682         /* In inband mode, the link may come up at any time while the link
 683          * is not forced down. Force the link down while we reconfigure the
 684          * interface mode.
 685          */
 686         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 687             chip->info->ops->port_set_link)
 688                 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 689
 690         err = mv88e6xxx_port_config_interface(chip, port, state->interface);
 691         if (err && err != -EOPNOTSUPP)
 692                 goto err_unlock;
 693
 694         err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
 695                                           state->advertising);
 696         /* FIXME: we should restart negotiation if something changed - which
 697          * is something we get if we convert to using phylinks PCS operations.
 698          */
 699         if (err > 0)
 700                 err = 0;
 701
 702         /* Undo the forced down state above after completing configuration
 703          * irrespective of its state on entry, which allows the link to come up.
 704          */
 705         if (mode == MLO_AN_INBAND && p->interface != state->interface &&
 706             chip->info->ops->port_set_link)
 707                 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 708
 709         p->interface = state->interface;
 710
 711 err_unlock:
 712         mv88e6xxx_reg_unlock(chip);
 713
 714         if (err && err != -EOPNOTSUPP)
 715                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 716 }
 717
 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 719                                     unsigned int mode,
 720                                     phy_interface_t interface)
 721 {
 722         struct mv88e6xxx_chip *chip = ds->priv;
 723         const struct mv88e6xxx_ops *ops;
 724         int err = 0;
 725
 726         ops = chip->info->ops;
 727
 728         mv88e6xxx_reg_lock(chip);
 729         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 730              mode == MLO_AN_FIXED) && ops->port_set_link)
 731                 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 732         mv88e6xxx_reg_unlock(chip);
 733
 734         if (err)
 735                 dev_err(chip->dev,
 736                         "p%d: failed to force MAC link down\n", port);
 737 }
 738
 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 740                                   unsigned int mode, phy_interface_t interface,
 741                                   struct phy_device *phydev,
 742                                   int speed, int duplex,
 743                                   bool tx_pause, bool rx_pause)
 744 {
 745         struct mv88e6xxx_chip *chip = ds->priv;
 746         const struct mv88e6xxx_ops *ops;
 747         int err = 0;
 748
 749         ops = chip->info->ops;
 750
 751         mv88e6xxx_reg_lock(chip);
 752         if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
 753                 /* FIXME: for an automedia port, should we force the link
 754                  * down here - what if the link comes up due to "other" media
 755                  * while we're bringing the port up, how is the exclusivity
 756                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 757                  * shared between internal PHY and Serdes.
 758                  */
 759                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 760                                                    duplex);
 761                 if (err)
 762                         goto error;
 763
 764                 if (ops->port_set_speed_duplex) {
 765                         err = ops->port_set_speed_duplex(chip, port,
 766                                                          speed, duplex);
 767                         if (err && err != -EOPNOTSUPP)
 768                                 goto error;
 769                 }
 770
 771                 if (ops->port_set_link)
 772                         err = ops->port_set_link(chip, port, LINK_FORCED_UP);
 773         }
 774 error:
 775         mv88e6xxx_reg_unlock(chip);
 776
 777         if (err && err != -EOPNOTSUPP)
 778                 dev_err(ds->dev,
 779                         "p%d: failed to configure MAC link up\n", port);
 780 }
 781
 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 783 {
 784         if (!chip->info->ops->stats_snapshot)
 785                 return -EOPNOTSUPP;
 786
 787         return chip->info->ops->stats_snapshot(chip, port);
 788 }
 789
 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 791         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 792         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 793         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 794         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 795         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 796         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 797         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 798         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 799         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 800         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 801         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 802         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 803         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 804         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 805         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 806         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 807         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 808         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 809         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 810         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 811         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 812         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 813         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 814         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 815         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 816         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 817         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 818         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 819         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 820         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 821         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 822         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 823         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 824         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 825         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 826         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 827         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 828         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 829         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 830         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 831         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 832         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 833         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 834         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 835         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 836         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 837         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 838         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 839         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 840         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 841         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 842         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 843         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 844         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 845         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 846         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 847         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 848         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 849         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 850 };
 851
 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 853                                             struct mv88e6xxx_hw_stat *s,
 854                                             int port, u16 bank1_select,
 855                                             u16 histogram)
 856 {
 857         u32 low;
 858         u32 high = 0;
 859         u16 reg = 0;
 860         int err;
 861         u64 value;
 862
 863         switch (s->type) {
 864         case STATS_TYPE_PORT:
 865                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 866                 if (err)
 867                         return U64_MAX;
 868
 869                 low = reg;
 870                 if (s->size == 4) {
 871                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 872                         if (err)
 873                                 return U64_MAX;
 874                         low |= ((u32)reg) << 16;
 875                 }
 876                 break;
 877         case STATS_TYPE_BANK1:
 878                 reg = bank1_select;
 879                 fallthrough;
 880         case STATS_TYPE_BANK0:
 881                 reg |= s->reg | histogram;
 882                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 883                 if (s->size == 8)
 884                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 885                 break;
 886         default:
 887                 return U64_MAX;
 888         }
 889         value = (((u64)high) << 32) | low;
 890         return value;
 891 }
 892
 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 894                                        uint8_t *data, int types)
 895 {
 896         struct mv88e6xxx_hw_stat *stat;
 897         int i, j;
 898
 899         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 900                 stat = &mv88e6xxx_hw_stats[i];
 901                 if (stat->type & types) {
 902                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 903                                ETH_GSTRING_LEN);
 904                         j++;
 905                 }
 906         }
 907
 908         return j;
 909 }
 910
 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 912                                        uint8_t *data)
 913 {
 914         return mv88e6xxx_stats_get_strings(chip, data,
 915                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 916 }
 917
 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 919                                        uint8_t *data)
 920 {
 921         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 922 }
 923
 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 925                                        uint8_t *data)
 926 {
 927         return mv88e6xxx_stats_get_strings(chip, data,
 928                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 929 }
 930
 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 932         "atu_member_violation",
 933         "atu_miss_violation",
 934         "atu_full_violation",
 935         "vtu_member_violation",
 936         "vtu_miss_violation",
 937 };
 938
 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 940 {
 941         unsigned int i;
 942
 943         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 944                 strlcpy(data + i * ETH_GSTRING_LEN,
 945                         mv88e6xxx_atu_vtu_stats_strings[i],
 946                         ETH_GSTRING_LEN);
 947 }
 948
 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 950                                   u32 stringset, uint8_t *data)
 951 {
 952         struct mv88e6xxx_chip *chip = ds->priv;
 953         int count = 0;
 954
 955         if (stringset != ETH_SS_STATS)
 956                 return;
 957
 958         mv88e6xxx_reg_lock(chip);
 959
 960         if (chip->info->ops->stats_get_strings)
 961                 count = chip->info->ops->stats_get_strings(chip, data);
 962
 963         if (chip->info->ops->serdes_get_strings) {
 964                 data += count * ETH_GSTRING_LEN;
 965                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 966         }
 967
 968         data += count * ETH_GSTRING_LEN;
 969         mv88e6xxx_atu_vtu_get_strings(data);
 970
 971         mv88e6xxx_reg_unlock(chip);
 972 }
 973
 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 975                                           int types)
 976 {
 977         struct mv88e6xxx_hw_stat *stat;
 978         int i, j;
 979
 980         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 981                 stat = &mv88e6xxx_hw_stats[i];
 982                 if (stat->type & types)
 983                         j++;
 984         }
 985         return j;
 986 }
 987
 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 989 {
 990         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 991                                               STATS_TYPE_PORT);
 992 }
 993
 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 995 {
 996         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 997 }
 998
 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1000 {
1001         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1002                                               STATS_TYPE_BANK1);
1003 }
1004
1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1006 {
1007         struct mv88e6xxx_chip *chip = ds->priv;
1008         int serdes_count = 0;
1009         int count = 0;
1010
1011         if (sset != ETH_SS_STATS)
1012                 return 0;
1013
1014         mv88e6xxx_reg_lock(chip);
1015         if (chip->info->ops->stats_get_sset_count)
1016                 count = chip->info->ops->stats_get_sset_count(chip);
1017         if (count < 0)
1018                 goto out;
1019
1020         if (chip->info->ops->serdes_get_sset_count)
1021                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1022                                                                       port);
1023         if (serdes_count < 0) {
1024                 count = serdes_count;
1025                 goto out;
1026         }
1027         count += serdes_count;
1028         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1029
1030 out:
1031         mv88e6xxx_reg_unlock(chip);
1032
1033         return count;
1034 }
1035
1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1037                                      uint64_t *data, int types,
1038                                      u16 bank1_select, u16 histogram)
1039 {
1040         struct mv88e6xxx_hw_stat *stat;
1041         int i, j;
1042
1043         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1044                 stat = &mv88e6xxx_hw_stats[i];
1045                 if (stat->type & types) {
1046                         mv88e6xxx_reg_lock(chip);
1047                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1048                                                               bank1_select,
1049                                                               histogram);
1050                         mv88e6xxx_reg_unlock(chip);
1051
1052                         j++;
1053                 }
1054         }
1055         return j;
1056 }
1057
1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1059                                      uint64_t *data)
1060 {
1061         return mv88e6xxx_stats_get_stats(chip, port, data,
1062                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1063                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1064 }
1065
1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1067                                      uint64_t *data)
1068 {
1069         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1070                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1071 }
1072
1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1074                                      uint64_t *data)
1075 {
1076         return mv88e6xxx_stats_get_stats(chip, port, data,
1077                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1078                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1079                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1080 }
1081
1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1083                                      uint64_t *data)
1084 {
1085         return mv88e6xxx_stats_get_stats(chip, port, data,
1086                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1087                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1088                                          0);
1089 }
1090
1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1092                                         uint64_t *data)
1093 {
1094         *data++ = chip->ports[port].atu_member_violation;
1095         *data++ = chip->ports[port].atu_miss_violation;
1096         *data++ = chip->ports[port].atu_full_violation;
1097         *data++ = chip->ports[port].vtu_member_violation;
1098         *data++ = chip->ports[port].vtu_miss_violation;
1099 }
1100
1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1102                                 uint64_t *data)
1103 {
1104         int count = 0;
1105
1106         if (chip->info->ops->stats_get_stats)
1107                 count = chip->info->ops->stats_get_stats(chip, port, data);
1108
1109         mv88e6xxx_reg_lock(chip);
1110         if (chip->info->ops->serdes_get_stats) {
1111                 data += count;
1112                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1113         }
1114         data += count;
1115         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1116         mv88e6xxx_reg_unlock(chip);
1117 }
1118
1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1120                                         uint64_t *data)
1121 {
1122         struct mv88e6xxx_chip *chip = ds->priv;
1123         int ret;
1124
1125         mv88e6xxx_reg_lock(chip);
1126
1127         ret = mv88e6xxx_stats_snapshot(chip, port);
1128         mv88e6xxx_reg_unlock(chip);
1129
1130         if (ret < 0)
1131                 return;
1132
1133         mv88e6xxx_get_stats(chip, port, data);
1134
1135 }
1136
1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1138 {
1139         struct mv88e6xxx_chip *chip = ds->priv;
1140         int len;
1141
1142         len = 32 * sizeof(u16);
1143         if (chip->info->ops->serdes_get_regs_len)
1144                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1145
1146         return len;
1147 }
1148
1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1150                                struct ethtool_regs *regs, void *_p)
1151 {
1152         struct mv88e6xxx_chip *chip = ds->priv;
1153         int err;
1154         u16 reg;
1155         u16 *p = _p;
1156         int i;
1157
1158         regs->version = chip->info->prod_num;
1159
1160         memset(p, 0xff, 32 * sizeof(u16));
1161
1162         mv88e6xxx_reg_lock(chip);
1163
1164         for (i = 0; i < 32; i++) {
1165
1166                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1167                 if (!err)
1168                         p[i] = reg;
1169         }
1170
1171         if (chip->info->ops->serdes_get_regs)
1172                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1173
1174         mv88e6xxx_reg_unlock(chip);
1175 }
1176
1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1178                                  struct ethtool_eee *e)
1179 {
1180         /* Nothing to do on the port's MAC */
1181         return 0;
1182 }
1183
1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1185                                  struct ethtool_eee *e)
1186 {
1187         /* Nothing to do on the port's MAC */
1188         return 0;
1189 }
1190
1191 /* Mask of the local ports allowed to receive frames from a given fabric port */
1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1193 {
1194         struct dsa_switch *ds = chip->ds;
1195         struct dsa_switch_tree *dst = ds->dst;
1196         struct net_device *br;
1197         struct dsa_port *dp;
1198         bool found = false;
1199         u16 pvlan;
1200
1201         list_for_each_entry(dp, &dst->ports, list) {
1202                 if (dp->ds->index == dev && dp->index == port) {
1203                         found = true;
1204                         break;
1205                 }
1206         }
1207
1208         /* Prevent frames from unknown switch or port */
1209         if (!found)
1210                 return 0;
1211
1212         /* Frames from DSA links and CPU ports can egress any local port */
1213         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1214                 return mv88e6xxx_port_mask(chip);
1215
1216         br = dp->bridge_dev;
1217         pvlan = 0;
1218
1219         /* Frames from user ports can egress any local DSA links and CPU ports,
1220          * as well as any local member of their bridge group.
1221          */
1222         list_for_each_entry(dp, &dst->ports, list)
1223                 if (dp->ds == ds &&
1224                     (dp->type == DSA_PORT_TYPE_CPU ||
1225                      dp->type == DSA_PORT_TYPE_DSA ||
1226                      (br && dp->bridge_dev == br)))
1227                         pvlan |= BIT(dp->index);
1228
1229         return pvlan;
1230 }
1231
1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1233 {
1234         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1235
1236         /* prevent frames from going back out of the port they came in on */
1237         output_ports &= ~BIT(port);
1238
1239         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1240 }
1241
1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1243                                          u8 state)
1244 {
1245         struct mv88e6xxx_chip *chip = ds->priv;
1246         int err;
1247
1248         mv88e6xxx_reg_lock(chip);
1249         err = mv88e6xxx_port_set_state(chip, port, state);
1250         mv88e6xxx_reg_unlock(chip);
1251
1252         if (err)
1253                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1254 }
1255
1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1257 {
1258         int err;
1259
1260         if (chip->info->ops->ieee_pri_map) {
1261                 err = chip->info->ops->ieee_pri_map(chip);
1262                 if (err)
1263                         return err;
1264         }
1265
1266         if (chip->info->ops->ip_pri_map) {
1267                 err = chip->info->ops->ip_pri_map(chip);
1268                 if (err)
1269                         return err;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1276 {
1277         struct dsa_switch *ds = chip->ds;
1278         int target, port;
1279         int err;
1280
1281         if (!chip->info->global2_addr)
1282                 return 0;
1283
1284         /* Initialize the routing port to the 32 possible target devices */
1285         for (target = 0; target < 32; target++) {
1286                 port = dsa_routing_port(ds, target);
1287                 if (port == ds->num_ports)
1288                         port = 0x1f;
1289
1290                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1291                 if (err)
1292                         return err;
1293         }
1294
1295         if (chip->info->ops->set_cascade_port) {
1296                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1297                 err = chip->info->ops->set_cascade_port(chip, port);
1298                 if (err)
1299                         return err;
1300         }
1301
1302         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1303         if (err)
1304                 return err;
1305
1306         return 0;
1307 }
1308
1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1310 {
1311         /* Clear all trunk masks and mapping */
1312         if (chip->info->global2_addr)
1313                 return mv88e6xxx_g2_trunk_clear(chip);
1314
1315         return 0;
1316 }
1317
1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1319 {
1320         if (chip->info->ops->rmu_disable)
1321                 return chip->info->ops->rmu_disable(chip);
1322
1323         return 0;
1324 }
1325
1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1327 {
1328         if (chip->info->ops->pot_clear)
1329                 return chip->info->ops->pot_clear(chip);
1330
1331         return 0;
1332 }
1333
1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1335 {
1336         if (chip->info->ops->mgmt_rsvd2cpu)
1337                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1338
1339         return 0;
1340 }
1341
1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1343 {
1344         int err;
1345
1346         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1347         if (err)
1348                 return err;
1349
1350         err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1351         if (err)
1352                 return err;
1353
1354         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1355 }
1356
1357 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1358 {
1359         int port;
1360         int err;
1361
1362         if (!chip->info->ops->irl_init_all)
1363                 return 0;
1364
1365         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1366                 /* Disable ingress rate limiting by resetting all per port
1367                  * ingress rate limit resources to their initial state.
1368                  */
1369                 err = chip->info->ops->irl_init_all(chip, port);
1370                 if (err)
1371                         return err;
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1378 {
1379         if (chip->info->ops->set_switch_mac) {
1380                 u8 addr[ETH_ALEN];
1381
1382                 eth_random_addr(addr);
1383
1384                 return chip->info->ops->set_switch_mac(chip, addr);
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1391 {
1392         u16 pvlan = 0;
1393
1394         if (!mv88e6xxx_has_pvt(chip))
1395                 return 0;
1396
1397         /* Skip the local source device, which uses in-chip port VLAN */
1398         if (dev != chip->ds->index)
1399                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1400
1401         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1402 }
1403
1404 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1405 {
1406         int dev, port;
1407         int err;
1408
1409         if (!mv88e6xxx_has_pvt(chip))
1410                 return 0;
1411
1412         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1413          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1414          */
1415         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1416         if (err)
1417                 return err;
1418
1419         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1420                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1421                         err = mv88e6xxx_pvt_map(chip, dev, port);
1422                         if (err)
1423                                 return err;
1424                 }
1425         }
1426
1427         return 0;
1428 }
1429
1430 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1431 {
1432         struct mv88e6xxx_chip *chip = ds->priv;
1433         int err;
1434
1435         mv88e6xxx_reg_lock(chip);
1436         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1437         mv88e6xxx_reg_unlock(chip);
1438
1439         if (err)
1440                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1441 }
1442
1443 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1444 {
1445         if (!chip->info->max_vid)
1446                 return 0;
1447
1448         return mv88e6xxx_g1_vtu_flush(chip);
1449 }
1450
1451 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1452                                  struct mv88e6xxx_vtu_entry *entry)
1453 {
1454         if (!chip->info->ops->vtu_getnext)
1455                 return -EOPNOTSUPP;
1456
1457         return chip->info->ops->vtu_getnext(chip, entry);
1458 }
1459
1460 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1461                                    struct mv88e6xxx_vtu_entry *entry)
1462 {
1463         if (!chip->info->ops->vtu_loadpurge)
1464                 return -EOPNOTSUPP;
1465
1466         return chip->info->ops->vtu_loadpurge(chip, entry);
1467 }
1468
1469 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1470 {
1471         struct mv88e6xxx_vtu_entry vlan;
1472         int i, err;
1473         u16 fid;
1474
1475         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1476
1477         /* Set every FID bit used by the (un)bridged ports */
1478         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1479                 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1480                 if (err)
1481                         return err;
1482
1483                 set_bit(fid, fid_bitmap);
1484         }
1485
1486         /* Set every FID bit used by the VLAN entries */
1487         vlan.vid = chip->info->max_vid;
1488         vlan.valid = false;
1489
1490         do {
1491                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1492                 if (err)
1493                         return err;
1494
1495                 if (!vlan.valid)
1496                         break;
1497
1498                 set_bit(vlan.fid, fid_bitmap);
1499         } while (vlan.vid < chip->info->max_vid);
1500
1501         return 0;
1502 }
1503
1504 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1505 {
1506         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1507         int err;
1508
1509         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1510         if (err)
1511                 return err;
1512
1513         /* The reset value 0x000 is used to indicate that multiple address
1514          * databases are not needed. Return the next positive available.
1515          */
1516         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1517         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1518                 return -ENOSPC;
1519
1520         /* Clear the database */
1521         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1522 }
1523
1524 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1525                                         u16 vid_begin, u16 vid_end)
1526 {
1527         struct mv88e6xxx_chip *chip = ds->priv;
1528         struct mv88e6xxx_vtu_entry vlan;
1529         int i, err;
1530
1531         /* DSA and CPU ports have to be members of multiple vlans */
1532         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1533                 return 0;
1534
1535         if (!vid_begin)
1536                 return -EOPNOTSUPP;
1537
1538         vlan.vid = vid_begin - 1;
1539         vlan.valid = false;
1540
1541         do {
1542                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1543                 if (err)
1544                         return err;
1545
1546                 if (!vlan.valid)
1547                         break;
1548
1549                 if (vlan.vid > vid_end)
1550                         break;
1551
1552                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1553                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1554                                 continue;
1555
1556                         if (!dsa_to_port(ds, i)->slave)
1557                                 continue;
1558
1559                         if (vlan.member[i] ==
1560                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1561                                 continue;
1562
1563                         if (dsa_to_port(ds, i)->bridge_dev ==
1564                             dsa_to_port(ds, port)->bridge_dev)
1565                                 break; /* same bridge, check next VLAN */
1566
1567                         if (!dsa_to_port(ds, i)->bridge_dev)
1568                                 continue;
1569
1570                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1571                                 port, vlan.vid, i,
1572                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1573                         return -EOPNOTSUPP;
1574                 }
1575         } while (vlan.vid < vid_end);
1576
1577         return 0;
1578 }
1579
1580 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1581                                          bool vlan_filtering,
1582                                          struct switchdev_trans *trans)
1583 {
1584         struct mv88e6xxx_chip *chip = ds->priv;
1585         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1586                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1587         int err;
1588
1589         if (switchdev_trans_ph_prepare(trans))
1590                 return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1591
1592         mv88e6xxx_reg_lock(chip);
1593         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1594         mv88e6xxx_reg_unlock(chip);
1595
1596         return err;
1597 }
1598
1599 static int
1600 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1601                             const struct switchdev_obj_port_vlan *vlan)
1602 {
1603         struct mv88e6xxx_chip *chip = ds->priv;
1604         int err;
1605
1606         if (!chip->info->max_vid)
1607                 return -EOPNOTSUPP;
1608
1609         /* If the requested port doesn't belong to the same bridge as the VLAN
1610          * members, do not support it (yet) and fallback to software VLAN.
1611          */
1612         mv88e6xxx_reg_lock(chip);
1613         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1614                                            vlan->vid_end);
1615         mv88e6xxx_reg_unlock(chip);
1616
1617         /* We don't need any dynamic resource from the kernel (yet),
1618          * so skip the prepare phase.
1619          */
1620         return err;
1621 }
1622
1623 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1624                                         const unsigned char *addr, u16 vid,
1625                                         u8 state)
1626 {
1627         struct mv88e6xxx_atu_entry entry;
1628         struct mv88e6xxx_vtu_entry vlan;
1629         u16 fid;
1630         int err;
1631
1632         /* Null VLAN ID corresponds to the port private database */
1633         if (vid == 0) {
1634                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1635                 if (err)
1636                         return err;
1637         } else {
1638                 vlan.vid = vid - 1;
1639                 vlan.valid = false;
1640
1641                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1642                 if (err)
1643                         return err;
1644
1645                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1646                 if (vlan.vid != vid || !vlan.valid)
1647                         return -EOPNOTSUPP;
1648
1649                 fid = vlan.fid;
1650         }
1651
1652         entry.state = 0;
1653         ether_addr_copy(entry.mac, addr);
1654         eth_addr_dec(entry.mac);
1655
1656         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1657         if (err)
1658                 return err;
1659
1660         /* Initialize a fresh ATU entry if it isn't found */
1661         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1662                 memset(&entry, 0, sizeof(entry));
1663                 ether_addr_copy(entry.mac, addr);
1664         }
1665
1666         /* Purge the ATU entry only if no port is using it anymore */
1667         if (!state) {
1668                 entry.portvec &= ~BIT(port);
1669                 if (!entry.portvec)
1670                         entry.state = 0;
1671         } else {
1672                 entry.portvec |= BIT(port);
1673                 entry.state = state;
1674         }
1675
1676         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1677 }
1678
1679 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1680                                   const struct mv88e6xxx_policy *policy)
1681 {
1682         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1683         enum mv88e6xxx_policy_action action = policy->action;
1684         const u8 *addr = policy->addr;
1685         u16 vid = policy->vid;
1686         u8 state;
1687         int err;
1688         int id;
1689
1690         if (!chip->info->ops->port_set_policy)
1691                 return -EOPNOTSUPP;
1692
1693         switch (mapping) {
1694         case MV88E6XXX_POLICY_MAPPING_DA:
1695         case MV88E6XXX_POLICY_MAPPING_SA:
1696                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1697                         state = 0; /* Dissociate the port and address */
1698                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1699                          is_multicast_ether_addr(addr))
1700                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1701                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1702                          is_unicast_ether_addr(addr))
1703                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1704                 else
1705                         return -EOPNOTSUPP;
1706
1707                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1708                                                    state);
1709                 if (err)
1710                         return err;
1711                 break;
1712         default:
1713                 return -EOPNOTSUPP;
1714         }
1715
1716         /* Skip the port's policy clearing if the mapping is still in use */
1717         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1718                 idr_for_each_entry(&chip->policies, policy, id)
1719                         if (policy->port == port &&
1720                             policy->mapping == mapping &&
1721                             policy->action != action)
1722                                 return 0;
1723
1724         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1725 }
1726
1727 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1728                                    struct ethtool_rx_flow_spec *fs)
1729 {
1730         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1731         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1732         enum mv88e6xxx_policy_mapping mapping;
1733         enum mv88e6xxx_policy_action action;
1734         struct mv88e6xxx_policy *policy;
1735         u16 vid = 0;
1736         u8 *addr;
1737         int err;
1738         int id;
1739
1740         if (fs->location != RX_CLS_LOC_ANY)
1741                 return -EINVAL;
1742
1743         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1744                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1745         else
1746                 return -EOPNOTSUPP;
1747
1748         switch (fs->flow_type & ~FLOW_EXT) {
1749         case ETHER_FLOW:
1750                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1751                     is_zero_ether_addr(mac_mask->h_source)) {
1752                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1753                         addr = mac_entry->h_dest;
1754                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1755                     !is_zero_ether_addr(mac_mask->h_source)) {
1756                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1757                         addr = mac_entry->h_source;
1758                 } else {
1759                         /* Cannot support DA and SA mapping in the same rule */
1760                         return -EOPNOTSUPP;
1761                 }
1762                 break;
1763         default:
1764                 return -EOPNOTSUPP;
1765         }
1766
1767         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1768                 if (fs->m_ext.vlan_tci != htons(0xffff))
1769                         return -EOPNOTSUPP;
1770                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1771         }
1772
1773         idr_for_each_entry(&chip->policies, policy, id) {
1774                 if (policy->port == port && policy->mapping == mapping &&
1775                     policy->action == action && policy->vid == vid &&
1776                     ether_addr_equal(policy->addr, addr))
1777                         return -EEXIST;
1778         }
1779
1780         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1781         if (!policy)
1782                 return -ENOMEM;
1783
1784         fs->location = 0;
1785         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1786                             GFP_KERNEL);
1787         if (err) {
1788                 devm_kfree(chip->dev, policy);
1789                 return err;
1790         }
1791
1792         memcpy(&policy->fs, fs, sizeof(*fs));
1793         ether_addr_copy(policy->addr, addr);
1794         policy->mapping = mapping;
1795         policy->action = action;
1796         policy->port = port;
1797         policy->vid = vid;
1798
1799         err = mv88e6xxx_policy_apply(chip, port, policy);
1800         if (err) {
1801                 idr_remove(&chip->policies, fs->location);
1802                 devm_kfree(chip->dev, policy);
1803                 return err;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1810                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1811 {
1812         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1813         struct mv88e6xxx_chip *chip = ds->priv;
1814         struct mv88e6xxx_policy *policy;
1815         int err;
1816         int id;
1817
1818         mv88e6xxx_reg_lock(chip);
1819
1820         switch (rxnfc->cmd) {
1821         case ETHTOOL_GRXCLSRLCNT:
1822                 rxnfc->data = 0;
1823                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1824                 rxnfc->rule_cnt = 0;
1825                 idr_for_each_entry(&chip->policies, policy, id)
1826                         if (policy->port == port)
1827                                 rxnfc->rule_cnt++;
1828                 err = 0;
1829                 break;
1830         case ETHTOOL_GRXCLSRULE:
1831                 err = -ENOENT;
1832                 policy = idr_find(&chip->policies, fs->location);
1833                 if (policy) {
1834                         memcpy(fs, &policy->fs, sizeof(*fs));
1835                         err = 0;
1836                 }
1837                 break;
1838         case ETHTOOL_GRXCLSRLALL:
1839                 rxnfc->data = 0;
1840                 rxnfc->rule_cnt = 0;
1841                 idr_for_each_entry(&chip->policies, policy, id)
1842                         if (policy->port == port)
1843                                 rule_locs[rxnfc->rule_cnt++] = id;
1844                 err = 0;
1845                 break;
1846         default:
1847                 err = -EOPNOTSUPP;
1848                 break;
1849         }
1850
1851         mv88e6xxx_reg_unlock(chip);
1852
1853         return err;
1854 }
1855
1856 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1857                                struct ethtool_rxnfc *rxnfc)
1858 {
1859         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1860         struct mv88e6xxx_chip *chip = ds->priv;
1861         struct mv88e6xxx_policy *policy;
1862         int err;
1863
1864         mv88e6xxx_reg_lock(chip);
1865
1866         switch (rxnfc->cmd) {
1867         case ETHTOOL_SRXCLSRLINS:
1868                 err = mv88e6xxx_policy_insert(chip, port, fs);
1869                 break;
1870         case ETHTOOL_SRXCLSRLDEL:
1871                 err = -ENOENT;
1872                 policy = idr_remove(&chip->policies, fs->location);
1873                 if (policy) {
1874                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1875                         err = mv88e6xxx_policy_apply(chip, port, policy);
1876                         devm_kfree(chip->dev, policy);
1877                 }
1878                 break;
1879         default:
1880                 err = -EOPNOTSUPP;
1881                 break;
1882         }
1883
1884         mv88e6xxx_reg_unlock(chip);
1885
1886         return err;
1887 }
1888
1889 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1890                                         u16 vid)
1891 {
1892         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1893         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1894
1895         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1896 }
1897
1898 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1899 {
1900         int port;
1901         int err;
1902
1903         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1904                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1905                 if (err)
1906                         return err;
1907         }
1908
1909         return 0;
1910 }
1911
1912 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1913                                     u16 vid, u8 member, bool warn)
1914 {
1915         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1916         struct mv88e6xxx_vtu_entry vlan;
1917         int i, err;
1918
1919         if (!vid)
1920                 return -EOPNOTSUPP;
1921
1922         vlan.vid = vid - 1;
1923         vlan.valid = false;
1924
1925         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1926         if (err)
1927                 return err;
1928
1929         if (vlan.vid != vid || !vlan.valid) {
1930                 memset(&vlan, 0, sizeof(vlan));
1931
1932                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1933                 if (err)
1934                         return err;
1935
1936                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1937                         if (i == port)
1938                                 vlan.member[i] = member;
1939                         else
1940                                 vlan.member[i] = non_member;
1941
1942                 vlan.vid = vid;
1943                 vlan.valid = true;
1944
1945                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1946                 if (err)
1947                         return err;
1948
1949                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1950                 if (err)
1951                         return err;
1952         } else if (vlan.member[port] != member) {
1953                 vlan.member[port] = member;
1954
1955                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1956                 if (err)
1957                         return err;
1958         } else if (warn) {
1959                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1960                          port, vid);
1961         }
1962
1963         return 0;
1964 }
1965
1966 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1967                                     const struct switchdev_obj_port_vlan *vlan)
1968 {
1969         struct mv88e6xxx_chip *chip = ds->priv;
1970         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1971         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1972         bool warn;
1973         u8 member;
1974         u16 vid;
1975
1976         if (!chip->info->max_vid)
1977                 return;
1978
1979         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1980                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1981         else if (untagged)
1982                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1983         else
1984                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1985
1986         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
1987          * and then the CPU port. Do not warn for duplicates for the CPU port.
1988          */
1989         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
1990
1991         mv88e6xxx_reg_lock(chip);
1992
1993         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1994                 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
1995                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1996                                 vid, untagged ? 'u' : 't');
1997
1998         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1999                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
2000                         vlan->vid_end);
2001
2002         mv88e6xxx_reg_unlock(chip);
2003 }
2004
2005 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2006                                      int port, u16 vid)
2007 {
2008         struct mv88e6xxx_vtu_entry vlan;
2009         int i, err;
2010
2011         if (!vid)
2012                 return -EOPNOTSUPP;
2013
2014         vlan.vid = vid - 1;
2015         vlan.valid = false;
2016
2017         err = mv88e6xxx_vtu_getnext(chip, &vlan);
2018         if (err)
2019                 return err;
2020
2021         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2022          * tell switchdev that this VLAN is likely handled in software.
2023          */
2024         if (vlan.vid != vid || !vlan.valid ||
2025             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2026                 return -EOPNOTSUPP;
2027
2028         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2029
2030         /* keep the VLAN unless all ports are excluded */
2031         vlan.valid = false;
2032         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2033                 if (vlan.member[i] !=
2034                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2035                         vlan.valid = true;
2036                         break;
2037                 }
2038         }
2039
2040         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2041         if (err)
2042                 return err;
2043
2044         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2045 }
2046
2047 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2048                                    const struct switchdev_obj_port_vlan *vlan)
2049 {
2050         struct mv88e6xxx_chip *chip = ds->priv;
2051         u16 pvid, vid;
2052         int err = 0;
2053
2054         if (!chip->info->max_vid)
2055                 return -EOPNOTSUPP;
2056
2057         mv88e6xxx_reg_lock(chip);
2058
2059         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2060         if (err)
2061                 goto unlock;
2062
2063         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2064                 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2065                 if (err)
2066                         goto unlock;
2067
2068                 if (vid == pvid) {
2069                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
2070                         if (err)
2071                                 goto unlock;
2072                 }
2073         }
2074
2075 unlock:
2076         mv88e6xxx_reg_unlock(chip);
2077
2078         return err;
2079 }
2080
2081 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2082                                   const unsigned char *addr, u16 vid)
2083 {
2084         struct mv88e6xxx_chip *chip = ds->priv;
2085         int err;
2086
2087         mv88e6xxx_reg_lock(chip);
2088         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2089                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2090         mv88e6xxx_reg_unlock(chip);
2091
2092         return err;
2093 }
2094
2095 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2096                                   const unsigned char *addr, u16 vid)
2097 {
2098         struct mv88e6xxx_chip *chip = ds->priv;
2099         int err;
2100
2101         mv88e6xxx_reg_lock(chip);
2102         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2103         mv88e6xxx_reg_unlock(chip);
2104
2105         return err;
2106 }
2107
2108 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2109                                       u16 fid, u16 vid, int port,
2110                                       dsa_fdb_dump_cb_t *cb, void *data)
2111 {
2112         struct mv88e6xxx_atu_entry addr;
2113         bool is_static;
2114         int err;
2115
2116         addr.state = 0;
2117         eth_broadcast_addr(addr.mac);
2118
2119         do {
2120                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2121                 if (err)
2122                         return err;
2123
2124                 if (!addr.state)
2125                         break;
2126
2127                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2128                         continue;
2129
2130                 if (!is_unicast_ether_addr(addr.mac))
2131                         continue;
2132
2133                 is_static = (addr.state ==
2134                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2135                 err = cb(addr.mac, vid, is_static, data);
2136                 if (err)
2137                         return err;
2138         } while (!is_broadcast_ether_addr(addr.mac));
2139
2140         return err;
2141 }
2142
2143 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2144                                   dsa_fdb_dump_cb_t *cb, void *data)
2145 {
2146         struct mv88e6xxx_vtu_entry vlan;
2147         u16 fid;
2148         int err;
2149
2150         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2151         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2152         if (err)
2153                 return err;
2154
2155         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2156         if (err)
2157                 return err;
2158
2159         /* Dump VLANs' Filtering Information Databases */
2160         vlan.vid = chip->info->max_vid;
2161         vlan.valid = false;
2162
2163         do {
2164                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2165                 if (err)
2166                         return err;
2167
2168                 if (!vlan.valid)
2169                         break;
2170
2171                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2172                                                  cb, data);
2173                 if (err)
2174                         return err;
2175         } while (vlan.vid < chip->info->max_vid);
2176
2177         return err;
2178 }
2179
2180 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2181                                    dsa_fdb_dump_cb_t *cb, void *data)
2182 {
2183         struct mv88e6xxx_chip *chip = ds->priv;
2184         int err;
2185
2186         mv88e6xxx_reg_lock(chip);
2187         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2188         mv88e6xxx_reg_unlock(chip);
2189
2190         return err;
2191 }
2192
2193 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2194                                 struct net_device *br)
2195 {
2196         struct dsa_switch *ds = chip->ds;
2197         struct dsa_switch_tree *dst = ds->dst;
2198         struct dsa_port *dp;
2199         int err;
2200
2201         list_for_each_entry(dp, &dst->ports, list) {
2202                 if (dp->bridge_dev == br) {
2203                         if (dp->ds == ds) {
2204                                 /* This is a local bridge group member,
2205                                  * remap its Port VLAN Map.
2206                                  */
2207                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2208                                 if (err)
2209                                         return err;
2210                         } else {
2211                                 /* This is an external bridge group member,
2212                                  * remap its cross-chip Port VLAN Table entry.
2213                                  */
2214                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2215                                                         dp->index);
2216                                 if (err)
2217                                         return err;
2218                         }
2219                 }
2220         }
2221
2222         return 0;
2223 }
2224
2225 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2226                                       struct net_device *br)
2227 {
2228         struct mv88e6xxx_chip *chip = ds->priv;
2229         int err;
2230
2231         mv88e6xxx_reg_lock(chip);
2232         err = mv88e6xxx_bridge_map(chip, br);
2233         mv88e6xxx_reg_unlock(chip);
2234
2235         return err;
2236 }
2237
2238 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2239                                         struct net_device *br)
2240 {
2241         struct mv88e6xxx_chip *chip = ds->priv;
2242
2243         mv88e6xxx_reg_lock(chip);
2244         if (mv88e6xxx_bridge_map(chip, br) ||
2245             mv88e6xxx_port_vlan_map(chip, port))
2246                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2247         mv88e6xxx_reg_unlock(chip);
2248 }
2249
2250 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2251                                            int tree_index, int sw_index,
2252                                            int port, struct net_device *br)
2253 {
2254         struct mv88e6xxx_chip *chip = ds->priv;
2255         int err;
2256
2257         if (tree_index != ds->dst->index)
2258                 return 0;
2259
2260         mv88e6xxx_reg_lock(chip);
2261         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2262         mv88e6xxx_reg_unlock(chip);
2263
2264         return err;
2265 }
2266
2267 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2268                                              int tree_index, int sw_index,
2269                                              int port, struct net_device *br)
2270 {
2271         struct mv88e6xxx_chip *chip = ds->priv;
2272
2273         if (tree_index != ds->dst->index)
2274                 return;
2275
2276         mv88e6xxx_reg_lock(chip);
2277         if (mv88e6xxx_pvt_map(chip, sw_index, port))
2278                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2279         mv88e6xxx_reg_unlock(chip);
2280 }
2281
2282 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2283 {
2284         if (chip->info->ops->reset)
2285                 return chip->info->ops->reset(chip);
2286
2287         return 0;
2288 }
2289
2290 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2291 {
2292         struct gpio_desc *gpiod = chip->reset;
2293
2294         /* If there is a GPIO connected to the reset pin, toggle it */
2295         if (gpiod) {
2296                 gpiod_set_value_cansleep(gpiod, 1);
2297                 usleep_range(10000, 20000);
2298                 gpiod_set_value_cansleep(gpiod, 0);
2299                 usleep_range(10000, 20000);
2300
2301                 mv88e6xxx_g1_wait_eeprom_done(chip);
2302         }
2303 }
2304
2305 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2306 {
2307         int i, err;
2308
2309         /* Set all ports to the Disabled state */
2310         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2311                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2312                 if (err)
2313                         return err;
2314         }
2315
2316         /* Wait for transmit queues to drain,
2317          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2318          */
2319         usleep_range(2000, 4000);
2320
2321         return 0;
2322 }
2323
2324 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2325 {
2326         int err;
2327
2328         err = mv88e6xxx_disable_ports(chip);
2329         if (err)
2330                 return err;
2331
2332         mv88e6xxx_hardware_reset(chip);
2333
2334         return mv88e6xxx_software_reset(chip);
2335 }
2336
2337 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2338                                    enum mv88e6xxx_frame_mode frame,
2339                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2340 {
2341         int err;
2342
2343         if (!chip->info->ops->port_set_frame_mode)
2344                 return -EOPNOTSUPP;
2345
2346         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2347         if (err)
2348                 return err;
2349
2350         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2351         if (err)
2352                 return err;
2353
2354         if (chip->info->ops->port_set_ether_type)
2355                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2356
2357         return 0;
2358 }
2359
2360 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2361 {
2362         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2363                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2364                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2365 }
2366
2367 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2368 {
2369         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2370                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2371                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2372 }
2373
2374 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2375 {
2376         return mv88e6xxx_set_port_mode(chip, port,
2377                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2378                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2379                                        ETH_P_EDSA);
2380 }
2381
2382 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2383 {
2384         if (dsa_is_dsa_port(chip->ds, port))
2385                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2386
2387         if (dsa_is_user_port(chip->ds, port))
2388                 return mv88e6xxx_set_port_mode_normal(chip, port);
2389
2390         /* Setup CPU port mode depending on its supported tag format */
2391         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2392                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2393
2394         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2395                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2396
2397         return -EINVAL;
2398 }
2399
2400 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2401 {
2402         bool message = dsa_is_dsa_port(chip->ds, port);
2403
2404         return mv88e6xxx_port_set_message_port(chip, port, message);
2405 }
2406
2407 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2408 {
2409         struct dsa_switch *ds = chip->ds;
2410         bool flood;
2411
2412         /* Upstream ports flood frames with unknown unicast or multicast DA */
2413         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2414         if (chip->info->ops->port_set_egress_floods)
2415                 return chip->info->ops->port_set_egress_floods(chip, port,
2416                                                                flood, flood);
2417
2418         return 0;
2419 }
2420
2421 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2422 {
2423         struct mv88e6xxx_port *mvp = dev_id;
2424         struct mv88e6xxx_chip *chip = mvp->chip;
2425         irqreturn_t ret = IRQ_NONE;
2426         int port = mvp->port;
2427         u8 lane;
2428
2429         mv88e6xxx_reg_lock(chip);
2430         lane = mv88e6xxx_serdes_get_lane(chip, port);
2431         if (lane)
2432                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2433         mv88e6xxx_reg_unlock(chip);
2434
2435         return ret;
2436 }
2437
2438 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2439                                         u8 lane)
2440 {
2441         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2442         unsigned int irq;
2443         int err;
2444
2445         /* Nothing to request if this SERDES port has no IRQ */
2446         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2447         if (!irq)
2448                 return 0;
2449
2450         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2451                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2452
2453         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2454         mv88e6xxx_reg_unlock(chip);
2455         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2456                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
2457                                    dev_id);
2458         mv88e6xxx_reg_lock(chip);
2459         if (err)
2460                 return err;
2461
2462         dev_id->serdes_irq = irq;
2463
2464         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2465 }
2466
2467 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2468                                      u8 lane)
2469 {
2470         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2471         unsigned int irq = dev_id->serdes_irq;
2472         int err;
2473
2474         /* Nothing to free if no IRQ has been requested */
2475         if (!irq)
2476                 return 0;
2477
2478         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2479
2480         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2481         mv88e6xxx_reg_unlock(chip);
2482         free_irq(irq, dev_id);
2483         mv88e6xxx_reg_lock(chip);
2484
2485         dev_id->serdes_irq = 0;
2486
2487         return err;
2488 }
2489
2490 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2491                                   bool on)
2492 {
2493         u8 lane;
2494         int err;
2495
2496         lane = mv88e6xxx_serdes_get_lane(chip, port);
2497         if (!lane)
2498                 return 0;
2499
2500         if (on) {
2501                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2502                 if (err)
2503                         return err;
2504
2505                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2506         } else {
2507                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2508                 if (err)
2509                         return err;
2510
2511                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2512         }
2513
2514         return err;
2515 }
2516
2517 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2518 {
2519         struct dsa_switch *ds = chip->ds;
2520         int upstream_port;
2521         int err;
2522
2523         upstream_port = dsa_upstream_port(ds, port);
2524         if (chip->info->ops->port_set_upstream_port) {
2525                 err = chip->info->ops->port_set_upstream_port(chip, port,
2526                                                               upstream_port);
2527                 if (err)
2528                         return err;
2529         }
2530
2531         if (port == upstream_port) {
2532                 if (chip->info->ops->set_cpu_port) {
2533                         err = chip->info->ops->set_cpu_port(chip,
2534                                                             upstream_port);
2535                         if (err)
2536                                 return err;
2537                 }
2538
2539                 if (chip->info->ops->set_egress_port) {
2540                         err = chip->info->ops->set_egress_port(chip,
2541                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
2542                                                 upstream_port);
2543                         if (err)
2544                                 return err;
2545
2546                         err = chip->info->ops->set_egress_port(chip,
2547                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
2548                                                 upstream_port);
2549                         if (err)
2550                                 return err;
2551                 }
2552         }
2553
2554         return 0;
2555 }
2556
2557 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2558 {
2559         struct dsa_switch *ds = chip->ds;
2560         int err;
2561         u16 reg;
2562
2563         chip->ports[port].chip = chip;
2564         chip->ports[port].port = port;
2565
2566         /* MAC Forcing register: don't force link, speed, duplex or flow control
2567          * state to any particular values on physical ports, but force the CPU
2568          * port and all DSA ports to their maximum bandwidth and full duplex.
2569          */
2570         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2571                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2572                                                SPEED_MAX, DUPLEX_FULL,
2573                                                PAUSE_OFF,
2574                                                PHY_INTERFACE_MODE_NA);
2575         else
2576                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2577                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2578                                                PAUSE_ON,
2579                                                PHY_INTERFACE_MODE_NA);
2580         if (err)
2581                 return err;
2582
2583         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2584          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2585          * tunneling, determine priority by looking at 802.1p and IP
2586          * priority fields (IP prio has precedence), and set STP state
2587          * to Forwarding.
2588          *
2589          * If this is the CPU link, use DSA or EDSA tagging depending
2590          * on which tagging mode was configured.
2591          *
2592          * If this is a link to another switch, use DSA tagging mode.
2593          *
2594          * If this is the upstream port for this switch, enable
2595          * forwarding of unknown unicasts and multicasts.
2596          */
2597         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2598                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2599                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2600         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2601         if (err)
2602                 return err;
2603
2604         err = mv88e6xxx_setup_port_mode(chip, port);
2605         if (err)
2606                 return err;
2607
2608         err = mv88e6xxx_setup_egress_floods(chip, port);
2609         if (err)
2610                 return err;
2611
2612         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2613          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2614          * untagged frames on this port, do a destination address lookup on all
2615          * received packets as usual, disable ARP mirroring and don't send a
2616          * copy of all transmitted/received frames on this port to the CPU.
2617          */
2618         err = mv88e6xxx_port_set_map_da(chip, port);
2619         if (err)
2620                 return err;
2621
2622         err = mv88e6xxx_setup_upstream_port(chip, port);
2623         if (err)
2624                 return err;
2625
2626         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2627                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2628         if (err)
2629                 return err;
2630
2631         if (chip->info->ops->port_set_jumbo_size) {
2632                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2633                 if (err)
2634                         return err;
2635         }
2636
2637         /* Port Association Vector: when learning source addresses
2638          * of packets, add the address to the address database using
2639          * a port bitmap that has only the bit for this port set and
2640          * the other bits clear.
2641          */
2642         reg = 1 << port;
2643         /* Disable learning for CPU port */
2644         if (dsa_is_cpu_port(ds, port))
2645                 reg = 0;
2646
2647         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2648                                    reg);
2649         if (err)
2650                 return err;
2651
2652         /* Egress rate control 2: disable egress rate control. */
2653         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2654                                    0x0000);
2655         if (err)
2656                 return err;
2657
2658         if (chip->info->ops->port_pause_limit) {
2659                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2660                 if (err)
2661                         return err;
2662         }
2663
2664         if (chip->info->ops->port_disable_learn_limit) {
2665                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2666                 if (err)
2667                         return err;
2668         }
2669
2670         if (chip->info->ops->port_disable_pri_override) {
2671                 err = chip->info->ops->port_disable_pri_override(chip, port);
2672                 if (err)
2673                         return err;
2674         }
2675
2676         if (chip->info->ops->port_tag_remap) {
2677                 err = chip->info->ops->port_tag_remap(chip, port);
2678                 if (err)
2679                         return err;
2680         }
2681
2682         if (chip->info->ops->port_egress_rate_limiting) {
2683                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2684                 if (err)
2685                         return err;
2686         }
2687
2688         if (chip->info->ops->port_setup_message_port) {
2689                 err = chip->info->ops->port_setup_message_port(chip, port);
2690                 if (err)
2691                         return err;
2692         }
2693
2694         /* Port based VLAN map: give each port the same default address
2695          * database, and allow bidirectional communication between the
2696          * CPU and DSA port(s), and the other ports.
2697          */
2698         err = mv88e6xxx_port_set_fid(chip, port, 0);
2699         if (err)
2700                 return err;
2701
2702         err = mv88e6xxx_port_vlan_map(chip, port);
2703         if (err)
2704                 return err;
2705
2706         /* Default VLAN ID and priority: don't set a default VLAN
2707          * ID, and set the default packet priority to zero.
2708          */
2709         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2710 }
2711
2712 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2713 {
2714         struct mv88e6xxx_chip *chip = ds->priv;
2715
2716         if (chip->info->ops->port_set_jumbo_size)
2717                 return 10240;
2718         else if (chip->info->ops->set_max_frame_size)
2719                 return 1632;
2720         return 1522;
2721 }
2722
2723 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2724 {
2725         struct mv88e6xxx_chip *chip = ds->priv;
2726         int ret = 0;
2727
2728         mv88e6xxx_reg_lock(chip);
2729         if (chip->info->ops->port_set_jumbo_size)
2730                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2731         else if (chip->info->ops->set_max_frame_size)
2732                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2733         else
2734                 if (new_mtu > 1522)
2735                         ret = -EINVAL;
2736         mv88e6xxx_reg_unlock(chip);
2737
2738         return ret;
2739 }
2740
2741 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2742                                  struct phy_device *phydev)
2743 {
2744         struct mv88e6xxx_chip *chip = ds->priv;
2745         int err;
2746
2747         mv88e6xxx_reg_lock(chip);
2748         err = mv88e6xxx_serdes_power(chip, port, true);
2749         mv88e6xxx_reg_unlock(chip);
2750
2751         return err;
2752 }
2753
2754 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2755 {
2756         struct mv88e6xxx_chip *chip = ds->priv;
2757
2758         mv88e6xxx_reg_lock(chip);
2759         if (mv88e6xxx_serdes_power(chip, port, false))
2760                 dev_err(chip->dev, "failed to power off SERDES\n");
2761         mv88e6xxx_reg_unlock(chip);
2762 }
2763
2764 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2765                                      unsigned int ageing_time)
2766 {
2767         struct mv88e6xxx_chip *chip = ds->priv;
2768         int err;
2769
2770         mv88e6xxx_reg_lock(chip);
2771         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2772         mv88e6xxx_reg_unlock(chip);
2773
2774         return err;
2775 }
2776
2777 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2778 {
2779         int err;
2780
2781         /* Initialize the statistics unit */
2782         if (chip->info->ops->stats_set_histogram) {
2783                 err = chip->info->ops->stats_set_histogram(chip);
2784                 if (err)
2785                         return err;
2786         }
2787
2788         return mv88e6xxx_g1_stats_clear(chip);
2789 }
2790
2791 /* Check if the errata has already been applied. */
2792 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2793 {
2794         int port;
2795         int err;
2796         u16 val;
2797
2798         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2799                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2800                 if (err) {
2801                         dev_err(chip->dev,
2802                                 "Error reading hidden register: %d\n", err);
2803                         return false;
2804                 }
2805                 if (val != 0x01c0)
2806                         return false;
2807         }
2808
2809         return true;
2810 }
2811
2812 /* The 6390 copper ports have an errata which require poking magic
2813  * values into undocumented hidden registers and then performing a
2814  * software reset.
2815  */
2816 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2817 {
2818         int port;
2819         int err;
2820
2821         if (mv88e6390_setup_errata_applied(chip))
2822                 return 0;
2823
2824         /* Set the ports into blocking mode */
2825         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2826                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2827                 if (err)
2828                         return err;
2829         }
2830
2831         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2832                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2833                 if (err)
2834                         return err;
2835         }
2836
2837         return mv88e6xxx_software_reset(chip);
2838 }
2839
2840 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2841 {
2842         mv88e6xxx_teardown_devlink_params(ds);
2843         dsa_devlink_resources_unregister(ds);
2844         mv88e6xxx_teardown_devlink_regions(ds);
2845 }
2846
2847 static int mv88e6xxx_setup(struct dsa_switch *ds)
2848 {
2849         struct mv88e6xxx_chip *chip = ds->priv;
2850         u8 cmode;
2851         int err;
2852         int i;
2853
2854         chip->ds = ds;
2855         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2856
2857         mv88e6xxx_reg_lock(chip);
2858
2859         if (chip->info->ops->setup_errata) {
2860                 err = chip->info->ops->setup_errata(chip);
2861                 if (err)
2862                         goto unlock;
2863         }
2864
2865         /* Cache the cmode of each port. */
2866         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2867                 if (chip->info->ops->port_get_cmode) {
2868                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2869                         if (err)
2870                                 goto unlock;
2871
2872                         chip->ports[i].cmode = cmode;
2873                 }
2874         }
2875
2876         /* Setup Switch Port Registers */
2877         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2878                 if (dsa_is_unused_port(ds, i))
2879                         continue;
2880
2881                 /* Prevent the use of an invalid port. */
2882                 if (mv88e6xxx_is_invalid_port(chip, i)) {
2883                         dev_err(chip->dev, "port %d is invalid\n", i);
2884                         err = -EINVAL;
2885                         goto unlock;
2886                 }
2887
2888                 err = mv88e6xxx_setup_port(chip, i);
2889                 if (err)
2890                         goto unlock;
2891         }
2892
2893         err = mv88e6xxx_irl_setup(chip);
2894         if (err)
2895                 goto unlock;
2896
2897         err = mv88e6xxx_mac_setup(chip);
2898         if (err)
2899                 goto unlock;
2900
2901         err = mv88e6xxx_phy_setup(chip);
2902         if (err)
2903                 goto unlock;
2904
2905         err = mv88e6xxx_vtu_setup(chip);
2906         if (err)
2907                 goto unlock;
2908
2909         err = mv88e6xxx_pvt_setup(chip);
2910         if (err)
2911                 goto unlock;
2912
2913         err = mv88e6xxx_atu_setup(chip);
2914         if (err)
2915                 goto unlock;
2916
2917         err = mv88e6xxx_broadcast_setup(chip, 0);
2918         if (err)
2919                 goto unlock;
2920
2921         err = mv88e6xxx_pot_setup(chip);
2922         if (err)
2923                 goto unlock;
2924
2925         err = mv88e6xxx_rmu_setup(chip);
2926         if (err)
2927                 goto unlock;
2928
2929         err = mv88e6xxx_rsvd2cpu_setup(chip);
2930         if (err)
2931                 goto unlock;
2932
2933         err = mv88e6xxx_trunk_setup(chip);
2934         if (err)
2935                 goto unlock;
2936
2937         err = mv88e6xxx_devmap_setup(chip);
2938         if (err)
2939                 goto unlock;
2940
2941         err = mv88e6xxx_pri_setup(chip);
2942         if (err)
2943                 goto unlock;
2944
2945         /* Setup PTP Hardware Clock and timestamping */
2946         if (chip->info->ptp_support) {
2947                 err = mv88e6xxx_ptp_setup(chip);
2948                 if (err)
2949                         goto unlock;
2950
2951                 err = mv88e6xxx_hwtstamp_setup(chip);
2952                 if (err)
2953                         goto unlock;
2954         }
2955
2956         err = mv88e6xxx_stats_setup(chip);
2957         if (err)
2958                 goto unlock;
2959
2960 unlock:
2961         mv88e6xxx_reg_unlock(chip);
2962
2963         if (err)
2964                 return err;
2965
2966         /* Have to be called without holding the register lock, since
2967          * they take the devlink lock, and we later take the locks in
2968          * the reverse order when getting/setting parameters or
2969          * resource occupancy.
2970          */
2971         err = mv88e6xxx_setup_devlink_resources(ds);
2972         if (err)
2973                 return err;
2974
2975         err = mv88e6xxx_setup_devlink_params(ds);
2976         if (err)
2977                 goto out_resources;
2978
2979         err = mv88e6xxx_setup_devlink_regions(ds);
2980         if (err)
2981                 goto out_params;
2982
2983         return 0;
2984
2985 out_params:
2986         mv88e6xxx_teardown_devlink_params(ds);
2987 out_resources:
2988         dsa_devlink_resources_unregister(ds);
2989
2990         return err;
2991 }
2992
2993 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2994 {
2995         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2996         struct mv88e6xxx_chip *chip = mdio_bus->chip;
2997         u16 val;
2998         int err;
2999
3000         if (!chip->info->ops->phy_read)
3001                 return -EOPNOTSUPP;
3002
3003         mv88e6xxx_reg_lock(chip);
3004         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3005         mv88e6xxx_reg_unlock(chip);
3006
3007         if (reg == MII_PHYSID2) {
3008                 /* Some internal PHYs don't have a model number. */
3009                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3010                         /* Then there is the 6165 family. It gets is
3011                          * PHYs correct. But it can also have two
3012                          * SERDES interfaces in the PHY address
3013                          * space. And these don't have a model
3014                          * number. But they are not PHYs, so we don't
3015                          * want to give them something a PHY driver
3016                          * will recognise.
3017                          *
3018                          * Use the mv88e6390 family model number
3019                          * instead, for anything which really could be
3020                          * a PHY,
3021                          */
3022                         if (!(val & 0x3f0))
3023                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3024         }
3025
3026         return err ? err : val;
3027 }
3028
3029 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3030 {
3031         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3032         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3033         int err;
3034
3035         if (!chip->info->ops->phy_write)
3036                 return -EOPNOTSUPP;
3037
3038         mv88e6xxx_reg_lock(chip);
3039         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3040         mv88e6xxx_reg_unlock(chip);
3041
3042         return err;
3043 }
3044
3045 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3046                                    struct device_node *np,
3047                                    bool external)
3048 {
3049         static int index;
3050         struct mv88e6xxx_mdio_bus *mdio_bus;
3051         struct mii_bus *bus;
3052         int err;
3053
3054         if (external) {
3055                 mv88e6xxx_reg_lock(chip);
3056                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3057                 mv88e6xxx_reg_unlock(chip);
3058
3059                 if (err)
3060                         return err;
3061         }
3062
3063         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3064         if (!bus)
3065                 return -ENOMEM;
3066
3067         mdio_bus = bus->priv;
3068         mdio_bus->bus = bus;
3069         mdio_bus->chip = chip;
3070         INIT_LIST_HEAD(&mdio_bus->list);
3071         mdio_bus->external = external;
3072
3073         if (np) {
3074                 bus->name = np->full_name;
3075                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3076         } else {
3077                 bus->name = "mv88e6xxx SMI";
3078                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3079         }
3080
3081         bus->read = mv88e6xxx_mdio_read;
3082         bus->write = mv88e6xxx_mdio_write;
3083         bus->parent = chip->dev;
3084
3085         if (!external) {
3086                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3087                 if (err)
3088                         return err;
3089         }
3090
3091         err = of_mdiobus_register(bus, np);
3092         if (err) {
3093                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3094                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3095                 return err;
3096         }
3097
3098         if (external)
3099                 list_add_tail(&mdio_bus->list, &chip->mdios);
3100         else
3101                 list_add(&mdio_bus->list, &chip->mdios);
3102
3103         return 0;
3104 }
3105
3106 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3107
3108 {
3109         struct mv88e6xxx_mdio_bus *mdio_bus;
3110         struct mii_bus *bus;
3111
3112         list_for_each_entry(mdio_bus, &chip->mdios, list) {
3113                 bus = mdio_bus->bus;
3114
3115                 if (!mdio_bus->external)
3116                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3117
3118                 mdiobus_unregister(bus);
3119         }
3120 }
3121
3122 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3123                                     struct device_node *np)
3124 {
3125         struct device_node *child;
3126         int err;
3127
3128         /* Always register one mdio bus for the internal/default mdio
3129          * bus. This maybe represented in the device tree, but is
3130          * optional.
3131          */
3132         child = of_get_child_by_name(np, "mdio");
3133         err = mv88e6xxx_mdio_register(chip, child, false);
3134         if (err)
3135                 return err;
3136
3137         /* Walk the device tree, and see if there are any other nodes
3138          * which say they are compatible with the external mdio
3139          * bus.
3140          */
3141         for_each_available_child_of_node(np, child) {
3142                 if (of_device_is_compatible(
3143                             child, "marvell,mv88e6xxx-mdio-external")) {
3144                         err = mv88e6xxx_mdio_register(chip, child, true);
3145                         if (err) {
3146                                 mv88e6xxx_mdios_unregister(chip);
3147                                 of_node_put(child);
3148                                 return err;
3149                         }
3150                 }
3151         }
3152
3153         return 0;
3154 }
3155
3156 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3157 {
3158         struct mv88e6xxx_chip *chip = ds->priv;
3159
3160         return chip->eeprom_len;
3161 }
3162
3163 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3164                                 struct ethtool_eeprom *eeprom, u8 *data)
3165 {
3166         struct mv88e6xxx_chip *chip = ds->priv;
3167         int err;
3168
3169         if (!chip->info->ops->get_eeprom)
3170                 return -EOPNOTSUPP;
3171
3172         mv88e6xxx_reg_lock(chip);
3173         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3174         mv88e6xxx_reg_unlock(chip);
3175
3176         if (err)
3177                 return err;
3178
3179         eeprom->magic = 0xc3ec4951;
3180
3181         return 0;
3182 }
3183
3184 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3185                                 struct ethtool_eeprom *eeprom, u8 *data)
3186 {
3187         struct mv88e6xxx_chip *chip = ds->priv;
3188         int err;
3189
3190         if (!chip->info->ops->set_eeprom)
3191                 return -EOPNOTSUPP;
3192
3193         if (eeprom->magic != 0xc3ec4951)
3194                 return -EINVAL;
3195
3196         mv88e6xxx_reg_lock(chip);
3197         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3198         mv88e6xxx_reg_unlock(chip);
3199
3200         return err;
3201 }
3202
3203 static const struct mv88e6xxx_ops mv88e6085_ops = {
3204         /* MV88E6XXX_FAMILY_6097 */
3205         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3206         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3207         .irl_init_all = mv88e6352_g2_irl_init_all,
3208         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3209         .phy_read = mv88e6185_phy_ppu_read,
3210         .phy_write = mv88e6185_phy_ppu_write,
3211         .port_set_link = mv88e6xxx_port_set_link,
3212         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3213         .port_tag_remap = mv88e6095_port_tag_remap,
3214         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3215         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3216         .port_set_ether_type = mv88e6351_port_set_ether_type,
3217         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3218         .port_pause_limit = mv88e6097_port_pause_limit,
3219         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3220         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3221         .port_get_cmode = mv88e6185_port_get_cmode,
3222         .port_setup_message_port = mv88e6xxx_setup_message_port,
3223         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3224         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3225         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3226         .stats_get_strings = mv88e6095_stats_get_strings,
3227         .stats_get_stats = mv88e6095_stats_get_stats,
3228         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3229         .set_egress_port = mv88e6095_g1_set_egress_port,
3230         .watchdog_ops = &mv88e6097_watchdog_ops,
3231         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3232         .pot_clear = mv88e6xxx_g2_pot_clear,
3233         .ppu_enable = mv88e6185_g1_ppu_enable,
3234         .ppu_disable = mv88e6185_g1_ppu_disable,
3235         .reset = mv88e6185_g1_reset,
3236         .rmu_disable = mv88e6085_g1_rmu_disable,
3237         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3238         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3239         .phylink_validate = mv88e6185_phylink_validate,
3240         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3241 };
3242
3243 static const struct mv88e6xxx_ops mv88e6095_ops = {
3244         /* MV88E6XXX_FAMILY_6095 */
3245         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3246         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3247         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3248         .phy_read = mv88e6185_phy_ppu_read,
3249         .phy_write = mv88e6185_phy_ppu_write,
3250         .port_set_link = mv88e6xxx_port_set_link,
3251         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3252         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3253         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3254         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3255         .port_get_cmode = mv88e6185_port_get_cmode,
3256         .port_setup_message_port = mv88e6xxx_setup_message_port,
3257         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3258         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3259         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3260         .stats_get_strings = mv88e6095_stats_get_strings,
3261         .stats_get_stats = mv88e6095_stats_get_stats,
3262         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3263         .ppu_enable = mv88e6185_g1_ppu_enable,
3264         .ppu_disable = mv88e6185_g1_ppu_disable,
3265         .reset = mv88e6185_g1_reset,
3266         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3267         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3268         .phylink_validate = mv88e6185_phylink_validate,
3269         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3270 };
3271
3272 static const struct mv88e6xxx_ops mv88e6097_ops = {
3273         /* MV88E6XXX_FAMILY_6097 */
3274         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3275         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3276         .irl_init_all = mv88e6352_g2_irl_init_all,
3277         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3278         .phy_read = mv88e6xxx_g2_smi_phy_read,
3279         .phy_write = mv88e6xxx_g2_smi_phy_write,
3280         .port_set_link = mv88e6xxx_port_set_link,
3281         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3282         .port_tag_remap = mv88e6095_port_tag_remap,
3283         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3284         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3285         .port_set_ether_type = mv88e6351_port_set_ether_type,
3286         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3287         .port_pause_limit = mv88e6097_port_pause_limit,
3288         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3289         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3290         .port_get_cmode = mv88e6185_port_get_cmode,
3291         .port_setup_message_port = mv88e6xxx_setup_message_port,
3292         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3293         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3294         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3295         .stats_get_strings = mv88e6095_stats_get_strings,
3296         .stats_get_stats = mv88e6095_stats_get_stats,
3297         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3298         .set_egress_port = mv88e6095_g1_set_egress_port,
3299         .watchdog_ops = &mv88e6097_watchdog_ops,
3300         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3301         .pot_clear = mv88e6xxx_g2_pot_clear,
3302         .reset = mv88e6352_g1_reset,
3303         .rmu_disable = mv88e6085_g1_rmu_disable,
3304         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3305         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3306         .phylink_validate = mv88e6185_phylink_validate,
3307         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3308 };
3309
3310 static const struct mv88e6xxx_ops mv88e6123_ops = {
3311         /* MV88E6XXX_FAMILY_6165 */
3312         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3313         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3314         .irl_init_all = mv88e6352_g2_irl_init_all,
3315         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3316         .phy_read = mv88e6xxx_g2_smi_phy_read,
3317         .phy_write = mv88e6xxx_g2_smi_phy_write,
3318         .port_set_link = mv88e6xxx_port_set_link,
3319         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3320         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3321         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3322         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3323         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3324         .port_get_cmode = mv88e6185_port_get_cmode,
3325         .port_setup_message_port = mv88e6xxx_setup_message_port,
3326         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3327         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3328         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3329         .stats_get_strings = mv88e6095_stats_get_strings,
3330         .stats_get_stats = mv88e6095_stats_get_stats,
3331         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3332         .set_egress_port = mv88e6095_g1_set_egress_port,
3333         .watchdog_ops = &mv88e6097_watchdog_ops,
3334         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3335         .pot_clear = mv88e6xxx_g2_pot_clear,
3336         .reset = mv88e6352_g1_reset,
3337         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3338         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3339         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3340         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3341         .phylink_validate = mv88e6185_phylink_validate,
3342         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3343 };
3344
3345 static const struct mv88e6xxx_ops mv88e6131_ops = {
3346         /* MV88E6XXX_FAMILY_6185 */
3347         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3348         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3349         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3350         .phy_read = mv88e6185_phy_ppu_read,
3351         .phy_write = mv88e6185_phy_ppu_write,
3352         .port_set_link = mv88e6xxx_port_set_link,
3353         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3354         .port_tag_remap = mv88e6095_port_tag_remap,
3355         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3356         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3357         .port_set_ether_type = mv88e6351_port_set_ether_type,
3358         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3359         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3360         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3361         .port_pause_limit = mv88e6097_port_pause_limit,
3362         .port_set_pause = mv88e6185_port_set_pause,
3363         .port_get_cmode = mv88e6185_port_get_cmode,
3364         .port_setup_message_port = mv88e6xxx_setup_message_port,
3365         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3366         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3367         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3368         .stats_get_strings = mv88e6095_stats_get_strings,
3369         .stats_get_stats = mv88e6095_stats_get_stats,
3370         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3371         .set_egress_port = mv88e6095_g1_set_egress_port,
3372         .watchdog_ops = &mv88e6097_watchdog_ops,
3373         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3374         .ppu_enable = mv88e6185_g1_ppu_enable,
3375         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3376         .ppu_disable = mv88e6185_g1_ppu_disable,
3377         .reset = mv88e6185_g1_reset,
3378         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3379         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3380         .phylink_validate = mv88e6185_phylink_validate,
3381 };
3382
3383 static const struct mv88e6xxx_ops mv88e6141_ops = {
3384         /* MV88E6XXX_FAMILY_6341 */
3385         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3386         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3387         .irl_init_all = mv88e6352_g2_irl_init_all,
3388         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3389         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3390         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3391         .phy_read = mv88e6xxx_g2_smi_phy_read,
3392         .phy_write = mv88e6xxx_g2_smi_phy_write,
3393         .port_set_link = mv88e6xxx_port_set_link,
3394         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3395         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3396         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3397         .port_tag_remap = mv88e6095_port_tag_remap,
3398         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3399         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3400         .port_set_ether_type = mv88e6351_port_set_ether_type,
3401         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3402         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3403         .port_pause_limit = mv88e6097_port_pause_limit,
3404         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3405         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3406         .port_get_cmode = mv88e6352_port_get_cmode,
3407         .port_set_cmode = mv88e6341_port_set_cmode,
3408         .port_setup_message_port = mv88e6xxx_setup_message_port,
3409         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3410         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3411         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3412         .stats_get_strings = mv88e6320_stats_get_strings,
3413         .stats_get_stats = mv88e6390_stats_get_stats,
3414         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3415         .set_egress_port = mv88e6390_g1_set_egress_port,
3416         .watchdog_ops = &mv88e6390_watchdog_ops,
3417         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3418         .pot_clear = mv88e6xxx_g2_pot_clear,
3419         .reset = mv88e6352_g1_reset,
3420         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3421         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3422         .serdes_power = mv88e6390_serdes_power,
3423         .serdes_get_lane = mv88e6341_serdes_get_lane,
3424         /* Check status register pause & lpa register */
3425         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3426         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3427         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3428         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3429         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3430         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3431         .serdes_irq_status = mv88e6390_serdes_irq_status,
3432         .gpio_ops = &mv88e6352_gpio_ops,
3433         .phylink_validate = mv88e6341_phylink_validate,
3434 };
3435
3436 static const struct mv88e6xxx_ops mv88e6161_ops = {
3437         /* MV88E6XXX_FAMILY_6165 */
3438         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3439         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3440         .irl_init_all = mv88e6352_g2_irl_init_all,
3441         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3442         .phy_read = mv88e6xxx_g2_smi_phy_read,
3443         .phy_write = mv88e6xxx_g2_smi_phy_write,
3444         .port_set_link = mv88e6xxx_port_set_link,
3445         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3446         .port_tag_remap = mv88e6095_port_tag_remap,
3447         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3448         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3449         .port_set_ether_type = mv88e6351_port_set_ether_type,
3450         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3451         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3452         .port_pause_limit = mv88e6097_port_pause_limit,
3453         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3454         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3455         .port_get_cmode = mv88e6185_port_get_cmode,
3456         .port_setup_message_port = mv88e6xxx_setup_message_port,
3457         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3458         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3459         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3460         .stats_get_strings = mv88e6095_stats_get_strings,
3461         .stats_get_stats = mv88e6095_stats_get_stats,
3462         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3463         .set_egress_port = mv88e6095_g1_set_egress_port,
3464         .watchdog_ops = &mv88e6097_watchdog_ops,
3465         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3466         .pot_clear = mv88e6xxx_g2_pot_clear,
3467         .reset = mv88e6352_g1_reset,
3468         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3469         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3470         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3471         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3472         .avb_ops = &mv88e6165_avb_ops,
3473         .ptp_ops = &mv88e6165_ptp_ops,
3474         .phylink_validate = mv88e6185_phylink_validate,
3475 };
3476
3477 static const struct mv88e6xxx_ops mv88e6165_ops = {
3478         /* MV88E6XXX_FAMILY_6165 */
3479         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3480         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3481         .irl_init_all = mv88e6352_g2_irl_init_all,
3482         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3483         .phy_read = mv88e6165_phy_read,
3484         .phy_write = mv88e6165_phy_write,
3485         .port_set_link = mv88e6xxx_port_set_link,
3486         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3487         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3488         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3489         .port_get_cmode = mv88e6185_port_get_cmode,
3490         .port_setup_message_port = mv88e6xxx_setup_message_port,
3491         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3492         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3493         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3494         .stats_get_strings = mv88e6095_stats_get_strings,
3495         .stats_get_stats = mv88e6095_stats_get_stats,
3496         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3497         .set_egress_port = mv88e6095_g1_set_egress_port,
3498         .watchdog_ops = &mv88e6097_watchdog_ops,
3499         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3500         .pot_clear = mv88e6xxx_g2_pot_clear,
3501         .reset = mv88e6352_g1_reset,
3502         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3503         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3504         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3505         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3506         .avb_ops = &mv88e6165_avb_ops,
3507         .ptp_ops = &mv88e6165_ptp_ops,
3508         .phylink_validate = mv88e6185_phylink_validate,
3509 };
3510
3511 static const struct mv88e6xxx_ops mv88e6171_ops = {
3512         /* MV88E6XXX_FAMILY_6351 */
3513         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3514         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3515         .irl_init_all = mv88e6352_g2_irl_init_all,
3516         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3517         .phy_read = mv88e6xxx_g2_smi_phy_read,
3518         .phy_write = mv88e6xxx_g2_smi_phy_write,
3519         .port_set_link = mv88e6xxx_port_set_link,
3520         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3521         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3522         .port_tag_remap = mv88e6095_port_tag_remap,
3523         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3524         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3525         .port_set_ether_type = mv88e6351_port_set_ether_type,
3526         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3527         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3528         .port_pause_limit = mv88e6097_port_pause_limit,
3529         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3530         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3531         .port_get_cmode = mv88e6352_port_get_cmode,
3532         .port_setup_message_port = mv88e6xxx_setup_message_port,
3533         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3534         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3535         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3536         .stats_get_strings = mv88e6095_stats_get_strings,
3537         .stats_get_stats = mv88e6095_stats_get_stats,
3538         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3539         .set_egress_port = mv88e6095_g1_set_egress_port,
3540         .watchdog_ops = &mv88e6097_watchdog_ops,
3541         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3542         .pot_clear = mv88e6xxx_g2_pot_clear,
3543         .reset = mv88e6352_g1_reset,
3544         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3545         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3546         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3547         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3548         .phylink_validate = mv88e6185_phylink_validate,
3549 };
3550
3551 static const struct mv88e6xxx_ops mv88e6172_ops = {
3552         /* MV88E6XXX_FAMILY_6352 */
3553         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3554         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3555         .irl_init_all = mv88e6352_g2_irl_init_all,
3556         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3557         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3558         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3559         .phy_read = mv88e6xxx_g2_smi_phy_read,
3560         .phy_write = mv88e6xxx_g2_smi_phy_write,
3561         .port_set_link = mv88e6xxx_port_set_link,
3562         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3563         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3564         .port_tag_remap = mv88e6095_port_tag_remap,
3565         .port_set_policy = mv88e6352_port_set_policy,
3566         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3567         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3568         .port_set_ether_type = mv88e6351_port_set_ether_type,
3569         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3570         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3571         .port_pause_limit = mv88e6097_port_pause_limit,
3572         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3573         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3574         .port_get_cmode = mv88e6352_port_get_cmode,
3575         .port_setup_message_port = mv88e6xxx_setup_message_port,
3576         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3577         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3578         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3579         .stats_get_strings = mv88e6095_stats_get_strings,
3580         .stats_get_stats = mv88e6095_stats_get_stats,
3581         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3582         .set_egress_port = mv88e6095_g1_set_egress_port,
3583         .watchdog_ops = &mv88e6097_watchdog_ops,
3584         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3585         .pot_clear = mv88e6xxx_g2_pot_clear,
3586         .reset = mv88e6352_g1_reset,
3587         .rmu_disable = mv88e6352_g1_rmu_disable,
3588         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3589         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3590         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3591         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3592         .serdes_get_lane = mv88e6352_serdes_get_lane,
3593         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3594         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3595         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3596         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3597         .serdes_power = mv88e6352_serdes_power,
3598         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3599         .serdes_get_regs = mv88e6352_serdes_get_regs,
3600         .gpio_ops = &mv88e6352_gpio_ops,
3601         .phylink_validate = mv88e6352_phylink_validate,
3602 };
3603
3604 static const struct mv88e6xxx_ops mv88e6175_ops = {
3605         /* MV88E6XXX_FAMILY_6351 */
3606         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3607         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3608         .irl_init_all = mv88e6352_g2_irl_init_all,
3609         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3610         .phy_read = mv88e6xxx_g2_smi_phy_read,
3611         .phy_write = mv88e6xxx_g2_smi_phy_write,
3612         .port_set_link = mv88e6xxx_port_set_link,
3613         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3614         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3615         .port_tag_remap = mv88e6095_port_tag_remap,
3616         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3617         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3618         .port_set_ether_type = mv88e6351_port_set_ether_type,
3619         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3620         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3621         .port_pause_limit = mv88e6097_port_pause_limit,
3622         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3623         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3624         .port_get_cmode = mv88e6352_port_get_cmode,
3625         .port_setup_message_port = mv88e6xxx_setup_message_port,
3626         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3627         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3628         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3629         .stats_get_strings = mv88e6095_stats_get_strings,
3630         .stats_get_stats = mv88e6095_stats_get_stats,
3631         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3632         .set_egress_port = mv88e6095_g1_set_egress_port,
3633         .watchdog_ops = &mv88e6097_watchdog_ops,
3634         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3635         .pot_clear = mv88e6xxx_g2_pot_clear,
3636         .reset = mv88e6352_g1_reset,
3637         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3638         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3639         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3640         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3641         .phylink_validate = mv88e6185_phylink_validate,
3642 };
3643
3644 static const struct mv88e6xxx_ops mv88e6176_ops = {
3645         /* MV88E6XXX_FAMILY_6352 */
3646         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3647         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3648         .irl_init_all = mv88e6352_g2_irl_init_all,
3649         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3650         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3651         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3652         .phy_read = mv88e6xxx_g2_smi_phy_read,
3653         .phy_write = mv88e6xxx_g2_smi_phy_write,
3654         .port_set_link = mv88e6xxx_port_set_link,
3655         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3656         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3657         .port_tag_remap = mv88e6095_port_tag_remap,
3658         .port_set_policy = mv88e6352_port_set_policy,
3659         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3660         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3661         .port_set_ether_type = mv88e6351_port_set_ether_type,
3662         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3663         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3664         .port_pause_limit = mv88e6097_port_pause_limit,
3665         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3666         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3667         .port_get_cmode = mv88e6352_port_get_cmode,
3668         .port_setup_message_port = mv88e6xxx_setup_message_port,
3669         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3670         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3671         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3672         .stats_get_strings = mv88e6095_stats_get_strings,
3673         .stats_get_stats = mv88e6095_stats_get_stats,
3674         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3675         .set_egress_port = mv88e6095_g1_set_egress_port,
3676         .watchdog_ops = &mv88e6097_watchdog_ops,
3677         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3678         .pot_clear = mv88e6xxx_g2_pot_clear,
3679         .reset = mv88e6352_g1_reset,
3680         .rmu_disable = mv88e6352_g1_rmu_disable,
3681         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3682         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3683         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3684         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3685         .serdes_get_lane = mv88e6352_serdes_get_lane,
3686         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3687         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3688         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3689         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3690         .serdes_power = mv88e6352_serdes_power,
3691         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3692         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3693         .serdes_irq_status = mv88e6352_serdes_irq_status,
3694         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3695         .serdes_get_regs = mv88e6352_serdes_get_regs,
3696         .gpio_ops = &mv88e6352_gpio_ops,
3697         .phylink_validate = mv88e6352_phylink_validate,
3698 };
3699
3700 static const struct mv88e6xxx_ops mv88e6185_ops = {
3701         /* MV88E6XXX_FAMILY_6185 */
3702         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3703         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3704         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3705         .phy_read = mv88e6185_phy_ppu_read,
3706         .phy_write = mv88e6185_phy_ppu_write,
3707         .port_set_link = mv88e6xxx_port_set_link,
3708         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3709         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3710         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3711         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3712         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3713         .port_set_pause = mv88e6185_port_set_pause,
3714         .port_get_cmode = mv88e6185_port_get_cmode,
3715         .port_setup_message_port = mv88e6xxx_setup_message_port,
3716         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3717         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3718         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3719         .stats_get_strings = mv88e6095_stats_get_strings,
3720         .stats_get_stats = mv88e6095_stats_get_stats,
3721         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3722         .set_egress_port = mv88e6095_g1_set_egress_port,
3723         .watchdog_ops = &mv88e6097_watchdog_ops,
3724         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3725         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3726         .ppu_enable = mv88e6185_g1_ppu_enable,
3727         .ppu_disable = mv88e6185_g1_ppu_disable,
3728         .reset = mv88e6185_g1_reset,
3729         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3730         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3731         .phylink_validate = mv88e6185_phylink_validate,
3732         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3733 };
3734
3735 static const struct mv88e6xxx_ops mv88e6190_ops = {
3736         /* MV88E6XXX_FAMILY_6390 */
3737         .setup_errata = mv88e6390_setup_errata,
3738         .irl_init_all = mv88e6390_g2_irl_init_all,
3739         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3740         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3741         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3742         .phy_read = mv88e6xxx_g2_smi_phy_read,
3743         .phy_write = mv88e6xxx_g2_smi_phy_write,
3744         .port_set_link = mv88e6xxx_port_set_link,
3745         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3746         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3747         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3748         .port_tag_remap = mv88e6390_port_tag_remap,
3749         .port_set_policy = mv88e6352_port_set_policy,
3750         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3751         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3752         .port_set_ether_type = mv88e6351_port_set_ether_type,
3753         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3754         .port_pause_limit = mv88e6390_port_pause_limit,
3755         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3756         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3757         .port_get_cmode = mv88e6352_port_get_cmode,
3758         .port_set_cmode = mv88e6390_port_set_cmode,
3759         .port_setup_message_port = mv88e6xxx_setup_message_port,
3760         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3761         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3762         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3763         .stats_get_strings = mv88e6320_stats_get_strings,
3764         .stats_get_stats = mv88e6390_stats_get_stats,
3765         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3766         .set_egress_port = mv88e6390_g1_set_egress_port,
3767         .watchdog_ops = &mv88e6390_watchdog_ops,
3768         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3769         .pot_clear = mv88e6xxx_g2_pot_clear,
3770         .reset = mv88e6352_g1_reset,
3771         .rmu_disable = mv88e6390_g1_rmu_disable,
3772         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3773         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3774         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3775         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3776         .serdes_power = mv88e6390_serdes_power,
3777         .serdes_get_lane = mv88e6390_serdes_get_lane,
3778         /* Check status register pause & lpa register */
3779         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3780         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3781         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3782         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3783         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3784         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3785         .serdes_irq_status = mv88e6390_serdes_irq_status,
3786         .serdes_get_strings = mv88e6390_serdes_get_strings,
3787         .serdes_get_stats = mv88e6390_serdes_get_stats,
3788         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3789         .serdes_get_regs = mv88e6390_serdes_get_regs,
3790         .gpio_ops = &mv88e6352_gpio_ops,
3791         .phylink_validate = mv88e6390_phylink_validate,
3792 };
3793
3794 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3795         /* MV88E6XXX_FAMILY_6390 */
3796         .setup_errata = mv88e6390_setup_errata,
3797         .irl_init_all = mv88e6390_g2_irl_init_all,
3798         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3799         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3800         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3801         .phy_read = mv88e6xxx_g2_smi_phy_read,
3802         .phy_write = mv88e6xxx_g2_smi_phy_write,
3803         .port_set_link = mv88e6xxx_port_set_link,
3804         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3805         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3806         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3807         .port_tag_remap = mv88e6390_port_tag_remap,
3808         .port_set_policy = mv88e6352_port_set_policy,
3809         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3810         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3811         .port_set_ether_type = mv88e6351_port_set_ether_type,
3812         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3813         .port_pause_limit = mv88e6390_port_pause_limit,
3814         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3815         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3816         .port_get_cmode = mv88e6352_port_get_cmode,
3817         .port_set_cmode = mv88e6390x_port_set_cmode,
3818         .port_setup_message_port = mv88e6xxx_setup_message_port,
3819         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3820         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3821         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3822         .stats_get_strings = mv88e6320_stats_get_strings,
3823         .stats_get_stats = mv88e6390_stats_get_stats,
3824         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3825         .set_egress_port = mv88e6390_g1_set_egress_port,
3826         .watchdog_ops = &mv88e6390_watchdog_ops,
3827         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3828         .pot_clear = mv88e6xxx_g2_pot_clear,
3829         .reset = mv88e6352_g1_reset,
3830         .rmu_disable = mv88e6390_g1_rmu_disable,
3831         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3832         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3833         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3834         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3835         .serdes_power = mv88e6390_serdes_power,
3836         .serdes_get_lane = mv88e6390x_serdes_get_lane,
3837         /* Check status register pause & lpa register */
3838         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3839         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3840         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3841         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3842         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3843         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3844         .serdes_irq_status = mv88e6390_serdes_irq_status,
3845         .serdes_get_strings = mv88e6390_serdes_get_strings,
3846         .serdes_get_stats = mv88e6390_serdes_get_stats,
3847         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3848         .serdes_get_regs = mv88e6390_serdes_get_regs,
3849         .gpio_ops = &mv88e6352_gpio_ops,
3850         .phylink_validate = mv88e6390x_phylink_validate,
3851 };
3852
3853 static const struct mv88e6xxx_ops mv88e6191_ops = {
3854         /* MV88E6XXX_FAMILY_6390 */
3855         .setup_errata = mv88e6390_setup_errata,
3856         .irl_init_all = mv88e6390_g2_irl_init_all,
3857         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3858         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3859         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3860         .phy_read = mv88e6xxx_g2_smi_phy_read,
3861         .phy_write = mv88e6xxx_g2_smi_phy_write,
3862         .port_set_link = mv88e6xxx_port_set_link,
3863         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3864         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3865         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3866         .port_tag_remap = mv88e6390_port_tag_remap,
3867         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3868         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3869         .port_set_ether_type = mv88e6351_port_set_ether_type,
3870         .port_pause_limit = mv88e6390_port_pause_limit,
3871         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3872         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3873         .port_get_cmode = mv88e6352_port_get_cmode,
3874         .port_set_cmode = mv88e6390_port_set_cmode,
3875         .port_setup_message_port = mv88e6xxx_setup_message_port,
3876         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3877         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3878         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3879         .stats_get_strings = mv88e6320_stats_get_strings,
3880         .stats_get_stats = mv88e6390_stats_get_stats,
3881         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3882         .set_egress_port = mv88e6390_g1_set_egress_port,
3883         .watchdog_ops = &mv88e6390_watchdog_ops,
3884         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3885         .pot_clear = mv88e6xxx_g2_pot_clear,
3886         .reset = mv88e6352_g1_reset,
3887         .rmu_disable = mv88e6390_g1_rmu_disable,
3888         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3889         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3890         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3891         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3892         .serdes_power = mv88e6390_serdes_power,
3893         .serdes_get_lane = mv88e6390_serdes_get_lane,
3894         /* Check status register pause & lpa register */
3895         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3896         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3897         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3898         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3899         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3900         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3901         .serdes_irq_status = mv88e6390_serdes_irq_status,
3902         .serdes_get_strings = mv88e6390_serdes_get_strings,
3903         .serdes_get_stats = mv88e6390_serdes_get_stats,
3904         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3905         .serdes_get_regs = mv88e6390_serdes_get_regs,
3906         .avb_ops = &mv88e6390_avb_ops,
3907         .ptp_ops = &mv88e6352_ptp_ops,
3908         .phylink_validate = mv88e6390_phylink_validate,
3909 };
3910
3911 static const struct mv88e6xxx_ops mv88e6240_ops = {
3912         /* MV88E6XXX_FAMILY_6352 */
3913         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3914         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3915         .irl_init_all = mv88e6352_g2_irl_init_all,
3916         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3917         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3918         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3919         .phy_read = mv88e6xxx_g2_smi_phy_read,
3920         .phy_write = mv88e6xxx_g2_smi_phy_write,
3921         .port_set_link = mv88e6xxx_port_set_link,
3922         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3923         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3924         .port_tag_remap = mv88e6095_port_tag_remap,
3925         .port_set_policy = mv88e6352_port_set_policy,
3926         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3927         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3928         .port_set_ether_type = mv88e6351_port_set_ether_type,
3929         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3930         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3931         .port_pause_limit = mv88e6097_port_pause_limit,
3932         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3933         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3934         .port_get_cmode = mv88e6352_port_get_cmode,
3935         .port_setup_message_port = mv88e6xxx_setup_message_port,
3936         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3937         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3938         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3939         .stats_get_strings = mv88e6095_stats_get_strings,
3940         .stats_get_stats = mv88e6095_stats_get_stats,
3941         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3942         .set_egress_port = mv88e6095_g1_set_egress_port,
3943         .watchdog_ops = &mv88e6097_watchdog_ops,
3944         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3945         .pot_clear = mv88e6xxx_g2_pot_clear,
3946         .reset = mv88e6352_g1_reset,
3947         .rmu_disable = mv88e6352_g1_rmu_disable,
3948         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3949         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3950         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3951         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3952         .serdes_get_lane = mv88e6352_serdes_get_lane,
3953         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3954         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3955         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3956         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3957         .serdes_power = mv88e6352_serdes_power,
3958         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3959         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3960         .serdes_irq_status = mv88e6352_serdes_irq_status,
3961         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3962         .serdes_get_regs = mv88e6352_serdes_get_regs,
3963         .gpio_ops = &mv88e6352_gpio_ops,
3964         .avb_ops = &mv88e6352_avb_ops,
3965         .ptp_ops = &mv88e6352_ptp_ops,
3966         .phylink_validate = mv88e6352_phylink_validate,
3967 };
3968
3969 static const struct mv88e6xxx_ops mv88e6250_ops = {
3970         /* MV88E6XXX_FAMILY_6250 */
3971         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3972         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3973         .irl_init_all = mv88e6352_g2_irl_init_all,
3974         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3975         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3976         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3977         .phy_read = mv88e6xxx_g2_smi_phy_read,
3978         .phy_write = mv88e6xxx_g2_smi_phy_write,
3979         .port_set_link = mv88e6xxx_port_set_link,
3980         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3981         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
3982         .port_tag_remap = mv88e6095_port_tag_remap,
3983         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3984         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3985         .port_set_ether_type = mv88e6351_port_set_ether_type,
3986         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3987         .port_pause_limit = mv88e6097_port_pause_limit,
3988         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3989         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3990         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3991         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
3992         .stats_get_strings = mv88e6250_stats_get_strings,
3993         .stats_get_stats = mv88e6250_stats_get_stats,
3994         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3995         .set_egress_port = mv88e6095_g1_set_egress_port,
3996         .watchdog_ops = &mv88e6250_watchdog_ops,
3997         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3998         .pot_clear = mv88e6xxx_g2_pot_clear,
3999         .reset = mv88e6250_g1_reset,
4000         .vtu_getnext = mv88e6250_g1_vtu_getnext,
4001         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4002         .avb_ops = &mv88e6352_avb_ops,
4003         .ptp_ops = &mv88e6250_ptp_ops,
4004         .phylink_validate = mv88e6065_phylink_validate,
4005 };
4006
4007 static const struct mv88e6xxx_ops mv88e6290_ops = {
4008         /* MV88E6XXX_FAMILY_6390 */
4009         .setup_errata = mv88e6390_setup_errata,
4010         .irl_init_all = mv88e6390_g2_irl_init_all,
4011         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4012         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4013         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4014         .phy_read = mv88e6xxx_g2_smi_phy_read,
4015         .phy_write = mv88e6xxx_g2_smi_phy_write,
4016         .port_set_link = mv88e6xxx_port_set_link,
4017         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4018         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4019         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4020         .port_tag_remap = mv88e6390_port_tag_remap,
4021         .port_set_policy = mv88e6352_port_set_policy,
4022         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4023         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4024         .port_set_ether_type = mv88e6351_port_set_ether_type,
4025         .port_pause_limit = mv88e6390_port_pause_limit,
4026         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4027         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4028         .port_get_cmode = mv88e6352_port_get_cmode,
4029         .port_set_cmode = mv88e6390_port_set_cmode,
4030         .port_setup_message_port = mv88e6xxx_setup_message_port,
4031         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4032         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4033         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4034         .stats_get_strings = mv88e6320_stats_get_strings,
4035         .stats_get_stats = mv88e6390_stats_get_stats,
4036         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4037         .set_egress_port = mv88e6390_g1_set_egress_port,
4038         .watchdog_ops = &mv88e6390_watchdog_ops,
4039         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4040         .pot_clear = mv88e6xxx_g2_pot_clear,
4041         .reset = mv88e6352_g1_reset,
4042         .rmu_disable = mv88e6390_g1_rmu_disable,
4043         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4044         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4045         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4046         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4047         .serdes_power = mv88e6390_serdes_power,
4048         .serdes_get_lane = mv88e6390_serdes_get_lane,
4049         /* Check status register pause & lpa register */
4050         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4051         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4052         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4053         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4054         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4055         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4056         .serdes_irq_status = mv88e6390_serdes_irq_status,
4057         .serdes_get_strings = mv88e6390_serdes_get_strings,
4058         .serdes_get_stats = mv88e6390_serdes_get_stats,
4059         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4060         .serdes_get_regs = mv88e6390_serdes_get_regs,
4061         .gpio_ops = &mv88e6352_gpio_ops,
4062         .avb_ops = &mv88e6390_avb_ops,
4063         .ptp_ops = &mv88e6352_ptp_ops,
4064         .phylink_validate = mv88e6390_phylink_validate,
4065 };
4066
4067 static const struct mv88e6xxx_ops mv88e6320_ops = {
4068         /* MV88E6XXX_FAMILY_6320 */
4069         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4070         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4071         .irl_init_all = mv88e6352_g2_irl_init_all,
4072         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4073         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4074         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4075         .phy_read = mv88e6xxx_g2_smi_phy_read,
4076         .phy_write = mv88e6xxx_g2_smi_phy_write,
4077         .port_set_link = mv88e6xxx_port_set_link,
4078         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4079         .port_tag_remap = mv88e6095_port_tag_remap,
4080         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4081         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4082         .port_set_ether_type = mv88e6351_port_set_ether_type,
4083         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4084         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4085         .port_pause_limit = mv88e6097_port_pause_limit,
4086         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4087         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4088         .port_get_cmode = mv88e6352_port_get_cmode,
4089         .port_setup_message_port = mv88e6xxx_setup_message_port,
4090         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4091         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4092         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4093         .stats_get_strings = mv88e6320_stats_get_strings,
4094         .stats_get_stats = mv88e6320_stats_get_stats,
4095         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4096         .set_egress_port = mv88e6095_g1_set_egress_port,
4097         .watchdog_ops = &mv88e6390_watchdog_ops,
4098         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4099         .pot_clear = mv88e6xxx_g2_pot_clear,
4100         .reset = mv88e6352_g1_reset,
4101         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4102         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4103         .gpio_ops = &mv88e6352_gpio_ops,
4104         .avb_ops = &mv88e6352_avb_ops,
4105         .ptp_ops = &mv88e6352_ptp_ops,
4106         .phylink_validate = mv88e6185_phylink_validate,
4107 };
4108
4109 static const struct mv88e6xxx_ops mv88e6321_ops = {
4110         /* MV88E6XXX_FAMILY_6320 */
4111         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4112         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4113         .irl_init_all = mv88e6352_g2_irl_init_all,
4114         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4115         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4116         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4117         .phy_read = mv88e6xxx_g2_smi_phy_read,
4118         .phy_write = mv88e6xxx_g2_smi_phy_write,
4119         .port_set_link = mv88e6xxx_port_set_link,
4120         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4121         .port_tag_remap = mv88e6095_port_tag_remap,
4122         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4123         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4124         .port_set_ether_type = mv88e6351_port_set_ether_type,
4125         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4126         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4127         .port_pause_limit = mv88e6097_port_pause_limit,
4128         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4129         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4130         .port_get_cmode = mv88e6352_port_get_cmode,
4131         .port_setup_message_port = mv88e6xxx_setup_message_port,
4132         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4133         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4134         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4135         .stats_get_strings = mv88e6320_stats_get_strings,
4136         .stats_get_stats = mv88e6320_stats_get_stats,
4137         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4138         .set_egress_port = mv88e6095_g1_set_egress_port,
4139         .watchdog_ops = &mv88e6390_watchdog_ops,
4140         .reset = mv88e6352_g1_reset,
4141         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4142         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4143         .gpio_ops = &mv88e6352_gpio_ops,
4144         .avb_ops = &mv88e6352_avb_ops,
4145         .ptp_ops = &mv88e6352_ptp_ops,
4146         .phylink_validate = mv88e6185_phylink_validate,
4147 };
4148
4149 static const struct mv88e6xxx_ops mv88e6341_ops = {
4150         /* MV88E6XXX_FAMILY_6341 */
4151         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4152         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4153         .irl_init_all = mv88e6352_g2_irl_init_all,
4154         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4155         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4156         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4157         .phy_read = mv88e6xxx_g2_smi_phy_read,
4158         .phy_write = mv88e6xxx_g2_smi_phy_write,
4159         .port_set_link = mv88e6xxx_port_set_link,
4160         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4161         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4162         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4163         .port_tag_remap = mv88e6095_port_tag_remap,
4164         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4165         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4166         .port_set_ether_type = mv88e6351_port_set_ether_type,
4167         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4168         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4169         .port_pause_limit = mv88e6097_port_pause_limit,
4170         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4171         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4172         .port_get_cmode = mv88e6352_port_get_cmode,
4173         .port_set_cmode = mv88e6341_port_set_cmode,
4174         .port_setup_message_port = mv88e6xxx_setup_message_port,
4175         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4176         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4177         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4178         .stats_get_strings = mv88e6320_stats_get_strings,
4179         .stats_get_stats = mv88e6390_stats_get_stats,
4180         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4181         .set_egress_port = mv88e6390_g1_set_egress_port,
4182         .watchdog_ops = &mv88e6390_watchdog_ops,
4183         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4184         .pot_clear = mv88e6xxx_g2_pot_clear,
4185         .reset = mv88e6352_g1_reset,
4186         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4187         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4188         .serdes_power = mv88e6390_serdes_power,
4189         .serdes_get_lane = mv88e6341_serdes_get_lane,
4190         /* Check status register pause & lpa register */
4191         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4192         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4193         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4194         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4195         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4196         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4197         .serdes_irq_status = mv88e6390_serdes_irq_status,
4198         .gpio_ops = &mv88e6352_gpio_ops,
4199         .avb_ops = &mv88e6390_avb_ops,
4200         .ptp_ops = &mv88e6352_ptp_ops,
4201         .phylink_validate = mv88e6341_phylink_validate,
4202 };
4203
4204 static const struct mv88e6xxx_ops mv88e6350_ops = {
4205         /* MV88E6XXX_FAMILY_6351 */
4206         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4207         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4208         .irl_init_all = mv88e6352_g2_irl_init_all,
4209         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4210         .phy_read = mv88e6xxx_g2_smi_phy_read,
4211         .phy_write = mv88e6xxx_g2_smi_phy_write,
4212         .port_set_link = mv88e6xxx_port_set_link,
4213         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4214         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4215         .port_tag_remap = mv88e6095_port_tag_remap,
4216         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4217         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4218         .port_set_ether_type = mv88e6351_port_set_ether_type,
4219         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4220         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4221         .port_pause_limit = mv88e6097_port_pause_limit,
4222         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4223         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4224         .port_get_cmode = mv88e6352_port_get_cmode,
4225         .port_setup_message_port = mv88e6xxx_setup_message_port,
4226         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4227         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4228         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4229         .stats_get_strings = mv88e6095_stats_get_strings,
4230         .stats_get_stats = mv88e6095_stats_get_stats,
4231         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4232         .set_egress_port = mv88e6095_g1_set_egress_port,
4233         .watchdog_ops = &mv88e6097_watchdog_ops,
4234         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4235         .pot_clear = mv88e6xxx_g2_pot_clear,
4236         .reset = mv88e6352_g1_reset,
4237         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4238         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4239         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4240         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4241         .phylink_validate = mv88e6185_phylink_validate,
4242 };
4243
4244 static const struct mv88e6xxx_ops mv88e6351_ops = {
4245         /* MV88E6XXX_FAMILY_6351 */
4246         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4247         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4248         .irl_init_all = mv88e6352_g2_irl_init_all,
4249         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4250         .phy_read = mv88e6xxx_g2_smi_phy_read,
4251         .phy_write = mv88e6xxx_g2_smi_phy_write,
4252         .port_set_link = mv88e6xxx_port_set_link,
4253         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4254         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4255         .port_tag_remap = mv88e6095_port_tag_remap,
4256         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4257         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4258         .port_set_ether_type = mv88e6351_port_set_ether_type,
4259         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4260         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4261         .port_pause_limit = mv88e6097_port_pause_limit,
4262         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4263         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4264         .port_get_cmode = mv88e6352_port_get_cmode,
4265         .port_setup_message_port = mv88e6xxx_setup_message_port,
4266         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4267         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4268         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4269         .stats_get_strings = mv88e6095_stats_get_strings,
4270         .stats_get_stats = mv88e6095_stats_get_stats,
4271         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4272         .set_egress_port = mv88e6095_g1_set_egress_port,
4273         .watchdog_ops = &mv88e6097_watchdog_ops,
4274         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4275         .pot_clear = mv88e6xxx_g2_pot_clear,
4276         .reset = mv88e6352_g1_reset,
4277         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4278         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4279         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4280         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4281         .avb_ops = &mv88e6352_avb_ops,
4282         .ptp_ops = &mv88e6352_ptp_ops,
4283         .phylink_validate = mv88e6185_phylink_validate,
4284 };
4285
4286 static const struct mv88e6xxx_ops mv88e6352_ops = {
4287         /* MV88E6XXX_FAMILY_6352 */
4288         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4289         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4290         .irl_init_all = mv88e6352_g2_irl_init_all,
4291         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4292         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4293         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4294         .phy_read = mv88e6xxx_g2_smi_phy_read,
4295         .phy_write = mv88e6xxx_g2_smi_phy_write,
4296         .port_set_link = mv88e6xxx_port_set_link,
4297         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4298         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4299         .port_tag_remap = mv88e6095_port_tag_remap,
4300         .port_set_policy = mv88e6352_port_set_policy,
4301         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4302         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4303         .port_set_ether_type = mv88e6351_port_set_ether_type,
4304         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4305         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4306         .port_pause_limit = mv88e6097_port_pause_limit,
4307         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4308         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4309         .port_get_cmode = mv88e6352_port_get_cmode,
4310         .port_setup_message_port = mv88e6xxx_setup_message_port,
4311         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4312         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4313         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4314         .stats_get_strings = mv88e6095_stats_get_strings,
4315         .stats_get_stats = mv88e6095_stats_get_stats,
4316         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4317         .set_egress_port = mv88e6095_g1_set_egress_port,
4318         .watchdog_ops = &mv88e6097_watchdog_ops,
4319         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4320         .pot_clear = mv88e6xxx_g2_pot_clear,
4321         .reset = mv88e6352_g1_reset,
4322         .rmu_disable = mv88e6352_g1_rmu_disable,
4323         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4324         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4325         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4326         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4327         .serdes_get_lane = mv88e6352_serdes_get_lane,
4328         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4329         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4330         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4331         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4332         .serdes_power = mv88e6352_serdes_power,
4333         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4334         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4335         .serdes_irq_status = mv88e6352_serdes_irq_status,
4336         .gpio_ops = &mv88e6352_gpio_ops,
4337         .avb_ops = &mv88e6352_avb_ops,
4338         .ptp_ops = &mv88e6352_ptp_ops,
4339         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4340         .serdes_get_strings = mv88e6352_serdes_get_strings,
4341         .serdes_get_stats = mv88e6352_serdes_get_stats,
4342         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4343         .serdes_get_regs = mv88e6352_serdes_get_regs,
4344         .phylink_validate = mv88e6352_phylink_validate,
4345 };
4346
4347 static const struct mv88e6xxx_ops mv88e6390_ops = {
4348         /* MV88E6XXX_FAMILY_6390 */
4349         .setup_errata = mv88e6390_setup_errata,
4350         .irl_init_all = mv88e6390_g2_irl_init_all,
4351         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4352         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4353         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4354         .phy_read = mv88e6xxx_g2_smi_phy_read,
4355         .phy_write = mv88e6xxx_g2_smi_phy_write,
4356         .port_set_link = mv88e6xxx_port_set_link,
4357         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4358         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4359         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4360         .port_tag_remap = mv88e6390_port_tag_remap,
4361         .port_set_policy = mv88e6352_port_set_policy,
4362         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4363         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4364         .port_set_ether_type = mv88e6351_port_set_ether_type,
4365         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4366         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4367         .port_pause_limit = mv88e6390_port_pause_limit,
4368         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4369         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4370         .port_get_cmode = mv88e6352_port_get_cmode,
4371         .port_set_cmode = mv88e6390_port_set_cmode,
4372         .port_setup_message_port = mv88e6xxx_setup_message_port,
4373         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4374         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4375         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4376         .stats_get_strings = mv88e6320_stats_get_strings,
4377         .stats_get_stats = mv88e6390_stats_get_stats,
4378         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4379         .set_egress_port = mv88e6390_g1_set_egress_port,
4380         .watchdog_ops = &mv88e6390_watchdog_ops,
4381         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4382         .pot_clear = mv88e6xxx_g2_pot_clear,
4383         .reset = mv88e6352_g1_reset,
4384         .rmu_disable = mv88e6390_g1_rmu_disable,
4385         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4386         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4387         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4388         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4389         .serdes_power = mv88e6390_serdes_power,
4390         .serdes_get_lane = mv88e6390_serdes_get_lane,
4391         /* Check status register pause & lpa register */
4392         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4393         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4394         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4395         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4396         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4397         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4398         .serdes_irq_status = mv88e6390_serdes_irq_status,
4399         .gpio_ops = &mv88e6352_gpio_ops,
4400         .avb_ops = &mv88e6390_avb_ops,
4401         .ptp_ops = &mv88e6352_ptp_ops,
4402         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4403         .serdes_get_strings = mv88e6390_serdes_get_strings,
4404         .serdes_get_stats = mv88e6390_serdes_get_stats,
4405         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4406         .serdes_get_regs = mv88e6390_serdes_get_regs,
4407         .phylink_validate = mv88e6390_phylink_validate,
4408 };
4409
4410 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4411         /* MV88E6XXX_FAMILY_6390 */
4412         .setup_errata = mv88e6390_setup_errata,
4413         .irl_init_all = mv88e6390_g2_irl_init_all,
4414         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4415         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4416         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4417         .phy_read = mv88e6xxx_g2_smi_phy_read,
4418         .phy_write = mv88e6xxx_g2_smi_phy_write,
4419         .port_set_link = mv88e6xxx_port_set_link,
4420         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4421         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4422         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4423         .port_tag_remap = mv88e6390_port_tag_remap,
4424         .port_set_policy = mv88e6352_port_set_policy,
4425         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4426         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4427         .port_set_ether_type = mv88e6351_port_set_ether_type,
4428         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4429         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4430         .port_pause_limit = mv88e6390_port_pause_limit,
4431         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4432         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4433         .port_get_cmode = mv88e6352_port_get_cmode,
4434         .port_set_cmode = mv88e6390x_port_set_cmode,
4435         .port_setup_message_port = mv88e6xxx_setup_message_port,
4436         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4437         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4438         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4439         .stats_get_strings = mv88e6320_stats_get_strings,
4440         .stats_get_stats = mv88e6390_stats_get_stats,
4441         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4442         .set_egress_port = mv88e6390_g1_set_egress_port,
4443         .watchdog_ops = &mv88e6390_watchdog_ops,
4444         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4445         .pot_clear = mv88e6xxx_g2_pot_clear,
4446         .reset = mv88e6352_g1_reset,
4447         .rmu_disable = mv88e6390_g1_rmu_disable,
4448         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4449         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4450         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4451         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4452         .serdes_power = mv88e6390_serdes_power,
4453         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4454         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4455         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4456         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4457         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4458         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4459         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4460         .serdes_irq_status = mv88e6390_serdes_irq_status,
4461         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4462         .serdes_get_strings = mv88e6390_serdes_get_strings,
4463         .serdes_get_stats = mv88e6390_serdes_get_stats,
4464         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4465         .serdes_get_regs = mv88e6390_serdes_get_regs,
4466         .gpio_ops = &mv88e6352_gpio_ops,
4467         .avb_ops = &mv88e6390_avb_ops,
4468         .ptp_ops = &mv88e6352_ptp_ops,
4469         .phylink_validate = mv88e6390x_phylink_validate,
4470 };
4471
4472 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4473         [MV88E6085] = {
4474                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4475                 .family = MV88E6XXX_FAMILY_6097,
4476                 .name = "Marvell 88E6085",
4477                 .num_databases = 4096,
4478                 .num_macs = 8192,
4479                 .num_ports = 10,
4480                 .num_internal_phys = 5,
4481                 .max_vid = 4095,
4482                 .port_base_addr = 0x10,
4483                 .phy_base_addr = 0x0,
4484                 .global1_addr = 0x1b,
4485                 .global2_addr = 0x1c,
4486                 .age_time_coeff = 15000,
4487                 .g1_irqs = 8,
4488                 .g2_irqs = 10,
4489                 .atu_move_port_mask = 0xf,
4490                 .pvt = true,
4491                 .multi_chip = true,
4492                 .tag_protocol = DSA_TAG_PROTO_DSA,
4493                 .ops = &mv88e6085_ops,
4494         },
4495
4496         [MV88E6095] = {
4497                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4498                 .family = MV88E6XXX_FAMILY_6095,
4499                 .name = "Marvell 88E6095/88E6095F",
4500                 .num_databases = 256,
4501                 .num_macs = 8192,
4502                 .num_ports = 11,
4503                 .num_internal_phys = 0,
4504                 .max_vid = 4095,
4505                 .port_base_addr = 0x10,
4506                 .phy_base_addr = 0x0,
4507                 .global1_addr = 0x1b,
4508                 .global2_addr = 0x1c,
4509                 .age_time_coeff = 15000,
4510                 .g1_irqs = 8,
4511                 .atu_move_port_mask = 0xf,
4512                 .multi_chip = true,
4513                 .tag_protocol = DSA_TAG_PROTO_DSA,
4514                 .ops = &mv88e6095_ops,
4515         },
4516
4517         [MV88E6097] = {
4518                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4519                 .family = MV88E6XXX_FAMILY_6097,
4520                 .name = "Marvell 88E6097/88E6097F",
4521                 .num_databases = 4096,
4522                 .num_macs = 8192,
4523                 .num_ports = 11,
4524                 .num_internal_phys = 8,
4525                 .max_vid = 4095,
4526                 .port_base_addr = 0x10,
4527                 .phy_base_addr = 0x0,
4528                 .global1_addr = 0x1b,
4529                 .global2_addr = 0x1c,
4530                 .age_time_coeff = 15000,
4531                 .g1_irqs = 8,
4532                 .g2_irqs = 10,
4533                 .atu_move_port_mask = 0xf,
4534                 .pvt = true,
4535                 .multi_chip = true,
4536                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4537                 .ops = &mv88e6097_ops,
4538         },
4539
4540         [MV88E6123] = {
4541                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4542                 .family = MV88E6XXX_FAMILY_6165,
4543                 .name = "Marvell 88E6123",
4544                 .num_databases = 4096,
4545                 .num_macs = 1024,
4546                 .num_ports = 3,
4547                 .num_internal_phys = 5,
4548                 .max_vid = 4095,
4549                 .port_base_addr = 0x10,
4550                 .phy_base_addr = 0x0,
4551                 .global1_addr = 0x1b,
4552                 .global2_addr = 0x1c,
4553                 .age_time_coeff = 15000,
4554                 .g1_irqs = 9,
4555                 .g2_irqs = 10,
4556                 .atu_move_port_mask = 0xf,
4557                 .pvt = true,
4558                 .multi_chip = true,
4559                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4560                 .ops = &mv88e6123_ops,
4561         },
4562
4563         [MV88E6131] = {
4564                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4565                 .family = MV88E6XXX_FAMILY_6185,
4566                 .name = "Marvell 88E6131",
4567                 .num_databases = 256,
4568                 .num_macs = 8192,
4569                 .num_ports = 8,
4570                 .num_internal_phys = 0,
4571                 .max_vid = 4095,
4572                 .port_base_addr = 0x10,
4573                 .phy_base_addr = 0x0,
4574                 .global1_addr = 0x1b,
4575                 .global2_addr = 0x1c,
4576                 .age_time_coeff = 15000,
4577                 .g1_irqs = 9,
4578                 .atu_move_port_mask = 0xf,
4579                 .multi_chip = true,
4580                 .tag_protocol = DSA_TAG_PROTO_DSA,
4581                 .ops = &mv88e6131_ops,
4582         },
4583
4584         [MV88E6141] = {
4585                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4586                 .family = MV88E6XXX_FAMILY_6341,
4587                 .name = "Marvell 88E6141",
4588                 .num_databases = 4096,
4589                 .num_macs = 2048,
4590                 .num_ports = 6,
4591                 .num_internal_phys = 5,
4592                 .num_gpio = 11,
4593                 .max_vid = 4095,
4594                 .port_base_addr = 0x10,
4595                 .phy_base_addr = 0x10,
4596                 .global1_addr = 0x1b,
4597                 .global2_addr = 0x1c,
4598                 .age_time_coeff = 3750,
4599                 .atu_move_port_mask = 0x1f,
4600                 .g1_irqs = 9,
4601                 .g2_irqs = 10,
4602                 .pvt = true,
4603                 .multi_chip = true,
4604                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4605                 .ops = &mv88e6141_ops,
4606         },
4607
4608         [MV88E6161] = {
4609                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4610                 .family = MV88E6XXX_FAMILY_6165,
4611                 .name = "Marvell 88E6161",
4612                 .num_databases = 4096,
4613                 .num_macs = 1024,
4614                 .num_ports = 6,
4615                 .num_internal_phys = 5,
4616                 .max_vid = 4095,
4617                 .port_base_addr = 0x10,
4618                 .phy_base_addr = 0x0,
4619                 .global1_addr = 0x1b,
4620                 .global2_addr = 0x1c,
4621                 .age_time_coeff = 15000,
4622                 .g1_irqs = 9,
4623                 .g2_irqs = 10,
4624                 .atu_move_port_mask = 0xf,
4625                 .pvt = true,
4626                 .multi_chip = true,
4627                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4628                 .ptp_support = true,
4629                 .ops = &mv88e6161_ops,
4630         },
4631
4632         [MV88E6165] = {
4633                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4634                 .family = MV88E6XXX_FAMILY_6165,
4635                 .name = "Marvell 88E6165",
4636                 .num_databases = 4096,
4637                 .num_macs = 8192,
4638                 .num_ports = 6,
4639                 .num_internal_phys = 0,
4640                 .max_vid = 4095,
4641                 .port_base_addr = 0x10,
4642                 .phy_base_addr = 0x0,
4643                 .global1_addr = 0x1b,
4644                 .global2_addr = 0x1c,
4645                 .age_time_coeff = 15000,
4646                 .g1_irqs = 9,
4647                 .g2_irqs = 10,
4648                 .atu_move_port_mask = 0xf,
4649                 .pvt = true,
4650                 .multi_chip = true,
4651                 .tag_protocol = DSA_TAG_PROTO_DSA,
4652                 .ptp_support = true,
4653                 .ops = &mv88e6165_ops,
4654         },
4655
4656         [MV88E6171] = {
4657                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4658                 .family = MV88E6XXX_FAMILY_6351,
4659                 .name = "Marvell 88E6171",
4660                 .num_databases = 4096,
4661                 .num_macs = 8192,
4662                 .num_ports = 7,
4663                 .num_internal_phys = 5,
4664                 .max_vid = 4095,
4665                 .port_base_addr = 0x10,
4666                 .phy_base_addr = 0x0,
4667                 .global1_addr = 0x1b,
4668                 .global2_addr = 0x1c,
4669                 .age_time_coeff = 15000,
4670                 .g1_irqs = 9,
4671                 .g2_irqs = 10,
4672                 .atu_move_port_mask = 0xf,
4673                 .pvt = true,
4674                 .multi_chip = true,
4675                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4676                 .ops = &mv88e6171_ops,
4677         },
4678
4679         [MV88E6172] = {
4680                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4681                 .family = MV88E6XXX_FAMILY_6352,
4682                 .name = "Marvell 88E6172",
4683                 .num_databases = 4096,
4684                 .num_macs = 8192,
4685                 .num_ports = 7,
4686                 .num_internal_phys = 5,
4687                 .num_gpio = 15,
4688                 .max_vid = 4095,
4689                 .port_base_addr = 0x10,
4690                 .phy_base_addr = 0x0,
4691                 .global1_addr = 0x1b,
4692                 .global2_addr = 0x1c,
4693                 .age_time_coeff = 15000,
4694                 .g1_irqs = 9,
4695                 .g2_irqs = 10,
4696                 .atu_move_port_mask = 0xf,
4697                 .pvt = true,
4698                 .multi_chip = true,
4699                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4700                 .ops = &mv88e6172_ops,
4701         },
4702
4703         [MV88E6175] = {
4704                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4705                 .family = MV88E6XXX_FAMILY_6351,
4706                 .name = "Marvell 88E6175",
4707                 .num_databases = 4096,
4708                 .num_macs = 8192,
4709                 .num_ports = 7,
4710                 .num_internal_phys = 5,
4711                 .max_vid = 4095,
4712                 .port_base_addr = 0x10,
4713                 .phy_base_addr = 0x0,
4714                 .global1_addr = 0x1b,
4715                 .global2_addr = 0x1c,
4716                 .age_time_coeff = 15000,
4717                 .g1_irqs = 9,
4718                 .g2_irqs = 10,
4719                 .atu_move_port_mask = 0xf,
4720                 .pvt = true,
4721                 .multi_chip = true,
4722                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4723                 .ops = &mv88e6175_ops,
4724         },
4725
4726         [MV88E6176] = {
4727                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4728                 .family = MV88E6XXX_FAMILY_6352,
4729                 .name = "Marvell 88E6176",
4730                 .num_databases = 4096,
4731                 .num_macs = 8192,
4732                 .num_ports = 7,
4733                 .num_internal_phys = 5,
4734                 .num_gpio = 15,
4735                 .max_vid = 4095,
4736                 .port_base_addr = 0x10,
4737                 .phy_base_addr = 0x0,
4738                 .global1_addr = 0x1b,
4739                 .global2_addr = 0x1c,
4740                 .age_time_coeff = 15000,
4741                 .g1_irqs = 9,
4742                 .g2_irqs = 10,
4743                 .atu_move_port_mask = 0xf,
4744                 .pvt = true,
4745                 .multi_chip = true,
4746                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4747                 .ops = &mv88e6176_ops,
4748         },
4749
4750         [MV88E6185] = {
4751                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4752                 .family = MV88E6XXX_FAMILY_6185,
4753                 .name = "Marvell 88E6185",
4754                 .num_databases = 256,
4755                 .num_macs = 8192,
4756                 .num_ports = 10,
4757                 .num_internal_phys = 0,
4758                 .max_vid = 4095,
4759                 .port_base_addr = 0x10,
4760                 .phy_base_addr = 0x0,
4761                 .global1_addr = 0x1b,
4762                 .global2_addr = 0x1c,
4763                 .age_time_coeff = 15000,
4764                 .g1_irqs = 8,
4765                 .atu_move_port_mask = 0xf,
4766                 .multi_chip = true,
4767                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4768                 .ops = &mv88e6185_ops,
4769         },
4770
4771         [MV88E6190] = {
4772                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4773                 .family = MV88E6XXX_FAMILY_6390,
4774                 .name = "Marvell 88E6190",
4775                 .num_databases = 4096,
4776                 .num_macs = 16384,
4777                 .num_ports = 11,        /* 10 + Z80 */
4778                 .num_internal_phys = 9,
4779                 .num_gpio = 16,
4780                 .max_vid = 8191,
4781                 .port_base_addr = 0x0,
4782                 .phy_base_addr = 0x0,
4783                 .global1_addr = 0x1b,
4784                 .global2_addr = 0x1c,
4785                 .tag_protocol = DSA_TAG_PROTO_DSA,
4786                 .age_time_coeff = 3750,
4787                 .g1_irqs = 9,
4788                 .g2_irqs = 14,
4789                 .pvt = true,
4790                 .multi_chip = true,
4791                 .atu_move_port_mask = 0x1f,
4792                 .ops = &mv88e6190_ops,
4793         },
4794
4795         [MV88E6190X] = {
4796                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4797                 .family = MV88E6XXX_FAMILY_6390,
4798                 .name = "Marvell 88E6190X",
4799                 .num_databases = 4096,
4800                 .num_macs = 16384,
4801                 .num_ports = 11,        /* 10 + Z80 */
4802                 .num_internal_phys = 9,
4803                 .num_gpio = 16,
4804                 .max_vid = 8191,
4805                 .port_base_addr = 0x0,
4806                 .phy_base_addr = 0x0,
4807                 .global1_addr = 0x1b,
4808                 .global2_addr = 0x1c,
4809                 .age_time_coeff = 3750,
4810                 .g1_irqs = 9,
4811                 .g2_irqs = 14,
4812                 .atu_move_port_mask = 0x1f,
4813                 .pvt = true,
4814                 .multi_chip = true,
4815                 .tag_protocol = DSA_TAG_PROTO_DSA,
4816                 .ops = &mv88e6190x_ops,
4817         },
4818
4819         [MV88E6191] = {
4820                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4821                 .family = MV88E6XXX_FAMILY_6390,
4822                 .name = "Marvell 88E6191",
4823                 .num_databases = 4096,
4824                 .num_macs = 16384,
4825                 .num_ports = 11,        /* 10 + Z80 */
4826                 .num_internal_phys = 9,
4827                 .max_vid = 8191,
4828                 .port_base_addr = 0x0,
4829                 .phy_base_addr = 0x0,
4830                 .global1_addr = 0x1b,
4831                 .global2_addr = 0x1c,
4832                 .age_time_coeff = 3750,
4833                 .g1_irqs = 9,
4834                 .g2_irqs = 14,
4835                 .atu_move_port_mask = 0x1f,
4836                 .pvt = true,
4837                 .multi_chip = true,
4838                 .tag_protocol = DSA_TAG_PROTO_DSA,
4839                 .ptp_support = true,
4840                 .ops = &mv88e6191_ops,
4841         },
4842
4843         [MV88E6220] = {
4844                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4845                 .family = MV88E6XXX_FAMILY_6250,
4846                 .name = "Marvell 88E6220",
4847                 .num_databases = 64,
4848
4849                 /* Ports 2-4 are not routed to pins
4850                  * => usable ports 0, 1, 5, 6
4851                  */
4852                 .num_ports = 7,
4853                 .num_internal_phys = 2,
4854                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4855                 .max_vid = 4095,
4856                 .port_base_addr = 0x08,
4857                 .phy_base_addr = 0x00,
4858                 .global1_addr = 0x0f,
4859                 .global2_addr = 0x07,
4860                 .age_time_coeff = 15000,
4861                 .g1_irqs = 9,
4862                 .g2_irqs = 10,
4863                 .atu_move_port_mask = 0xf,
4864                 .dual_chip = true,
4865                 .tag_protocol = DSA_TAG_PROTO_DSA,
4866                 .ptp_support = true,
4867                 .ops = &mv88e6250_ops,
4868         },
4869
4870         [MV88E6240] = {
4871                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4872                 .family = MV88E6XXX_FAMILY_6352,
4873                 .name = "Marvell 88E6240",
4874                 .num_databases = 4096,
4875                 .num_macs = 8192,
4876                 .num_ports = 7,
4877                 .num_internal_phys = 5,
4878                 .num_gpio = 15,
4879                 .max_vid = 4095,
4880                 .port_base_addr = 0x10,
4881                 .phy_base_addr = 0x0,
4882                 .global1_addr = 0x1b,
4883                 .global2_addr = 0x1c,
4884                 .age_time_coeff = 15000,
4885                 .g1_irqs = 9,
4886                 .g2_irqs = 10,
4887                 .atu_move_port_mask = 0xf,
4888                 .pvt = true,
4889                 .multi_chip = true,
4890                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4891                 .ptp_support = true,
4892                 .ops = &mv88e6240_ops,
4893         },
4894
4895         [MV88E6250] = {
4896                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4897                 .family = MV88E6XXX_FAMILY_6250,
4898                 .name = "Marvell 88E6250",
4899                 .num_databases = 64,
4900                 .num_ports = 7,
4901                 .num_internal_phys = 5,
4902                 .max_vid = 4095,
4903                 .port_base_addr = 0x08,
4904                 .phy_base_addr = 0x00,
4905                 .global1_addr = 0x0f,
4906                 .global2_addr = 0x07,
4907                 .age_time_coeff = 15000,
4908                 .g1_irqs = 9,
4909                 .g2_irqs = 10,
4910                 .atu_move_port_mask = 0xf,
4911                 .dual_chip = true,
4912                 .tag_protocol = DSA_TAG_PROTO_DSA,
4913                 .ptp_support = true,
4914                 .ops = &mv88e6250_ops,
4915         },
4916
4917         [MV88E6290] = {
4918                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4919                 .family = MV88E6XXX_FAMILY_6390,
4920                 .name = "Marvell 88E6290",
4921                 .num_databases = 4096,
4922                 .num_ports = 11,        /* 10 + Z80 */
4923                 .num_internal_phys = 9,
4924                 .num_gpio = 16,
4925                 .max_vid = 8191,
4926                 .port_base_addr = 0x0,
4927                 .phy_base_addr = 0x0,
4928                 .global1_addr = 0x1b,
4929                 .global2_addr = 0x1c,
4930                 .age_time_coeff = 3750,
4931                 .g1_irqs = 9,
4932                 .g2_irqs = 14,
4933                 .atu_move_port_mask = 0x1f,
4934                 .pvt = true,
4935                 .multi_chip = true,
4936                 .tag_protocol = DSA_TAG_PROTO_DSA,
4937                 .ptp_support = true,
4938                 .ops = &mv88e6290_ops,
4939         },
4940
4941         [MV88E6320] = {
4942                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4943                 .family = MV88E6XXX_FAMILY_6320,
4944                 .name = "Marvell 88E6320",
4945                 .num_databases = 4096,
4946                 .num_macs = 8192,
4947                 .num_ports = 7,
4948                 .num_internal_phys = 5,
4949                 .num_gpio = 15,
4950                 .max_vid = 4095,
4951                 .port_base_addr = 0x10,
4952                 .phy_base_addr = 0x0,
4953                 .global1_addr = 0x1b,
4954                 .global2_addr = 0x1c,
4955                 .age_time_coeff = 15000,
4956                 .g1_irqs = 8,
4957                 .g2_irqs = 10,
4958                 .atu_move_port_mask = 0xf,
4959                 .pvt = true,
4960                 .multi_chip = true,
4961                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4962                 .ptp_support = true,
4963                 .ops = &mv88e6320_ops,
4964         },
4965
4966         [MV88E6321] = {
4967                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4968                 .family = MV88E6XXX_FAMILY_6320,
4969                 .name = "Marvell 88E6321",
4970                 .num_databases = 4096,
4971                 .num_macs = 8192,
4972                 .num_ports = 7,
4973                 .num_internal_phys = 5,
4974                 .num_gpio = 15,
4975                 .max_vid = 4095,
4976                 .port_base_addr = 0x10,
4977                 .phy_base_addr = 0x0,
4978                 .global1_addr = 0x1b,
4979                 .global2_addr = 0x1c,
4980                 .age_time_coeff = 15000,
4981                 .g1_irqs = 8,
4982                 .g2_irqs = 10,
4983                 .atu_move_port_mask = 0xf,
4984                 .multi_chip = true,
4985                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4986                 .ptp_support = true,
4987                 .ops = &mv88e6321_ops,
4988         },
4989
4990         [MV88E6341] = {
4991                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4992                 .family = MV88E6XXX_FAMILY_6341,
4993                 .name = "Marvell 88E6341",
4994                 .num_databases = 4096,
4995                 .num_macs = 2048,
4996                 .num_internal_phys = 5,
4997                 .num_ports = 6,
4998                 .num_gpio = 11,
4999                 .max_vid = 4095,
5000                 .port_base_addr = 0x10,
5001                 .phy_base_addr = 0x10,
5002                 .global1_addr = 0x1b,
5003                 .global2_addr = 0x1c,
5004                 .age_time_coeff = 3750,
5005                 .atu_move_port_mask = 0x1f,
5006                 .g1_irqs = 9,
5007                 .g2_irqs = 10,
5008                 .pvt = true,
5009                 .multi_chip = true,
5010                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5011                 .ptp_support = true,
5012                 .ops = &mv88e6341_ops,
5013         },
5014
5015         [MV88E6350] = {
5016                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5017                 .family = MV88E6XXX_FAMILY_6351,
5018                 .name = "Marvell 88E6350",
5019                 .num_databases = 4096,
5020                 .num_macs = 8192,
5021                 .num_ports = 7,
5022                 .num_internal_phys = 5,
5023                 .max_vid = 4095,
5024                 .port_base_addr = 0x10,
5025                 .phy_base_addr = 0x0,
5026                 .global1_addr = 0x1b,
5027                 .global2_addr = 0x1c,
5028                 .age_time_coeff = 15000,
5029                 .g1_irqs = 9,
5030                 .g2_irqs = 10,
5031                 .atu_move_port_mask = 0xf,
5032                 .pvt = true,
5033                 .multi_chip = true,
5034                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5035                 .ops = &mv88e6350_ops,
5036         },
5037
5038         [MV88E6351] = {
5039                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5040                 .family = MV88E6XXX_FAMILY_6351,
5041                 .name = "Marvell 88E6351",
5042                 .num_databases = 4096,
5043                 .num_macs = 8192,
5044                 .num_ports = 7,
5045                 .num_internal_phys = 5,
5046                 .max_vid = 4095,
5047                 .port_base_addr = 0x10,
5048                 .phy_base_addr = 0x0,
5049                 .global1_addr = 0x1b,
5050                 .global2_addr = 0x1c,
5051                 .age_time_coeff = 15000,
5052                 .g1_irqs = 9,
5053                 .g2_irqs = 10,
5054                 .atu_move_port_mask = 0xf,
5055                 .pvt = true,
5056                 .multi_chip = true,
5057                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5058                 .ops = &mv88e6351_ops,
5059         },
5060
5061         [MV88E6352] = {
5062                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5063                 .family = MV88E6XXX_FAMILY_6352,
5064                 .name = "Marvell 88E6352",
5065                 .num_databases = 4096,
5066                 .num_macs = 8192,
5067                 .num_ports = 7,
5068                 .num_internal_phys = 5,
5069                 .num_gpio = 15,
5070                 .max_vid = 4095,
5071                 .port_base_addr = 0x10,
5072                 .phy_base_addr = 0x0,
5073                 .global1_addr = 0x1b,
5074                 .global2_addr = 0x1c,
5075                 .age_time_coeff = 15000,
5076                 .g1_irqs = 9,
5077                 .g2_irqs = 10,
5078                 .atu_move_port_mask = 0xf,
5079                 .pvt = true,
5080                 .multi_chip = true,
5081                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5082                 .ptp_support = true,
5083                 .ops = &mv88e6352_ops,
5084         },
5085         [MV88E6390] = {
5086                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5087                 .family = MV88E6XXX_FAMILY_6390,
5088                 .name = "Marvell 88E6390",
5089                 .num_databases = 4096,
5090                 .num_macs = 16384,
5091                 .num_ports = 11,        /* 10 + Z80 */
5092                 .num_internal_phys = 9,
5093                 .num_gpio = 16,
5094                 .max_vid = 8191,
5095                 .port_base_addr = 0x0,
5096                 .phy_base_addr = 0x0,
5097                 .global1_addr = 0x1b,
5098                 .global2_addr = 0x1c,
5099                 .age_time_coeff = 3750,
5100                 .g1_irqs = 9,
5101                 .g2_irqs = 14,
5102                 .atu_move_port_mask = 0x1f,
5103                 .pvt = true,
5104                 .multi_chip = true,
5105                 .tag_protocol = DSA_TAG_PROTO_DSA,
5106                 .ptp_support = true,
5107                 .ops = &mv88e6390_ops,
5108         },
5109         [MV88E6390X] = {
5110                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5111                 .family = MV88E6XXX_FAMILY_6390,
5112                 .name = "Marvell 88E6390X",
5113                 .num_databases = 4096,
5114                 .num_macs = 16384,
5115                 .num_ports = 11,        /* 10 + Z80 */
5116                 .num_internal_phys = 9,
5117                 .num_gpio = 16,
5118                 .max_vid = 8191,
5119                 .port_base_addr = 0x0,
5120                 .phy_base_addr = 0x0,
5121                 .global1_addr = 0x1b,
5122                 .global2_addr = 0x1c,
5123                 .age_time_coeff = 3750,
5124                 .g1_irqs = 9,
5125                 .g2_irqs = 14,
5126                 .atu_move_port_mask = 0x1f,
5127                 .pvt = true,
5128                 .multi_chip = true,
5129                 .tag_protocol = DSA_TAG_PROTO_DSA,
5130                 .ptp_support = true,
5131                 .ops = &mv88e6390x_ops,
5132         },
5133 };
5134
5135 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5136 {
5137         int i;
5138
5139         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5140                 if (mv88e6xxx_table[i].prod_num == prod_num)
5141                         return &mv88e6xxx_table[i];
5142
5143         return NULL;
5144 }
5145
5146 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5147 {
5148         const struct mv88e6xxx_info *info;
5149         unsigned int prod_num, rev;
5150         u16 id;
5151         int err;
5152
5153         mv88e6xxx_reg_lock(chip);
5154         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5155         mv88e6xxx_reg_unlock(chip);
5156         if (err)
5157                 return err;
5158
5159         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5160         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5161
5162         info = mv88e6xxx_lookup_info(prod_num);
5163         if (!info)
5164                 return -ENODEV;
5165
5166         /* Update the compatible info with the probed one */
5167         chip->info = info;
5168
5169         err = mv88e6xxx_g2_require(chip);
5170         if (err)
5171                 return err;
5172
5173         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5174                  chip->info->prod_num, chip->info->name, rev);
5175
5176         return 0;
5177 }
5178
5179 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5180 {
5181         struct mv88e6xxx_chip *chip;
5182
5183         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5184         if (!chip)
5185                 return NULL;
5186
5187         chip->dev = dev;
5188
5189         mutex_init(&chip->reg_lock);
5190         INIT_LIST_HEAD(&chip->mdios);
5191         idr_init(&chip->policies);
5192
5193         return chip;
5194 }
5195
5196 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5197                                                         int port,
5198                                                         enum dsa_tag_protocol m)
5199 {
5200         struct mv88e6xxx_chip *chip = ds->priv;
5201
5202         return chip->info->tag_protocol;
5203 }
5204
5205 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5206                                       const struct switchdev_obj_port_mdb *mdb)
5207 {
5208         /* We don't need any dynamic resource from the kernel (yet),
5209          * so skip the prepare phase.
5210          */
5211
5212         return 0;
5213 }
5214
5215 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5216                                    const struct switchdev_obj_port_mdb *mdb)
5217 {
5218         struct mv88e6xxx_chip *chip = ds->priv;
5219
5220         mv88e6xxx_reg_lock(chip);
5221         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5222                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5223                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5224                         port);
5225         mv88e6xxx_reg_unlock(chip);
5226 }
5227
5228 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5229                                   const struct switchdev_obj_port_mdb *mdb)
5230 {
5231         struct mv88e6xxx_chip *chip = ds->priv;
5232         int err;
5233
5234         mv88e6xxx_reg_lock(chip);
5235         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5236         mv88e6xxx_reg_unlock(chip);
5237
5238         return err;
5239 }
5240
5241 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5242                                      struct dsa_mall_mirror_tc_entry *mirror,
5243                                      bool ingress)
5244 {
5245         enum mv88e6xxx_egress_direction direction = ingress ?
5246                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5247                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5248         struct mv88e6xxx_chip *chip = ds->priv;
5249         bool other_mirrors = false;
5250         int i;
5251         int err;
5252
5253         if (!chip->info->ops->set_egress_port)
5254                 return -EOPNOTSUPP;
5255
5256         mutex_lock(&chip->reg_lock);
5257         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5258             mirror->to_local_port) {
5259                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5260                         other_mirrors |= ingress ?
5261                                          chip->ports[i].mirror_ingress :
5262                                          chip->ports[i].mirror_egress;
5263
5264                 /* Can't change egress port when other mirror is active */
5265                 if (other_mirrors) {
5266                         err = -EBUSY;
5267                         goto out;
5268                 }
5269
5270                 err = chip->info->ops->set_egress_port(chip,
5271                                                        direction,
5272                                                        mirror->to_local_port);
5273                 if (err)
5274                         goto out;
5275         }
5276
5277         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5278 out:
5279         mutex_unlock(&chip->reg_lock);
5280
5281         return err;
5282 }
5283
5284 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5285                                       struct dsa_mall_mirror_tc_entry *mirror)
5286 {
5287         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5288                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5289                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5290         struct mv88e6xxx_chip *chip = ds->priv;
5291         bool other_mirrors = false;
5292         int i;
5293
5294         mutex_lock(&chip->reg_lock);
5295         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5296                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5297
5298         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5299                 other_mirrors |= mirror->ingress ?
5300                                  chip->ports[i].mirror_ingress :
5301                                  chip->ports[i].mirror_egress;
5302
5303         /* Reset egress port when no other mirror is active */
5304         if (!other_mirrors) {
5305                 if (chip->info->ops->set_egress_port(chip,
5306                                                      direction,
5307                                                      dsa_upstream_port(ds,
5308                                                                        port)))
5309                         dev_err(ds->dev, "failed to set egress port\n");
5310         }
5311
5312         mutex_unlock(&chip->reg_lock);
5313 }
5314
5315 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5316                                          bool unicast, bool multicast)
5317 {
5318         struct mv88e6xxx_chip *chip = ds->priv;
5319         int err = -EOPNOTSUPP;
5320
5321         mv88e6xxx_reg_lock(chip);
5322         if (chip->info->ops->port_set_egress_floods)
5323                 err = chip->info->ops->port_set_egress_floods(chip, port,
5324                                                               unicast,
5325                                                               multicast);
5326         mv88e6xxx_reg_unlock(chip);
5327
5328         return err;
5329 }
5330
5331 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5332         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
5333         .setup                  = mv88e6xxx_setup,
5334         .teardown               = mv88e6xxx_teardown,
5335         .phylink_validate       = mv88e6xxx_validate,
5336         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5337         .phylink_mac_config     = mv88e6xxx_mac_config,
5338         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5339         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
5340         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
5341         .get_strings            = mv88e6xxx_get_strings,
5342         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
5343         .get_sset_count         = mv88e6xxx_get_sset_count,
5344         .port_enable            = mv88e6xxx_port_enable,
5345         .port_disable           = mv88e6xxx_port_disable,
5346         .port_max_mtu           = mv88e6xxx_get_max_mtu,
5347         .port_change_mtu        = mv88e6xxx_change_mtu,
5348         .get_mac_eee            = mv88e6xxx_get_mac_eee,
5349         .set_mac_eee            = mv88e6xxx_set_mac_eee,
5350         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
5351         .get_eeprom             = mv88e6xxx_get_eeprom,
5352         .set_eeprom             = mv88e6xxx_set_eeprom,
5353         .get_regs_len           = mv88e6xxx_get_regs_len,
5354         .get_regs               = mv88e6xxx_get_regs,
5355         .get_rxnfc              = mv88e6xxx_get_rxnfc,
5356         .set_rxnfc              = mv88e6xxx_set_rxnfc,
5357         .set_ageing_time        = mv88e6xxx_set_ageing_time,
5358         .port_bridge_join       = mv88e6xxx_port_bridge_join,
5359         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
5360         .port_egress_floods     = mv88e6xxx_port_egress_floods,
5361         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
5362         .port_fast_age          = mv88e6xxx_port_fast_age,
5363         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
5364         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
5365         .port_vlan_add          = mv88e6xxx_port_vlan_add,
5366         .port_vlan_del          = mv88e6xxx_port_vlan_del,
5367         .port_fdb_add           = mv88e6xxx_port_fdb_add,
5368         .port_fdb_del           = mv88e6xxx_port_fdb_del,
5369         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5370         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5371         .port_mdb_add           = mv88e6xxx_port_mdb_add,
5372         .port_mdb_del           = mv88e6xxx_port_mdb_del,
5373         .port_mirror_add        = mv88e6xxx_port_mirror_add,
5374         .port_mirror_del        = mv88e6xxx_port_mirror_del,
5375         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
5376         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5377         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
5378         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
5379         .port_txtstamp          = mv88e6xxx_port_txtstamp,
5380         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
5381         .get_ts_info            = mv88e6xxx_get_ts_info,
5382         .devlink_param_get      = mv88e6xxx_devlink_param_get,
5383         .devlink_param_set      = mv88e6xxx_devlink_param_set,
5384         .devlink_info_get       = mv88e6xxx_devlink_info_get,
5385 };
5386
5387 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5388 {
5389         struct device *dev = chip->dev;
5390         struct dsa_switch *ds;
5391
5392         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5393         if (!ds)
5394                 return -ENOMEM;
5395
5396         ds->dev = dev;
5397         ds->num_ports = mv88e6xxx_num_ports(chip);
5398         ds->priv = chip;
5399         ds->dev = dev;
5400         ds->ops = &mv88e6xxx_switch_ops;
5401         ds->ageing_time_min = chip->info->age_time_coeff;
5402         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5403
5404         dev_set_drvdata(dev, ds);
5405
5406         return dsa_register_switch(ds);
5407 }
5408
5409 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5410 {
5411         dsa_unregister_switch(chip->ds);
5412 }
5413
5414 static const void *pdata_device_get_match_data(struct device *dev)
5415 {
5416         const struct of_device_id *matches = dev->driver->of_match_table;
5417         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5418
5419         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5420              matches++) {
5421                 if (!strcmp(pdata->compatible, matches->compatible))
5422                         return matches->data;
5423         }
5424         return NULL;
5425 }
5426
5427 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5428  * would be lost after a power cycle so prevent it to be suspended.
5429  */
5430 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5431 {
5432         return -EOPNOTSUPP;
5433 }
5434
5435 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5436 {
5437         return 0;
5438 }
5439
5440 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5441
5442 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5443 {
5444         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5445         const struct mv88e6xxx_info *compat_info = NULL;
5446         struct device *dev = &mdiodev->dev;
5447         struct device_node *np = dev->of_node;
5448         struct mv88e6xxx_chip *chip;
5449         int port;
5450         int err;
5451
5452         if (!np && !pdata)
5453                 return -EINVAL;
5454
5455         if (np)
5456                 compat_info = of_device_get_match_data(dev);
5457
5458         if (pdata) {
5459                 compat_info = pdata_device_get_match_data(dev);
5460
5461                 if (!pdata->netdev)
5462                         return -EINVAL;
5463
5464                 for (port = 0; port < DSA_MAX_PORTS; port++) {
5465                         if (!(pdata->enabled_ports & (1 << port)))
5466                                 continue;
5467                         if (strcmp(pdata->cd.port_names[port], "cpu"))
5468                                 continue;
5469                         pdata->cd.netdev[port] = &pdata->netdev->dev;
5470                         break;
5471                 }
5472         }
5473
5474         if (!compat_info)
5475                 return -EINVAL;
5476
5477         chip = mv88e6xxx_alloc_chip(dev);
5478         if (!chip) {
5479                 err = -ENOMEM;
5480                 goto out;
5481         }
5482
5483         chip->info = compat_info;
5484
5485         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5486         if (err)
5487                 goto out;
5488
5489         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5490         if (IS_ERR(chip->reset)) {
5491                 err = PTR_ERR(chip->reset);
5492                 goto out;
5493         }
5494         if (chip->reset)
5495                 usleep_range(1000, 2000);
5496
5497         err = mv88e6xxx_detect(chip);
5498         if (err)
5499                 goto out;
5500
5501         mv88e6xxx_phy_init(chip);
5502
5503         if (chip->info->ops->get_eeprom) {
5504                 if (np)
5505                         of_property_read_u32(np, "eeprom-length",
5506                                              &chip->eeprom_len);
5507                 else
5508                         chip->eeprom_len = pdata->eeprom_len;
5509         }
5510
5511         mv88e6xxx_reg_lock(chip);
5512         err = mv88e6xxx_switch_reset(chip);
5513         mv88e6xxx_reg_unlock(chip);
5514         if (err)
5515                 goto out;
5516
5517         if (np) {
5518                 chip->irq = of_irq_get(np, 0);
5519                 if (chip->irq == -EPROBE_DEFER) {
5520                         err = chip->irq;
5521                         goto out;
5522                 }
5523         }
5524
5525         if (pdata)
5526                 chip->irq = pdata->irq;
5527
5528         /* Has to be performed before the MDIO bus is created, because
5529          * the PHYs will link their interrupts to these interrupt
5530          * controllers
5531          */
5532         mv88e6xxx_reg_lock(chip);
5533         if (chip->irq > 0)
5534                 err = mv88e6xxx_g1_irq_setup(chip);
5535         else
5536                 err = mv88e6xxx_irq_poll_setup(chip);
5537         mv88e6xxx_reg_unlock(chip);
5538
5539         if (err)
5540                 goto out;
5541
5542         if (chip->info->g2_irqs > 0) {
5543                 err = mv88e6xxx_g2_irq_setup(chip);
5544                 if (err)
5545                         goto out_g1_irq;
5546         }
5547
5548         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5549         if (err)
5550                 goto out_g2_irq;
5551
5552         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5553         if (err)
5554                 goto out_g1_atu_prob_irq;
5555
5556         err = mv88e6xxx_mdios_register(chip, np);
5557         if (err)
5558                 goto out_g1_vtu_prob_irq;
5559
5560         err = mv88e6xxx_register_switch(chip);
5561         if (err)
5562                 goto out_mdio;
5563
5564         return 0;
5565
5566 out_mdio:
5567         mv88e6xxx_mdios_unregister(chip);
5568 out_g1_vtu_prob_irq:
5569         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5570 out_g1_atu_prob_irq:
5571         mv88e6xxx_g1_atu_prob_irq_free(chip);
5572 out_g2_irq:
5573         if (chip->info->g2_irqs > 0)
5574                 mv88e6xxx_g2_irq_free(chip);
5575 out_g1_irq:
5576         if (chip->irq > 0)
5577                 mv88e6xxx_g1_irq_free(chip);
5578         else
5579                 mv88e6xxx_irq_poll_free(chip);
5580 out:
5581         if (pdata)
5582                 dev_put(pdata->netdev);
5583
5584         return err;
5585 }
5586
5587 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5588 {
5589         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5590         struct mv88e6xxx_chip *chip = ds->priv;
5591
5592         if (chip->info->ptp_support) {
5593                 mv88e6xxx_hwtstamp_free(chip);
5594                 mv88e6xxx_ptp_free(chip);
5595         }
5596
5597         mv88e6xxx_phy_destroy(chip);
5598         mv88e6xxx_unregister_switch(chip);
5599         mv88e6xxx_mdios_unregister(chip);
5600
5601         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5602         mv88e6xxx_g1_atu_prob_irq_free(chip);
5603
5604         if (chip->info->g2_irqs > 0)
5605                 mv88e6xxx_g2_irq_free(chip);
5606
5607         if (chip->irq > 0)
5608                 mv88e6xxx_g1_irq_free(chip);
5609         else
5610                 mv88e6xxx_irq_poll_free(chip);
5611 }
5612
5613 static const struct of_device_id mv88e6xxx_of_match[] = {
5614         {
5615                 .compatible = "marvell,mv88e6085",
5616                 .data = &mv88e6xxx_table[MV88E6085],
5617         },
5618         {
5619                 .compatible = "marvell,mv88e6190",
5620                 .data = &mv88e6xxx_table[MV88E6190],
5621         },
5622         {
5623                 .compatible = "marvell,mv88e6250",
5624                 .data = &mv88e6xxx_table[MV88E6250],
5625         },
5626         { /* sentinel */ },
5627 };
5628
5629 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5630
5631 static struct mdio_driver mv88e6xxx_driver = {
5632         .probe  = mv88e6xxx_probe,
5633         .remove = mv88e6xxx_remove,
5634         .mdiodrv.driver = {
5635                 .name = "mv88e6085",
5636                 .of_match_table = mv88e6xxx_of_match,
5637                 .pm = &mv88e6xxx_pm_ops,
5638         },
5639 };
5640
5641 mdio_module_driver(mv88e6xxx_driver);
5642
5643 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5644 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5645 MODULE_LICENSE("GPL");