drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "global1.h"
  36 #include "global2.h"
  37 #include "hwtstamp.h"
  38 #include "phy.h"
  39 #include "port.h"
  40 #include "ptp.h"
  41 #include "serdes.h"
  42 #include "smi.h"
  43
  44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  45 {
  46         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  47                 dev_err(chip->dev, "Switch registers lock not held!\n");
  48                 dump_stack();
  49         }
  50 }
  51
  52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  53 {
  54         int err;
  55
  56         assert_reg_lock(chip);
  57
  58         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  59         if (err)
  60                 return err;
  61
  62         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  63                 addr, reg, *val);
  64
  65         return 0;
  66 }
  67
  68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  69 {
  70         int err;
  71
  72         assert_reg_lock(chip);
  73
  74         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  75         if (err)
  76                 return err;
  77
  78         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  79                 addr, reg, val);
  80
  81         return 0;
  82 }
  83
  84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  85                         u16 mask, u16 val)
  86 {
  87         u16 data;
  88         int err;
  89         int i;
  90
  91         /* There's no bus specific operation to wait for a mask */
  92         for (i = 0; i < 16; i++) {
  93                 err = mv88e6xxx_read(chip, addr, reg, &data);
  94                 if (err)
  95                         return err;
  96
  97                 if ((data & mask) == val)
  98                         return 0;
  99
 100                 usleep_range(1000, 2000);
 101         }
 102
 103         dev_err(chip->dev, "Timeout while waiting for switch\n");
 104         return -ETIMEDOUT;
 105 }
 106
 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 108                        int bit, int val)
 109 {
 110         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 111                                    val ? BIT(bit) : 0x0000);
 112 }
 113
 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 115 {
 116         struct mv88e6xxx_mdio_bus *mdio_bus;
 117
 118         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 119                                     list);
 120         if (!mdio_bus)
 121                 return NULL;
 122
 123         return mdio_bus->bus;
 124 }
 125
 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 127 {
 128         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 129         unsigned int n = d->hwirq;
 130
 131         chip->g1_irq.masked |= (1 << n);
 132 }
 133
 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 135 {
 136         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 137         unsigned int n = d->hwirq;
 138
 139         chip->g1_irq.masked &= ~(1 << n);
 140 }
 141
 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 143 {
 144         unsigned int nhandled = 0;
 145         unsigned int sub_irq;
 146         unsigned int n;
 147         u16 reg;
 148         u16 ctl1;
 149         int err;
 150
 151         mv88e6xxx_reg_lock(chip);
 152         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 153         mv88e6xxx_reg_unlock(chip);
 154
 155         if (err)
 156                 goto out;
 157
 158         do {
 159                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 160                         if (reg & (1 << n)) {
 161                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 162                                                            n);
 163                                 handle_nested_irq(sub_irq);
 164                                 ++nhandled;
 165                         }
 166                 }
 167
 168                 mv88e6xxx_reg_lock(chip);
 169                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 170                 if (err)
 171                         goto unlock;
 172                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 173 unlock:
 174                 mv88e6xxx_reg_unlock(chip);
 175                 if (err)
 176                         goto out;
 177                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 178         } while (reg & ctl1);
 179
 180 out:
 181         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 182 }
 183
 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 185 {
 186         struct mv88e6xxx_chip *chip = dev_id;
 187
 188         return mv88e6xxx_g1_irq_thread_work(chip);
 189 }
 190
 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 192 {
 193         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 194
 195         mv88e6xxx_reg_lock(chip);
 196 }
 197
 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 199 {
 200         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 201         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 202         u16 reg;
 203         int err;
 204
 205         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 206         if (err)
 207                 goto out;
 208
 209         reg &= ~mask;
 210         reg |= (~chip->g1_irq.masked & mask);
 211
 212         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 213         if (err)
 214                 goto out;
 215
 216 out:
 217         mv88e6xxx_reg_unlock(chip);
 218 }
 219
 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 221         .name                   = "mv88e6xxx-g1",
 222         .irq_mask               = mv88e6xxx_g1_irq_mask,
 223         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 224         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 225         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 226 };
 227
 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 229                                        unsigned int irq,
 230                                        irq_hw_number_t hwirq)
 231 {
 232         struct mv88e6xxx_chip *chip = d->host_data;
 233
 234         irq_set_chip_data(irq, d->host_data);
 235         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 236         irq_set_noprobe(irq);
 237
 238         return 0;
 239 }
 240
 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 242         .map    = mv88e6xxx_g1_irq_domain_map,
 243         .xlate  = irq_domain_xlate_twocell,
 244 };
 245
 246 /* To be called with reg_lock held */
 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 248 {
 249         int irq, virq;
 250         u16 mask;
 251
 252         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 253         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 254         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 255
 256         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 257                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 258                 irq_dispose_mapping(virq);
 259         }
 260
 261         irq_domain_remove(chip->g1_irq.domain);
 262 }
 263
 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 265 {
 266         /*
 267          * free_irq must be called without reg_lock taken because the irq
 268          * handler takes this lock, too.
 269          */
 270         free_irq(chip->irq, chip);
 271
 272         mv88e6xxx_reg_lock(chip);
 273         mv88e6xxx_g1_irq_free_common(chip);
 274         mv88e6xxx_reg_unlock(chip);
 275 }
 276
 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 278 {
 279         int err, irq, virq;
 280         u16 reg, mask;
 281
 282         chip->g1_irq.nirqs = chip->info->g1_irqs;
 283         chip->g1_irq.domain = irq_domain_add_simple(
 284                 NULL, chip->g1_irq.nirqs, 0,
 285                 &mv88e6xxx_g1_irq_domain_ops, chip);
 286         if (!chip->g1_irq.domain)
 287                 return -ENOMEM;
 288
 289         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 290                 irq_create_mapping(chip->g1_irq.domain, irq);
 291
 292         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 293         chip->g1_irq.masked = ~0;
 294
 295         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 296         if (err)
 297                 goto out_mapping;
 298
 299         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 300
 301         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 302         if (err)
 303                 goto out_disable;
 304
 305         /* Reading the interrupt status clears (most of) them */
 306         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 307         if (err)
 308                 goto out_disable;
 309
 310         return 0;
 311
 312 out_disable:
 313         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 314         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 315
 316 out_mapping:
 317         for (irq = 0; irq < 16; irq++) {
 318                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 319                 irq_dispose_mapping(virq);
 320         }
 321
 322         irq_domain_remove(chip->g1_irq.domain);
 323
 324         return err;
 325 }
 326
 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 328 {
 329         static struct lock_class_key lock_key;
 330         static struct lock_class_key request_key;
 331         int err;
 332
 333         err = mv88e6xxx_g1_irq_setup_common(chip);
 334         if (err)
 335                 return err;
 336
 337         /* These lock classes tells lockdep that global 1 irqs are in
 338          * a different category than their parent GPIO, so it won't
 339          * report false recursion.
 340          */
 341         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 342
 343         snprintf(chip->irq_name, sizeof(chip->irq_name),
 344                  "mv88e6xxx-%s", dev_name(chip->dev));
 345
 346         mv88e6xxx_reg_unlock(chip);
 347         err = request_threaded_irq(chip->irq, NULL,
 348                                    mv88e6xxx_g1_irq_thread_fn,
 349                                    IRQF_ONESHOT | IRQF_SHARED,
 350                                    chip->irq_name, chip);
 351         mv88e6xxx_reg_lock(chip);
 352         if (err)
 353                 mv88e6xxx_g1_irq_free_common(chip);
 354
 355         return err;
 356 }
 357
 358 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 359 {
 360         struct mv88e6xxx_chip *chip = container_of(work,
 361                                                    struct mv88e6xxx_chip,
 362                                                    irq_poll_work.work);
 363         mv88e6xxx_g1_irq_thread_work(chip);
 364
 365         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 366                                    msecs_to_jiffies(100));
 367 }
 368
 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 370 {
 371         int err;
 372
 373         err = mv88e6xxx_g1_irq_setup_common(chip);
 374         if (err)
 375                 return err;
 376
 377         kthread_init_delayed_work(&chip->irq_poll_work,
 378                                   mv88e6xxx_irq_poll);
 379
 380         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 381         if (IS_ERR(chip->kworker))
 382                 return PTR_ERR(chip->kworker);
 383
 384         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 385                                    msecs_to_jiffies(100));
 386
 387         return 0;
 388 }
 389
 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 391 {
 392         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 393         kthread_destroy_worker(chip->kworker);
 394
 395         mv88e6xxx_reg_lock(chip);
 396         mv88e6xxx_g1_irq_free_common(chip);
 397         mv88e6xxx_reg_unlock(chip);
 398 }
 399
 400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 401                                            int port, phy_interface_t interface)
 402 {
 403         int err;
 404
 405         if (chip->info->ops->port_set_rgmii_delay) {
 406                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 407                                                             interface);
 408                 if (err && err != -EOPNOTSUPP)
 409                         return err;
 410         }
 411
 412         if (chip->info->ops->port_set_cmode) {
 413                 err = chip->info->ops->port_set_cmode(chip, port,
 414                                                       interface);
 415                 if (err && err != -EOPNOTSUPP)
 416                         return err;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 423                                     int link, int speed, int duplex, int pause,
 424                                     phy_interface_t mode)
 425 {
 426         int err;
 427
 428         if (!chip->info->ops->port_set_link)
 429                 return 0;
 430
 431         /* Port's MAC control must not be changed unless the link is down */
 432         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 433         if (err)
 434                 return err;
 435
 436         if (chip->info->ops->port_set_speed_duplex) {
 437                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 438                                                              speed, duplex);
 439                 if (err && err != -EOPNOTSUPP)
 440                         goto restore_link;
 441         }
 442
 443         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 444                 mode = chip->info->ops->port_max_speed_mode(port);
 445
 446         if (chip->info->ops->port_set_pause) {
 447                 err = chip->info->ops->port_set_pause(chip, port, pause);
 448                 if (err)
 449                         goto restore_link;
 450         }
 451
 452         err = mv88e6xxx_port_config_interface(chip, port, mode);
 453 restore_link:
 454         if (chip->info->ops->port_set_link(chip, port, link))
 455                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 456
 457         return err;
 458 }
 459
 460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 461 {
 462         struct mv88e6xxx_chip *chip = ds->priv;
 463
 464         return port < chip->info->num_internal_phys;
 465 }
 466
 467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 468 {
 469         u16 reg;
 470         int err;
 471
 472         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 473         if (err) {
 474                 dev_err(chip->dev,
 475                         "p%d: %s: failed to read port status\n",
 476                         port, __func__);
 477                 return err;
 478         }
 479
 480         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 481 }
 482
 483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 484                                           struct phylink_link_state *state)
 485 {
 486         struct mv88e6xxx_chip *chip = ds->priv;
 487         u8 lane;
 488         int err;
 489
 490         mv88e6xxx_reg_lock(chip);
 491         lane = mv88e6xxx_serdes_get_lane(chip, port);
 492         if (lane && chip->info->ops->serdes_pcs_get_state)
 493                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 494                                                             state);
 495         else
 496                 err = -EOPNOTSUPP;
 497         mv88e6xxx_reg_unlock(chip);
 498
 499         return err;
 500 }
 501
 502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 503                                        unsigned int mode,
 504                                        phy_interface_t interface,
 505                                        const unsigned long *advertise)
 506 {
 507         const struct mv88e6xxx_ops *ops = chip->info->ops;
 508         u8 lane;
 509
 510         if (ops->serdes_pcs_config) {
 511                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 512                 if (lane)
 513                         return ops->serdes_pcs_config(chip, port, lane, mode,
 514                                                       interface, advertise);
 515         }
 516
 517         return 0;
 518 }
 519
 520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 521 {
 522         struct mv88e6xxx_chip *chip = ds->priv;
 523         const struct mv88e6xxx_ops *ops;
 524         int err = 0;
 525         u8 lane;
 526
 527         ops = chip->info->ops;
 528
 529         if (ops->serdes_pcs_an_restart) {
 530                 mv88e6xxx_reg_lock(chip);
 531                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 532                 if (lane)
 533                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 534                 mv88e6xxx_reg_unlock(chip);
 535
 536                 if (err)
 537                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 538         }
 539 }
 540
 541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 542                                         unsigned int mode,
 543                                         int speed, int duplex)
 544 {
 545         const struct mv88e6xxx_ops *ops = chip->info->ops;
 546         u8 lane;
 547
 548         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 549                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 550                 if (lane)
 551                         return ops->serdes_pcs_link_up(chip, port, lane,
 552                                                        speed, duplex);
 553         }
 554
 555         return 0;
 556 }
 557
 558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 559                                        unsigned long *mask,
 560                                        struct phylink_link_state *state)
 561 {
 562         if (!phy_interface_mode_is_8023z(state->interface)) {
 563                 /* 10M and 100M are only supported in non-802.3z mode */
 564                 phylink_set(mask, 10baseT_Half);
 565                 phylink_set(mask, 10baseT_Full);
 566                 phylink_set(mask, 100baseT_Half);
 567                 phylink_set(mask, 100baseT_Full);
 568         }
 569 }
 570
 571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 572                                        unsigned long *mask,
 573                                        struct phylink_link_state *state)
 574 {
 575         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 576          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 577          */
 578         phylink_set(mask, 1000baseT_Full);
 579         phylink_set(mask, 1000baseX_Full);
 580
 581         mv88e6065_phylink_validate(chip, port, mask, state);
 582 }
 583
 584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 585                                        unsigned long *mask,
 586                                        struct phylink_link_state *state)
 587 {
 588         if (port >= 5)
 589                 phylink_set(mask, 2500baseX_Full);
 590
 591         /* No ethtool bits for 200Mbps */
 592         phylink_set(mask, 1000baseT_Full);
 593         phylink_set(mask, 1000baseX_Full);
 594
 595         mv88e6065_phylink_validate(chip, port, mask, state);
 596 }
 597
 598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 599                                        unsigned long *mask,
 600                                        struct phylink_link_state *state)
 601 {
 602         /* No ethtool bits for 200Mbps */
 603         phylink_set(mask, 1000baseT_Full);
 604         phylink_set(mask, 1000baseX_Full);
 605
 606         mv88e6065_phylink_validate(chip, port, mask, state);
 607 }
 608
 609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 610                                        unsigned long *mask,
 611                                        struct phylink_link_state *state)
 612 {
 613         if (port >= 9) {
 614                 phylink_set(mask, 2500baseX_Full);
 615                 phylink_set(mask, 2500baseT_Full);
 616         }
 617
 618         /* No ethtool bits for 200Mbps */
 619         phylink_set(mask, 1000baseT_Full);
 620         phylink_set(mask, 1000baseX_Full);
 621
 622         mv88e6065_phylink_validate(chip, port, mask, state);
 623 }
 624
 625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 626                                         unsigned long *mask,
 627                                         struct phylink_link_state *state)
 628 {
 629         if (port >= 9) {
 630                 phylink_set(mask, 10000baseT_Full);
 631                 phylink_set(mask, 10000baseKR_Full);
 632         }
 633
 634         mv88e6390_phylink_validate(chip, port, mask, state);
 635 }
 636
 637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 638                                unsigned long *supported,
 639                                struct phylink_link_state *state)
 640 {
 641         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 642         struct mv88e6xxx_chip *chip = ds->priv;
 643
 644         /* Allow all the expected bits */
 645         phylink_set(mask, Autoneg);
 646         phylink_set(mask, Pause);
 647         phylink_set_port_modes(mask);
 648
 649         if (chip->info->ops->phylink_validate)
 650                 chip->info->ops->phylink_validate(chip, port, mask, state);
 651
 652         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 653         bitmap_and(state->advertising, state->advertising, mask,
 654                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 655
 656         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 657          * to advertise both, only report advertising at 2500BaseX.
 658          */
 659         phylink_helper_basex_speed(state);
 660 }
 661
 662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 663                                  unsigned int mode,
 664                                  const struct phylink_link_state *state)
 665 {
 666         struct mv88e6xxx_chip *chip = ds->priv;
 667         int err;
 668
 669         /* FIXME: is this the correct test? If we're in fixed mode on an
 670          * internal port, why should we process this any different from
 671          * PHY mode? On the other hand, the port may be automedia between
 672          * an internal PHY and the serdes...
 673          */
 674         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 675                 return;
 676
 677         mv88e6xxx_reg_lock(chip);
 678         /* FIXME: should we force the link down here - but if we do, how
 679          * do we restore the link force/unforce state? The driver layering
 680          * gets in the way.
 681          */
 682         err = mv88e6xxx_port_config_interface(chip, port, state->interface);
 683         if (err && err != -EOPNOTSUPP)
 684                 goto err_unlock;
 685
 686         err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
 687                                           state->advertising);
 688         /* FIXME: we should restart negotiation if something changed - which
 689          * is something we get if we convert to using phylinks PCS operations.
 690          */
 691         if (err > 0)
 692                 err = 0;
 693
 694 err_unlock:
 695         mv88e6xxx_reg_unlock(chip);
 696
 697         if (err && err != -EOPNOTSUPP)
 698                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 699 }
 700
 701 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 702                                     unsigned int mode,
 703                                     phy_interface_t interface)
 704 {
 705         struct mv88e6xxx_chip *chip = ds->priv;
 706         const struct mv88e6xxx_ops *ops;
 707         int err = 0;
 708
 709         ops = chip->info->ops;
 710
 711         mv88e6xxx_reg_lock(chip);
 712         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 713              mode == MLO_AN_FIXED) && ops->port_set_link)
 714                 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 715         mv88e6xxx_reg_unlock(chip);
 716
 717         if (err)
 718                 dev_err(chip->dev,
 719                         "p%d: failed to force MAC link down\n", port);
 720 }
 721
 722 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 723                                   unsigned int mode, phy_interface_t interface,
 724                                   struct phy_device *phydev,
 725                                   int speed, int duplex,
 726                                   bool tx_pause, bool rx_pause)
 727 {
 728         struct mv88e6xxx_chip *chip = ds->priv;
 729         const struct mv88e6xxx_ops *ops;
 730         int err = 0;
 731
 732         ops = chip->info->ops;
 733
 734         mv88e6xxx_reg_lock(chip);
 735         if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
 736                 /* FIXME: for an automedia port, should we force the link
 737                  * down here - what if the link comes up due to "other" media
 738                  * while we're bringing the port up, how is the exclusivity
 739                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 740                  * shared between internal PHY and Serdes.
 741                  */
 742                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 743                                                    duplex);
 744                 if (err)
 745                         goto error;
 746
 747                 if (ops->port_set_speed_duplex) {
 748                         err = ops->port_set_speed_duplex(chip, port,
 749                                                          speed, duplex);
 750                         if (err && err != -EOPNOTSUPP)
 751                                 goto error;
 752                 }
 753
 754                 if (ops->port_set_link)
 755                         err = ops->port_set_link(chip, port, LINK_FORCED_UP);
 756         }
 757 error:
 758         mv88e6xxx_reg_unlock(chip);
 759
 760         if (err && err != -EOPNOTSUPP)
 761                 dev_err(ds->dev,
 762                         "p%d: failed to configure MAC link up\n", port);
 763 }
 764
 765 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 766 {
 767         if (!chip->info->ops->stats_snapshot)
 768                 return -EOPNOTSUPP;
 769
 770         return chip->info->ops->stats_snapshot(chip, port);
 771 }
 772
 773 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 774         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 775         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 776         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 777         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 778         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 779         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 780         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 781         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 782         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 783         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 784         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 785         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 786         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 787         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 788         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 789         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 790         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 791         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 792         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 793         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 794         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 795         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 796         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 797         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 798         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 799         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 800         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 801         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 802         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 803         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 804         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 805         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 806         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 807         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 808         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 809         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 810         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 811         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 812         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 813         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 814         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 815         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 816         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 817         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 818         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 819         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 820         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 821         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 822         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 823         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 824         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 825         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 826         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 827         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 828         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 829         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 830         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 831         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 832         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 833 };
 834
 835 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 836                                             struct mv88e6xxx_hw_stat *s,
 837                                             int port, u16 bank1_select,
 838                                             u16 histogram)
 839 {
 840         u32 low;
 841         u32 high = 0;
 842         u16 reg = 0;
 843         int err;
 844         u64 value;
 845
 846         switch (s->type) {
 847         case STATS_TYPE_PORT:
 848                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 849                 if (err)
 850                         return U64_MAX;
 851
 852                 low = reg;
 853                 if (s->size == 4) {
 854                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 855                         if (err)
 856                                 return U64_MAX;
 857                         low |= ((u32)reg) << 16;
 858                 }
 859                 break;
 860         case STATS_TYPE_BANK1:
 861                 reg = bank1_select;
 862                 /* fall through */
 863         case STATS_TYPE_BANK0:
 864                 reg |= s->reg | histogram;
 865                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 866                 if (s->size == 8)
 867                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 868                 break;
 869         default:
 870                 return U64_MAX;
 871         }
 872         value = (((u64)high) << 32) | low;
 873         return value;
 874 }
 875
 876 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 877                                        uint8_t *data, int types)
 878 {
 879         struct mv88e6xxx_hw_stat *stat;
 880         int i, j;
 881
 882         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 883                 stat = &mv88e6xxx_hw_stats[i];
 884                 if (stat->type & types) {
 885                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 886                                ETH_GSTRING_LEN);
 887                         j++;
 888                 }
 889         }
 890
 891         return j;
 892 }
 893
 894 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 895                                        uint8_t *data)
 896 {
 897         return mv88e6xxx_stats_get_strings(chip, data,
 898                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 899 }
 900
 901 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 902                                        uint8_t *data)
 903 {
 904         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 905 }
 906
 907 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 908                                        uint8_t *data)
 909 {
 910         return mv88e6xxx_stats_get_strings(chip, data,
 911                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 912 }
 913
 914 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 915         "atu_member_violation",
 916         "atu_miss_violation",
 917         "atu_full_violation",
 918         "vtu_member_violation",
 919         "vtu_miss_violation",
 920 };
 921
 922 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 923 {
 924         unsigned int i;
 925
 926         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 927                 strlcpy(data + i * ETH_GSTRING_LEN,
 928                         mv88e6xxx_atu_vtu_stats_strings[i],
 929                         ETH_GSTRING_LEN);
 930 }
 931
 932 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 933                                   u32 stringset, uint8_t *data)
 934 {
 935         struct mv88e6xxx_chip *chip = ds->priv;
 936         int count = 0;
 937
 938         if (stringset != ETH_SS_STATS)
 939                 return;
 940
 941         mv88e6xxx_reg_lock(chip);
 942
 943         if (chip->info->ops->stats_get_strings)
 944                 count = chip->info->ops->stats_get_strings(chip, data);
 945
 946         if (chip->info->ops->serdes_get_strings) {
 947                 data += count * ETH_GSTRING_LEN;
 948                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 949         }
 950
 951         data += count * ETH_GSTRING_LEN;
 952         mv88e6xxx_atu_vtu_get_strings(data);
 953
 954         mv88e6xxx_reg_unlock(chip);
 955 }
 956
 957 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 958                                           int types)
 959 {
 960         struct mv88e6xxx_hw_stat *stat;
 961         int i, j;
 962
 963         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 964                 stat = &mv88e6xxx_hw_stats[i];
 965                 if (stat->type & types)
 966                         j++;
 967         }
 968         return j;
 969 }
 970
 971 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 972 {
 973         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 974                                               STATS_TYPE_PORT);
 975 }
 976
 977 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 978 {
 979         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 980 }
 981
 982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 983 {
 984         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 985                                               STATS_TYPE_BANK1);
 986 }
 987
 988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
 989 {
 990         struct mv88e6xxx_chip *chip = ds->priv;
 991         int serdes_count = 0;
 992         int count = 0;
 993
 994         if (sset != ETH_SS_STATS)
 995                 return 0;
 996
 997         mv88e6xxx_reg_lock(chip);
 998         if (chip->info->ops->stats_get_sset_count)
 999                 count = chip->info->ops->stats_get_sset_count(chip);
1000         if (count < 0)
1001                 goto out;
1002
1003         if (chip->info->ops->serdes_get_sset_count)
1004                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1005                                                                       port);
1006         if (serdes_count < 0) {
1007                 count = serdes_count;
1008                 goto out;
1009         }
1010         count += serdes_count;
1011         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1012
1013 out:
1014         mv88e6xxx_reg_unlock(chip);
1015
1016         return count;
1017 }
1018
1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1020                                      uint64_t *data, int types,
1021                                      u16 bank1_select, u16 histogram)
1022 {
1023         struct mv88e6xxx_hw_stat *stat;
1024         int i, j;
1025
1026         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1027                 stat = &mv88e6xxx_hw_stats[i];
1028                 if (stat->type & types) {
1029                         mv88e6xxx_reg_lock(chip);
1030                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1031                                                               bank1_select,
1032                                                               histogram);
1033                         mv88e6xxx_reg_unlock(chip);
1034
1035                         j++;
1036                 }
1037         }
1038         return j;
1039 }
1040
1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1042                                      uint64_t *data)
1043 {
1044         return mv88e6xxx_stats_get_stats(chip, port, data,
1045                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1046                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1047 }
1048
1049 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1050                                      uint64_t *data)
1051 {
1052         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1053                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1054 }
1055
1056 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1057                                      uint64_t *data)
1058 {
1059         return mv88e6xxx_stats_get_stats(chip, port, data,
1060                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1061                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1062                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1063 }
1064
1065 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1066                                      uint64_t *data)
1067 {
1068         return mv88e6xxx_stats_get_stats(chip, port, data,
1069                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1070                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1071                                          0);
1072 }
1073
1074 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1075                                         uint64_t *data)
1076 {
1077         *data++ = chip->ports[port].atu_member_violation;
1078         *data++ = chip->ports[port].atu_miss_violation;
1079         *data++ = chip->ports[port].atu_full_violation;
1080         *data++ = chip->ports[port].vtu_member_violation;
1081         *data++ = chip->ports[port].vtu_miss_violation;
1082 }
1083
1084 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1085                                 uint64_t *data)
1086 {
1087         int count = 0;
1088
1089         if (chip->info->ops->stats_get_stats)
1090                 count = chip->info->ops->stats_get_stats(chip, port, data);
1091
1092         mv88e6xxx_reg_lock(chip);
1093         if (chip->info->ops->serdes_get_stats) {
1094                 data += count;
1095                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1096         }
1097         data += count;
1098         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1099         mv88e6xxx_reg_unlock(chip);
1100 }
1101
1102 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1103                                         uint64_t *data)
1104 {
1105         struct mv88e6xxx_chip *chip = ds->priv;
1106         int ret;
1107
1108         mv88e6xxx_reg_lock(chip);
1109
1110         ret = mv88e6xxx_stats_snapshot(chip, port);
1111         mv88e6xxx_reg_unlock(chip);
1112
1113         if (ret < 0)
1114                 return;
1115
1116         mv88e6xxx_get_stats(chip, port, data);
1117
1118 }
1119
1120 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1121 {
1122         struct mv88e6xxx_chip *chip = ds->priv;
1123         int len;
1124
1125         len = 32 * sizeof(u16);
1126         if (chip->info->ops->serdes_get_regs_len)
1127                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1128
1129         return len;
1130 }
1131
1132 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1133                                struct ethtool_regs *regs, void *_p)
1134 {
1135         struct mv88e6xxx_chip *chip = ds->priv;
1136         int err;
1137         u16 reg;
1138         u16 *p = _p;
1139         int i;
1140
1141         regs->version = chip->info->prod_num;
1142
1143         memset(p, 0xff, 32 * sizeof(u16));
1144
1145         mv88e6xxx_reg_lock(chip);
1146
1147         for (i = 0; i < 32; i++) {
1148
1149                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1150                 if (!err)
1151                         p[i] = reg;
1152         }
1153
1154         if (chip->info->ops->serdes_get_regs)
1155                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1156
1157         mv88e6xxx_reg_unlock(chip);
1158 }
1159
1160 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1161                                  struct ethtool_eee *e)
1162 {
1163         /* Nothing to do on the port's MAC */
1164         return 0;
1165 }
1166
1167 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1168                                  struct ethtool_eee *e)
1169 {
1170         /* Nothing to do on the port's MAC */
1171         return 0;
1172 }
1173
1174 /* Mask of the local ports allowed to receive frames from a given fabric port */
1175 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1176 {
1177         struct dsa_switch *ds = chip->ds;
1178         struct dsa_switch_tree *dst = ds->dst;
1179         struct net_device *br;
1180         struct dsa_port *dp;
1181         bool found = false;
1182         u16 pvlan;
1183
1184         list_for_each_entry(dp, &dst->ports, list) {
1185                 if (dp->ds->index == dev && dp->index == port) {
1186                         found = true;
1187                         break;
1188                 }
1189         }
1190
1191         /* Prevent frames from unknown switch or port */
1192         if (!found)
1193                 return 0;
1194
1195         /* Frames from DSA links and CPU ports can egress any local port */
1196         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1197                 return mv88e6xxx_port_mask(chip);
1198
1199         br = dp->bridge_dev;
1200         pvlan = 0;
1201
1202         /* Frames from user ports can egress any local DSA links and CPU ports,
1203          * as well as any local member of their bridge group.
1204          */
1205         list_for_each_entry(dp, &dst->ports, list)
1206                 if (dp->ds == ds &&
1207                     (dp->type == DSA_PORT_TYPE_CPU ||
1208                      dp->type == DSA_PORT_TYPE_DSA ||
1209                      (br && dp->bridge_dev == br)))
1210                         pvlan |= BIT(dp->index);
1211
1212         return pvlan;
1213 }
1214
1215 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1216 {
1217         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1218
1219         /* prevent frames from going back out of the port they came in on */
1220         output_ports &= ~BIT(port);
1221
1222         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1223 }
1224
1225 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1226                                          u8 state)
1227 {
1228         struct mv88e6xxx_chip *chip = ds->priv;
1229         int err;
1230
1231         mv88e6xxx_reg_lock(chip);
1232         err = mv88e6xxx_port_set_state(chip, port, state);
1233         mv88e6xxx_reg_unlock(chip);
1234
1235         if (err)
1236                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1237 }
1238
1239 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1240 {
1241         int err;
1242
1243         if (chip->info->ops->ieee_pri_map) {
1244                 err = chip->info->ops->ieee_pri_map(chip);
1245                 if (err)
1246                         return err;
1247         }
1248
1249         if (chip->info->ops->ip_pri_map) {
1250                 err = chip->info->ops->ip_pri_map(chip);
1251                 if (err)
1252                         return err;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1259 {
1260         struct dsa_switch *ds = chip->ds;
1261         int target, port;
1262         int err;
1263
1264         if (!chip->info->global2_addr)
1265                 return 0;
1266
1267         /* Initialize the routing port to the 32 possible target devices */
1268         for (target = 0; target < 32; target++) {
1269                 port = dsa_routing_port(ds, target);
1270                 if (port == ds->num_ports)
1271                         port = 0x1f;
1272
1273                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1274                 if (err)
1275                         return err;
1276         }
1277
1278         if (chip->info->ops->set_cascade_port) {
1279                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1280                 err = chip->info->ops->set_cascade_port(chip, port);
1281                 if (err)
1282                         return err;
1283         }
1284
1285         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1286         if (err)
1287                 return err;
1288
1289         return 0;
1290 }
1291
1292 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1293 {
1294         /* Clear all trunk masks and mapping */
1295         if (chip->info->global2_addr)
1296                 return mv88e6xxx_g2_trunk_clear(chip);
1297
1298         return 0;
1299 }
1300
1301 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1302 {
1303         if (chip->info->ops->rmu_disable)
1304                 return chip->info->ops->rmu_disable(chip);
1305
1306         return 0;
1307 }
1308
1309 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1310 {
1311         if (chip->info->ops->pot_clear)
1312                 return chip->info->ops->pot_clear(chip);
1313
1314         return 0;
1315 }
1316
1317 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1318 {
1319         if (chip->info->ops->mgmt_rsvd2cpu)
1320                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1321
1322         return 0;
1323 }
1324
1325 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1326 {
1327         int err;
1328
1329         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1330         if (err)
1331                 return err;
1332
1333         err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1334         if (err)
1335                 return err;
1336
1337         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1338 }
1339
1340 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1341 {
1342         int port;
1343         int err;
1344
1345         if (!chip->info->ops->irl_init_all)
1346                 return 0;
1347
1348         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1349                 /* Disable ingress rate limiting by resetting all per port
1350                  * ingress rate limit resources to their initial state.
1351                  */
1352                 err = chip->info->ops->irl_init_all(chip, port);
1353                 if (err)
1354                         return err;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1361 {
1362         if (chip->info->ops->set_switch_mac) {
1363                 u8 addr[ETH_ALEN];
1364
1365                 eth_random_addr(addr);
1366
1367                 return chip->info->ops->set_switch_mac(chip, addr);
1368         }
1369
1370         return 0;
1371 }
1372
1373 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1374 {
1375         u16 pvlan = 0;
1376
1377         if (!mv88e6xxx_has_pvt(chip))
1378                 return 0;
1379
1380         /* Skip the local source device, which uses in-chip port VLAN */
1381         if (dev != chip->ds->index)
1382                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1383
1384         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1385 }
1386
1387 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1388 {
1389         int dev, port;
1390         int err;
1391
1392         if (!mv88e6xxx_has_pvt(chip))
1393                 return 0;
1394
1395         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1396          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1397          */
1398         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1399         if (err)
1400                 return err;
1401
1402         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1403                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1404                         err = mv88e6xxx_pvt_map(chip, dev, port);
1405                         if (err)
1406                                 return err;
1407                 }
1408         }
1409
1410         return 0;
1411 }
1412
1413 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1414 {
1415         struct mv88e6xxx_chip *chip = ds->priv;
1416         int err;
1417
1418         mv88e6xxx_reg_lock(chip);
1419         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1420         mv88e6xxx_reg_unlock(chip);
1421
1422         if (err)
1423                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1424 }
1425
1426 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1427 {
1428         if (!chip->info->max_vid)
1429                 return 0;
1430
1431         return mv88e6xxx_g1_vtu_flush(chip);
1432 }
1433
1434 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1435                                  struct mv88e6xxx_vtu_entry *entry)
1436 {
1437         if (!chip->info->ops->vtu_getnext)
1438                 return -EOPNOTSUPP;
1439
1440         return chip->info->ops->vtu_getnext(chip, entry);
1441 }
1442
1443 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1444                                    struct mv88e6xxx_vtu_entry *entry)
1445 {
1446         if (!chip->info->ops->vtu_loadpurge)
1447                 return -EOPNOTSUPP;
1448
1449         return chip->info->ops->vtu_loadpurge(chip, entry);
1450 }
1451
1452 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1453 {
1454         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1455         struct mv88e6xxx_vtu_entry vlan;
1456         int i, err;
1457
1458         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1459
1460         /* Set every FID bit used by the (un)bridged ports */
1461         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1462                 err = mv88e6xxx_port_get_fid(chip, i, fid);
1463                 if (err)
1464                         return err;
1465
1466                 set_bit(*fid, fid_bitmap);
1467         }
1468
1469         /* Set every FID bit used by the VLAN entries */
1470         vlan.vid = chip->info->max_vid;
1471         vlan.valid = false;
1472
1473         do {
1474                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1475                 if (err)
1476                         return err;
1477
1478                 if (!vlan.valid)
1479                         break;
1480
1481                 set_bit(vlan.fid, fid_bitmap);
1482         } while (vlan.vid < chip->info->max_vid);
1483
1484         /* The reset value 0x000 is used to indicate that multiple address
1485          * databases are not needed. Return the next positive available.
1486          */
1487         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1488         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1489                 return -ENOSPC;
1490
1491         /* Clear the database */
1492         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1493 }
1494
1495 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
1496 {
1497         if (chip->info->ops->atu_get_hash)
1498                 return chip->info->ops->atu_get_hash(chip, hash);
1499
1500         return -EOPNOTSUPP;
1501 }
1502
1503 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
1504 {
1505         if (chip->info->ops->atu_set_hash)
1506                 return chip->info->ops->atu_set_hash(chip, hash);
1507
1508         return -EOPNOTSUPP;
1509 }
1510
1511 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1512                                         u16 vid_begin, u16 vid_end)
1513 {
1514         struct mv88e6xxx_chip *chip = ds->priv;
1515         struct mv88e6xxx_vtu_entry vlan;
1516         int i, err;
1517
1518         /* DSA and CPU ports have to be members of multiple vlans */
1519         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1520                 return 0;
1521
1522         if (!vid_begin)
1523                 return -EOPNOTSUPP;
1524
1525         vlan.vid = vid_begin - 1;
1526         vlan.valid = false;
1527
1528         do {
1529                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1530                 if (err)
1531                         return err;
1532
1533                 if (!vlan.valid)
1534                         break;
1535
1536                 if (vlan.vid > vid_end)
1537                         break;
1538
1539                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1540                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1541                                 continue;
1542
1543                         if (!dsa_to_port(ds, i)->slave)
1544                                 continue;
1545
1546                         if (vlan.member[i] ==
1547                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1548                                 continue;
1549
1550                         if (dsa_to_port(ds, i)->bridge_dev ==
1551                             dsa_to_port(ds, port)->bridge_dev)
1552                                 break; /* same bridge, check next VLAN */
1553
1554                         if (!dsa_to_port(ds, i)->bridge_dev)
1555                                 continue;
1556
1557                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1558                                 port, vlan.vid, i,
1559                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1560                         return -EOPNOTSUPP;
1561                 }
1562         } while (vlan.vid < vid_end);
1563
1564         return 0;
1565 }
1566
1567 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1568                                          bool vlan_filtering)
1569 {
1570         struct mv88e6xxx_chip *chip = ds->priv;
1571         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1572                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1573         int err;
1574
1575         if (!chip->info->max_vid)
1576                 return -EOPNOTSUPP;
1577
1578         mv88e6xxx_reg_lock(chip);
1579         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1580         mv88e6xxx_reg_unlock(chip);
1581
1582         return err;
1583 }
1584
1585 static int
1586 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1587                             const struct switchdev_obj_port_vlan *vlan)
1588 {
1589         struct mv88e6xxx_chip *chip = ds->priv;
1590         int err;
1591
1592         if (!chip->info->max_vid)
1593                 return -EOPNOTSUPP;
1594
1595         /* If the requested port doesn't belong to the same bridge as the VLAN
1596          * members, do not support it (yet) and fallback to software VLAN.
1597          */
1598         mv88e6xxx_reg_lock(chip);
1599         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1600                                            vlan->vid_end);
1601         mv88e6xxx_reg_unlock(chip);
1602
1603         /* We don't need any dynamic resource from the kernel (yet),
1604          * so skip the prepare phase.
1605          */
1606         return err;
1607 }
1608
1609 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1610                                         const unsigned char *addr, u16 vid,
1611                                         u8 state)
1612 {
1613         struct mv88e6xxx_atu_entry entry;
1614         struct mv88e6xxx_vtu_entry vlan;
1615         u16 fid;
1616         int err;
1617
1618         /* Null VLAN ID corresponds to the port private database */
1619         if (vid == 0) {
1620                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1621                 if (err)
1622                         return err;
1623         } else {
1624                 vlan.vid = vid - 1;
1625                 vlan.valid = false;
1626
1627                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1628                 if (err)
1629                         return err;
1630
1631                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1632                 if (vlan.vid != vid || !vlan.valid)
1633                         return -EOPNOTSUPP;
1634
1635                 fid = vlan.fid;
1636         }
1637
1638         entry.state = 0;
1639         ether_addr_copy(entry.mac, addr);
1640         eth_addr_dec(entry.mac);
1641
1642         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1643         if (err)
1644                 return err;
1645
1646         /* Initialize a fresh ATU entry if it isn't found */
1647         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1648                 memset(&entry, 0, sizeof(entry));
1649                 ether_addr_copy(entry.mac, addr);
1650         }
1651
1652         /* Purge the ATU entry only if no port is using it anymore */
1653         if (!state) {
1654                 entry.portvec &= ~BIT(port);
1655                 if (!entry.portvec)
1656                         entry.state = 0;
1657         } else {
1658                 entry.portvec |= BIT(port);
1659                 entry.state = state;
1660         }
1661
1662         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1663 }
1664
1665 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1666                                   const struct mv88e6xxx_policy *policy)
1667 {
1668         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1669         enum mv88e6xxx_policy_action action = policy->action;
1670         const u8 *addr = policy->addr;
1671         u16 vid = policy->vid;
1672         u8 state;
1673         int err;
1674         int id;
1675
1676         if (!chip->info->ops->port_set_policy)
1677                 return -EOPNOTSUPP;
1678
1679         switch (mapping) {
1680         case MV88E6XXX_POLICY_MAPPING_DA:
1681         case MV88E6XXX_POLICY_MAPPING_SA:
1682                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1683                         state = 0; /* Dissociate the port and address */
1684                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1685                          is_multicast_ether_addr(addr))
1686                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1687                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1688                          is_unicast_ether_addr(addr))
1689                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1690                 else
1691                         return -EOPNOTSUPP;
1692
1693                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1694                                                    state);
1695                 if (err)
1696                         return err;
1697                 break;
1698         default:
1699                 return -EOPNOTSUPP;
1700         }
1701
1702         /* Skip the port's policy clearing if the mapping is still in use */
1703         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1704                 idr_for_each_entry(&chip->policies, policy, id)
1705                         if (policy->port == port &&
1706                             policy->mapping == mapping &&
1707                             policy->action != action)
1708                                 return 0;
1709
1710         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1711 }
1712
1713 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1714                                    struct ethtool_rx_flow_spec *fs)
1715 {
1716         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1717         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1718         enum mv88e6xxx_policy_mapping mapping;
1719         enum mv88e6xxx_policy_action action;
1720         struct mv88e6xxx_policy *policy;
1721         u16 vid = 0;
1722         u8 *addr;
1723         int err;
1724         int id;
1725
1726         if (fs->location != RX_CLS_LOC_ANY)
1727                 return -EINVAL;
1728
1729         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1730                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1731         else
1732                 return -EOPNOTSUPP;
1733
1734         switch (fs->flow_type & ~FLOW_EXT) {
1735         case ETHER_FLOW:
1736                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1737                     is_zero_ether_addr(mac_mask->h_source)) {
1738                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1739                         addr = mac_entry->h_dest;
1740                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1741                     !is_zero_ether_addr(mac_mask->h_source)) {
1742                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1743                         addr = mac_entry->h_source;
1744                 } else {
1745                         /* Cannot support DA and SA mapping in the same rule */
1746                         return -EOPNOTSUPP;
1747                 }
1748                 break;
1749         default:
1750                 return -EOPNOTSUPP;
1751         }
1752
1753         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1754                 if (fs->m_ext.vlan_tci != 0xffff)
1755                         return -EOPNOTSUPP;
1756                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1757         }
1758
1759         idr_for_each_entry(&chip->policies, policy, id) {
1760                 if (policy->port == port && policy->mapping == mapping &&
1761                     policy->action == action && policy->vid == vid &&
1762                     ether_addr_equal(policy->addr, addr))
1763                         return -EEXIST;
1764         }
1765
1766         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1767         if (!policy)
1768                 return -ENOMEM;
1769
1770         fs->location = 0;
1771         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1772                             GFP_KERNEL);
1773         if (err) {
1774                 devm_kfree(chip->dev, policy);
1775                 return err;
1776         }
1777
1778         memcpy(&policy->fs, fs, sizeof(*fs));
1779         ether_addr_copy(policy->addr, addr);
1780         policy->mapping = mapping;
1781         policy->action = action;
1782         policy->port = port;
1783         policy->vid = vid;
1784
1785         err = mv88e6xxx_policy_apply(chip, port, policy);
1786         if (err) {
1787                 idr_remove(&chip->policies, fs->location);
1788                 devm_kfree(chip->dev, policy);
1789                 return err;
1790         }
1791
1792         return 0;
1793 }
1794
1795 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1796                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1797 {
1798         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1799         struct mv88e6xxx_chip *chip = ds->priv;
1800         struct mv88e6xxx_policy *policy;
1801         int err;
1802         int id;
1803
1804         mv88e6xxx_reg_lock(chip);
1805
1806         switch (rxnfc->cmd) {
1807         case ETHTOOL_GRXCLSRLCNT:
1808                 rxnfc->data = 0;
1809                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1810                 rxnfc->rule_cnt = 0;
1811                 idr_for_each_entry(&chip->policies, policy, id)
1812                         if (policy->port == port)
1813                                 rxnfc->rule_cnt++;
1814                 err = 0;
1815                 break;
1816         case ETHTOOL_GRXCLSRULE:
1817                 err = -ENOENT;
1818                 policy = idr_find(&chip->policies, fs->location);
1819                 if (policy) {
1820                         memcpy(fs, &policy->fs, sizeof(*fs));
1821                         err = 0;
1822                 }
1823                 break;
1824         case ETHTOOL_GRXCLSRLALL:
1825                 rxnfc->data = 0;
1826                 rxnfc->rule_cnt = 0;
1827                 idr_for_each_entry(&chip->policies, policy, id)
1828                         if (policy->port == port)
1829                                 rule_locs[rxnfc->rule_cnt++] = id;
1830                 err = 0;
1831                 break;
1832         default:
1833                 err = -EOPNOTSUPP;
1834                 break;
1835         }
1836
1837         mv88e6xxx_reg_unlock(chip);
1838
1839         return err;
1840 }
1841
1842 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1843                                struct ethtool_rxnfc *rxnfc)
1844 {
1845         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1846         struct mv88e6xxx_chip *chip = ds->priv;
1847         struct mv88e6xxx_policy *policy;
1848         int err;
1849
1850         mv88e6xxx_reg_lock(chip);
1851
1852         switch (rxnfc->cmd) {
1853         case ETHTOOL_SRXCLSRLINS:
1854                 err = mv88e6xxx_policy_insert(chip, port, fs);
1855                 break;
1856         case ETHTOOL_SRXCLSRLDEL:
1857                 err = -ENOENT;
1858                 policy = idr_remove(&chip->policies, fs->location);
1859                 if (policy) {
1860                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1861                         err = mv88e6xxx_policy_apply(chip, port, policy);
1862                         devm_kfree(chip->dev, policy);
1863                 }
1864                 break;
1865         default:
1866                 err = -EOPNOTSUPP;
1867                 break;
1868         }
1869
1870         mv88e6xxx_reg_unlock(chip);
1871
1872         return err;
1873 }
1874
1875 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1876                                         u16 vid)
1877 {
1878         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1879         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1880
1881         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1882 }
1883
1884 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1885 {
1886         int port;
1887         int err;
1888
1889         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1890                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1891                 if (err)
1892                         return err;
1893         }
1894
1895         return 0;
1896 }
1897
1898 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1899                                     u16 vid, u8 member, bool warn)
1900 {
1901         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1902         struct mv88e6xxx_vtu_entry vlan;
1903         int i, err;
1904
1905         if (!vid)
1906                 return -EOPNOTSUPP;
1907
1908         vlan.vid = vid - 1;
1909         vlan.valid = false;
1910
1911         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1912         if (err)
1913                 return err;
1914
1915         if (vlan.vid != vid || !vlan.valid) {
1916                 memset(&vlan, 0, sizeof(vlan));
1917
1918                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1919                 if (err)
1920                         return err;
1921
1922                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1923                         if (i == port)
1924                                 vlan.member[i] = member;
1925                         else
1926                                 vlan.member[i] = non_member;
1927
1928                 vlan.vid = vid;
1929                 vlan.valid = true;
1930
1931                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1932                 if (err)
1933                         return err;
1934
1935                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1936                 if (err)
1937                         return err;
1938         } else if (vlan.member[port] != member) {
1939                 vlan.member[port] = member;
1940
1941                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1942                 if (err)
1943                         return err;
1944         } else if (warn) {
1945                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1946                          port, vid);
1947         }
1948
1949         return 0;
1950 }
1951
1952 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1953                                     const struct switchdev_obj_port_vlan *vlan)
1954 {
1955         struct mv88e6xxx_chip *chip = ds->priv;
1956         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1957         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1958         bool warn;
1959         u8 member;
1960         u16 vid;
1961
1962         if (!chip->info->max_vid)
1963                 return;
1964
1965         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1966                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1967         else if (untagged)
1968                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1969         else
1970                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1971
1972         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
1973          * and then the CPU port. Do not warn for duplicates for the CPU port.
1974          */
1975         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
1976
1977         mv88e6xxx_reg_lock(chip);
1978
1979         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1980                 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
1981                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1982                                 vid, untagged ? 'u' : 't');
1983
1984         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1985                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1986                         vlan->vid_end);
1987
1988         mv88e6xxx_reg_unlock(chip);
1989 }
1990
1991 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
1992                                      int port, u16 vid)
1993 {
1994         struct mv88e6xxx_vtu_entry vlan;
1995         int i, err;
1996
1997         if (!vid)
1998                 return -EOPNOTSUPP;
1999
2000         vlan.vid = vid - 1;
2001         vlan.valid = false;
2002
2003         err = mv88e6xxx_vtu_getnext(chip, &vlan);
2004         if (err)
2005                 return err;
2006
2007         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2008          * tell switchdev that this VLAN is likely handled in software.
2009          */
2010         if (vlan.vid != vid || !vlan.valid ||
2011             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2012                 return -EOPNOTSUPP;
2013
2014         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2015
2016         /* keep the VLAN unless all ports are excluded */
2017         vlan.valid = false;
2018         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2019                 if (vlan.member[i] !=
2020                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2021                         vlan.valid = true;
2022                         break;
2023                 }
2024         }
2025
2026         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2027         if (err)
2028                 return err;
2029
2030         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2031 }
2032
2033 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2034                                    const struct switchdev_obj_port_vlan *vlan)
2035 {
2036         struct mv88e6xxx_chip *chip = ds->priv;
2037         u16 pvid, vid;
2038         int err = 0;
2039
2040         if (!chip->info->max_vid)
2041                 return -EOPNOTSUPP;
2042
2043         mv88e6xxx_reg_lock(chip);
2044
2045         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2046         if (err)
2047                 goto unlock;
2048
2049         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2050                 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2051                 if (err)
2052                         goto unlock;
2053
2054                 if (vid == pvid) {
2055                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
2056                         if (err)
2057                                 goto unlock;
2058                 }
2059         }
2060
2061 unlock:
2062         mv88e6xxx_reg_unlock(chip);
2063
2064         return err;
2065 }
2066
2067 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2068                                   const unsigned char *addr, u16 vid)
2069 {
2070         struct mv88e6xxx_chip *chip = ds->priv;
2071         int err;
2072
2073         mv88e6xxx_reg_lock(chip);
2074         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2075                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2076         mv88e6xxx_reg_unlock(chip);
2077
2078         return err;
2079 }
2080
2081 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2082                                   const unsigned char *addr, u16 vid)
2083 {
2084         struct mv88e6xxx_chip *chip = ds->priv;
2085         int err;
2086
2087         mv88e6xxx_reg_lock(chip);
2088         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2089         mv88e6xxx_reg_unlock(chip);
2090
2091         return err;
2092 }
2093
2094 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2095                                       u16 fid, u16 vid, int port,
2096                                       dsa_fdb_dump_cb_t *cb, void *data)
2097 {
2098         struct mv88e6xxx_atu_entry addr;
2099         bool is_static;
2100         int err;
2101
2102         addr.state = 0;
2103         eth_broadcast_addr(addr.mac);
2104
2105         do {
2106                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2107                 if (err)
2108                         return err;
2109
2110                 if (!addr.state)
2111                         break;
2112
2113                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2114                         continue;
2115
2116                 if (!is_unicast_ether_addr(addr.mac))
2117                         continue;
2118
2119                 is_static = (addr.state ==
2120                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2121                 err = cb(addr.mac, vid, is_static, data);
2122                 if (err)
2123                         return err;
2124         } while (!is_broadcast_ether_addr(addr.mac));
2125
2126         return err;
2127 }
2128
2129 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2130                                   dsa_fdb_dump_cb_t *cb, void *data)
2131 {
2132         struct mv88e6xxx_vtu_entry vlan;
2133         u16 fid;
2134         int err;
2135
2136         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2137         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2138         if (err)
2139                 return err;
2140
2141         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2142         if (err)
2143                 return err;
2144
2145         /* Dump VLANs' Filtering Information Databases */
2146         vlan.vid = chip->info->max_vid;
2147         vlan.valid = false;
2148
2149         do {
2150                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2151                 if (err)
2152                         return err;
2153
2154                 if (!vlan.valid)
2155                         break;
2156
2157                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2158                                                  cb, data);
2159                 if (err)
2160                         return err;
2161         } while (vlan.vid < chip->info->max_vid);
2162
2163         return err;
2164 }
2165
2166 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2167                                    dsa_fdb_dump_cb_t *cb, void *data)
2168 {
2169         struct mv88e6xxx_chip *chip = ds->priv;
2170         int err;
2171
2172         mv88e6xxx_reg_lock(chip);
2173         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2174         mv88e6xxx_reg_unlock(chip);
2175
2176         return err;
2177 }
2178
2179 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2180                                 struct net_device *br)
2181 {
2182         struct dsa_switch *ds = chip->ds;
2183         struct dsa_switch_tree *dst = ds->dst;
2184         struct dsa_port *dp;
2185         int err;
2186
2187         list_for_each_entry(dp, &dst->ports, list) {
2188                 if (dp->bridge_dev == br) {
2189                         if (dp->ds == ds) {
2190                                 /* This is a local bridge group member,
2191                                  * remap its Port VLAN Map.
2192                                  */
2193                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2194                                 if (err)
2195                                         return err;
2196                         } else {
2197                                 /* This is an external bridge group member,
2198                                  * remap its cross-chip Port VLAN Table entry.
2199                                  */
2200                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2201                                                         dp->index);
2202                                 if (err)
2203                                         return err;
2204                         }
2205                 }
2206         }
2207
2208         return 0;
2209 }
2210
2211 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2212                                       struct net_device *br)
2213 {
2214         struct mv88e6xxx_chip *chip = ds->priv;
2215         int err;
2216
2217         mv88e6xxx_reg_lock(chip);
2218         err = mv88e6xxx_bridge_map(chip, br);
2219         mv88e6xxx_reg_unlock(chip);
2220
2221         return err;
2222 }
2223
2224 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2225                                         struct net_device *br)
2226 {
2227         struct mv88e6xxx_chip *chip = ds->priv;
2228
2229         mv88e6xxx_reg_lock(chip);
2230         if (mv88e6xxx_bridge_map(chip, br) ||
2231             mv88e6xxx_port_vlan_map(chip, port))
2232                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2233         mv88e6xxx_reg_unlock(chip);
2234 }
2235
2236 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2237                                            int port, struct net_device *br)
2238 {
2239         struct mv88e6xxx_chip *chip = ds->priv;
2240         int err;
2241
2242         mv88e6xxx_reg_lock(chip);
2243         err = mv88e6xxx_pvt_map(chip, dev, port);
2244         mv88e6xxx_reg_unlock(chip);
2245
2246         return err;
2247 }
2248
2249 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2250                                              int port, struct net_device *br)
2251 {
2252         struct mv88e6xxx_chip *chip = ds->priv;
2253
2254         mv88e6xxx_reg_lock(chip);
2255         if (mv88e6xxx_pvt_map(chip, dev, port))
2256                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2257         mv88e6xxx_reg_unlock(chip);
2258 }
2259
2260 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2261 {
2262         if (chip->info->ops->reset)
2263                 return chip->info->ops->reset(chip);
2264
2265         return 0;
2266 }
2267
2268 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2269 {
2270         struct gpio_desc *gpiod = chip->reset;
2271
2272         /* If there is a GPIO connected to the reset pin, toggle it */
2273         if (gpiod) {
2274                 gpiod_set_value_cansleep(gpiod, 1);
2275                 usleep_range(10000, 20000);
2276                 gpiod_set_value_cansleep(gpiod, 0);
2277                 usleep_range(10000, 20000);
2278         }
2279 }
2280
2281 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2282 {
2283         int i, err;
2284
2285         /* Set all ports to the Disabled state */
2286         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2287                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2288                 if (err)
2289                         return err;
2290         }
2291
2292         /* Wait for transmit queues to drain,
2293          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2294          */
2295         usleep_range(2000, 4000);
2296
2297         return 0;
2298 }
2299
2300 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2301 {
2302         int err;
2303
2304         err = mv88e6xxx_disable_ports(chip);
2305         if (err)
2306                 return err;
2307
2308         mv88e6xxx_hardware_reset(chip);
2309
2310         return mv88e6xxx_software_reset(chip);
2311 }
2312
2313 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2314                                    enum mv88e6xxx_frame_mode frame,
2315                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2316 {
2317         int err;
2318
2319         if (!chip->info->ops->port_set_frame_mode)
2320                 return -EOPNOTSUPP;
2321
2322         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2323         if (err)
2324                 return err;
2325
2326         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2327         if (err)
2328                 return err;
2329
2330         if (chip->info->ops->port_set_ether_type)
2331                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2332
2333         return 0;
2334 }
2335
2336 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2337 {
2338         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2339                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2340                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2341 }
2342
2343 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2344 {
2345         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2346                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2347                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2348 }
2349
2350 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2351 {
2352         return mv88e6xxx_set_port_mode(chip, port,
2353                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2354                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2355                                        ETH_P_EDSA);
2356 }
2357
2358 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2359 {
2360         if (dsa_is_dsa_port(chip->ds, port))
2361                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2362
2363         if (dsa_is_user_port(chip->ds, port))
2364                 return mv88e6xxx_set_port_mode_normal(chip, port);
2365
2366         /* Setup CPU port mode depending on its supported tag format */
2367         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2368                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2369
2370         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2371                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2372
2373         return -EINVAL;
2374 }
2375
2376 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2377 {
2378         bool message = dsa_is_dsa_port(chip->ds, port);
2379
2380         return mv88e6xxx_port_set_message_port(chip, port, message);
2381 }
2382
2383 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2384 {
2385         struct dsa_switch *ds = chip->ds;
2386         bool flood;
2387
2388         /* Upstream ports flood frames with unknown unicast or multicast DA */
2389         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2390         if (chip->info->ops->port_set_egress_floods)
2391                 return chip->info->ops->port_set_egress_floods(chip, port,
2392                                                                flood, flood);
2393
2394         return 0;
2395 }
2396
2397 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2398 {
2399         struct mv88e6xxx_port *mvp = dev_id;
2400         struct mv88e6xxx_chip *chip = mvp->chip;
2401         irqreturn_t ret = IRQ_NONE;
2402         int port = mvp->port;
2403         u8 lane;
2404
2405         mv88e6xxx_reg_lock(chip);
2406         lane = mv88e6xxx_serdes_get_lane(chip, port);
2407         if (lane)
2408                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2409         mv88e6xxx_reg_unlock(chip);
2410
2411         return ret;
2412 }
2413
2414 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2415                                         u8 lane)
2416 {
2417         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2418         unsigned int irq;
2419         int err;
2420
2421         /* Nothing to request if this SERDES port has no IRQ */
2422         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2423         if (!irq)
2424                 return 0;
2425
2426         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2427                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2428
2429         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2430         mv88e6xxx_reg_unlock(chip);
2431         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2432                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
2433                                    dev_id);
2434         mv88e6xxx_reg_lock(chip);
2435         if (err)
2436                 return err;
2437
2438         dev_id->serdes_irq = irq;
2439
2440         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2441 }
2442
2443 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2444                                      u8 lane)
2445 {
2446         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2447         unsigned int irq = dev_id->serdes_irq;
2448         int err;
2449
2450         /* Nothing to free if no IRQ has been requested */
2451         if (!irq)
2452                 return 0;
2453
2454         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2455
2456         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2457         mv88e6xxx_reg_unlock(chip);
2458         free_irq(irq, dev_id);
2459         mv88e6xxx_reg_lock(chip);
2460
2461         dev_id->serdes_irq = 0;
2462
2463         return err;
2464 }
2465
2466 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2467                                   bool on)
2468 {
2469         u8 lane;
2470         int err;
2471
2472         lane = mv88e6xxx_serdes_get_lane(chip, port);
2473         if (!lane)
2474                 return 0;
2475
2476         if (on) {
2477                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2478                 if (err)
2479                         return err;
2480
2481                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2482         } else {
2483                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2484                 if (err)
2485                         return err;
2486
2487                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2488         }
2489
2490         return err;
2491 }
2492
2493 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2494 {
2495         struct dsa_switch *ds = chip->ds;
2496         int upstream_port;
2497         int err;
2498
2499         upstream_port = dsa_upstream_port(ds, port);
2500         if (chip->info->ops->port_set_upstream_port) {
2501                 err = chip->info->ops->port_set_upstream_port(chip, port,
2502                                                               upstream_port);
2503                 if (err)
2504                         return err;
2505         }
2506
2507         if (port == upstream_port) {
2508                 if (chip->info->ops->set_cpu_port) {
2509                         err = chip->info->ops->set_cpu_port(chip,
2510                                                             upstream_port);
2511                         if (err)
2512                                 return err;
2513                 }
2514
2515                 if (chip->info->ops->set_egress_port) {
2516                         err = chip->info->ops->set_egress_port(chip,
2517                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
2518                                                 upstream_port);
2519                         if (err)
2520                                 return err;
2521
2522                         err = chip->info->ops->set_egress_port(chip,
2523                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
2524                                                 upstream_port);
2525                         if (err)
2526                                 return err;
2527                 }
2528         }
2529
2530         return 0;
2531 }
2532
2533 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2534 {
2535         struct dsa_switch *ds = chip->ds;
2536         int err;
2537         u16 reg;
2538
2539         chip->ports[port].chip = chip;
2540         chip->ports[port].port = port;
2541
2542         /* MAC Forcing register: don't force link, speed, duplex or flow control
2543          * state to any particular values on physical ports, but force the CPU
2544          * port and all DSA ports to their maximum bandwidth and full duplex.
2545          */
2546         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2547                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2548                                                SPEED_MAX, DUPLEX_FULL,
2549                                                PAUSE_OFF,
2550                                                PHY_INTERFACE_MODE_NA);
2551         else
2552                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2553                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2554                                                PAUSE_ON,
2555                                                PHY_INTERFACE_MODE_NA);
2556         if (err)
2557                 return err;
2558
2559         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2560          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2561          * tunneling, determine priority by looking at 802.1p and IP
2562          * priority fields (IP prio has precedence), and set STP state
2563          * to Forwarding.
2564          *
2565          * If this is the CPU link, use DSA or EDSA tagging depending
2566          * on which tagging mode was configured.
2567          *
2568          * If this is a link to another switch, use DSA tagging mode.
2569          *
2570          * If this is the upstream port for this switch, enable
2571          * forwarding of unknown unicasts and multicasts.
2572          */
2573         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2574                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2575                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2576         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2577         if (err)
2578                 return err;
2579
2580         err = mv88e6xxx_setup_port_mode(chip, port);
2581         if (err)
2582                 return err;
2583
2584         err = mv88e6xxx_setup_egress_floods(chip, port);
2585         if (err)
2586                 return err;
2587
2588         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2589          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2590          * untagged frames on this port, do a destination address lookup on all
2591          * received packets as usual, disable ARP mirroring and don't send a
2592          * copy of all transmitted/received frames on this port to the CPU.
2593          */
2594         err = mv88e6xxx_port_set_map_da(chip, port);
2595         if (err)
2596                 return err;
2597
2598         err = mv88e6xxx_setup_upstream_port(chip, port);
2599         if (err)
2600                 return err;
2601
2602         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2603                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2604         if (err)
2605                 return err;
2606
2607         if (chip->info->ops->port_set_jumbo_size) {
2608                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2609                 if (err)
2610                         return err;
2611         }
2612
2613         /* Port Association Vector: when learning source addresses
2614          * of packets, add the address to the address database using
2615          * a port bitmap that has only the bit for this port set and
2616          * the other bits clear.
2617          */
2618         reg = 1 << port;
2619         /* Disable learning for CPU port */
2620         if (dsa_is_cpu_port(ds, port))
2621                 reg = 0;
2622
2623         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2624                                    reg);
2625         if (err)
2626                 return err;
2627
2628         /* Egress rate control 2: disable egress rate control. */
2629         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2630                                    0x0000);
2631         if (err)
2632                 return err;
2633
2634         if (chip->info->ops->port_pause_limit) {
2635                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2636                 if (err)
2637                         return err;
2638         }
2639
2640         if (chip->info->ops->port_disable_learn_limit) {
2641                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2642                 if (err)
2643                         return err;
2644         }
2645
2646         if (chip->info->ops->port_disable_pri_override) {
2647                 err = chip->info->ops->port_disable_pri_override(chip, port);
2648                 if (err)
2649                         return err;
2650         }
2651
2652         if (chip->info->ops->port_tag_remap) {
2653                 err = chip->info->ops->port_tag_remap(chip, port);
2654                 if (err)
2655                         return err;
2656         }
2657
2658         if (chip->info->ops->port_egress_rate_limiting) {
2659                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2660                 if (err)
2661                         return err;
2662         }
2663
2664         if (chip->info->ops->port_setup_message_port) {
2665                 err = chip->info->ops->port_setup_message_port(chip, port);
2666                 if (err)
2667                         return err;
2668         }
2669
2670         /* Port based VLAN map: give each port the same default address
2671          * database, and allow bidirectional communication between the
2672          * CPU and DSA port(s), and the other ports.
2673          */
2674         err = mv88e6xxx_port_set_fid(chip, port, 0);
2675         if (err)
2676                 return err;
2677
2678         err = mv88e6xxx_port_vlan_map(chip, port);
2679         if (err)
2680                 return err;
2681
2682         /* Default VLAN ID and priority: don't set a default VLAN
2683          * ID, and set the default packet priority to zero.
2684          */
2685         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2686 }
2687
2688 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2689                                  struct phy_device *phydev)
2690 {
2691         struct mv88e6xxx_chip *chip = ds->priv;
2692         int err;
2693
2694         mv88e6xxx_reg_lock(chip);
2695         err = mv88e6xxx_serdes_power(chip, port, true);
2696         mv88e6xxx_reg_unlock(chip);
2697
2698         return err;
2699 }
2700
2701 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2702 {
2703         struct mv88e6xxx_chip *chip = ds->priv;
2704
2705         mv88e6xxx_reg_lock(chip);
2706         if (mv88e6xxx_serdes_power(chip, port, false))
2707                 dev_err(chip->dev, "failed to power off SERDES\n");
2708         mv88e6xxx_reg_unlock(chip);
2709 }
2710
2711 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2712                                      unsigned int ageing_time)
2713 {
2714         struct mv88e6xxx_chip *chip = ds->priv;
2715         int err;
2716
2717         mv88e6xxx_reg_lock(chip);
2718         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2719         mv88e6xxx_reg_unlock(chip);
2720
2721         return err;
2722 }
2723
2724 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2725 {
2726         int err;
2727
2728         /* Initialize the statistics unit */
2729         if (chip->info->ops->stats_set_histogram) {
2730                 err = chip->info->ops->stats_set_histogram(chip);
2731                 if (err)
2732                         return err;
2733         }
2734
2735         return mv88e6xxx_g1_stats_clear(chip);
2736 }
2737
2738 /* Check if the errata has already been applied. */
2739 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2740 {
2741         int port;
2742         int err;
2743         u16 val;
2744
2745         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2746                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2747                 if (err) {
2748                         dev_err(chip->dev,
2749                                 "Error reading hidden register: %d\n", err);
2750                         return false;
2751                 }
2752                 if (val != 0x01c0)
2753                         return false;
2754         }
2755
2756         return true;
2757 }
2758
2759 /* The 6390 copper ports have an errata which require poking magic
2760  * values into undocumented hidden registers and then performing a
2761  * software reset.
2762  */
2763 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2764 {
2765         int port;
2766         int err;
2767
2768         if (mv88e6390_setup_errata_applied(chip))
2769                 return 0;
2770
2771         /* Set the ports into blocking mode */
2772         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2773                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2774                 if (err)
2775                         return err;
2776         }
2777
2778         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2779                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2780                 if (err)
2781                         return err;
2782         }
2783
2784         return mv88e6xxx_software_reset(chip);
2785 }
2786
2787 enum mv88e6xxx_devlink_param_id {
2788         MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
2789         MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2790 };
2791
2792 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
2793                                        struct devlink_param_gset_ctx *ctx)
2794 {
2795         struct mv88e6xxx_chip *chip = ds->priv;
2796         int err;
2797
2798         mv88e6xxx_reg_lock(chip);
2799
2800         switch (id) {
2801         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2802                 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
2803                 break;
2804         default:
2805                 err = -EOPNOTSUPP;
2806                 break;
2807         }
2808
2809         mv88e6xxx_reg_unlock(chip);
2810
2811         return err;
2812 }
2813
2814 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
2815                                        struct devlink_param_gset_ctx *ctx)
2816 {
2817         struct mv88e6xxx_chip *chip = ds->priv;
2818         int err;
2819
2820         mv88e6xxx_reg_lock(chip);
2821
2822         switch (id) {
2823         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2824                 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
2825                 break;
2826         default:
2827                 err = -EOPNOTSUPP;
2828                 break;
2829         }
2830
2831         mv88e6xxx_reg_unlock(chip);
2832
2833         return err;
2834 }
2835
2836 static const struct devlink_param mv88e6xxx_devlink_params[] = {
2837         DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2838                                  "ATU_hash", DEVLINK_PARAM_TYPE_U8,
2839                                  BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
2840 };
2841
2842 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
2843 {
2844         return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
2845                                            ARRAY_SIZE(mv88e6xxx_devlink_params));
2846 }
2847
2848 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
2849 {
2850         dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
2851                                       ARRAY_SIZE(mv88e6xxx_devlink_params));
2852 }
2853
2854 enum mv88e6xxx_devlink_resource_id {
2855         MV88E6XXX_RESOURCE_ID_ATU,
2856         MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2857         MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2858         MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2859         MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2860 };
2861
2862 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip,
2863                                          u16 bin)
2864 {
2865         u16 occupancy = 0;
2866         int err;
2867
2868         mv88e6xxx_reg_lock(chip);
2869
2870         err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL,
2871                                          bin);
2872         if (err) {
2873                 dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
2874                 goto unlock;
2875         }
2876
2877         err = mv88e6xxx_g1_atu_get_next(chip, 0);
2878         if (err) {
2879                 dev_err(chip->dev, "failed to perform ATU get next\n");
2880                 goto unlock;
2881         }
2882
2883         err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy);
2884         if (err) {
2885                 dev_err(chip->dev, "failed to get ATU stats\n");
2886                 goto unlock;
2887         }
2888
2889         occupancy &= MV88E6XXX_G2_ATU_STATS_MASK;
2890
2891 unlock:
2892         mv88e6xxx_reg_unlock(chip);
2893
2894         return occupancy;
2895 }
2896
2897 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv)
2898 {
2899         struct mv88e6xxx_chip *chip = priv;
2900
2901         return mv88e6xxx_devlink_atu_bin_get(chip,
2902                                              MV88E6XXX_G2_ATU_STATS_BIN_0);
2903 }
2904
2905 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv)
2906 {
2907         struct mv88e6xxx_chip *chip = priv;
2908
2909         return mv88e6xxx_devlink_atu_bin_get(chip,
2910                                              MV88E6XXX_G2_ATU_STATS_BIN_1);
2911 }
2912
2913 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv)
2914 {
2915         struct mv88e6xxx_chip *chip = priv;
2916
2917         return mv88e6xxx_devlink_atu_bin_get(chip,
2918                                              MV88E6XXX_G2_ATU_STATS_BIN_2);
2919 }
2920
2921 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv)
2922 {
2923         struct mv88e6xxx_chip *chip = priv;
2924
2925         return mv88e6xxx_devlink_atu_bin_get(chip,
2926                                              MV88E6XXX_G2_ATU_STATS_BIN_3);
2927 }
2928
2929 static u64 mv88e6xxx_devlink_atu_get(void *priv)
2930 {
2931         return mv88e6xxx_devlink_atu_bin_0_get(priv) +
2932                 mv88e6xxx_devlink_atu_bin_1_get(priv) +
2933                 mv88e6xxx_devlink_atu_bin_2_get(priv) +
2934                 mv88e6xxx_devlink_atu_bin_3_get(priv);
2935 }
2936
2937 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds)
2938 {
2939         struct devlink_resource_size_params size_params;
2940         struct mv88e6xxx_chip *chip = ds->priv;
2941         int err;
2942
2943         devlink_resource_size_params_init(&size_params,
2944                                           mv88e6xxx_num_macs(chip),
2945                                           mv88e6xxx_num_macs(chip),
2946                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
2947
2948         err = dsa_devlink_resource_register(ds, "ATU",
2949                                             mv88e6xxx_num_macs(chip),
2950                                             MV88E6XXX_RESOURCE_ID_ATU,
2951                                             DEVLINK_RESOURCE_ID_PARENT_TOP,
2952                                             &size_params);
2953         if (err)
2954                 goto out;
2955
2956         devlink_resource_size_params_init(&size_params,
2957                                           mv88e6xxx_num_macs(chip) / 4,
2958                                           mv88e6xxx_num_macs(chip) / 4,
2959                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
2960
2961         err = dsa_devlink_resource_register(ds, "ATU_bin_0",
2962                                             mv88e6xxx_num_macs(chip) / 4,
2963                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2964                                             MV88E6XXX_RESOURCE_ID_ATU,
2965                                             &size_params);
2966         if (err)
2967                 goto out;
2968
2969         err = dsa_devlink_resource_register(ds, "ATU_bin_1",
2970                                             mv88e6xxx_num_macs(chip) / 4,
2971                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2972                                             MV88E6XXX_RESOURCE_ID_ATU,
2973                                             &size_params);
2974         if (err)
2975                 goto out;
2976
2977         err = dsa_devlink_resource_register(ds, "ATU_bin_2",
2978                                             mv88e6xxx_num_macs(chip) / 4,
2979                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2980                                             MV88E6XXX_RESOURCE_ID_ATU,
2981                                             &size_params);
2982         if (err)
2983                 goto out;
2984
2985         err = dsa_devlink_resource_register(ds, "ATU_bin_3",
2986                                             mv88e6xxx_num_macs(chip) / 4,
2987                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2988                                             MV88E6XXX_RESOURCE_ID_ATU,
2989                                             &size_params);
2990         if (err)
2991                 goto out;
2992
2993         dsa_devlink_resource_occ_get_register(ds,
2994                                               MV88E6XXX_RESOURCE_ID_ATU,
2995                                               mv88e6xxx_devlink_atu_get,
2996                                               chip);
2997
2998         dsa_devlink_resource_occ_get_register(ds,
2999                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
3000                                               mv88e6xxx_devlink_atu_bin_0_get,
3001                                               chip);
3002
3003         dsa_devlink_resource_occ_get_register(ds,
3004                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
3005                                               mv88e6xxx_devlink_atu_bin_1_get,
3006                                               chip);
3007
3008         dsa_devlink_resource_occ_get_register(ds,
3009                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
3010                                               mv88e6xxx_devlink_atu_bin_2_get,
3011                                               chip);
3012
3013         dsa_devlink_resource_occ_get_register(ds,
3014                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
3015                                               mv88e6xxx_devlink_atu_bin_3_get,
3016                                               chip);
3017
3018         return 0;
3019
3020 out:
3021         dsa_devlink_resources_unregister(ds);
3022         return err;
3023 }
3024
3025 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3026 {
3027         mv88e6xxx_teardown_devlink_params(ds);
3028         dsa_devlink_resources_unregister(ds);
3029 }
3030
3031 static int mv88e6xxx_setup(struct dsa_switch *ds)
3032 {
3033         struct mv88e6xxx_chip *chip = ds->priv;
3034         u8 cmode;
3035         int err;
3036         int i;
3037
3038         chip->ds = ds;
3039         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3040
3041         mv88e6xxx_reg_lock(chip);
3042
3043         if (chip->info->ops->setup_errata) {
3044                 err = chip->info->ops->setup_errata(chip);
3045                 if (err)
3046                         goto unlock;
3047         }
3048
3049         /* Cache the cmode of each port. */
3050         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3051                 if (chip->info->ops->port_get_cmode) {
3052                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3053                         if (err)
3054                                 goto unlock;
3055
3056                         chip->ports[i].cmode = cmode;
3057                 }
3058         }
3059
3060         /* Setup Switch Port Registers */
3061         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3062                 if (dsa_is_unused_port(ds, i))
3063                         continue;
3064
3065                 /* Prevent the use of an invalid port. */
3066                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3067                         dev_err(chip->dev, "port %d is invalid\n", i);
3068                         err = -EINVAL;
3069                         goto unlock;
3070                 }
3071
3072                 err = mv88e6xxx_setup_port(chip, i);
3073                 if (err)
3074                         goto unlock;
3075         }
3076
3077         err = mv88e6xxx_irl_setup(chip);
3078         if (err)
3079                 goto unlock;
3080
3081         err = mv88e6xxx_mac_setup(chip);
3082         if (err)
3083                 goto unlock;
3084
3085         err = mv88e6xxx_phy_setup(chip);
3086         if (err)
3087                 goto unlock;
3088
3089         err = mv88e6xxx_vtu_setup(chip);
3090         if (err)
3091                 goto unlock;
3092
3093         err = mv88e6xxx_pvt_setup(chip);
3094         if (err)
3095                 goto unlock;
3096
3097         err = mv88e6xxx_atu_setup(chip);
3098         if (err)
3099                 goto unlock;
3100
3101         err = mv88e6xxx_broadcast_setup(chip, 0);
3102         if (err)
3103                 goto unlock;
3104
3105         err = mv88e6xxx_pot_setup(chip);
3106         if (err)
3107                 goto unlock;
3108
3109         err = mv88e6xxx_rmu_setup(chip);
3110         if (err)
3111                 goto unlock;
3112
3113         err = mv88e6xxx_rsvd2cpu_setup(chip);
3114         if (err)
3115                 goto unlock;
3116
3117         err = mv88e6xxx_trunk_setup(chip);
3118         if (err)
3119                 goto unlock;
3120
3121         err = mv88e6xxx_devmap_setup(chip);
3122         if (err)
3123                 goto unlock;
3124
3125         err = mv88e6xxx_pri_setup(chip);
3126         if (err)
3127                 goto unlock;
3128
3129         /* Setup PTP Hardware Clock and timestamping */
3130         if (chip->info->ptp_support) {
3131                 err = mv88e6xxx_ptp_setup(chip);
3132                 if (err)
3133                         goto unlock;
3134
3135                 err = mv88e6xxx_hwtstamp_setup(chip);
3136                 if (err)
3137                         goto unlock;
3138         }
3139
3140         err = mv88e6xxx_stats_setup(chip);
3141         if (err)
3142                 goto unlock;
3143
3144 unlock:
3145         mv88e6xxx_reg_unlock(chip);
3146
3147         if (err)
3148                 return err;
3149
3150         /* Have to be called without holding the register lock, since
3151          * they take the devlink lock, and we later take the locks in
3152          * the reverse order when getting/setting parameters or
3153          * resource occupancy.
3154          */
3155         err = mv88e6xxx_setup_devlink_resources(ds);
3156         if (err)
3157                 return err;
3158
3159         err = mv88e6xxx_setup_devlink_params(ds);
3160         if (err)
3161                 dsa_devlink_resources_unregister(ds);
3162
3163         return err;
3164 }
3165
3166 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3167 {
3168         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3169         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3170         u16 val;
3171         int err;
3172
3173         if (!chip->info->ops->phy_read)
3174                 return -EOPNOTSUPP;
3175
3176         mv88e6xxx_reg_lock(chip);
3177         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3178         mv88e6xxx_reg_unlock(chip);
3179
3180         if (reg == MII_PHYSID2) {
3181                 /* Some internal PHYs don't have a model number. */
3182                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3183                         /* Then there is the 6165 family. It gets is
3184                          * PHYs correct. But it can also have two
3185                          * SERDES interfaces in the PHY address
3186                          * space. And these don't have a model
3187                          * number. But they are not PHYs, so we don't
3188                          * want to give them something a PHY driver
3189                          * will recognise.
3190                          *
3191                          * Use the mv88e6390 family model number
3192                          * instead, for anything which really could be
3193                          * a PHY,
3194                          */
3195                         if (!(val & 0x3f0))
3196                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3197         }
3198
3199         return err ? err : val;
3200 }
3201
3202 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3203 {
3204         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3205         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3206         int err;
3207
3208         if (!chip->info->ops->phy_write)
3209                 return -EOPNOTSUPP;
3210
3211         mv88e6xxx_reg_lock(chip);
3212         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3213         mv88e6xxx_reg_unlock(chip);
3214
3215         return err;
3216 }
3217
3218 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3219                                    struct device_node *np,
3220                                    bool external)
3221 {
3222         static int index;
3223         struct mv88e6xxx_mdio_bus *mdio_bus;
3224         struct mii_bus *bus;
3225         int err;
3226
3227         if (external) {
3228                 mv88e6xxx_reg_lock(chip);
3229                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3230                 mv88e6xxx_reg_unlock(chip);
3231
3232                 if (err)
3233                         return err;
3234         }
3235
3236         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3237         if (!bus)
3238                 return -ENOMEM;
3239
3240         mdio_bus = bus->priv;
3241         mdio_bus->bus = bus;
3242         mdio_bus->chip = chip;
3243         INIT_LIST_HEAD(&mdio_bus->list);
3244         mdio_bus->external = external;
3245
3246         if (np) {
3247                 bus->name = np->full_name;
3248                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3249         } else {
3250                 bus->name = "mv88e6xxx SMI";
3251                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3252         }
3253
3254         bus->read = mv88e6xxx_mdio_read;
3255         bus->write = mv88e6xxx_mdio_write;
3256         bus->parent = chip->dev;
3257
3258         if (!external) {
3259                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3260                 if (err)
3261                         return err;
3262         }
3263
3264         err = of_mdiobus_register(bus, np);
3265         if (err) {
3266                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3267                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3268                 return err;
3269         }
3270
3271         if (external)
3272                 list_add_tail(&mdio_bus->list, &chip->mdios);
3273         else
3274                 list_add(&mdio_bus->list, &chip->mdios);
3275
3276         return 0;
3277 }
3278
3279 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3280         { .compatible = "marvell,mv88e6xxx-mdio-external",
3281           .data = (void *)true },
3282         { },
3283 };
3284
3285 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3286
3287 {
3288         struct mv88e6xxx_mdio_bus *mdio_bus;
3289         struct mii_bus *bus;
3290
3291         list_for_each_entry(mdio_bus, &chip->mdios, list) {
3292                 bus = mdio_bus->bus;
3293
3294                 if (!mdio_bus->external)
3295                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3296
3297                 mdiobus_unregister(bus);
3298         }
3299 }
3300
3301 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3302                                     struct device_node *np)
3303 {
3304         const struct of_device_id *match;
3305         struct device_node *child;
3306         int err;
3307
3308         /* Always register one mdio bus for the internal/default mdio
3309          * bus. This maybe represented in the device tree, but is
3310          * optional.
3311          */
3312         child = of_get_child_by_name(np, "mdio");
3313         err = mv88e6xxx_mdio_register(chip, child, false);
3314         if (err)
3315                 return err;
3316
3317         /* Walk the device tree, and see if there are any other nodes
3318          * which say they are compatible with the external mdio
3319          * bus.
3320          */
3321         for_each_available_child_of_node(np, child) {
3322                 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3323                 if (match) {
3324                         err = mv88e6xxx_mdio_register(chip, child, true);
3325                         if (err) {
3326                                 mv88e6xxx_mdios_unregister(chip);
3327                                 of_node_put(child);
3328                                 return err;
3329                         }
3330                 }
3331         }
3332
3333         return 0;
3334 }
3335
3336 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3337 {
3338         struct mv88e6xxx_chip *chip = ds->priv;
3339
3340         return chip->eeprom_len;
3341 }
3342
3343 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3344                                 struct ethtool_eeprom *eeprom, u8 *data)
3345 {
3346         struct mv88e6xxx_chip *chip = ds->priv;
3347         int err;
3348
3349         if (!chip->info->ops->get_eeprom)
3350                 return -EOPNOTSUPP;
3351
3352         mv88e6xxx_reg_lock(chip);
3353         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3354         mv88e6xxx_reg_unlock(chip);
3355
3356         if (err)
3357                 return err;
3358
3359         eeprom->magic = 0xc3ec4951;
3360
3361         return 0;
3362 }
3363
3364 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3365                                 struct ethtool_eeprom *eeprom, u8 *data)
3366 {
3367         struct mv88e6xxx_chip *chip = ds->priv;
3368         int err;
3369
3370         if (!chip->info->ops->set_eeprom)
3371                 return -EOPNOTSUPP;
3372
3373         if (eeprom->magic != 0xc3ec4951)
3374                 return -EINVAL;
3375
3376         mv88e6xxx_reg_lock(chip);
3377         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3378         mv88e6xxx_reg_unlock(chip);
3379
3380         return err;
3381 }
3382
3383 static const struct mv88e6xxx_ops mv88e6085_ops = {
3384         /* MV88E6XXX_FAMILY_6097 */
3385         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3386         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3387         .irl_init_all = mv88e6352_g2_irl_init_all,
3388         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3389         .phy_read = mv88e6185_phy_ppu_read,
3390         .phy_write = mv88e6185_phy_ppu_write,
3391         .port_set_link = mv88e6xxx_port_set_link,
3392         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3393         .port_tag_remap = mv88e6095_port_tag_remap,
3394         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3395         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3396         .port_set_ether_type = mv88e6351_port_set_ether_type,
3397         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3398         .port_pause_limit = mv88e6097_port_pause_limit,
3399         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3400         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3401         .port_get_cmode = mv88e6185_port_get_cmode,
3402         .port_setup_message_port = mv88e6xxx_setup_message_port,
3403         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3404         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3405         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3406         .stats_get_strings = mv88e6095_stats_get_strings,
3407         .stats_get_stats = mv88e6095_stats_get_stats,
3408         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3409         .set_egress_port = mv88e6095_g1_set_egress_port,
3410         .watchdog_ops = &mv88e6097_watchdog_ops,
3411         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3412         .pot_clear = mv88e6xxx_g2_pot_clear,
3413         .ppu_enable = mv88e6185_g1_ppu_enable,
3414         .ppu_disable = mv88e6185_g1_ppu_disable,
3415         .reset = mv88e6185_g1_reset,
3416         .rmu_disable = mv88e6085_g1_rmu_disable,
3417         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3418         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3419         .phylink_validate = mv88e6185_phylink_validate,
3420 };
3421
3422 static const struct mv88e6xxx_ops mv88e6095_ops = {
3423         /* MV88E6XXX_FAMILY_6095 */
3424         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3425         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3426         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3427         .phy_read = mv88e6185_phy_ppu_read,
3428         .phy_write = mv88e6185_phy_ppu_write,
3429         .port_set_link = mv88e6xxx_port_set_link,
3430         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3431         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3432         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3433         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3434         .port_get_cmode = mv88e6185_port_get_cmode,
3435         .port_setup_message_port = mv88e6xxx_setup_message_port,
3436         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3437         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3438         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3439         .stats_get_strings = mv88e6095_stats_get_strings,
3440         .stats_get_stats = mv88e6095_stats_get_stats,
3441         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3442         .ppu_enable = mv88e6185_g1_ppu_enable,
3443         .ppu_disable = mv88e6185_g1_ppu_disable,
3444         .reset = mv88e6185_g1_reset,
3445         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3446         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3447         .phylink_validate = mv88e6185_phylink_validate,
3448 };
3449
3450 static const struct mv88e6xxx_ops mv88e6097_ops = {
3451         /* MV88E6XXX_FAMILY_6097 */
3452         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3453         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3454         .irl_init_all = mv88e6352_g2_irl_init_all,
3455         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3456         .phy_read = mv88e6xxx_g2_smi_phy_read,
3457         .phy_write = mv88e6xxx_g2_smi_phy_write,
3458         .port_set_link = mv88e6xxx_port_set_link,
3459         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3460         .port_tag_remap = mv88e6095_port_tag_remap,
3461         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3462         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3463         .port_set_ether_type = mv88e6351_port_set_ether_type,
3464         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3465         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3466         .port_pause_limit = mv88e6097_port_pause_limit,
3467         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3468         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3469         .port_get_cmode = mv88e6185_port_get_cmode,
3470         .port_setup_message_port = mv88e6xxx_setup_message_port,
3471         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3472         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3473         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3474         .stats_get_strings = mv88e6095_stats_get_strings,
3475         .stats_get_stats = mv88e6095_stats_get_stats,
3476         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3477         .set_egress_port = mv88e6095_g1_set_egress_port,
3478         .watchdog_ops = &mv88e6097_watchdog_ops,
3479         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3480         .pot_clear = mv88e6xxx_g2_pot_clear,
3481         .reset = mv88e6352_g1_reset,
3482         .rmu_disable = mv88e6085_g1_rmu_disable,
3483         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3484         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3485         .phylink_validate = mv88e6185_phylink_validate,
3486 };
3487
3488 static const struct mv88e6xxx_ops mv88e6123_ops = {
3489         /* MV88E6XXX_FAMILY_6165 */
3490         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3491         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3492         .irl_init_all = mv88e6352_g2_irl_init_all,
3493         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3494         .phy_read = mv88e6xxx_g2_smi_phy_read,
3495         .phy_write = mv88e6xxx_g2_smi_phy_write,
3496         .port_set_link = mv88e6xxx_port_set_link,
3497         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3498         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3499         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3500         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3501         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3502         .port_get_cmode = mv88e6185_port_get_cmode,
3503         .port_setup_message_port = mv88e6xxx_setup_message_port,
3504         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3505         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3506         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3507         .stats_get_strings = mv88e6095_stats_get_strings,
3508         .stats_get_stats = mv88e6095_stats_get_stats,
3509         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3510         .set_egress_port = mv88e6095_g1_set_egress_port,
3511         .watchdog_ops = &mv88e6097_watchdog_ops,
3512         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3513         .pot_clear = mv88e6xxx_g2_pot_clear,
3514         .reset = mv88e6352_g1_reset,
3515         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3516         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3517         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3518         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3519         .phylink_validate = mv88e6185_phylink_validate,
3520 };
3521
3522 static const struct mv88e6xxx_ops mv88e6131_ops = {
3523         /* MV88E6XXX_FAMILY_6185 */
3524         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3525         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3526         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3527         .phy_read = mv88e6185_phy_ppu_read,
3528         .phy_write = mv88e6185_phy_ppu_write,
3529         .port_set_link = mv88e6xxx_port_set_link,
3530         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3531         .port_tag_remap = mv88e6095_port_tag_remap,
3532         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3533         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3534         .port_set_ether_type = mv88e6351_port_set_ether_type,
3535         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3536         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3537         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3538         .port_pause_limit = mv88e6097_port_pause_limit,
3539         .port_set_pause = mv88e6185_port_set_pause,
3540         .port_get_cmode = mv88e6185_port_get_cmode,
3541         .port_setup_message_port = mv88e6xxx_setup_message_port,
3542         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3543         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3544         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3545         .stats_get_strings = mv88e6095_stats_get_strings,
3546         .stats_get_stats = mv88e6095_stats_get_stats,
3547         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3548         .set_egress_port = mv88e6095_g1_set_egress_port,
3549         .watchdog_ops = &mv88e6097_watchdog_ops,
3550         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3551         .ppu_enable = mv88e6185_g1_ppu_enable,
3552         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3553         .ppu_disable = mv88e6185_g1_ppu_disable,
3554         .reset = mv88e6185_g1_reset,
3555         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3556         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3557         .phylink_validate = mv88e6185_phylink_validate,
3558 };
3559
3560 static const struct mv88e6xxx_ops mv88e6141_ops = {
3561         /* MV88E6XXX_FAMILY_6341 */
3562         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3563         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3564         .irl_init_all = mv88e6352_g2_irl_init_all,
3565         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3566         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3567         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3568         .phy_read = mv88e6xxx_g2_smi_phy_read,
3569         .phy_write = mv88e6xxx_g2_smi_phy_write,
3570         .port_set_link = mv88e6xxx_port_set_link,
3571         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3572         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3573         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3574         .port_tag_remap = mv88e6095_port_tag_remap,
3575         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3576         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3577         .port_set_ether_type = mv88e6351_port_set_ether_type,
3578         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3579         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3580         .port_pause_limit = mv88e6097_port_pause_limit,
3581         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3582         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3583         .port_get_cmode = mv88e6352_port_get_cmode,
3584         .port_set_cmode = mv88e6341_port_set_cmode,
3585         .port_setup_message_port = mv88e6xxx_setup_message_port,
3586         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3587         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3588         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3589         .stats_get_strings = mv88e6320_stats_get_strings,
3590         .stats_get_stats = mv88e6390_stats_get_stats,
3591         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3592         .set_egress_port = mv88e6390_g1_set_egress_port,
3593         .watchdog_ops = &mv88e6390_watchdog_ops,
3594         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3595         .pot_clear = mv88e6xxx_g2_pot_clear,
3596         .reset = mv88e6352_g1_reset,
3597         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3598         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3599         .serdes_power = mv88e6390_serdes_power,
3600         .serdes_get_lane = mv88e6341_serdes_get_lane,
3601         /* Check status register pause & lpa register */
3602         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3603         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3604         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3605         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3606         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3607         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3608         .serdes_irq_status = mv88e6390_serdes_irq_status,
3609         .gpio_ops = &mv88e6352_gpio_ops,
3610         .phylink_validate = mv88e6341_phylink_validate,
3611 };
3612
3613 static const struct mv88e6xxx_ops mv88e6161_ops = {
3614         /* MV88E6XXX_FAMILY_6165 */
3615         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3616         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3617         .irl_init_all = mv88e6352_g2_irl_init_all,
3618         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3619         .phy_read = mv88e6xxx_g2_smi_phy_read,
3620         .phy_write = mv88e6xxx_g2_smi_phy_write,
3621         .port_set_link = mv88e6xxx_port_set_link,
3622         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3623         .port_tag_remap = mv88e6095_port_tag_remap,
3624         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3625         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3626         .port_set_ether_type = mv88e6351_port_set_ether_type,
3627         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3628         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3629         .port_pause_limit = mv88e6097_port_pause_limit,
3630         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3631         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3632         .port_get_cmode = mv88e6185_port_get_cmode,
3633         .port_setup_message_port = mv88e6xxx_setup_message_port,
3634         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3635         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3636         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3637         .stats_get_strings = mv88e6095_stats_get_strings,
3638         .stats_get_stats = mv88e6095_stats_get_stats,
3639         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3640         .set_egress_port = mv88e6095_g1_set_egress_port,
3641         .watchdog_ops = &mv88e6097_watchdog_ops,
3642         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3643         .pot_clear = mv88e6xxx_g2_pot_clear,
3644         .reset = mv88e6352_g1_reset,
3645         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3646         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3647         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3648         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3649         .avb_ops = &mv88e6165_avb_ops,
3650         .ptp_ops = &mv88e6165_ptp_ops,
3651         .phylink_validate = mv88e6185_phylink_validate,
3652 };
3653
3654 static const struct mv88e6xxx_ops mv88e6165_ops = {
3655         /* MV88E6XXX_FAMILY_6165 */
3656         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3657         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3658         .irl_init_all = mv88e6352_g2_irl_init_all,
3659         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3660         .phy_read = mv88e6165_phy_read,
3661         .phy_write = mv88e6165_phy_write,
3662         .port_set_link = mv88e6xxx_port_set_link,
3663         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3664         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3665         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3666         .port_get_cmode = mv88e6185_port_get_cmode,
3667         .port_setup_message_port = mv88e6xxx_setup_message_port,
3668         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3669         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3670         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3671         .stats_get_strings = mv88e6095_stats_get_strings,
3672         .stats_get_stats = mv88e6095_stats_get_stats,
3673         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3674         .set_egress_port = mv88e6095_g1_set_egress_port,
3675         .watchdog_ops = &mv88e6097_watchdog_ops,
3676         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3677         .pot_clear = mv88e6xxx_g2_pot_clear,
3678         .reset = mv88e6352_g1_reset,
3679         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3680         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3681         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3682         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3683         .avb_ops = &mv88e6165_avb_ops,
3684         .ptp_ops = &mv88e6165_ptp_ops,
3685         .phylink_validate = mv88e6185_phylink_validate,
3686 };
3687
3688 static const struct mv88e6xxx_ops mv88e6171_ops = {
3689         /* MV88E6XXX_FAMILY_6351 */
3690         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3691         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3692         .irl_init_all = mv88e6352_g2_irl_init_all,
3693         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3694         .phy_read = mv88e6xxx_g2_smi_phy_read,
3695         .phy_write = mv88e6xxx_g2_smi_phy_write,
3696         .port_set_link = mv88e6xxx_port_set_link,
3697         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3698         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3699         .port_tag_remap = mv88e6095_port_tag_remap,
3700         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3701         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3702         .port_set_ether_type = mv88e6351_port_set_ether_type,
3703         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3704         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3705         .port_pause_limit = mv88e6097_port_pause_limit,
3706         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3707         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3708         .port_get_cmode = mv88e6352_port_get_cmode,
3709         .port_setup_message_port = mv88e6xxx_setup_message_port,
3710         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3711         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3712         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3713         .stats_get_strings = mv88e6095_stats_get_strings,
3714         .stats_get_stats = mv88e6095_stats_get_stats,
3715         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3716         .set_egress_port = mv88e6095_g1_set_egress_port,
3717         .watchdog_ops = &mv88e6097_watchdog_ops,
3718         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3719         .pot_clear = mv88e6xxx_g2_pot_clear,
3720         .reset = mv88e6352_g1_reset,
3721         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3722         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3723         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3724         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3725         .phylink_validate = mv88e6185_phylink_validate,
3726 };
3727
3728 static const struct mv88e6xxx_ops mv88e6172_ops = {
3729         /* MV88E6XXX_FAMILY_6352 */
3730         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3731         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3732         .irl_init_all = mv88e6352_g2_irl_init_all,
3733         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3734         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3735         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3736         .phy_read = mv88e6xxx_g2_smi_phy_read,
3737         .phy_write = mv88e6xxx_g2_smi_phy_write,
3738         .port_set_link = mv88e6xxx_port_set_link,
3739         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3740         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3741         .port_tag_remap = mv88e6095_port_tag_remap,
3742         .port_set_policy = mv88e6352_port_set_policy,
3743         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3744         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3745         .port_set_ether_type = mv88e6351_port_set_ether_type,
3746         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3747         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3748         .port_pause_limit = mv88e6097_port_pause_limit,
3749         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3750         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3751         .port_get_cmode = mv88e6352_port_get_cmode,
3752         .port_setup_message_port = mv88e6xxx_setup_message_port,
3753         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3754         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3755         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3756         .stats_get_strings = mv88e6095_stats_get_strings,
3757         .stats_get_stats = mv88e6095_stats_get_stats,
3758         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3759         .set_egress_port = mv88e6095_g1_set_egress_port,
3760         .watchdog_ops = &mv88e6097_watchdog_ops,
3761         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3762         .pot_clear = mv88e6xxx_g2_pot_clear,
3763         .reset = mv88e6352_g1_reset,
3764         .rmu_disable = mv88e6352_g1_rmu_disable,
3765         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3766         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3767         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3768         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3769         .serdes_get_lane = mv88e6352_serdes_get_lane,
3770         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3771         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3772         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3773         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3774         .serdes_power = mv88e6352_serdes_power,
3775         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3776         .serdes_get_regs = mv88e6352_serdes_get_regs,
3777         .gpio_ops = &mv88e6352_gpio_ops,
3778         .phylink_validate = mv88e6352_phylink_validate,
3779 };
3780
3781 static const struct mv88e6xxx_ops mv88e6175_ops = {
3782         /* MV88E6XXX_FAMILY_6351 */
3783         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3784         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3785         .irl_init_all = mv88e6352_g2_irl_init_all,
3786         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3787         .phy_read = mv88e6xxx_g2_smi_phy_read,
3788         .phy_write = mv88e6xxx_g2_smi_phy_write,
3789         .port_set_link = mv88e6xxx_port_set_link,
3790         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3791         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3792         .port_tag_remap = mv88e6095_port_tag_remap,
3793         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3794         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3795         .port_set_ether_type = mv88e6351_port_set_ether_type,
3796         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3797         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3798         .port_pause_limit = mv88e6097_port_pause_limit,
3799         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3800         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3801         .port_get_cmode = mv88e6352_port_get_cmode,
3802         .port_setup_message_port = mv88e6xxx_setup_message_port,
3803         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3804         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3805         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3806         .stats_get_strings = mv88e6095_stats_get_strings,
3807         .stats_get_stats = mv88e6095_stats_get_stats,
3808         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3809         .set_egress_port = mv88e6095_g1_set_egress_port,
3810         .watchdog_ops = &mv88e6097_watchdog_ops,
3811         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3812         .pot_clear = mv88e6xxx_g2_pot_clear,
3813         .reset = mv88e6352_g1_reset,
3814         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3815         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3816         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3817         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3818         .phylink_validate = mv88e6185_phylink_validate,
3819 };
3820
3821 static const struct mv88e6xxx_ops mv88e6176_ops = {
3822         /* MV88E6XXX_FAMILY_6352 */
3823         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3824         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3825         .irl_init_all = mv88e6352_g2_irl_init_all,
3826         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3827         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3828         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3829         .phy_read = mv88e6xxx_g2_smi_phy_read,
3830         .phy_write = mv88e6xxx_g2_smi_phy_write,
3831         .port_set_link = mv88e6xxx_port_set_link,
3832         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3833         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3834         .port_tag_remap = mv88e6095_port_tag_remap,
3835         .port_set_policy = mv88e6352_port_set_policy,
3836         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3837         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3838         .port_set_ether_type = mv88e6351_port_set_ether_type,
3839         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3840         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3841         .port_pause_limit = mv88e6097_port_pause_limit,
3842         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3843         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3844         .port_get_cmode = mv88e6352_port_get_cmode,
3845         .port_setup_message_port = mv88e6xxx_setup_message_port,
3846         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3847         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3848         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3849         .stats_get_strings = mv88e6095_stats_get_strings,
3850         .stats_get_stats = mv88e6095_stats_get_stats,
3851         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3852         .set_egress_port = mv88e6095_g1_set_egress_port,
3853         .watchdog_ops = &mv88e6097_watchdog_ops,
3854         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3855         .pot_clear = mv88e6xxx_g2_pot_clear,
3856         .reset = mv88e6352_g1_reset,
3857         .rmu_disable = mv88e6352_g1_rmu_disable,
3858         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3859         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3860         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3861         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3862         .serdes_get_lane = mv88e6352_serdes_get_lane,
3863         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3864         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3865         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3866         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3867         .serdes_power = mv88e6352_serdes_power,
3868         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3869         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3870         .serdes_irq_status = mv88e6352_serdes_irq_status,
3871         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3872         .serdes_get_regs = mv88e6352_serdes_get_regs,
3873         .gpio_ops = &mv88e6352_gpio_ops,
3874         .phylink_validate = mv88e6352_phylink_validate,
3875 };
3876
3877 static const struct mv88e6xxx_ops mv88e6185_ops = {
3878         /* MV88E6XXX_FAMILY_6185 */
3879         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3880         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3881         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3882         .phy_read = mv88e6185_phy_ppu_read,
3883         .phy_write = mv88e6185_phy_ppu_write,
3884         .port_set_link = mv88e6xxx_port_set_link,
3885         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3886         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3887         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3888         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3889         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3890         .port_set_pause = mv88e6185_port_set_pause,
3891         .port_get_cmode = mv88e6185_port_get_cmode,
3892         .port_setup_message_port = mv88e6xxx_setup_message_port,
3893         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3894         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3895         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3896         .stats_get_strings = mv88e6095_stats_get_strings,
3897         .stats_get_stats = mv88e6095_stats_get_stats,
3898         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3899         .set_egress_port = mv88e6095_g1_set_egress_port,
3900         .watchdog_ops = &mv88e6097_watchdog_ops,
3901         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3902         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3903         .ppu_enable = mv88e6185_g1_ppu_enable,
3904         .ppu_disable = mv88e6185_g1_ppu_disable,
3905         .reset = mv88e6185_g1_reset,
3906         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3907         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3908         .phylink_validate = mv88e6185_phylink_validate,
3909 };
3910
3911 static const struct mv88e6xxx_ops mv88e6190_ops = {
3912         /* MV88E6XXX_FAMILY_6390 */
3913         .setup_errata = mv88e6390_setup_errata,
3914         .irl_init_all = mv88e6390_g2_irl_init_all,
3915         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3916         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3917         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3918         .phy_read = mv88e6xxx_g2_smi_phy_read,
3919         .phy_write = mv88e6xxx_g2_smi_phy_write,
3920         .port_set_link = mv88e6xxx_port_set_link,
3921         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3922         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3923         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3924         .port_tag_remap = mv88e6390_port_tag_remap,
3925         .port_set_policy = mv88e6352_port_set_policy,
3926         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3927         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3928         .port_set_ether_type = mv88e6351_port_set_ether_type,
3929         .port_pause_limit = mv88e6390_port_pause_limit,
3930         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3931         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3932         .port_get_cmode = mv88e6352_port_get_cmode,
3933         .port_set_cmode = mv88e6390_port_set_cmode,
3934         .port_setup_message_port = mv88e6xxx_setup_message_port,
3935         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3936         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3937         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3938         .stats_get_strings = mv88e6320_stats_get_strings,
3939         .stats_get_stats = mv88e6390_stats_get_stats,
3940         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3941         .set_egress_port = mv88e6390_g1_set_egress_port,
3942         .watchdog_ops = &mv88e6390_watchdog_ops,
3943         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3944         .pot_clear = mv88e6xxx_g2_pot_clear,
3945         .reset = mv88e6352_g1_reset,
3946         .rmu_disable = mv88e6390_g1_rmu_disable,
3947         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3948         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3949         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3950         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3951         .serdes_power = mv88e6390_serdes_power,
3952         .serdes_get_lane = mv88e6390_serdes_get_lane,
3953         /* Check status register pause & lpa register */
3954         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3955         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3956         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3957         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3958         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3959         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3960         .serdes_irq_status = mv88e6390_serdes_irq_status,
3961         .serdes_get_strings = mv88e6390_serdes_get_strings,
3962         .serdes_get_stats = mv88e6390_serdes_get_stats,
3963         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3964         .serdes_get_regs = mv88e6390_serdes_get_regs,
3965         .gpio_ops = &mv88e6352_gpio_ops,
3966         .phylink_validate = mv88e6390_phylink_validate,
3967 };
3968
3969 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3970         /* MV88E6XXX_FAMILY_6390 */
3971         .setup_errata = mv88e6390_setup_errata,
3972         .irl_init_all = mv88e6390_g2_irl_init_all,
3973         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3974         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3975         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3976         .phy_read = mv88e6xxx_g2_smi_phy_read,
3977         .phy_write = mv88e6xxx_g2_smi_phy_write,
3978         .port_set_link = mv88e6xxx_port_set_link,
3979         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3980         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3981         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3982         .port_tag_remap = mv88e6390_port_tag_remap,
3983         .port_set_policy = mv88e6352_port_set_policy,
3984         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3985         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3986         .port_set_ether_type = mv88e6351_port_set_ether_type,
3987         .port_pause_limit = mv88e6390_port_pause_limit,
3988         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3989         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3990         .port_get_cmode = mv88e6352_port_get_cmode,
3991         .port_set_cmode = mv88e6390x_port_set_cmode,
3992         .port_setup_message_port = mv88e6xxx_setup_message_port,
3993         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3994         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3995         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3996         .stats_get_strings = mv88e6320_stats_get_strings,
3997         .stats_get_stats = mv88e6390_stats_get_stats,
3998         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3999         .set_egress_port = mv88e6390_g1_set_egress_port,
4000         .watchdog_ops = &mv88e6390_watchdog_ops,
4001         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4002         .pot_clear = mv88e6xxx_g2_pot_clear,
4003         .reset = mv88e6352_g1_reset,
4004         .rmu_disable = mv88e6390_g1_rmu_disable,
4005         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4006         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4007         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4008         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4009         .serdes_power = mv88e6390_serdes_power,
4010         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4011         /* Check status register pause & lpa register */
4012         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4013         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4014         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4015         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4016         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4017         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4018         .serdes_irq_status = mv88e6390_serdes_irq_status,
4019         .serdes_get_strings = mv88e6390_serdes_get_strings,
4020         .serdes_get_stats = mv88e6390_serdes_get_stats,
4021         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4022         .serdes_get_regs = mv88e6390_serdes_get_regs,
4023         .gpio_ops = &mv88e6352_gpio_ops,
4024         .phylink_validate = mv88e6390x_phylink_validate,
4025 };
4026
4027 static const struct mv88e6xxx_ops mv88e6191_ops = {
4028         /* MV88E6XXX_FAMILY_6390 */
4029         .setup_errata = mv88e6390_setup_errata,
4030         .irl_init_all = mv88e6390_g2_irl_init_all,
4031         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4032         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4033         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4034         .phy_read = mv88e6xxx_g2_smi_phy_read,
4035         .phy_write = mv88e6xxx_g2_smi_phy_write,
4036         .port_set_link = mv88e6xxx_port_set_link,
4037         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4038         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4039         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4040         .port_tag_remap = mv88e6390_port_tag_remap,
4041         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4042         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4043         .port_set_ether_type = mv88e6351_port_set_ether_type,
4044         .port_pause_limit = mv88e6390_port_pause_limit,
4045         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4046         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4047         .port_get_cmode = mv88e6352_port_get_cmode,
4048         .port_set_cmode = mv88e6390_port_set_cmode,
4049         .port_setup_message_port = mv88e6xxx_setup_message_port,
4050         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4051         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4052         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4053         .stats_get_strings = mv88e6320_stats_get_strings,
4054         .stats_get_stats = mv88e6390_stats_get_stats,
4055         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4056         .set_egress_port = mv88e6390_g1_set_egress_port,
4057         .watchdog_ops = &mv88e6390_watchdog_ops,
4058         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4059         .pot_clear = mv88e6xxx_g2_pot_clear,
4060         .reset = mv88e6352_g1_reset,
4061         .rmu_disable = mv88e6390_g1_rmu_disable,
4062         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4063         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4064         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4065         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4066         .serdes_power = mv88e6390_serdes_power,
4067         .serdes_get_lane = mv88e6390_serdes_get_lane,
4068         /* Check status register pause & lpa register */
4069         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4070         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4071         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4072         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4073         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4074         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4075         .serdes_irq_status = mv88e6390_serdes_irq_status,
4076         .serdes_get_strings = mv88e6390_serdes_get_strings,
4077         .serdes_get_stats = mv88e6390_serdes_get_stats,
4078         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4079         .serdes_get_regs = mv88e6390_serdes_get_regs,
4080         .avb_ops = &mv88e6390_avb_ops,
4081         .ptp_ops = &mv88e6352_ptp_ops,
4082         .phylink_validate = mv88e6390_phylink_validate,
4083 };
4084
4085 static const struct mv88e6xxx_ops mv88e6240_ops = {
4086         /* MV88E6XXX_FAMILY_6352 */
4087         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4088         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4089         .irl_init_all = mv88e6352_g2_irl_init_all,
4090         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4091         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4092         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4093         .phy_read = mv88e6xxx_g2_smi_phy_read,
4094         .phy_write = mv88e6xxx_g2_smi_phy_write,
4095         .port_set_link = mv88e6xxx_port_set_link,
4096         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4097         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4098         .port_tag_remap = mv88e6095_port_tag_remap,
4099         .port_set_policy = mv88e6352_port_set_policy,
4100         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4101         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4102         .port_set_ether_type = mv88e6351_port_set_ether_type,
4103         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4104         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4105         .port_pause_limit = mv88e6097_port_pause_limit,
4106         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4107         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4108         .port_get_cmode = mv88e6352_port_get_cmode,
4109         .port_setup_message_port = mv88e6xxx_setup_message_port,
4110         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4111         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4112         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4113         .stats_get_strings = mv88e6095_stats_get_strings,
4114         .stats_get_stats = mv88e6095_stats_get_stats,
4115         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4116         .set_egress_port = mv88e6095_g1_set_egress_port,
4117         .watchdog_ops = &mv88e6097_watchdog_ops,
4118         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4119         .pot_clear = mv88e6xxx_g2_pot_clear,
4120         .reset = mv88e6352_g1_reset,
4121         .rmu_disable = mv88e6352_g1_rmu_disable,
4122         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4123         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4124         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4125         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4126         .serdes_get_lane = mv88e6352_serdes_get_lane,
4127         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4128         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4129         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4130         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4131         .serdes_power = mv88e6352_serdes_power,
4132         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4133         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4134         .serdes_irq_status = mv88e6352_serdes_irq_status,
4135         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4136         .serdes_get_regs = mv88e6352_serdes_get_regs,
4137         .gpio_ops = &mv88e6352_gpio_ops,
4138         .avb_ops = &mv88e6352_avb_ops,
4139         .ptp_ops = &mv88e6352_ptp_ops,
4140         .phylink_validate = mv88e6352_phylink_validate,
4141 };
4142
4143 static const struct mv88e6xxx_ops mv88e6250_ops = {
4144         /* MV88E6XXX_FAMILY_6250 */
4145         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4146         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4147         .irl_init_all = mv88e6352_g2_irl_init_all,
4148         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4149         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4150         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4151         .phy_read = mv88e6xxx_g2_smi_phy_read,
4152         .phy_write = mv88e6xxx_g2_smi_phy_write,
4153         .port_set_link = mv88e6xxx_port_set_link,
4154         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4155         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4156         .port_tag_remap = mv88e6095_port_tag_remap,
4157         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4158         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4159         .port_set_ether_type = mv88e6351_port_set_ether_type,
4160         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4161         .port_pause_limit = mv88e6097_port_pause_limit,
4162         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4163         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4164         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4165         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4166         .stats_get_strings = mv88e6250_stats_get_strings,
4167         .stats_get_stats = mv88e6250_stats_get_stats,
4168         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4169         .set_egress_port = mv88e6095_g1_set_egress_port,
4170         .watchdog_ops = &mv88e6250_watchdog_ops,
4171         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4172         .pot_clear = mv88e6xxx_g2_pot_clear,
4173         .reset = mv88e6250_g1_reset,
4174         .vtu_getnext = mv88e6250_g1_vtu_getnext,
4175         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4176         .avb_ops = &mv88e6352_avb_ops,
4177         .ptp_ops = &mv88e6250_ptp_ops,
4178         .phylink_validate = mv88e6065_phylink_validate,
4179 };
4180
4181 static const struct mv88e6xxx_ops mv88e6290_ops = {
4182         /* MV88E6XXX_FAMILY_6390 */
4183         .setup_errata = mv88e6390_setup_errata,
4184         .irl_init_all = mv88e6390_g2_irl_init_all,
4185         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4186         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4187         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4188         .phy_read = mv88e6xxx_g2_smi_phy_read,
4189         .phy_write = mv88e6xxx_g2_smi_phy_write,
4190         .port_set_link = mv88e6xxx_port_set_link,
4191         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4192         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4193         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4194         .port_tag_remap = mv88e6390_port_tag_remap,
4195         .port_set_policy = mv88e6352_port_set_policy,
4196         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4197         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4198         .port_set_ether_type = mv88e6351_port_set_ether_type,
4199         .port_pause_limit = mv88e6390_port_pause_limit,
4200         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4201         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4202         .port_get_cmode = mv88e6352_port_get_cmode,
4203         .port_set_cmode = mv88e6390_port_set_cmode,
4204         .port_setup_message_port = mv88e6xxx_setup_message_port,
4205         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4206         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4207         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4208         .stats_get_strings = mv88e6320_stats_get_strings,
4209         .stats_get_stats = mv88e6390_stats_get_stats,
4210         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4211         .set_egress_port = mv88e6390_g1_set_egress_port,
4212         .watchdog_ops = &mv88e6390_watchdog_ops,
4213         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4214         .pot_clear = mv88e6xxx_g2_pot_clear,
4215         .reset = mv88e6352_g1_reset,
4216         .rmu_disable = mv88e6390_g1_rmu_disable,
4217         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4218         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4219         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4220         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4221         .serdes_power = mv88e6390_serdes_power,
4222         .serdes_get_lane = mv88e6390_serdes_get_lane,
4223         /* Check status register pause & lpa register */
4224         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4225         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4226         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4227         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4228         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4229         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4230         .serdes_irq_status = mv88e6390_serdes_irq_status,
4231         .serdes_get_strings = mv88e6390_serdes_get_strings,
4232         .serdes_get_stats = mv88e6390_serdes_get_stats,
4233         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4234         .serdes_get_regs = mv88e6390_serdes_get_regs,
4235         .gpio_ops = &mv88e6352_gpio_ops,
4236         .avb_ops = &mv88e6390_avb_ops,
4237         .ptp_ops = &mv88e6352_ptp_ops,
4238         .phylink_validate = mv88e6390_phylink_validate,
4239 };
4240
4241 static const struct mv88e6xxx_ops mv88e6320_ops = {
4242         /* MV88E6XXX_FAMILY_6320 */
4243         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4244         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4245         .irl_init_all = mv88e6352_g2_irl_init_all,
4246         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4247         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4248         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4249         .phy_read = mv88e6xxx_g2_smi_phy_read,
4250         .phy_write = mv88e6xxx_g2_smi_phy_write,
4251         .port_set_link = mv88e6xxx_port_set_link,
4252         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4253         .port_tag_remap = mv88e6095_port_tag_remap,
4254         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4255         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4256         .port_set_ether_type = mv88e6351_port_set_ether_type,
4257         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4258         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4259         .port_pause_limit = mv88e6097_port_pause_limit,
4260         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4261         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4262         .port_get_cmode = mv88e6352_port_get_cmode,
4263         .port_setup_message_port = mv88e6xxx_setup_message_port,
4264         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4265         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4266         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4267         .stats_get_strings = mv88e6320_stats_get_strings,
4268         .stats_get_stats = mv88e6320_stats_get_stats,
4269         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4270         .set_egress_port = mv88e6095_g1_set_egress_port,
4271         .watchdog_ops = &mv88e6390_watchdog_ops,
4272         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4273         .pot_clear = mv88e6xxx_g2_pot_clear,
4274         .reset = mv88e6352_g1_reset,
4275         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4276         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4277         .gpio_ops = &mv88e6352_gpio_ops,
4278         .avb_ops = &mv88e6352_avb_ops,
4279         .ptp_ops = &mv88e6352_ptp_ops,
4280         .phylink_validate = mv88e6185_phylink_validate,
4281 };
4282
4283 static const struct mv88e6xxx_ops mv88e6321_ops = {
4284         /* MV88E6XXX_FAMILY_6320 */
4285         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4286         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4287         .irl_init_all = mv88e6352_g2_irl_init_all,
4288         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4289         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4290         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4291         .phy_read = mv88e6xxx_g2_smi_phy_read,
4292         .phy_write = mv88e6xxx_g2_smi_phy_write,
4293         .port_set_link = mv88e6xxx_port_set_link,
4294         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4295         .port_tag_remap = mv88e6095_port_tag_remap,
4296         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4297         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4298         .port_set_ether_type = mv88e6351_port_set_ether_type,
4299         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4300         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4301         .port_pause_limit = mv88e6097_port_pause_limit,
4302         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4303         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4304         .port_get_cmode = mv88e6352_port_get_cmode,
4305         .port_setup_message_port = mv88e6xxx_setup_message_port,
4306         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4307         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4308         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4309         .stats_get_strings = mv88e6320_stats_get_strings,
4310         .stats_get_stats = mv88e6320_stats_get_stats,
4311         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4312         .set_egress_port = mv88e6095_g1_set_egress_port,
4313         .watchdog_ops = &mv88e6390_watchdog_ops,
4314         .reset = mv88e6352_g1_reset,
4315         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4316         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4317         .gpio_ops = &mv88e6352_gpio_ops,
4318         .avb_ops = &mv88e6352_avb_ops,
4319         .ptp_ops = &mv88e6352_ptp_ops,
4320         .phylink_validate = mv88e6185_phylink_validate,
4321 };
4322
4323 static const struct mv88e6xxx_ops mv88e6341_ops = {
4324         /* MV88E6XXX_FAMILY_6341 */
4325         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4326         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4327         .irl_init_all = mv88e6352_g2_irl_init_all,
4328         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4329         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4330         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4331         .phy_read = mv88e6xxx_g2_smi_phy_read,
4332         .phy_write = mv88e6xxx_g2_smi_phy_write,
4333         .port_set_link = mv88e6xxx_port_set_link,
4334         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4335         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4336         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4337         .port_tag_remap = mv88e6095_port_tag_remap,
4338         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4339         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4340         .port_set_ether_type = mv88e6351_port_set_ether_type,
4341         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4342         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4343         .port_pause_limit = mv88e6097_port_pause_limit,
4344         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4345         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4346         .port_get_cmode = mv88e6352_port_get_cmode,
4347         .port_set_cmode = mv88e6341_port_set_cmode,
4348         .port_setup_message_port = mv88e6xxx_setup_message_port,
4349         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4350         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4351         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4352         .stats_get_strings = mv88e6320_stats_get_strings,
4353         .stats_get_stats = mv88e6390_stats_get_stats,
4354         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4355         .set_egress_port = mv88e6390_g1_set_egress_port,
4356         .watchdog_ops = &mv88e6390_watchdog_ops,
4357         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4358         .pot_clear = mv88e6xxx_g2_pot_clear,
4359         .reset = mv88e6352_g1_reset,
4360         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4361         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4362         .serdes_power = mv88e6390_serdes_power,
4363         .serdes_get_lane = mv88e6341_serdes_get_lane,
4364         /* Check status register pause & lpa register */
4365         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4366         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4367         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4368         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4369         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4370         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4371         .serdes_irq_status = mv88e6390_serdes_irq_status,
4372         .gpio_ops = &mv88e6352_gpio_ops,
4373         .avb_ops = &mv88e6390_avb_ops,
4374         .ptp_ops = &mv88e6352_ptp_ops,
4375         .phylink_validate = mv88e6341_phylink_validate,
4376 };
4377
4378 static const struct mv88e6xxx_ops mv88e6350_ops = {
4379         /* MV88E6XXX_FAMILY_6351 */
4380         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4381         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4382         .irl_init_all = mv88e6352_g2_irl_init_all,
4383         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4384         .phy_read = mv88e6xxx_g2_smi_phy_read,
4385         .phy_write = mv88e6xxx_g2_smi_phy_write,
4386         .port_set_link = mv88e6xxx_port_set_link,
4387         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4388         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4389         .port_tag_remap = mv88e6095_port_tag_remap,
4390         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4391         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4392         .port_set_ether_type = mv88e6351_port_set_ether_type,
4393         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4394         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4395         .port_pause_limit = mv88e6097_port_pause_limit,
4396         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4397         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4398         .port_get_cmode = mv88e6352_port_get_cmode,
4399         .port_setup_message_port = mv88e6xxx_setup_message_port,
4400         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4401         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4402         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4403         .stats_get_strings = mv88e6095_stats_get_strings,
4404         .stats_get_stats = mv88e6095_stats_get_stats,
4405         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4406         .set_egress_port = mv88e6095_g1_set_egress_port,
4407         .watchdog_ops = &mv88e6097_watchdog_ops,
4408         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4409         .pot_clear = mv88e6xxx_g2_pot_clear,
4410         .reset = mv88e6352_g1_reset,
4411         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4412         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4413         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4414         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4415         .phylink_validate = mv88e6185_phylink_validate,
4416 };
4417
4418 static const struct mv88e6xxx_ops mv88e6351_ops = {
4419         /* MV88E6XXX_FAMILY_6351 */
4420         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4421         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4422         .irl_init_all = mv88e6352_g2_irl_init_all,
4423         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4424         .phy_read = mv88e6xxx_g2_smi_phy_read,
4425         .phy_write = mv88e6xxx_g2_smi_phy_write,
4426         .port_set_link = mv88e6xxx_port_set_link,
4427         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4428         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4429         .port_tag_remap = mv88e6095_port_tag_remap,
4430         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4431         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4432         .port_set_ether_type = mv88e6351_port_set_ether_type,
4433         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4434         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4435         .port_pause_limit = mv88e6097_port_pause_limit,
4436         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4437         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4438         .port_get_cmode = mv88e6352_port_get_cmode,
4439         .port_setup_message_port = mv88e6xxx_setup_message_port,
4440         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4441         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4442         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4443         .stats_get_strings = mv88e6095_stats_get_strings,
4444         .stats_get_stats = mv88e6095_stats_get_stats,
4445         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4446         .set_egress_port = mv88e6095_g1_set_egress_port,
4447         .watchdog_ops = &mv88e6097_watchdog_ops,
4448         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4449         .pot_clear = mv88e6xxx_g2_pot_clear,
4450         .reset = mv88e6352_g1_reset,
4451         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4452         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4453         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4454         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4455         .avb_ops = &mv88e6352_avb_ops,
4456         .ptp_ops = &mv88e6352_ptp_ops,
4457         .phylink_validate = mv88e6185_phylink_validate,
4458 };
4459
4460 static const struct mv88e6xxx_ops mv88e6352_ops = {
4461         /* MV88E6XXX_FAMILY_6352 */
4462         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4463         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4464         .irl_init_all = mv88e6352_g2_irl_init_all,
4465         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4466         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4467         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4468         .phy_read = mv88e6xxx_g2_smi_phy_read,
4469         .phy_write = mv88e6xxx_g2_smi_phy_write,
4470         .port_set_link = mv88e6xxx_port_set_link,
4471         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4472         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4473         .port_tag_remap = mv88e6095_port_tag_remap,
4474         .port_set_policy = mv88e6352_port_set_policy,
4475         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4476         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4477         .port_set_ether_type = mv88e6351_port_set_ether_type,
4478         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4479         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4480         .port_pause_limit = mv88e6097_port_pause_limit,
4481         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4482         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4483         .port_get_cmode = mv88e6352_port_get_cmode,
4484         .port_setup_message_port = mv88e6xxx_setup_message_port,
4485         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4486         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4487         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4488         .stats_get_strings = mv88e6095_stats_get_strings,
4489         .stats_get_stats = mv88e6095_stats_get_stats,
4490         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4491         .set_egress_port = mv88e6095_g1_set_egress_port,
4492         .watchdog_ops = &mv88e6097_watchdog_ops,
4493         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4494         .pot_clear = mv88e6xxx_g2_pot_clear,
4495         .reset = mv88e6352_g1_reset,
4496         .rmu_disable = mv88e6352_g1_rmu_disable,
4497         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4498         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4499         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4500         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4501         .serdes_get_lane = mv88e6352_serdes_get_lane,
4502         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4503         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4504         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4505         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4506         .serdes_power = mv88e6352_serdes_power,
4507         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4508         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4509         .serdes_irq_status = mv88e6352_serdes_irq_status,
4510         .gpio_ops = &mv88e6352_gpio_ops,
4511         .avb_ops = &mv88e6352_avb_ops,
4512         .ptp_ops = &mv88e6352_ptp_ops,
4513         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4514         .serdes_get_strings = mv88e6352_serdes_get_strings,
4515         .serdes_get_stats = mv88e6352_serdes_get_stats,
4516         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4517         .serdes_get_regs = mv88e6352_serdes_get_regs,
4518         .phylink_validate = mv88e6352_phylink_validate,
4519 };
4520
4521 static const struct mv88e6xxx_ops mv88e6390_ops = {
4522         /* MV88E6XXX_FAMILY_6390 */
4523         .setup_errata = mv88e6390_setup_errata,
4524         .irl_init_all = mv88e6390_g2_irl_init_all,
4525         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4526         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4527         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4528         .phy_read = mv88e6xxx_g2_smi_phy_read,
4529         .phy_write = mv88e6xxx_g2_smi_phy_write,
4530         .port_set_link = mv88e6xxx_port_set_link,
4531         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4532         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4533         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4534         .port_tag_remap = mv88e6390_port_tag_remap,
4535         .port_set_policy = mv88e6352_port_set_policy,
4536         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4537         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4538         .port_set_ether_type = mv88e6351_port_set_ether_type,
4539         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4540         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4541         .port_pause_limit = mv88e6390_port_pause_limit,
4542         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4543         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4544         .port_get_cmode = mv88e6352_port_get_cmode,
4545         .port_set_cmode = mv88e6390_port_set_cmode,
4546         .port_setup_message_port = mv88e6xxx_setup_message_port,
4547         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4548         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4549         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4550         .stats_get_strings = mv88e6320_stats_get_strings,
4551         .stats_get_stats = mv88e6390_stats_get_stats,
4552         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4553         .set_egress_port = mv88e6390_g1_set_egress_port,
4554         .watchdog_ops = &mv88e6390_watchdog_ops,
4555         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4556         .pot_clear = mv88e6xxx_g2_pot_clear,
4557         .reset = mv88e6352_g1_reset,
4558         .rmu_disable = mv88e6390_g1_rmu_disable,
4559         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4560         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4561         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4562         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4563         .serdes_power = mv88e6390_serdes_power,
4564         .serdes_get_lane = mv88e6390_serdes_get_lane,
4565         /* Check status register pause & lpa register */
4566         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4567         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4568         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4569         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4570         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4571         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4572         .serdes_irq_status = mv88e6390_serdes_irq_status,
4573         .gpio_ops = &mv88e6352_gpio_ops,
4574         .avb_ops = &mv88e6390_avb_ops,
4575         .ptp_ops = &mv88e6352_ptp_ops,
4576         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4577         .serdes_get_strings = mv88e6390_serdes_get_strings,
4578         .serdes_get_stats = mv88e6390_serdes_get_stats,
4579         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4580         .serdes_get_regs = mv88e6390_serdes_get_regs,
4581         .phylink_validate = mv88e6390_phylink_validate,
4582 };
4583
4584 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4585         /* MV88E6XXX_FAMILY_6390 */
4586         .setup_errata = mv88e6390_setup_errata,
4587         .irl_init_all = mv88e6390_g2_irl_init_all,
4588         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4589         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4590         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4591         .phy_read = mv88e6xxx_g2_smi_phy_read,
4592         .phy_write = mv88e6xxx_g2_smi_phy_write,
4593         .port_set_link = mv88e6xxx_port_set_link,
4594         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4595         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4596         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4597         .port_tag_remap = mv88e6390_port_tag_remap,
4598         .port_set_policy = mv88e6352_port_set_policy,
4599         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4600         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4601         .port_set_ether_type = mv88e6351_port_set_ether_type,
4602         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4603         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4604         .port_pause_limit = mv88e6390_port_pause_limit,
4605         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4606         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4607         .port_get_cmode = mv88e6352_port_get_cmode,
4608         .port_set_cmode = mv88e6390x_port_set_cmode,
4609         .port_setup_message_port = mv88e6xxx_setup_message_port,
4610         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4611         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4612         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4613         .stats_get_strings = mv88e6320_stats_get_strings,
4614         .stats_get_stats = mv88e6390_stats_get_stats,
4615         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4616         .set_egress_port = mv88e6390_g1_set_egress_port,
4617         .watchdog_ops = &mv88e6390_watchdog_ops,
4618         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4619         .pot_clear = mv88e6xxx_g2_pot_clear,
4620         .reset = mv88e6352_g1_reset,
4621         .rmu_disable = mv88e6390_g1_rmu_disable,
4622         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4623         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4624         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4625         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4626         .serdes_power = mv88e6390_serdes_power,
4627         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4628         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4629         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4630         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4631         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4632         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4633         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4634         .serdes_irq_status = mv88e6390_serdes_irq_status,
4635         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4636         .serdes_get_strings = mv88e6390_serdes_get_strings,
4637         .serdes_get_stats = mv88e6390_serdes_get_stats,
4638         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4639         .serdes_get_regs = mv88e6390_serdes_get_regs,
4640         .gpio_ops = &mv88e6352_gpio_ops,
4641         .avb_ops = &mv88e6390_avb_ops,
4642         .ptp_ops = &mv88e6352_ptp_ops,
4643         .phylink_validate = mv88e6390x_phylink_validate,
4644 };
4645
4646 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4647         [MV88E6085] = {
4648                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4649                 .family = MV88E6XXX_FAMILY_6097,
4650                 .name = "Marvell 88E6085",
4651                 .num_databases = 4096,
4652                 .num_macs = 8192,
4653                 .num_ports = 10,
4654                 .num_internal_phys = 5,
4655                 .max_vid = 4095,
4656                 .port_base_addr = 0x10,
4657                 .phy_base_addr = 0x0,
4658                 .global1_addr = 0x1b,
4659                 .global2_addr = 0x1c,
4660                 .age_time_coeff = 15000,
4661                 .g1_irqs = 8,
4662                 .g2_irqs = 10,
4663                 .atu_move_port_mask = 0xf,
4664                 .pvt = true,
4665                 .multi_chip = true,
4666                 .tag_protocol = DSA_TAG_PROTO_DSA,
4667                 .ops = &mv88e6085_ops,
4668         },
4669
4670         [MV88E6095] = {
4671                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4672                 .family = MV88E6XXX_FAMILY_6095,
4673                 .name = "Marvell 88E6095/88E6095F",
4674                 .num_databases = 256,
4675                 .num_macs = 8192,
4676                 .num_ports = 11,
4677                 .num_internal_phys = 0,
4678                 .max_vid = 4095,
4679                 .port_base_addr = 0x10,
4680                 .phy_base_addr = 0x0,
4681                 .global1_addr = 0x1b,
4682                 .global2_addr = 0x1c,
4683                 .age_time_coeff = 15000,
4684                 .g1_irqs = 8,
4685                 .atu_move_port_mask = 0xf,
4686                 .multi_chip = true,
4687                 .tag_protocol = DSA_TAG_PROTO_DSA,
4688                 .ops = &mv88e6095_ops,
4689         },
4690
4691         [MV88E6097] = {
4692                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4693                 .family = MV88E6XXX_FAMILY_6097,
4694                 .name = "Marvell 88E6097/88E6097F",
4695                 .num_databases = 4096,
4696                 .num_macs = 8192,
4697                 .num_ports = 11,
4698                 .num_internal_phys = 8,
4699                 .max_vid = 4095,
4700                 .port_base_addr = 0x10,
4701                 .phy_base_addr = 0x0,
4702                 .global1_addr = 0x1b,
4703                 .global2_addr = 0x1c,
4704                 .age_time_coeff = 15000,
4705                 .g1_irqs = 8,
4706                 .g2_irqs = 10,
4707                 .atu_move_port_mask = 0xf,
4708                 .pvt = true,
4709                 .multi_chip = true,
4710                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4711                 .ops = &mv88e6097_ops,
4712         },
4713
4714         [MV88E6123] = {
4715                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4716                 .family = MV88E6XXX_FAMILY_6165,
4717                 .name = "Marvell 88E6123",
4718                 .num_databases = 4096,
4719                 .num_macs = 1024,
4720                 .num_ports = 3,
4721                 .num_internal_phys = 5,
4722                 .max_vid = 4095,
4723                 .port_base_addr = 0x10,
4724                 .phy_base_addr = 0x0,
4725                 .global1_addr = 0x1b,
4726                 .global2_addr = 0x1c,
4727                 .age_time_coeff = 15000,
4728                 .g1_irqs = 9,
4729                 .g2_irqs = 10,
4730                 .atu_move_port_mask = 0xf,
4731                 .pvt = true,
4732                 .multi_chip = true,
4733                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4734                 .ops = &mv88e6123_ops,
4735         },
4736
4737         [MV88E6131] = {
4738                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4739                 .family = MV88E6XXX_FAMILY_6185,
4740                 .name = "Marvell 88E6131",
4741                 .num_databases = 256,
4742                 .num_macs = 8192,
4743                 .num_ports = 8,
4744                 .num_internal_phys = 0,
4745                 .max_vid = 4095,
4746                 .port_base_addr = 0x10,
4747                 .phy_base_addr = 0x0,
4748                 .global1_addr = 0x1b,
4749                 .global2_addr = 0x1c,
4750                 .age_time_coeff = 15000,
4751                 .g1_irqs = 9,
4752                 .atu_move_port_mask = 0xf,
4753                 .multi_chip = true,
4754                 .tag_protocol = DSA_TAG_PROTO_DSA,
4755                 .ops = &mv88e6131_ops,
4756         },
4757
4758         [MV88E6141] = {
4759                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4760                 .family = MV88E6XXX_FAMILY_6341,
4761                 .name = "Marvell 88E6141",
4762                 .num_databases = 4096,
4763                 .num_macs = 2048,
4764                 .num_ports = 6,
4765                 .num_internal_phys = 5,
4766                 .num_gpio = 11,
4767                 .max_vid = 4095,
4768                 .port_base_addr = 0x10,
4769                 .phy_base_addr = 0x10,
4770                 .global1_addr = 0x1b,
4771                 .global2_addr = 0x1c,
4772                 .age_time_coeff = 3750,
4773                 .atu_move_port_mask = 0x1f,
4774                 .g1_irqs = 9,
4775                 .g2_irqs = 10,
4776                 .pvt = true,
4777                 .multi_chip = true,
4778                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4779                 .ops = &mv88e6141_ops,
4780         },
4781
4782         [MV88E6161] = {
4783                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4784                 .family = MV88E6XXX_FAMILY_6165,
4785                 .name = "Marvell 88E6161",
4786                 .num_databases = 4096,
4787                 .num_macs = 1024,
4788                 .num_ports = 6,
4789                 .num_internal_phys = 5,
4790                 .max_vid = 4095,
4791                 .port_base_addr = 0x10,
4792                 .phy_base_addr = 0x0,
4793                 .global1_addr = 0x1b,
4794                 .global2_addr = 0x1c,
4795                 .age_time_coeff = 15000,
4796                 .g1_irqs = 9,
4797                 .g2_irqs = 10,
4798                 .atu_move_port_mask = 0xf,
4799                 .pvt = true,
4800                 .multi_chip = true,
4801                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4802                 .ptp_support = true,
4803                 .ops = &mv88e6161_ops,
4804         },
4805
4806         [MV88E6165] = {
4807                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4808                 .family = MV88E6XXX_FAMILY_6165,
4809                 .name = "Marvell 88E6165",
4810                 .num_databases = 4096,
4811                 .num_macs = 8192,
4812                 .num_ports = 6,
4813                 .num_internal_phys = 0,
4814                 .max_vid = 4095,
4815                 .port_base_addr = 0x10,
4816                 .phy_base_addr = 0x0,
4817                 .global1_addr = 0x1b,
4818                 .global2_addr = 0x1c,
4819                 .age_time_coeff = 15000,
4820                 .g1_irqs = 9,
4821                 .g2_irqs = 10,
4822                 .atu_move_port_mask = 0xf,
4823                 .pvt = true,
4824                 .multi_chip = true,
4825                 .tag_protocol = DSA_TAG_PROTO_DSA,
4826                 .ptp_support = true,
4827                 .ops = &mv88e6165_ops,
4828         },
4829
4830         [MV88E6171] = {
4831                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4832                 .family = MV88E6XXX_FAMILY_6351,
4833                 .name = "Marvell 88E6171",
4834                 .num_databases = 4096,
4835                 .num_macs = 8192,
4836                 .num_ports = 7,
4837                 .num_internal_phys = 5,
4838                 .max_vid = 4095,
4839                 .port_base_addr = 0x10,
4840                 .phy_base_addr = 0x0,
4841                 .global1_addr = 0x1b,
4842                 .global2_addr = 0x1c,
4843                 .age_time_coeff = 15000,
4844                 .g1_irqs = 9,
4845                 .g2_irqs = 10,
4846                 .atu_move_port_mask = 0xf,
4847                 .pvt = true,
4848                 .multi_chip = true,
4849                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4850                 .ops = &mv88e6171_ops,
4851         },
4852
4853         [MV88E6172] = {
4854                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4855                 .family = MV88E6XXX_FAMILY_6352,
4856                 .name = "Marvell 88E6172",
4857                 .num_databases = 4096,
4858                 .num_macs = 8192,
4859                 .num_ports = 7,
4860                 .num_internal_phys = 5,
4861                 .num_gpio = 15,
4862                 .max_vid = 4095,
4863                 .port_base_addr = 0x10,
4864                 .phy_base_addr = 0x0,
4865                 .global1_addr = 0x1b,
4866                 .global2_addr = 0x1c,
4867                 .age_time_coeff = 15000,
4868                 .g1_irqs = 9,
4869                 .g2_irqs = 10,
4870                 .atu_move_port_mask = 0xf,
4871                 .pvt = true,
4872                 .multi_chip = true,
4873                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4874                 .ops = &mv88e6172_ops,
4875         },
4876
4877         [MV88E6175] = {
4878                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4879                 .family = MV88E6XXX_FAMILY_6351,
4880                 .name = "Marvell 88E6175",
4881                 .num_databases = 4096,
4882                 .num_macs = 8192,
4883                 .num_ports = 7,
4884                 .num_internal_phys = 5,
4885                 .max_vid = 4095,
4886                 .port_base_addr = 0x10,
4887                 .phy_base_addr = 0x0,
4888                 .global1_addr = 0x1b,
4889                 .global2_addr = 0x1c,
4890                 .age_time_coeff = 15000,
4891                 .g1_irqs = 9,
4892                 .g2_irqs = 10,
4893                 .atu_move_port_mask = 0xf,
4894                 .pvt = true,
4895                 .multi_chip = true,
4896                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4897                 .ops = &mv88e6175_ops,
4898         },
4899
4900         [MV88E6176] = {
4901                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4902                 .family = MV88E6XXX_FAMILY_6352,
4903                 .name = "Marvell 88E6176",
4904                 .num_databases = 4096,
4905                 .num_macs = 8192,
4906                 .num_ports = 7,
4907                 .num_internal_phys = 5,
4908                 .num_gpio = 15,
4909                 .max_vid = 4095,
4910                 .port_base_addr = 0x10,
4911                 .phy_base_addr = 0x0,
4912                 .global1_addr = 0x1b,
4913                 .global2_addr = 0x1c,
4914                 .age_time_coeff = 15000,
4915                 .g1_irqs = 9,
4916                 .g2_irqs = 10,
4917                 .atu_move_port_mask = 0xf,
4918                 .pvt = true,
4919                 .multi_chip = true,
4920                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4921                 .ops = &mv88e6176_ops,
4922         },
4923
4924         [MV88E6185] = {
4925                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4926                 .family = MV88E6XXX_FAMILY_6185,
4927                 .name = "Marvell 88E6185",
4928                 .num_databases = 256,
4929                 .num_macs = 8192,
4930                 .num_ports = 10,
4931                 .num_internal_phys = 0,
4932                 .max_vid = 4095,
4933                 .port_base_addr = 0x10,
4934                 .phy_base_addr = 0x0,
4935                 .global1_addr = 0x1b,
4936                 .global2_addr = 0x1c,
4937                 .age_time_coeff = 15000,
4938                 .g1_irqs = 8,
4939                 .atu_move_port_mask = 0xf,
4940                 .multi_chip = true,
4941                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4942                 .ops = &mv88e6185_ops,
4943         },
4944
4945         [MV88E6190] = {
4946                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4947                 .family = MV88E6XXX_FAMILY_6390,
4948                 .name = "Marvell 88E6190",
4949                 .num_databases = 4096,
4950                 .num_macs = 16384,
4951                 .num_ports = 11,        /* 10 + Z80 */
4952                 .num_internal_phys = 9,
4953                 .num_gpio = 16,
4954                 .max_vid = 8191,
4955                 .port_base_addr = 0x0,
4956                 .phy_base_addr = 0x0,
4957                 .global1_addr = 0x1b,
4958                 .global2_addr = 0x1c,
4959                 .tag_protocol = DSA_TAG_PROTO_DSA,
4960                 .age_time_coeff = 3750,
4961                 .g1_irqs = 9,
4962                 .g2_irqs = 14,
4963                 .pvt = true,
4964                 .multi_chip = true,
4965                 .atu_move_port_mask = 0x1f,
4966                 .ops = &mv88e6190_ops,
4967         },
4968
4969         [MV88E6190X] = {
4970                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4971                 .family = MV88E6XXX_FAMILY_6390,
4972                 .name = "Marvell 88E6190X",
4973                 .num_databases = 4096,
4974                 .num_macs = 16384,
4975                 .num_ports = 11,        /* 10 + Z80 */
4976                 .num_internal_phys = 9,
4977                 .num_gpio = 16,
4978                 .max_vid = 8191,
4979                 .port_base_addr = 0x0,
4980                 .phy_base_addr = 0x0,
4981                 .global1_addr = 0x1b,
4982                 .global2_addr = 0x1c,
4983                 .age_time_coeff = 3750,
4984                 .g1_irqs = 9,
4985                 .g2_irqs = 14,
4986                 .atu_move_port_mask = 0x1f,
4987                 .pvt = true,
4988                 .multi_chip = true,
4989                 .tag_protocol = DSA_TAG_PROTO_DSA,
4990                 .ops = &mv88e6190x_ops,
4991         },
4992
4993         [MV88E6191] = {
4994                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4995                 .family = MV88E6XXX_FAMILY_6390,
4996                 .name = "Marvell 88E6191",
4997                 .num_databases = 4096,
4998                 .num_macs = 16384,
4999                 .num_ports = 11,        /* 10 + Z80 */
5000                 .num_internal_phys = 9,
5001                 .max_vid = 8191,
5002                 .port_base_addr = 0x0,
5003                 .phy_base_addr = 0x0,
5004                 .global1_addr = 0x1b,
5005                 .global2_addr = 0x1c,
5006                 .age_time_coeff = 3750,
5007                 .g1_irqs = 9,
5008                 .g2_irqs = 14,
5009                 .atu_move_port_mask = 0x1f,
5010                 .pvt = true,
5011                 .multi_chip = true,
5012                 .tag_protocol = DSA_TAG_PROTO_DSA,
5013                 .ptp_support = true,
5014                 .ops = &mv88e6191_ops,
5015         },
5016
5017         [MV88E6220] = {
5018                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5019                 .family = MV88E6XXX_FAMILY_6250,
5020                 .name = "Marvell 88E6220",
5021                 .num_databases = 64,
5022
5023                 /* Ports 2-4 are not routed to pins
5024                  * => usable ports 0, 1, 5, 6
5025                  */
5026                 .num_ports = 7,
5027                 .num_internal_phys = 2,
5028                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5029                 .max_vid = 4095,
5030                 .port_base_addr = 0x08,
5031                 .phy_base_addr = 0x00,
5032                 .global1_addr = 0x0f,
5033                 .global2_addr = 0x07,
5034                 .age_time_coeff = 15000,
5035                 .g1_irqs = 9,
5036                 .g2_irqs = 10,
5037                 .atu_move_port_mask = 0xf,
5038                 .dual_chip = true,
5039                 .tag_protocol = DSA_TAG_PROTO_DSA,
5040                 .ptp_support = true,
5041                 .ops = &mv88e6250_ops,
5042         },
5043
5044         [MV88E6240] = {
5045                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5046                 .family = MV88E6XXX_FAMILY_6352,
5047                 .name = "Marvell 88E6240",
5048                 .num_databases = 4096,
5049                 .num_macs = 8192,
5050                 .num_ports = 7,
5051                 .num_internal_phys = 5,
5052                 .num_gpio = 15,
5053                 .max_vid = 4095,
5054                 .port_base_addr = 0x10,
5055                 .phy_base_addr = 0x0,
5056                 .global1_addr = 0x1b,
5057                 .global2_addr = 0x1c,
5058                 .age_time_coeff = 15000,
5059                 .g1_irqs = 9,
5060                 .g2_irqs = 10,
5061                 .atu_move_port_mask = 0xf,
5062                 .pvt = true,
5063                 .multi_chip = true,
5064                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5065                 .ptp_support = true,
5066                 .ops = &mv88e6240_ops,
5067         },
5068
5069         [MV88E6250] = {
5070                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5071                 .family = MV88E6XXX_FAMILY_6250,
5072                 .name = "Marvell 88E6250",
5073                 .num_databases = 64,
5074                 .num_ports = 7,
5075                 .num_internal_phys = 5,
5076                 .max_vid = 4095,
5077                 .port_base_addr = 0x08,
5078                 .phy_base_addr = 0x00,
5079                 .global1_addr = 0x0f,
5080                 .global2_addr = 0x07,
5081                 .age_time_coeff = 15000,
5082                 .g1_irqs = 9,
5083                 .g2_irqs = 10,
5084                 .atu_move_port_mask = 0xf,
5085                 .dual_chip = true,
5086                 .tag_protocol = DSA_TAG_PROTO_DSA,
5087                 .ptp_support = true,
5088                 .ops = &mv88e6250_ops,
5089         },
5090
5091         [MV88E6290] = {
5092                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5093                 .family = MV88E6XXX_FAMILY_6390,
5094                 .name = "Marvell 88E6290",
5095                 .num_databases = 4096,
5096                 .num_ports = 11,        /* 10 + Z80 */
5097                 .num_internal_phys = 9,
5098                 .num_gpio = 16,
5099                 .max_vid = 8191,
5100                 .port_base_addr = 0x0,
5101                 .phy_base_addr = 0x0,
5102                 .global1_addr = 0x1b,
5103                 .global2_addr = 0x1c,
5104                 .age_time_coeff = 3750,
5105                 .g1_irqs = 9,
5106                 .g2_irqs = 14,
5107                 .atu_move_port_mask = 0x1f,
5108                 .pvt = true,
5109                 .multi_chip = true,
5110                 .tag_protocol = DSA_TAG_PROTO_DSA,
5111                 .ptp_support = true,
5112                 .ops = &mv88e6290_ops,
5113         },
5114
5115         [MV88E6320] = {
5116                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5117                 .family = MV88E6XXX_FAMILY_6320,
5118                 .name = "Marvell 88E6320",
5119                 .num_databases = 4096,
5120                 .num_macs = 8192,
5121                 .num_ports = 7,
5122                 .num_internal_phys = 5,
5123                 .num_gpio = 15,
5124                 .max_vid = 4095,
5125                 .port_base_addr = 0x10,
5126                 .phy_base_addr = 0x0,
5127                 .global1_addr = 0x1b,
5128                 .global2_addr = 0x1c,
5129                 .age_time_coeff = 15000,
5130                 .g1_irqs = 8,
5131                 .g2_irqs = 10,
5132                 .atu_move_port_mask = 0xf,
5133                 .pvt = true,
5134                 .multi_chip = true,
5135                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5136                 .ptp_support = true,
5137                 .ops = &mv88e6320_ops,
5138         },
5139
5140         [MV88E6321] = {
5141                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5142                 .family = MV88E6XXX_FAMILY_6320,
5143                 .name = "Marvell 88E6321",
5144                 .num_databases = 4096,
5145                 .num_macs = 8192,
5146                 .num_ports = 7,
5147                 .num_internal_phys = 5,
5148                 .num_gpio = 15,
5149                 .max_vid = 4095,
5150                 .port_base_addr = 0x10,
5151                 .phy_base_addr = 0x0,
5152                 .global1_addr = 0x1b,
5153                 .global2_addr = 0x1c,
5154                 .age_time_coeff = 15000,
5155                 .g1_irqs = 8,
5156                 .g2_irqs = 10,
5157                 .atu_move_port_mask = 0xf,
5158                 .multi_chip = true,
5159                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5160                 .ptp_support = true,
5161                 .ops = &mv88e6321_ops,
5162         },
5163
5164         [MV88E6341] = {
5165                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5166                 .family = MV88E6XXX_FAMILY_6341,
5167                 .name = "Marvell 88E6341",
5168                 .num_databases = 4096,
5169                 .num_macs = 2048,
5170                 .num_internal_phys = 5,
5171                 .num_ports = 6,
5172                 .num_gpio = 11,
5173                 .max_vid = 4095,
5174                 .port_base_addr = 0x10,
5175                 .phy_base_addr = 0x10,
5176                 .global1_addr = 0x1b,
5177                 .global2_addr = 0x1c,
5178                 .age_time_coeff = 3750,
5179                 .atu_move_port_mask = 0x1f,
5180                 .g1_irqs = 9,
5181                 .g2_irqs = 10,
5182                 .pvt = true,
5183                 .multi_chip = true,
5184                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5185                 .ptp_support = true,
5186                 .ops = &mv88e6341_ops,
5187         },
5188
5189         [MV88E6350] = {
5190                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5191                 .family = MV88E6XXX_FAMILY_6351,
5192                 .name = "Marvell 88E6350",
5193                 .num_databases = 4096,
5194                 .num_macs = 8192,
5195                 .num_ports = 7,
5196                 .num_internal_phys = 5,
5197                 .max_vid = 4095,
5198                 .port_base_addr = 0x10,
5199                 .phy_base_addr = 0x0,
5200                 .global1_addr = 0x1b,
5201                 .global2_addr = 0x1c,
5202                 .age_time_coeff = 15000,
5203                 .g1_irqs = 9,
5204                 .g2_irqs = 10,
5205                 .atu_move_port_mask = 0xf,
5206                 .pvt = true,
5207                 .multi_chip = true,
5208                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5209                 .ops = &mv88e6350_ops,
5210         },
5211
5212         [MV88E6351] = {
5213                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5214                 .family = MV88E6XXX_FAMILY_6351,
5215                 .name = "Marvell 88E6351",
5216                 .num_databases = 4096,
5217                 .num_macs = 8192,
5218                 .num_ports = 7,
5219                 .num_internal_phys = 5,
5220                 .max_vid = 4095,
5221                 .port_base_addr = 0x10,
5222                 .phy_base_addr = 0x0,
5223                 .global1_addr = 0x1b,
5224                 .global2_addr = 0x1c,
5225                 .age_time_coeff = 15000,
5226                 .g1_irqs = 9,
5227                 .g2_irqs = 10,
5228                 .atu_move_port_mask = 0xf,
5229                 .pvt = true,
5230                 .multi_chip = true,
5231                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5232                 .ops = &mv88e6351_ops,
5233         },
5234
5235         [MV88E6352] = {
5236                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5237                 .family = MV88E6XXX_FAMILY_6352,
5238                 .name = "Marvell 88E6352",
5239                 .num_databases = 4096,
5240                 .num_macs = 8192,
5241                 .num_ports = 7,
5242                 .num_internal_phys = 5,
5243                 .num_gpio = 15,
5244                 .max_vid = 4095,
5245                 .port_base_addr = 0x10,
5246                 .phy_base_addr = 0x0,
5247                 .global1_addr = 0x1b,
5248                 .global2_addr = 0x1c,
5249                 .age_time_coeff = 15000,
5250                 .g1_irqs = 9,
5251                 .g2_irqs = 10,
5252                 .atu_move_port_mask = 0xf,
5253                 .pvt = true,
5254                 .multi_chip = true,
5255                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5256                 .ptp_support = true,
5257                 .ops = &mv88e6352_ops,
5258         },
5259         [MV88E6390] = {
5260                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5261                 .family = MV88E6XXX_FAMILY_6390,
5262                 .name = "Marvell 88E6390",
5263                 .num_databases = 4096,
5264                 .num_macs = 16384,
5265                 .num_ports = 11,        /* 10 + Z80 */
5266                 .num_internal_phys = 9,
5267                 .num_gpio = 16,
5268                 .max_vid = 8191,
5269                 .port_base_addr = 0x0,
5270                 .phy_base_addr = 0x0,
5271                 .global1_addr = 0x1b,
5272                 .global2_addr = 0x1c,
5273                 .age_time_coeff = 3750,
5274                 .g1_irqs = 9,
5275                 .g2_irqs = 14,
5276                 .atu_move_port_mask = 0x1f,
5277                 .pvt = true,
5278                 .multi_chip = true,
5279                 .tag_protocol = DSA_TAG_PROTO_DSA,
5280                 .ptp_support = true,
5281                 .ops = &mv88e6390_ops,
5282         },
5283         [MV88E6390X] = {
5284                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5285                 .family = MV88E6XXX_FAMILY_6390,
5286                 .name = "Marvell 88E6390X",
5287                 .num_databases = 4096,
5288                 .num_macs = 16384,
5289                 .num_ports = 11,        /* 10 + Z80 */
5290                 .num_internal_phys = 9,
5291                 .num_gpio = 16,
5292                 .max_vid = 8191,
5293                 .port_base_addr = 0x0,
5294                 .phy_base_addr = 0x0,
5295                 .global1_addr = 0x1b,
5296                 .global2_addr = 0x1c,
5297                 .age_time_coeff = 3750,
5298                 .g1_irqs = 9,
5299                 .g2_irqs = 14,
5300                 .atu_move_port_mask = 0x1f,
5301                 .pvt = true,
5302                 .multi_chip = true,
5303                 .tag_protocol = DSA_TAG_PROTO_DSA,
5304                 .ptp_support = true,
5305                 .ops = &mv88e6390x_ops,
5306         },
5307 };
5308
5309 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5310 {
5311         int i;
5312
5313         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5314                 if (mv88e6xxx_table[i].prod_num == prod_num)
5315                         return &mv88e6xxx_table[i];
5316
5317         return NULL;
5318 }
5319
5320 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5321 {
5322         const struct mv88e6xxx_info *info;
5323         unsigned int prod_num, rev;
5324         u16 id;
5325         int err;
5326
5327         mv88e6xxx_reg_lock(chip);
5328         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5329         mv88e6xxx_reg_unlock(chip);
5330         if (err)
5331                 return err;
5332
5333         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5334         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5335
5336         info = mv88e6xxx_lookup_info(prod_num);
5337         if (!info)
5338                 return -ENODEV;
5339
5340         /* Update the compatible info with the probed one */
5341         chip->info = info;
5342
5343         err = mv88e6xxx_g2_require(chip);
5344         if (err)
5345                 return err;
5346
5347         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5348                  chip->info->prod_num, chip->info->name, rev);
5349
5350         return 0;
5351 }
5352
5353 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5354 {
5355         struct mv88e6xxx_chip *chip;
5356
5357         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5358         if (!chip)
5359                 return NULL;
5360
5361         chip->dev = dev;
5362
5363         mutex_init(&chip->reg_lock);
5364         INIT_LIST_HEAD(&chip->mdios);
5365         idr_init(&chip->policies);
5366
5367         return chip;
5368 }
5369
5370 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5371                                                         int port,
5372                                                         enum dsa_tag_protocol m)
5373 {
5374         struct mv88e6xxx_chip *chip = ds->priv;
5375
5376         return chip->info->tag_protocol;
5377 }
5378
5379 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5380                                       const struct switchdev_obj_port_mdb *mdb)
5381 {
5382         /* We don't need any dynamic resource from the kernel (yet),
5383          * so skip the prepare phase.
5384          */
5385
5386         return 0;
5387 }
5388
5389 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5390                                    const struct switchdev_obj_port_mdb *mdb)
5391 {
5392         struct mv88e6xxx_chip *chip = ds->priv;
5393
5394         mv88e6xxx_reg_lock(chip);
5395         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5396                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5397                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5398                         port);
5399         mv88e6xxx_reg_unlock(chip);
5400 }
5401
5402 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5403                                   const struct switchdev_obj_port_mdb *mdb)
5404 {
5405         struct mv88e6xxx_chip *chip = ds->priv;
5406         int err;
5407
5408         mv88e6xxx_reg_lock(chip);
5409         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5410         mv88e6xxx_reg_unlock(chip);
5411
5412         return err;
5413 }
5414
5415 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5416                                      struct dsa_mall_mirror_tc_entry *mirror,
5417                                      bool ingress)
5418 {
5419         enum mv88e6xxx_egress_direction direction = ingress ?
5420                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5421                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5422         struct mv88e6xxx_chip *chip = ds->priv;
5423         bool other_mirrors = false;
5424         int i;
5425         int err;
5426
5427         if (!chip->info->ops->set_egress_port)
5428                 return -EOPNOTSUPP;
5429
5430         mutex_lock(&chip->reg_lock);
5431         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5432             mirror->to_local_port) {
5433                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5434                         other_mirrors |= ingress ?
5435                                          chip->ports[i].mirror_ingress :
5436                                          chip->ports[i].mirror_egress;
5437
5438                 /* Can't change egress port when other mirror is active */
5439                 if (other_mirrors) {
5440                         err = -EBUSY;
5441                         goto out;
5442                 }
5443
5444                 err = chip->info->ops->set_egress_port(chip,
5445                                                        direction,
5446                                                        mirror->to_local_port);
5447                 if (err)
5448                         goto out;
5449         }
5450
5451         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5452 out:
5453         mutex_unlock(&chip->reg_lock);
5454
5455         return err;
5456 }
5457
5458 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5459                                       struct dsa_mall_mirror_tc_entry *mirror)
5460 {
5461         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5462                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5463                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5464         struct mv88e6xxx_chip *chip = ds->priv;
5465         bool other_mirrors = false;
5466         int i;
5467
5468         mutex_lock(&chip->reg_lock);
5469         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5470                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5471
5472         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5473                 other_mirrors |= mirror->ingress ?
5474                                  chip->ports[i].mirror_ingress :
5475                                  chip->ports[i].mirror_egress;
5476
5477         /* Reset egress port when no other mirror is active */
5478         if (!other_mirrors) {
5479                 if (chip->info->ops->set_egress_port(chip,
5480                                                      direction,
5481                                                      dsa_upstream_port(ds,
5482                                                                        port)))
5483                         dev_err(ds->dev, "failed to set egress port\n");
5484         }
5485
5486         mutex_unlock(&chip->reg_lock);
5487 }
5488
5489 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5490                                          bool unicast, bool multicast)
5491 {
5492         struct mv88e6xxx_chip *chip = ds->priv;
5493         int err = -EOPNOTSUPP;
5494
5495         mv88e6xxx_reg_lock(chip);
5496         if (chip->info->ops->port_set_egress_floods)
5497                 err = chip->info->ops->port_set_egress_floods(chip, port,
5498                                                               unicast,
5499                                                               multicast);
5500         mv88e6xxx_reg_unlock(chip);
5501
5502         return err;
5503 }
5504
5505 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5506         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
5507         .setup                  = mv88e6xxx_setup,
5508         .teardown               = mv88e6xxx_teardown,
5509         .phylink_validate       = mv88e6xxx_validate,
5510         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5511         .phylink_mac_config     = mv88e6xxx_mac_config,
5512         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5513         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
5514         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
5515         .get_strings            = mv88e6xxx_get_strings,
5516         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
5517         .get_sset_count         = mv88e6xxx_get_sset_count,
5518         .port_enable            = mv88e6xxx_port_enable,
5519         .port_disable           = mv88e6xxx_port_disable,
5520         .get_mac_eee            = mv88e6xxx_get_mac_eee,
5521         .set_mac_eee            = mv88e6xxx_set_mac_eee,
5522         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
5523         .get_eeprom             = mv88e6xxx_get_eeprom,
5524         .set_eeprom             = mv88e6xxx_set_eeprom,
5525         .get_regs_len           = mv88e6xxx_get_regs_len,
5526         .get_regs               = mv88e6xxx_get_regs,
5527         .get_rxnfc              = mv88e6xxx_get_rxnfc,
5528         .set_rxnfc              = mv88e6xxx_set_rxnfc,
5529         .set_ageing_time        = mv88e6xxx_set_ageing_time,
5530         .port_bridge_join       = mv88e6xxx_port_bridge_join,
5531         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
5532         .port_egress_floods     = mv88e6xxx_port_egress_floods,
5533         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
5534         .port_fast_age          = mv88e6xxx_port_fast_age,
5535         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
5536         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
5537         .port_vlan_add          = mv88e6xxx_port_vlan_add,
5538         .port_vlan_del          = mv88e6xxx_port_vlan_del,
5539         .port_fdb_add           = mv88e6xxx_port_fdb_add,
5540         .port_fdb_del           = mv88e6xxx_port_fdb_del,
5541         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5542         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5543         .port_mdb_add           = mv88e6xxx_port_mdb_add,
5544         .port_mdb_del           = mv88e6xxx_port_mdb_del,
5545         .port_mirror_add        = mv88e6xxx_port_mirror_add,
5546         .port_mirror_del        = mv88e6xxx_port_mirror_del,
5547         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
5548         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5549         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
5550         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
5551         .port_txtstamp          = mv88e6xxx_port_txtstamp,
5552         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
5553         .get_ts_info            = mv88e6xxx_get_ts_info,
5554         .devlink_param_get      = mv88e6xxx_devlink_param_get,
5555         .devlink_param_set      = mv88e6xxx_devlink_param_set,
5556 };
5557
5558 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5559 {
5560         struct device *dev = chip->dev;
5561         struct dsa_switch *ds;
5562
5563         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5564         if (!ds)
5565                 return -ENOMEM;
5566
5567         ds->dev = dev;
5568         ds->num_ports = mv88e6xxx_num_ports(chip);
5569         ds->priv = chip;
5570         ds->dev = dev;
5571         ds->ops = &mv88e6xxx_switch_ops;
5572         ds->ageing_time_min = chip->info->age_time_coeff;
5573         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5574
5575         dev_set_drvdata(dev, ds);
5576
5577         return dsa_register_switch(ds);
5578 }
5579
5580 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5581 {
5582         dsa_unregister_switch(chip->ds);
5583 }
5584
5585 static const void *pdata_device_get_match_data(struct device *dev)
5586 {
5587         const struct of_device_id *matches = dev->driver->of_match_table;
5588         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5589
5590         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5591              matches++) {
5592                 if (!strcmp(pdata->compatible, matches->compatible))
5593                         return matches->data;
5594         }
5595         return NULL;
5596 }
5597
5598 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5599  * would be lost after a power cycle so prevent it to be suspended.
5600  */
5601 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5602 {
5603         return -EOPNOTSUPP;
5604 }
5605
5606 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5607 {
5608         return 0;
5609 }
5610
5611 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5612
5613 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5614 {
5615         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5616         const struct mv88e6xxx_info *compat_info = NULL;
5617         struct device *dev = &mdiodev->dev;
5618         struct device_node *np = dev->of_node;
5619         struct mv88e6xxx_chip *chip;
5620         int port;
5621         int err;
5622
5623         if (!np && !pdata)
5624                 return -EINVAL;
5625
5626         if (np)
5627                 compat_info = of_device_get_match_data(dev);
5628
5629         if (pdata) {
5630                 compat_info = pdata_device_get_match_data(dev);
5631
5632                 if (!pdata->netdev)
5633                         return -EINVAL;
5634
5635                 for (port = 0; port < DSA_MAX_PORTS; port++) {
5636                         if (!(pdata->enabled_ports & (1 << port)))
5637                                 continue;
5638                         if (strcmp(pdata->cd.port_names[port], "cpu"))
5639                                 continue;
5640                         pdata->cd.netdev[port] = &pdata->netdev->dev;
5641                         break;
5642                 }
5643         }
5644
5645         if (!compat_info)
5646                 return -EINVAL;
5647
5648         chip = mv88e6xxx_alloc_chip(dev);
5649         if (!chip) {
5650                 err = -ENOMEM;
5651                 goto out;
5652         }
5653
5654         chip->info = compat_info;
5655
5656         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5657         if (err)
5658                 goto out;
5659
5660         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5661         if (IS_ERR(chip->reset)) {
5662                 err = PTR_ERR(chip->reset);
5663                 goto out;
5664         }
5665         if (chip->reset)
5666                 usleep_range(1000, 2000);
5667
5668         err = mv88e6xxx_detect(chip);
5669         if (err)
5670                 goto out;
5671
5672         mv88e6xxx_phy_init(chip);
5673
5674         if (chip->info->ops->get_eeprom) {
5675                 if (np)
5676                         of_property_read_u32(np, "eeprom-length",
5677                                              &chip->eeprom_len);
5678                 else
5679                         chip->eeprom_len = pdata->eeprom_len;
5680         }
5681
5682         mv88e6xxx_reg_lock(chip);
5683         err = mv88e6xxx_switch_reset(chip);
5684         mv88e6xxx_reg_unlock(chip);
5685         if (err)
5686                 goto out;
5687
5688         if (np) {
5689                 chip->irq = of_irq_get(np, 0);
5690                 if (chip->irq == -EPROBE_DEFER) {
5691                         err = chip->irq;
5692                         goto out;
5693                 }
5694         }
5695
5696         if (pdata)
5697                 chip->irq = pdata->irq;
5698
5699         /* Has to be performed before the MDIO bus is created, because
5700          * the PHYs will link their interrupts to these interrupt
5701          * controllers
5702          */
5703         mv88e6xxx_reg_lock(chip);
5704         if (chip->irq > 0)
5705                 err = mv88e6xxx_g1_irq_setup(chip);
5706         else
5707                 err = mv88e6xxx_irq_poll_setup(chip);
5708         mv88e6xxx_reg_unlock(chip);
5709
5710         if (err)
5711                 goto out;
5712
5713         if (chip->info->g2_irqs > 0) {
5714                 err = mv88e6xxx_g2_irq_setup(chip);
5715                 if (err)
5716                         goto out_g1_irq;
5717         }
5718
5719         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5720         if (err)
5721                 goto out_g2_irq;
5722
5723         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5724         if (err)
5725                 goto out_g1_atu_prob_irq;
5726
5727         err = mv88e6xxx_mdios_register(chip, np);
5728         if (err)
5729                 goto out_g1_vtu_prob_irq;
5730
5731         err = mv88e6xxx_register_switch(chip);
5732         if (err)
5733                 goto out_mdio;
5734
5735         return 0;
5736
5737 out_mdio:
5738         mv88e6xxx_mdios_unregister(chip);
5739 out_g1_vtu_prob_irq:
5740         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5741 out_g1_atu_prob_irq:
5742         mv88e6xxx_g1_atu_prob_irq_free(chip);
5743 out_g2_irq:
5744         if (chip->info->g2_irqs > 0)
5745                 mv88e6xxx_g2_irq_free(chip);
5746 out_g1_irq:
5747         if (chip->irq > 0)
5748                 mv88e6xxx_g1_irq_free(chip);
5749         else
5750                 mv88e6xxx_irq_poll_free(chip);
5751 out:
5752         if (pdata)
5753                 dev_put(pdata->netdev);
5754
5755         return err;
5756 }
5757
5758 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5759 {
5760         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5761         struct mv88e6xxx_chip *chip = ds->priv;
5762
5763         if (chip->info->ptp_support) {
5764                 mv88e6xxx_hwtstamp_free(chip);
5765                 mv88e6xxx_ptp_free(chip);
5766         }
5767
5768         mv88e6xxx_phy_destroy(chip);
5769         mv88e6xxx_unregister_switch(chip);
5770         mv88e6xxx_mdios_unregister(chip);
5771
5772         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5773         mv88e6xxx_g1_atu_prob_irq_free(chip);
5774
5775         if (chip->info->g2_irqs > 0)
5776                 mv88e6xxx_g2_irq_free(chip);
5777
5778         if (chip->irq > 0)
5779                 mv88e6xxx_g1_irq_free(chip);
5780         else
5781                 mv88e6xxx_irq_poll_free(chip);
5782 }
5783
5784 static const struct of_device_id mv88e6xxx_of_match[] = {
5785         {
5786                 .compatible = "marvell,mv88e6085",
5787                 .data = &mv88e6xxx_table[MV88E6085],
5788         },
5789         {
5790                 .compatible = "marvell,mv88e6190",
5791                 .data = &mv88e6xxx_table[MV88E6190],
5792         },
5793         {
5794                 .compatible = "marvell,mv88e6250",
5795                 .data = &mv88e6xxx_table[MV88E6250],
5796         },
5797         { /* sentinel */ },
5798 };
5799
5800 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5801
5802 static struct mdio_driver mv88e6xxx_driver = {
5803         .probe  = mv88e6xxx_probe,
5804         .remove = mv88e6xxx_remove,
5805         .mdiodrv.driver = {
5806                 .name = "mv88e6085",
5807                 .of_match_table = mv88e6xxx_of_match,
5808                 .pm = &mv88e6xxx_pm_ops,
5809         },
5810 };
5811
5812 mdio_module_driver(mv88e6xxx_driver);
5813
5814 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5815 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5816 MODULE_LICENSE("GPL");