1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_mdio.h>
14 #include <linux/of_net.h>
15 #include <linux/of_platform.h>
16 #include <linux/phylink.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/gpio/consumer.h>
25 /* String, offset, and register size in bytes if different from 4 bytes */
26 static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
70 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
72 struct mii_bus *bus = priv->bus;
75 /* Write the desired MMD Devad */
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
80 /* Write the desired MMD register address */
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
85 /* Select the Function : DATA with no post increment */
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
90 /* Read the content of the MMD's selected register */
91 value = bus->read(bus, 0, MII_MMD_DATA);
95 dev_err(&bus->dev, "failed to read mmd register\n");
101 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
104 struct mii_bus *bus = priv->bus;
107 /* Write the desired MMD Devad */
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
112 /* Write the desired MMD register address */
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
117 /* Select the Function : DATA with no post increment */
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
122 /* Write the data into MMD's selected register */
123 ret = bus->write(bus, 0, MII_MMD_DATA, data);
127 "failed to write mmd register\n");
132 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
134 struct mii_bus *bus = priv->bus;
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
138 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
140 mutex_unlock(&bus->mdio_lock);
144 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
146 struct mii_bus *bus = priv->bus;
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
151 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
154 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
156 mutex_unlock(&bus->mdio_lock);
160 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
162 core_rmw(priv, reg, 0, val);
166 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
168 core_rmw(priv, reg, val, 0);
172 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
174 struct mii_bus *bus = priv->bus;
178 page = (reg >> 6) & 0x3ff;
179 r = (reg >> 2) & 0xf;
183 /* MT7530 uses 31 as the pseudo port */
184 ret = bus->write(bus, 0x1f, 0x1f, page);
188 ret = bus->write(bus, 0x1f, r, lo);
192 ret = bus->write(bus, 0x1f, 0x10, hi);
196 "failed to write mt7530 register\n");
201 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
203 struct mii_bus *bus = priv->bus;
207 page = (reg >> 6) & 0x3ff;
208 r = (reg >> 2) & 0xf;
210 /* MT7530 uses 31 as the pseudo port */
211 ret = bus->write(bus, 0x1f, 0x1f, page);
214 "failed to read mt7530 register\n");
218 lo = bus->read(bus, 0x1f, r);
219 hi = bus->read(bus, 0x1f, 0x10);
221 return (hi << 16) | (lo & 0xffff);
225 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
227 struct mii_bus *bus = priv->bus;
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
231 mt7530_mii_write(priv, reg, val);
233 mutex_unlock(&bus->mdio_lock);
237 _mt7530_read(struct mt7530_dummy_poll *p)
239 struct mii_bus *bus = p->priv->bus;
242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
244 val = mt7530_mii_read(p->priv, p->reg);
246 mutex_unlock(&bus->mdio_lock);
252 mt7530_read(struct mt7530_priv *priv, u32 reg)
254 struct mt7530_dummy_poll p;
256 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
257 return _mt7530_read(&p);
261 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
264 struct mii_bus *bus = priv->bus;
267 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
269 val = mt7530_mii_read(priv, reg);
272 mt7530_mii_write(priv, reg, val);
274 mutex_unlock(&bus->mdio_lock);
278 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
280 mt7530_rmw(priv, reg, 0, val);
284 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
286 mt7530_rmw(priv, reg, val, 0);
290 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
294 struct mt7530_dummy_poll p;
296 /* Set the command operating upon the MAC address entries */
297 val = ATC_BUSY | ATC_MAT(0) | cmd;
298 mt7530_write(priv, MT7530_ATC, val);
300 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
301 ret = readx_poll_timeout(_mt7530_read, &p, val,
302 !(val & ATC_BUSY), 20, 20000);
304 dev_err(priv->dev, "reset timeout\n");
308 /* Additional sanity for read command if the specified
311 val = mt7530_read(priv, MT7530_ATC);
312 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
322 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
327 /* Read from ARL table into an array */
328 for (i = 0; i < 3; i++) {
329 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
331 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
332 __func__, __LINE__, i, reg[i]);
335 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
336 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
337 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
338 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
339 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
340 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
341 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
342 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
343 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
344 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
348 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
349 u8 port_mask, const u8 *mac,
355 reg[1] |= vid & CVID_MASK;
356 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
357 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
358 /* STATIC_ENT indicate that entry is static wouldn't
359 * be aged out and STATIC_EMP specified as erasing an
362 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
363 reg[1] |= mac[5] << MAC_BYTE_5;
364 reg[1] |= mac[4] << MAC_BYTE_4;
365 reg[0] |= mac[3] << MAC_BYTE_3;
366 reg[0] |= mac[2] << MAC_BYTE_2;
367 reg[0] |= mac[1] << MAC_BYTE_1;
368 reg[0] |= mac[0] << MAC_BYTE_0;
370 /* Write array into the ARL table */
371 for (i = 0; i < 3; i++)
372 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
376 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
378 struct mt7530_priv *priv = ds->priv;
379 u32 ncpo1, ssc_delta, trgint, i, xtal;
381 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
383 if (xtal == HWTRAP_XTAL_20MHZ) {
385 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
391 case PHY_INTERFACE_MODE_RGMII:
393 /* PLL frequency: 125MHz */
396 case PHY_INTERFACE_MODE_TRGMII:
398 if (priv->id == ID_MT7621) {
399 /* PLL frequency: 150MHz: 1.2GBit */
400 if (xtal == HWTRAP_XTAL_40MHZ)
402 if (xtal == HWTRAP_XTAL_25MHZ)
404 } else { /* PLL frequency: 250MHz: 2.0Gbit */
405 if (xtal == HWTRAP_XTAL_40MHZ)
407 if (xtal == HWTRAP_XTAL_25MHZ)
412 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
416 if (xtal == HWTRAP_XTAL_25MHZ)
421 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
422 P6_INTF_MODE(trgint));
424 /* Lower Tx Driving for TRGMII path */
425 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
426 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
427 TD_DM_DRVP(8) | TD_DM_DRVN(8));
429 /* Setup core clock for MT7530 */
431 /* Disable MT7530 core clock */
432 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
434 /* Disable PLL, since phy_device has not yet been created
435 * provided for phy_[read,write]_mmd_indirect is called, we
436 * provide our own core_write_mmd_indirect to complete this
439 core_write_mmd_indirect(priv,
444 /* Set core clock into 500Mhz */
445 core_write(priv, CORE_GSWPLL_GRP2,
446 RG_GSWPLL_POSDIV_500M(1) |
447 RG_GSWPLL_FBKDIV_500M(25));
450 core_write(priv, CORE_GSWPLL_GRP1,
452 RG_GSWPLL_POSDIV_200M(2) |
453 RG_GSWPLL_FBKDIV_200M(32));
455 /* Enable MT7530 core clock */
456 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
459 /* Setup the MT7530 TRGMII Tx Clock */
460 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
461 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
462 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
463 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
464 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
465 core_write(priv, CORE_PLL_GROUP4,
466 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
467 RG_SYSPLL_BIAS_LPF_EN);
468 core_write(priv, CORE_PLL_GROUP2,
469 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
470 RG_SYSPLL_POSDIV(1));
471 core_write(priv, CORE_PLL_GROUP7,
472 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
473 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
474 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
475 REG_GSWCK_EN | REG_TRGMIICK_EN);
478 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
479 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
480 RD_TAP_MASK, RD_TAP(16));
485 mt7530_mib_reset(struct dsa_switch *ds)
487 struct mt7530_priv *priv = ds->priv;
489 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
490 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
493 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
495 struct mt7530_priv *priv = ds->priv;
497 return mdiobus_read_nested(priv->bus, port, regnum);
500 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
503 struct mt7530_priv *priv = ds->priv;
505 return mdiobus_write_nested(priv->bus, port, regnum, val);
509 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
514 if (stringset != ETH_SS_STATS)
517 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
518 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
523 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
526 struct mt7530_priv *priv = ds->priv;
527 const struct mt7530_mib_desc *mib;
531 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
532 mib = &mt7530_mib[i];
533 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
535 data[i] = mt7530_read(priv, reg);
536 if (mib->size == 2) {
537 hi = mt7530_read(priv, reg + 4);
544 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
546 if (sset != ETH_SS_STATS)
549 return ARRAY_SIZE(mt7530_mib);
552 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
554 struct mt7530_priv *priv = ds->priv;
558 mutex_lock(&priv->reg_mutex);
560 val = mt7530_read(priv, MT7530_MHWTRAP);
562 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
563 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
565 switch (priv->p5_intf_sel) {
566 case P5_INTF_SEL_PHY_P0:
567 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
568 val |= MHWTRAP_PHY0_SEL;
570 case P5_INTF_SEL_PHY_P4:
571 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
572 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
574 /* Setup the MAC by default for the cpu port */
575 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
577 case P5_INTF_SEL_GMAC5:
578 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
579 val &= ~MHWTRAP_P5_DIS;
582 interface = PHY_INTERFACE_MODE_NA;
585 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
590 /* Setup RGMII settings */
591 if (phy_interface_mode_is_rgmii(interface)) {
592 val |= MHWTRAP_P5_RGMII_MODE;
594 /* P5 RGMII RX Clock Control: delay setting for 1000M */
595 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
597 /* Don't set delay in DSA mode */
598 if (!dsa_is_dsa_port(priv->ds, 5) &&
599 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
600 interface == PHY_INTERFACE_MODE_RGMII_ID))
601 tx_delay = 4; /* n * 0.5 ns */
603 /* P5 RGMII TX Clock Control: delay x */
604 mt7530_write(priv, MT7530_P5RGMIITXCR,
605 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
607 /* reduce P5 RGMII Tx driving, 8mA */
608 mt7530_write(priv, MT7530_IO_DRV_CR,
609 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
612 mt7530_write(priv, MT7530_MHWTRAP, val);
614 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
615 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
617 priv->p5_interface = interface;
620 mutex_unlock(&priv->reg_mutex);
624 mt7530_cpu_port_enable(struct mt7530_priv *priv,
627 /* Enable Mediatek header mode on the cpu port */
628 mt7530_write(priv, MT7530_PVC_P(port),
631 /* Unknown multicast frame forwarding to the cpu port */
632 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
634 /* Set CPU port number */
635 if (priv->id == ID_MT7621)
636 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
638 /* CPU port gets connected to all user ports of
641 mt7530_write(priv, MT7530_PCR_P(port),
642 PCR_MATRIX(dsa_user_ports(priv->ds)));
648 mt7530_port_enable(struct dsa_switch *ds, int port,
649 struct phy_device *phy)
651 struct mt7530_priv *priv = ds->priv;
653 if (!dsa_is_user_port(ds, port))
656 mutex_lock(&priv->reg_mutex);
658 /* Allow the user port gets connected to the cpu port and also
659 * restore the port matrix if the port is the member of a certain
662 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
663 priv->ports[port].enable = true;
664 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
665 priv->ports[port].pm);
666 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
668 mutex_unlock(&priv->reg_mutex);
674 mt7530_port_disable(struct dsa_switch *ds, int port)
676 struct mt7530_priv *priv = ds->priv;
678 if (!dsa_is_user_port(ds, port))
681 mutex_lock(&priv->reg_mutex);
683 /* Clear up all port matrix which could be restored in the next
684 * enablement for the port.
686 priv->ports[port].enable = false;
687 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
689 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
691 mutex_unlock(&priv->reg_mutex);
695 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
697 struct mt7530_priv *priv = ds->priv;
701 case BR_STATE_DISABLED:
702 stp_state = MT7530_STP_DISABLED;
704 case BR_STATE_BLOCKING:
705 stp_state = MT7530_STP_BLOCKING;
707 case BR_STATE_LISTENING:
708 stp_state = MT7530_STP_LISTENING;
710 case BR_STATE_LEARNING:
711 stp_state = MT7530_STP_LEARNING;
713 case BR_STATE_FORWARDING:
715 stp_state = MT7530_STP_FORWARDING;
719 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
723 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
724 struct net_device *bridge)
726 struct mt7530_priv *priv = ds->priv;
727 u32 port_bitmap = BIT(MT7530_CPU_PORT);
730 mutex_lock(&priv->reg_mutex);
732 for (i = 0; i < MT7530_NUM_PORTS; i++) {
733 /* Add this port to the port matrix of the other ports in the
734 * same bridge. If the port is disabled, port matrix is kept
735 * and not being setup until the port becomes enabled.
737 if (dsa_is_user_port(ds, i) && i != port) {
738 if (dsa_to_port(ds, i)->bridge_dev != bridge)
740 if (priv->ports[i].enable)
741 mt7530_set(priv, MT7530_PCR_P(i),
742 PCR_MATRIX(BIT(port)));
743 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
745 port_bitmap |= BIT(i);
749 /* Add the all other ports to this port matrix. */
750 if (priv->ports[port].enable)
751 mt7530_rmw(priv, MT7530_PCR_P(port),
752 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
753 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
755 mutex_unlock(&priv->reg_mutex);
761 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
763 struct mt7530_priv *priv = ds->priv;
764 bool all_user_ports_removed = true;
767 /* When a port is removed from the bridge, the port would be set up
768 * back to the default as is at initial boot which is a VLAN-unaware
771 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
772 MT7530_PORT_MATRIX_MODE);
773 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
774 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
775 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
777 for (i = 0; i < MT7530_NUM_PORTS; i++) {
778 if (dsa_is_user_port(ds, i) &&
779 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
780 all_user_ports_removed = false;
785 /* CPU port also does the same thing until all user ports belonging to
786 * the CPU port get out of VLAN filtering mode.
788 if (all_user_ports_removed) {
789 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
790 PCR_MATRIX(dsa_user_ports(priv->ds)));
791 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
792 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
797 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
799 struct mt7530_priv *priv = ds->priv;
801 /* The real fabric path would be decided on the membership in the
802 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
803 * means potential VLAN can be consisting of certain subset of all
806 mt7530_rmw(priv, MT7530_PCR_P(port),
807 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
809 /* Trapped into security mode allows packet forwarding through VLAN
810 * table lookup. CPU port is set to fallback mode to let untagged
811 * frames pass through.
813 if (dsa_is_cpu_port(ds, port))
814 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
815 MT7530_PORT_FALLBACK_MODE);
817 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
818 MT7530_PORT_SECURITY_MODE);
820 /* Set the port as a user port which is to be able to recognize VID
821 * from incoming packets before fetching entry within the VLAN table.
823 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
824 VLAN_ATTR(MT7530_VLAN_USER) |
825 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
829 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
830 struct net_device *bridge)
832 struct mt7530_priv *priv = ds->priv;
835 mutex_lock(&priv->reg_mutex);
837 for (i = 0; i < MT7530_NUM_PORTS; i++) {
838 /* Remove this port from the port matrix of the other ports
839 * in the same bridge. If the port is disabled, port matrix
840 * is kept and not being setup until the port becomes enabled.
841 * And the other port's port matrix cannot be broken when the
842 * other port is still a VLAN-aware port.
844 if (dsa_is_user_port(ds, i) && i != port &&
845 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
846 if (dsa_to_port(ds, i)->bridge_dev != bridge)
848 if (priv->ports[i].enable)
849 mt7530_clear(priv, MT7530_PCR_P(i),
850 PCR_MATRIX(BIT(port)));
851 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
855 /* Set the cpu port to be the only one in the port matrix of
858 if (priv->ports[port].enable)
859 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
860 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
861 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
863 mutex_unlock(&priv->reg_mutex);
867 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
868 const unsigned char *addr, u16 vid)
870 struct mt7530_priv *priv = ds->priv;
872 u8 port_mask = BIT(port);
874 mutex_lock(&priv->reg_mutex);
875 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
876 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
877 mutex_unlock(&priv->reg_mutex);
883 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
884 const unsigned char *addr, u16 vid)
886 struct mt7530_priv *priv = ds->priv;
888 u8 port_mask = BIT(port);
890 mutex_lock(&priv->reg_mutex);
891 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
892 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
893 mutex_unlock(&priv->reg_mutex);
899 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
900 dsa_fdb_dump_cb_t *cb, void *data)
902 struct mt7530_priv *priv = ds->priv;
903 struct mt7530_fdb _fdb = { 0 };
904 int cnt = MT7530_NUM_FDB_RECORDS;
908 mutex_lock(&priv->reg_mutex);
910 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
915 if (rsp & ATC_SRCH_HIT) {
916 mt7530_fdb_read(priv, &_fdb);
917 if (_fdb.port_mask & BIT(port)) {
918 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
925 !(rsp & ATC_SRCH_END) &&
926 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
928 mutex_unlock(&priv->reg_mutex);
934 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
936 struct mt7530_dummy_poll p;
940 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
941 mt7530_write(priv, MT7530_VTCR, val);
943 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
944 ret = readx_poll_timeout(_mt7530_read, &p, val,
945 !(val & VTCR_BUSY), 20, 20000);
947 dev_err(priv->dev, "poll timeout\n");
951 val = mt7530_read(priv, MT7530_VTCR);
952 if (val & VTCR_INVALID) {
953 dev_err(priv->dev, "read VTCR invalid\n");
961 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
964 if (vlan_filtering) {
965 /* The port is being kept as VLAN-unaware port when bridge is
966 * set up with vlan_filtering not being set, Otherwise, the
967 * port and the corresponding CPU port is required the setup
968 * for becoming a VLAN-aware port.
970 mt7530_port_set_vlan_aware(ds, port);
971 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
973 mt7530_port_set_vlan_unaware(ds, port);
980 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
981 const struct switchdev_obj_port_vlan *vlan)
989 mt7530_hw_vlan_add(struct mt7530_priv *priv,
990 struct mt7530_hw_vlan_entry *entry)
995 new_members = entry->old_members | BIT(entry->port) |
996 BIT(MT7530_CPU_PORT);
998 /* Validate the entry with independent learning, create egress tag per
999 * VLAN and joining the port as one of the port members.
1001 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1002 mt7530_write(priv, MT7530_VAWD1, val);
1004 /* Decide whether adding tag or not for those outgoing packets from the
1005 * port inside the VLAN.
1007 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1008 MT7530_VLAN_EGRESS_TAG;
1009 mt7530_rmw(priv, MT7530_VAWD2,
1010 ETAG_CTRL_P_MASK(entry->port),
1011 ETAG_CTRL_P(entry->port, val));
1013 /* CPU port is always taken as a tagged port for serving more than one
1014 * VLANs across and also being applied with egress type stack mode for
1015 * that VLAN tags would be appended after hardware special tag used as
1018 mt7530_rmw(priv, MT7530_VAWD2,
1019 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1020 ETAG_CTRL_P(MT7530_CPU_PORT,
1021 MT7530_VLAN_EGRESS_STACK));
1025 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1026 struct mt7530_hw_vlan_entry *entry)
1031 new_members = entry->old_members & ~BIT(entry->port);
1033 val = mt7530_read(priv, MT7530_VAWD1);
1034 if (!(val & VLAN_VALID)) {
1036 "Cannot be deleted due to invalid entry\n");
1040 /* If certain member apart from CPU port is still alive in the VLAN,
1041 * the entry would be kept valid. Otherwise, the entry is got to be
1044 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1045 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1047 mt7530_write(priv, MT7530_VAWD1, val);
1049 mt7530_write(priv, MT7530_VAWD1, 0);
1050 mt7530_write(priv, MT7530_VAWD2, 0);
1055 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1056 struct mt7530_hw_vlan_entry *entry,
1057 mt7530_vlan_op vlan_op)
1062 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1064 val = mt7530_read(priv, MT7530_VAWD1);
1066 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1068 /* Manipulate entry */
1069 vlan_op(priv, entry);
1071 /* Flush result to hardware */
1072 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1076 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1077 const struct switchdev_obj_port_vlan *vlan)
1079 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1080 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1081 struct mt7530_hw_vlan_entry new_entry;
1082 struct mt7530_priv *priv = ds->priv;
1085 mutex_lock(&priv->reg_mutex);
1087 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1088 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1089 mt7530_hw_vlan_update(priv, vid, &new_entry,
1090 mt7530_hw_vlan_add);
1094 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1095 G0_PORT_VID(vlan->vid_end));
1096 priv->ports[port].pvid = vlan->vid_end;
1099 mutex_unlock(&priv->reg_mutex);
1103 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1104 const struct switchdev_obj_port_vlan *vlan)
1106 struct mt7530_hw_vlan_entry target_entry;
1107 struct mt7530_priv *priv = ds->priv;
1110 mutex_lock(&priv->reg_mutex);
1112 pvid = priv->ports[port].pvid;
1113 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1114 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1115 mt7530_hw_vlan_update(priv, vid, &target_entry,
1116 mt7530_hw_vlan_del);
1118 /* PVID is being restored to the default whenever the PVID port
1119 * is being removed from the VLAN.
1122 pvid = G0_PORT_VID_DEF;
1125 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1126 priv->ports[port].pvid = pvid;
1128 mutex_unlock(&priv->reg_mutex);
1133 static int mt7530_port_mirror_add(struct dsa_switch *ds, int port,
1134 struct dsa_mall_mirror_tc_entry *mirror,
1137 struct mt7530_priv *priv = ds->priv;
1140 /* Check for existent entry */
1141 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1144 val = mt7530_read(priv, MT7530_MFC);
1146 /* MT7530 only supports one monitor port */
1147 if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port)
1151 val &= ~MIRROR_MASK;
1152 val |= mirror->to_local_port;
1153 mt7530_write(priv, MT7530_MFC, val);
1155 val = mt7530_read(priv, MT7530_PCR_P(port));
1158 priv->mirror_rx |= BIT(port);
1161 priv->mirror_tx |= BIT(port);
1163 mt7530_write(priv, MT7530_PCR_P(port), val);
1168 static void mt7530_port_mirror_del(struct dsa_switch *ds, int port,
1169 struct dsa_mall_mirror_tc_entry *mirror)
1171 struct mt7530_priv *priv = ds->priv;
1174 val = mt7530_read(priv, MT7530_PCR_P(port));
1175 if (mirror->ingress) {
1176 val &= ~PORT_RX_MIR;
1177 priv->mirror_rx &= ~BIT(port);
1179 val &= ~PORT_TX_MIR;
1180 priv->mirror_tx &= ~BIT(port);
1182 mt7530_write(priv, MT7530_PCR_P(port), val);
1184 if (!priv->mirror_rx && !priv->mirror_tx) {
1185 val = mt7530_read(priv, MT7530_MFC);
1187 mt7530_write(priv, MT7530_MFC, val);
1191 static enum dsa_tag_protocol
1192 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1193 enum dsa_tag_protocol mp)
1195 struct mt7530_priv *priv = ds->priv;
1197 if (port != MT7530_CPU_PORT) {
1199 "port not matched with tagging CPU port\n");
1200 return DSA_TAG_PROTO_NONE;
1202 return DSA_TAG_PROTO_MTK;
1207 mt7530_setup(struct dsa_switch *ds)
1209 struct mt7530_priv *priv = ds->priv;
1210 struct device_node *phy_node;
1211 struct device_node *mac_np;
1212 struct mt7530_dummy_poll p;
1213 phy_interface_t interface;
1214 struct device_node *dn;
1218 /* The parent node of master netdev which holds the common system
1219 * controller also is the container for two GMACs nodes representing
1220 * as two netdev instances.
1222 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
1223 ds->configure_vlan_while_not_filtering = true;
1225 if (priv->id == ID_MT7530) {
1226 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1227 ret = regulator_enable(priv->core_pwr);
1230 "Failed to enable core power: %d\n", ret);
1234 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1235 ret = regulator_enable(priv->io_pwr);
1237 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1243 /* Reset whole chip through gpio pin or memory-mapped registers for
1244 * different type of hardware
1247 reset_control_assert(priv->rstc);
1248 usleep_range(1000, 1100);
1249 reset_control_deassert(priv->rstc);
1251 gpiod_set_value_cansleep(priv->reset, 0);
1252 usleep_range(1000, 1100);
1253 gpiod_set_value_cansleep(priv->reset, 1);
1256 /* Waiting for MT7530 got to stable */
1257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1258 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1261 dev_err(priv->dev, "reset timeout\n");
1265 id = mt7530_read(priv, MT7530_CREV);
1266 id >>= CHIP_NAME_SHIFT;
1267 if (id != MT7530_ID) {
1268 dev_err(priv->dev, "chip %x can't be supported\n", id);
1272 /* Reset the switch through internal reset */
1273 mt7530_write(priv, MT7530_SYS_CTRL,
1274 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1277 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1278 val = mt7530_read(priv, MT7530_MHWTRAP);
1279 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1280 val |= MHWTRAP_MANUAL;
1281 mt7530_write(priv, MT7530_MHWTRAP, val);
1283 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1285 /* Enable and reset MIB counters */
1286 mt7530_mib_reset(ds);
1288 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1289 /* Disable forwarding by default on all ports */
1290 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1293 if (dsa_is_cpu_port(ds, i))
1294 mt7530_cpu_port_enable(priv, i);
1296 mt7530_port_disable(ds, i);
1298 /* Enable consistent egress tag */
1299 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1300 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1304 priv->p5_intf_sel = P5_DISABLED;
1305 interface = PHY_INTERFACE_MODE_NA;
1307 if (!dsa_is_unused_port(ds, 5)) {
1308 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1309 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1310 if (ret && ret != -ENODEV)
1313 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1314 for_each_child_of_node(dn, mac_np) {
1315 if (!of_device_is_compatible(mac_np,
1316 "mediatek,eth-mac"))
1319 ret = of_property_read_u32(mac_np, "reg", &id);
1320 if (ret < 0 || id != 1)
1323 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1327 if (phy_node->parent == priv->dev->of_node->parent) {
1328 ret = of_get_phy_mode(mac_np, &interface);
1329 if (ret && ret != -ENODEV)
1331 id = of_mdio_parse_addr(ds->dev, phy_node);
1333 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1335 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1337 of_node_put(phy_node);
1342 mt7530_setup_port5(ds, interface);
1344 /* Flush the FDB table */
1345 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1352 static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
1354 const struct phylink_link_state *state)
1356 struct mt7530_priv *priv = ds->priv;
1357 u32 mcr_cur, mcr_new;
1360 case 0: /* Internal phy */
1365 if (state->interface != PHY_INTERFACE_MODE_GMII)
1368 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1369 if (priv->p5_interface == state->interface)
1371 if (!phy_interface_mode_is_rgmii(state->interface) &&
1372 state->interface != PHY_INTERFACE_MODE_MII &&
1373 state->interface != PHY_INTERFACE_MODE_GMII)
1376 mt7530_setup_port5(ds, state->interface);
1378 case 6: /* 1st cpu port */
1379 if (priv->p6_interface == state->interface)
1382 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1383 state->interface != PHY_INTERFACE_MODE_TRGMII)
1386 /* Setup TX circuit incluing relevant PAD and driving */
1387 mt7530_pad_clk_setup(ds, state->interface);
1389 priv->p6_interface = state->interface;
1392 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1396 if (phylink_autoneg_inband(mode)) {
1397 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1402 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
1404 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
1405 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
1406 PMCR_BACKPR_EN | PMCR_FORCE_MODE;
1408 /* Are we connected to external phy */
1409 if (port == 5 && dsa_is_user_port(ds, 5))
1410 mcr_new |= PMCR_EXT_PHY;
1412 if (mcr_new != mcr_cur)
1413 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
1416 static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
1418 phy_interface_t interface)
1420 struct mt7530_priv *priv = ds->priv;
1422 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1425 static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
1427 phy_interface_t interface,
1428 struct phy_device *phydev,
1429 int speed, int duplex,
1430 bool tx_pause, bool rx_pause)
1432 struct mt7530_priv *priv = ds->priv;
1435 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
1439 mcr |= PMCR_FORCE_SPEED_1000;
1442 mcr |= PMCR_FORCE_SPEED_100;
1445 if (duplex == DUPLEX_FULL) {
1446 mcr |= PMCR_FORCE_FDX;
1448 mcr |= PMCR_TX_FC_EN;
1450 mcr |= PMCR_RX_FC_EN;
1453 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
1456 static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
1457 unsigned long *supported,
1458 struct phylink_link_state *state)
1460 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1463 case 0: /* Internal phy */
1468 if (state->interface != PHY_INTERFACE_MODE_NA &&
1469 state->interface != PHY_INTERFACE_MODE_GMII)
1472 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1473 if (state->interface != PHY_INTERFACE_MODE_NA &&
1474 !phy_interface_mode_is_rgmii(state->interface) &&
1475 state->interface != PHY_INTERFACE_MODE_MII &&
1476 state->interface != PHY_INTERFACE_MODE_GMII)
1479 case 6: /* 1st cpu port */
1480 if (state->interface != PHY_INTERFACE_MODE_NA &&
1481 state->interface != PHY_INTERFACE_MODE_RGMII &&
1482 state->interface != PHY_INTERFACE_MODE_TRGMII)
1486 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1488 linkmode_zero(supported);
1492 phylink_set_port_modes(mask);
1493 phylink_set(mask, Autoneg);
1495 if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
1496 phylink_set(mask, 1000baseT_Full);
1498 phylink_set(mask, 10baseT_Half);
1499 phylink_set(mask, 10baseT_Full);
1500 phylink_set(mask, 100baseT_Half);
1501 phylink_set(mask, 100baseT_Full);
1503 if (state->interface != PHY_INTERFACE_MODE_MII) {
1504 phylink_set(mask, 1000baseT_Half);
1505 phylink_set(mask, 1000baseT_Full);
1507 phylink_set(mask, 1000baseX_Full);
1511 phylink_set(mask, Pause);
1512 phylink_set(mask, Asym_Pause);
1514 linkmode_and(supported, supported, mask);
1515 linkmode_and(state->advertising, state->advertising, mask);
1519 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
1520 struct phylink_link_state *state)
1522 struct mt7530_priv *priv = ds->priv;
1525 if (port < 0 || port >= MT7530_NUM_PORTS)
1528 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
1530 state->link = (pmsr & PMSR_LINK);
1531 state->an_complete = state->link;
1532 state->duplex = !!(pmsr & PMSR_DPX);
1534 switch (pmsr & PMSR_SPEED_MASK) {
1536 state->speed = SPEED_10;
1538 case PMSR_SPEED_100:
1539 state->speed = SPEED_100;
1541 case PMSR_SPEED_1000:
1542 state->speed = SPEED_1000;
1545 state->speed = SPEED_UNKNOWN;
1549 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
1550 if (pmsr & PMSR_RX_FC)
1551 state->pause |= MLO_PAUSE_RX;
1552 if (pmsr & PMSR_TX_FC)
1553 state->pause |= MLO_PAUSE_TX;
1558 static const struct dsa_switch_ops mt7530_switch_ops = {
1559 .get_tag_protocol = mtk_get_tag_protocol,
1560 .setup = mt7530_setup,
1561 .get_strings = mt7530_get_strings,
1562 .phy_read = mt7530_phy_read,
1563 .phy_write = mt7530_phy_write,
1564 .get_ethtool_stats = mt7530_get_ethtool_stats,
1565 .get_sset_count = mt7530_get_sset_count,
1566 .port_enable = mt7530_port_enable,
1567 .port_disable = mt7530_port_disable,
1568 .port_stp_state_set = mt7530_stp_state_set,
1569 .port_bridge_join = mt7530_port_bridge_join,
1570 .port_bridge_leave = mt7530_port_bridge_leave,
1571 .port_fdb_add = mt7530_port_fdb_add,
1572 .port_fdb_del = mt7530_port_fdb_del,
1573 .port_fdb_dump = mt7530_port_fdb_dump,
1574 .port_vlan_filtering = mt7530_port_vlan_filtering,
1575 .port_vlan_prepare = mt7530_port_vlan_prepare,
1576 .port_vlan_add = mt7530_port_vlan_add,
1577 .port_vlan_del = mt7530_port_vlan_del,
1578 .port_mirror_add = mt7530_port_mirror_add,
1579 .port_mirror_del = mt7530_port_mirror_del,
1580 .phylink_validate = mt7530_phylink_validate,
1581 .phylink_mac_link_state = mt7530_phylink_mac_link_state,
1582 .phylink_mac_config = mt7530_phylink_mac_config,
1583 .phylink_mac_link_down = mt7530_phylink_mac_link_down,
1584 .phylink_mac_link_up = mt7530_phylink_mac_link_up,
1587 static const struct of_device_id mt7530_of_match[] = {
1588 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1589 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1592 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1595 mt7530_probe(struct mdio_device *mdiodev)
1597 struct mt7530_priv *priv;
1598 struct device_node *dn;
1600 dn = mdiodev->dev.of_node;
1602 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1606 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1610 priv->ds->dev = &mdiodev->dev;
1611 priv->ds->num_ports = DSA_MAX_PORTS;
1613 /* Use medatek,mcm property to distinguish hardware type that would
1614 * casues a little bit differences on power-on sequence.
1616 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1618 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1620 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1621 if (IS_ERR(priv->rstc)) {
1622 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1623 return PTR_ERR(priv->rstc);
1627 /* Get the hardware identifier from the devicetree node.
1628 * We will need it for some of the clock and regulator setup.
1630 priv->id = (unsigned int)(unsigned long)
1631 of_device_get_match_data(&mdiodev->dev);
1633 if (priv->id == ID_MT7530) {
1634 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1635 if (IS_ERR(priv->core_pwr))
1636 return PTR_ERR(priv->core_pwr);
1638 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1639 if (IS_ERR(priv->io_pwr))
1640 return PTR_ERR(priv->io_pwr);
1643 /* Not MCM that indicates switch works as the remote standalone
1644 * integrated circuit so the GPIO pin would be used to complete
1645 * the reset, otherwise memory-mapped register accessing used
1646 * through syscon provides in the case of MCM.
1649 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1651 if (IS_ERR(priv->reset)) {
1652 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1653 return PTR_ERR(priv->reset);
1657 priv->bus = mdiodev->bus;
1658 priv->dev = &mdiodev->dev;
1659 priv->ds->priv = priv;
1660 priv->ds->ops = &mt7530_switch_ops;
1661 mutex_init(&priv->reg_mutex);
1662 dev_set_drvdata(&mdiodev->dev, priv);
1664 return dsa_register_switch(priv->ds);
1668 mt7530_remove(struct mdio_device *mdiodev)
1670 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1673 ret = regulator_disable(priv->core_pwr);
1676 "Failed to disable core power: %d\n", ret);
1678 ret = regulator_disable(priv->io_pwr);
1680 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1683 dsa_unregister_switch(priv->ds);
1684 mutex_destroy(&priv->reg_mutex);
1687 static struct mdio_driver mt7530_mdio_driver = {
1688 .probe = mt7530_probe,
1689 .remove = mt7530_remove,
1692 .of_match_table = mt7530_of_match,
1696 mdio_module_driver(mt7530_mdio_driver);
1698 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1699 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1700 MODULE_LICENSE("GPL");