1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_mdio.h>
14 #include <linux/of_net.h>
15 #include <linux/of_platform.h>
16 #include <linux/phylink.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/gpio/consumer.h>
25 /* String, offset, and register size in bytes if different from 4 bytes */
26 static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
70 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
74 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
77 "failed to priv write register\n");
82 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
87 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
90 "failed to priv read register\n");
98 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
103 val = mt7623_trgmii_read(priv, reg);
106 mt7623_trgmii_write(priv, reg, val);
110 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
112 mt7623_trgmii_rmw(priv, reg, 0, val);
116 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
118 mt7623_trgmii_rmw(priv, reg, val, 0);
122 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
124 struct mii_bus *bus = priv->bus;
127 /* Write the desired MMD Devad */
128 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
132 /* Write the desired MMD register address */
133 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
137 /* Select the Function : DATA with no post increment */
138 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
142 /* Read the content of the MMD's selected register */
143 value = bus->read(bus, 0, MII_MMD_DATA);
147 dev_err(&bus->dev, "failed to read mmd register\n");
153 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
156 struct mii_bus *bus = priv->bus;
159 /* Write the desired MMD Devad */
160 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
164 /* Write the desired MMD register address */
165 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
169 /* Select the Function : DATA with no post increment */
170 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
174 /* Write the data into MMD's selected register */
175 ret = bus->write(bus, 0, MII_MMD_DATA, data);
179 "failed to write mmd register\n");
184 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
186 struct mii_bus *bus = priv->bus;
188 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
190 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
192 mutex_unlock(&bus->mdio_lock);
196 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
198 struct mii_bus *bus = priv->bus;
201 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
203 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
206 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
208 mutex_unlock(&bus->mdio_lock);
212 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
214 core_rmw(priv, reg, 0, val);
218 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
220 core_rmw(priv, reg, val, 0);
224 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
226 struct mii_bus *bus = priv->bus;
230 page = (reg >> 6) & 0x3ff;
231 r = (reg >> 2) & 0xf;
235 /* MT7530 uses 31 as the pseudo port */
236 ret = bus->write(bus, 0x1f, 0x1f, page);
240 ret = bus->write(bus, 0x1f, r, lo);
244 ret = bus->write(bus, 0x1f, 0x10, hi);
248 "failed to write mt7530 register\n");
253 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
255 struct mii_bus *bus = priv->bus;
259 page = (reg >> 6) & 0x3ff;
260 r = (reg >> 2) & 0xf;
262 /* MT7530 uses 31 as the pseudo port */
263 ret = bus->write(bus, 0x1f, 0x1f, page);
266 "failed to read mt7530 register\n");
270 lo = bus->read(bus, 0x1f, r);
271 hi = bus->read(bus, 0x1f, 0x10);
273 return (hi << 16) | (lo & 0xffff);
277 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
279 struct mii_bus *bus = priv->bus;
281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
283 mt7530_mii_write(priv, reg, val);
285 mutex_unlock(&bus->mdio_lock);
289 _mt7530_read(struct mt7530_dummy_poll *p)
291 struct mii_bus *bus = p->priv->bus;
294 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
296 val = mt7530_mii_read(p->priv, p->reg);
298 mutex_unlock(&bus->mdio_lock);
304 mt7530_read(struct mt7530_priv *priv, u32 reg)
306 struct mt7530_dummy_poll p;
308 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
309 return _mt7530_read(&p);
313 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
316 struct mii_bus *bus = priv->bus;
319 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
321 val = mt7530_mii_read(priv, reg);
324 mt7530_mii_write(priv, reg, val);
326 mutex_unlock(&bus->mdio_lock);
330 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
332 mt7530_rmw(priv, reg, 0, val);
336 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
338 mt7530_rmw(priv, reg, val, 0);
342 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
346 struct mt7530_dummy_poll p;
348 /* Set the command operating upon the MAC address entries */
349 val = ATC_BUSY | ATC_MAT(0) | cmd;
350 mt7530_write(priv, MT7530_ATC, val);
352 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
353 ret = readx_poll_timeout(_mt7530_read, &p, val,
354 !(val & ATC_BUSY), 20, 20000);
356 dev_err(priv->dev, "reset timeout\n");
360 /* Additional sanity for read command if the specified
363 val = mt7530_read(priv, MT7530_ATC);
364 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
374 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
379 /* Read from ARL table into an array */
380 for (i = 0; i < 3; i++) {
381 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
383 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
384 __func__, __LINE__, i, reg[i]);
387 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
388 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
389 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
390 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
391 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
392 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
393 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
394 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
395 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
396 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
400 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
401 u8 port_mask, const u8 *mac,
407 reg[1] |= vid & CVID_MASK;
408 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
409 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
410 /* STATIC_ENT indicate that entry is static wouldn't
411 * be aged out and STATIC_EMP specified as erasing an
414 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
415 reg[1] |= mac[5] << MAC_BYTE_5;
416 reg[1] |= mac[4] << MAC_BYTE_4;
417 reg[0] |= mac[3] << MAC_BYTE_3;
418 reg[0] |= mac[2] << MAC_BYTE_2;
419 reg[0] |= mac[1] << MAC_BYTE_1;
420 reg[0] |= mac[0] << MAC_BYTE_0;
422 /* Write array into the ARL table */
423 for (i = 0; i < 3; i++)
424 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
428 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
430 struct mt7530_priv *priv = ds->priv;
431 u32 ncpo1, ssc_delta, trgint, i, xtal;
433 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
435 if (xtal == HWTRAP_XTAL_20MHZ) {
437 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
443 case PHY_INTERFACE_MODE_RGMII:
445 /* PLL frequency: 125MHz */
448 case PHY_INTERFACE_MODE_TRGMII:
450 if (priv->id == ID_MT7621) {
451 /* PLL frequency: 150MHz: 1.2GBit */
452 if (xtal == HWTRAP_XTAL_40MHZ)
454 if (xtal == HWTRAP_XTAL_25MHZ)
456 } else { /* PLL frequency: 250MHz: 2.0Gbit */
457 if (xtal == HWTRAP_XTAL_40MHZ)
459 if (xtal == HWTRAP_XTAL_25MHZ)
464 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
468 if (xtal == HWTRAP_XTAL_25MHZ)
473 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
474 P6_INTF_MODE(trgint));
476 /* Lower Tx Driving for TRGMII path */
477 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
478 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
479 TD_DM_DRVP(8) | TD_DM_DRVN(8));
481 /* Setup core clock for MT7530 */
483 /* Disable MT7530 core clock */
484 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
486 /* Disable PLL, since phy_device has not yet been created
487 * provided for phy_[read,write]_mmd_indirect is called, we
488 * provide our own core_write_mmd_indirect to complete this
491 core_write_mmd_indirect(priv,
496 /* Set core clock into 500Mhz */
497 core_write(priv, CORE_GSWPLL_GRP2,
498 RG_GSWPLL_POSDIV_500M(1) |
499 RG_GSWPLL_FBKDIV_500M(25));
502 core_write(priv, CORE_GSWPLL_GRP1,
504 RG_GSWPLL_POSDIV_200M(2) |
505 RG_GSWPLL_FBKDIV_200M(32));
507 /* Enable MT7530 core clock */
508 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
511 /* Setup the MT7530 TRGMII Tx Clock */
512 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
513 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
514 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
515 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
516 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
517 core_write(priv, CORE_PLL_GROUP4,
518 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
519 RG_SYSPLL_BIAS_LPF_EN);
520 core_write(priv, CORE_PLL_GROUP2,
521 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
522 RG_SYSPLL_POSDIV(1));
523 core_write(priv, CORE_PLL_GROUP7,
524 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
525 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
526 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
527 REG_GSWCK_EN | REG_TRGMIICK_EN);
530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
531 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
532 RD_TAP_MASK, RD_TAP(16));
534 if (priv->id != ID_MT7621)
535 mt7623_trgmii_set(priv, GSW_INTF_MODE,
542 mt7623_pad_clk_setup(struct dsa_switch *ds)
544 struct mt7530_priv *priv = ds->priv;
547 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
548 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
549 TD_DM_DRVP(8) | TD_DM_DRVN(8));
551 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
552 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
558 mt7530_mib_reset(struct dsa_switch *ds)
560 struct mt7530_priv *priv = ds->priv;
562 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
563 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
567 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
569 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
572 mt7530_set(priv, MT7530_PMCR_P(port), mask);
574 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
577 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
579 struct mt7530_priv *priv = ds->priv;
581 return mdiobus_read_nested(priv->bus, port, regnum);
584 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
587 struct mt7530_priv *priv = ds->priv;
589 return mdiobus_write_nested(priv->bus, port, regnum, val);
593 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
598 if (stringset != ETH_SS_STATS)
601 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
602 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
607 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
610 struct mt7530_priv *priv = ds->priv;
611 const struct mt7530_mib_desc *mib;
615 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
616 mib = &mt7530_mib[i];
617 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
619 data[i] = mt7530_read(priv, reg);
620 if (mib->size == 2) {
621 hi = mt7530_read(priv, reg + 4);
628 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
630 if (sset != ETH_SS_STATS)
633 return ARRAY_SIZE(mt7530_mib);
636 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
638 struct mt7530_priv *priv = ds->priv;
642 mutex_lock(&priv->reg_mutex);
644 val = mt7530_read(priv, MT7530_MHWTRAP);
646 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
647 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
649 switch (priv->p5_intf_sel) {
650 case P5_INTF_SEL_PHY_P0:
651 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
652 val |= MHWTRAP_PHY0_SEL;
654 case P5_INTF_SEL_PHY_P4:
655 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
656 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
658 /* Setup the MAC by default for the cpu port */
659 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
661 case P5_INTF_SEL_GMAC5:
662 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
663 val &= ~MHWTRAP_P5_DIS;
666 interface = PHY_INTERFACE_MODE_NA;
669 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
674 /* Setup RGMII settings */
675 if (phy_interface_mode_is_rgmii(interface)) {
676 val |= MHWTRAP_P5_RGMII_MODE;
678 /* P5 RGMII RX Clock Control: delay setting for 1000M */
679 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
681 /* Don't set delay in DSA mode */
682 if (!dsa_is_dsa_port(priv->ds, 5) &&
683 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
684 interface == PHY_INTERFACE_MODE_RGMII_ID))
685 tx_delay = 4; /* n * 0.5 ns */
687 /* P5 RGMII TX Clock Control: delay x */
688 mt7530_write(priv, MT7530_P5RGMIITXCR,
689 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
691 /* reduce P5 RGMII Tx driving, 8mA */
692 mt7530_write(priv, MT7530_IO_DRV_CR,
693 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
696 mt7530_write(priv, MT7530_MHWTRAP, val);
698 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
699 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
701 priv->p5_interface = interface;
704 mutex_unlock(&priv->reg_mutex);
708 mt7530_cpu_port_enable(struct mt7530_priv *priv,
711 /* Enable Mediatek header mode on the cpu port */
712 mt7530_write(priv, MT7530_PVC_P(port),
715 /* Disable auto learning on the cpu port */
716 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
718 /* Unknown unicast frame fordwarding to the cpu port */
719 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
721 /* Set CPU port number */
722 if (priv->id == ID_MT7621)
723 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
725 /* CPU port gets connected to all user ports of
728 mt7530_write(priv, MT7530_PCR_P(port),
729 PCR_MATRIX(dsa_user_ports(priv->ds)));
735 mt7530_port_enable(struct dsa_switch *ds, int port,
736 struct phy_device *phy)
738 struct mt7530_priv *priv = ds->priv;
740 if (!dsa_is_user_port(ds, port))
743 mutex_lock(&priv->reg_mutex);
745 /* Allow the user port gets connected to the cpu port and also
746 * restore the port matrix if the port is the member of a certain
749 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
750 priv->ports[port].enable = true;
751 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
752 priv->ports[port].pm);
753 mt7530_port_set_status(priv, port, 0);
755 mutex_unlock(&priv->reg_mutex);
761 mt7530_port_disable(struct dsa_switch *ds, int port)
763 struct mt7530_priv *priv = ds->priv;
765 if (!dsa_is_user_port(ds, port))
768 mutex_lock(&priv->reg_mutex);
770 /* Clear up all port matrix which could be restored in the next
771 * enablement for the port.
773 priv->ports[port].enable = false;
774 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
776 mt7530_port_set_status(priv, port, 0);
778 mutex_unlock(&priv->reg_mutex);
782 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
784 struct mt7530_priv *priv = ds->priv;
788 case BR_STATE_DISABLED:
789 stp_state = MT7530_STP_DISABLED;
791 case BR_STATE_BLOCKING:
792 stp_state = MT7530_STP_BLOCKING;
794 case BR_STATE_LISTENING:
795 stp_state = MT7530_STP_LISTENING;
797 case BR_STATE_LEARNING:
798 stp_state = MT7530_STP_LEARNING;
800 case BR_STATE_FORWARDING:
802 stp_state = MT7530_STP_FORWARDING;
806 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
810 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
811 struct net_device *bridge)
813 struct mt7530_priv *priv = ds->priv;
814 u32 port_bitmap = BIT(MT7530_CPU_PORT);
817 mutex_lock(&priv->reg_mutex);
819 for (i = 0; i < MT7530_NUM_PORTS; i++) {
820 /* Add this port to the port matrix of the other ports in the
821 * same bridge. If the port is disabled, port matrix is kept
822 * and not being setup until the port becomes enabled.
824 if (dsa_is_user_port(ds, i) && i != port) {
825 if (dsa_to_port(ds, i)->bridge_dev != bridge)
827 if (priv->ports[i].enable)
828 mt7530_set(priv, MT7530_PCR_P(i),
829 PCR_MATRIX(BIT(port)));
830 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
832 port_bitmap |= BIT(i);
836 /* Add the all other ports to this port matrix. */
837 if (priv->ports[port].enable)
838 mt7530_rmw(priv, MT7530_PCR_P(port),
839 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
840 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
842 mutex_unlock(&priv->reg_mutex);
848 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
850 struct mt7530_priv *priv = ds->priv;
851 bool all_user_ports_removed = true;
854 /* When a port is removed from the bridge, the port would be set up
855 * back to the default as is at initial boot which is a VLAN-unaware
858 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
859 MT7530_PORT_MATRIX_MODE);
860 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
861 VLAN_ATTR(MT7530_VLAN_TRANSPARENT));
863 for (i = 0; i < MT7530_NUM_PORTS; i++) {
864 if (dsa_is_user_port(ds, i) &&
865 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
866 all_user_ports_removed = false;
871 /* CPU port also does the same thing until all user ports belonging to
872 * the CPU port get out of VLAN filtering mode.
874 if (all_user_ports_removed) {
875 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
876 PCR_MATRIX(dsa_user_ports(priv->ds)));
877 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT),
883 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
885 struct mt7530_priv *priv = ds->priv;
887 /* The real fabric path would be decided on the membership in the
888 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
889 * means potential VLAN can be consisting of certain subset of all
892 mt7530_rmw(priv, MT7530_PCR_P(port),
893 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
895 /* Trapped into security mode allows packet forwarding through VLAN
898 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
899 MT7530_PORT_SECURITY_MODE);
901 /* Set the port as a user port which is to be able to recognize VID
902 * from incoming packets before fetching entry within the VLAN table.
904 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
905 VLAN_ATTR(MT7530_VLAN_USER));
909 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
910 struct net_device *bridge)
912 struct mt7530_priv *priv = ds->priv;
915 mutex_lock(&priv->reg_mutex);
917 for (i = 0; i < MT7530_NUM_PORTS; i++) {
918 /* Remove this port from the port matrix of the other ports
919 * in the same bridge. If the port is disabled, port matrix
920 * is kept and not being setup until the port becomes enabled.
921 * And the other port's port matrix cannot be broken when the
922 * other port is still a VLAN-aware port.
924 if (dsa_is_user_port(ds, i) && i != port &&
925 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
926 if (dsa_to_port(ds, i)->bridge_dev != bridge)
928 if (priv->ports[i].enable)
929 mt7530_clear(priv, MT7530_PCR_P(i),
930 PCR_MATRIX(BIT(port)));
931 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
935 /* Set the cpu port to be the only one in the port matrix of
938 if (priv->ports[port].enable)
939 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
940 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
941 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
943 mutex_unlock(&priv->reg_mutex);
947 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
948 const unsigned char *addr, u16 vid)
950 struct mt7530_priv *priv = ds->priv;
952 u8 port_mask = BIT(port);
954 mutex_lock(&priv->reg_mutex);
955 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
956 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
957 mutex_unlock(&priv->reg_mutex);
963 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
964 const unsigned char *addr, u16 vid)
966 struct mt7530_priv *priv = ds->priv;
968 u8 port_mask = BIT(port);
970 mutex_lock(&priv->reg_mutex);
971 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
972 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
973 mutex_unlock(&priv->reg_mutex);
979 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
980 dsa_fdb_dump_cb_t *cb, void *data)
982 struct mt7530_priv *priv = ds->priv;
983 struct mt7530_fdb _fdb = { 0 };
984 int cnt = MT7530_NUM_FDB_RECORDS;
988 mutex_lock(&priv->reg_mutex);
990 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
995 if (rsp & ATC_SRCH_HIT) {
996 mt7530_fdb_read(priv, &_fdb);
997 if (_fdb.port_mask & BIT(port)) {
998 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1005 !(rsp & ATC_SRCH_END) &&
1006 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1008 mutex_unlock(&priv->reg_mutex);
1014 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1016 struct mt7530_dummy_poll p;
1020 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1021 mt7530_write(priv, MT7530_VTCR, val);
1023 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1024 ret = readx_poll_timeout(_mt7530_read, &p, val,
1025 !(val & VTCR_BUSY), 20, 20000);
1027 dev_err(priv->dev, "poll timeout\n");
1031 val = mt7530_read(priv, MT7530_VTCR);
1032 if (val & VTCR_INVALID) {
1033 dev_err(priv->dev, "read VTCR invalid\n");
1041 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1042 bool vlan_filtering)
1044 if (vlan_filtering) {
1045 /* The port is being kept as VLAN-unaware port when bridge is
1046 * set up with vlan_filtering not being set, Otherwise, the
1047 * port and the corresponding CPU port is required the setup
1048 * for becoming a VLAN-aware port.
1050 mt7530_port_set_vlan_aware(ds, port);
1051 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1053 mt7530_port_set_vlan_unaware(ds, port);
1060 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1061 const struct switchdev_obj_port_vlan *vlan)
1063 /* nothing needed */
1069 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1070 struct mt7530_hw_vlan_entry *entry)
1075 new_members = entry->old_members | BIT(entry->port) |
1076 BIT(MT7530_CPU_PORT);
1078 /* Validate the entry with independent learning, create egress tag per
1079 * VLAN and joining the port as one of the port members.
1081 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1082 mt7530_write(priv, MT7530_VAWD1, val);
1084 /* Decide whether adding tag or not for those outgoing packets from the
1085 * port inside the VLAN.
1087 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1088 MT7530_VLAN_EGRESS_TAG;
1089 mt7530_rmw(priv, MT7530_VAWD2,
1090 ETAG_CTRL_P_MASK(entry->port),
1091 ETAG_CTRL_P(entry->port, val));
1093 /* CPU port is always taken as a tagged port for serving more than one
1094 * VLANs across and also being applied with egress type stack mode for
1095 * that VLAN tags would be appended after hardware special tag used as
1098 mt7530_rmw(priv, MT7530_VAWD2,
1099 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1100 ETAG_CTRL_P(MT7530_CPU_PORT,
1101 MT7530_VLAN_EGRESS_STACK));
1105 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1106 struct mt7530_hw_vlan_entry *entry)
1111 new_members = entry->old_members & ~BIT(entry->port);
1113 val = mt7530_read(priv, MT7530_VAWD1);
1114 if (!(val & VLAN_VALID)) {
1116 "Cannot be deleted due to invalid entry\n");
1120 /* If certain member apart from CPU port is still alive in the VLAN,
1121 * the entry would be kept valid. Otherwise, the entry is got to be
1124 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1125 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1127 mt7530_write(priv, MT7530_VAWD1, val);
1129 mt7530_write(priv, MT7530_VAWD1, 0);
1130 mt7530_write(priv, MT7530_VAWD2, 0);
1135 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1136 struct mt7530_hw_vlan_entry *entry,
1137 mt7530_vlan_op vlan_op)
1142 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1144 val = mt7530_read(priv, MT7530_VAWD1);
1146 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1148 /* Manipulate entry */
1149 vlan_op(priv, entry);
1151 /* Flush result to hardware */
1152 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1156 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1157 const struct switchdev_obj_port_vlan *vlan)
1159 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1160 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1161 struct mt7530_hw_vlan_entry new_entry;
1162 struct mt7530_priv *priv = ds->priv;
1165 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1168 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1171 mutex_lock(&priv->reg_mutex);
1173 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1174 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1175 mt7530_hw_vlan_update(priv, vid, &new_entry,
1176 mt7530_hw_vlan_add);
1180 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1181 G0_PORT_VID(vlan->vid_end));
1182 priv->ports[port].pvid = vlan->vid_end;
1185 mutex_unlock(&priv->reg_mutex);
1189 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1190 const struct switchdev_obj_port_vlan *vlan)
1192 struct mt7530_hw_vlan_entry target_entry;
1193 struct mt7530_priv *priv = ds->priv;
1196 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1199 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1202 mutex_lock(&priv->reg_mutex);
1204 pvid = priv->ports[port].pvid;
1205 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1206 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1207 mt7530_hw_vlan_update(priv, vid, &target_entry,
1208 mt7530_hw_vlan_del);
1210 /* PVID is being restored to the default whenever the PVID port
1211 * is being removed from the VLAN.
1214 pvid = G0_PORT_VID_DEF;
1217 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1218 priv->ports[port].pvid = pvid;
1220 mutex_unlock(&priv->reg_mutex);
1225 static enum dsa_tag_protocol
1226 mtk_get_tag_protocol(struct dsa_switch *ds, int port)
1228 struct mt7530_priv *priv = ds->priv;
1230 if (port != MT7530_CPU_PORT) {
1232 "port not matched with tagging CPU port\n");
1233 return DSA_TAG_PROTO_NONE;
1235 return DSA_TAG_PROTO_MTK;
1240 mt7530_setup(struct dsa_switch *ds)
1242 struct mt7530_priv *priv = ds->priv;
1243 struct device_node *phy_node;
1244 struct device_node *mac_np;
1245 struct mt7530_dummy_poll p;
1246 phy_interface_t interface;
1247 struct device_node *dn;
1251 /* The parent node of master netdev which holds the common system
1252 * controller also is the container for two GMACs nodes representing
1253 * as two netdev instances.
1255 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
1257 if (priv->id == ID_MT7530) {
1258 priv->ethernet = syscon_node_to_regmap(dn);
1259 if (IS_ERR(priv->ethernet))
1260 return PTR_ERR(priv->ethernet);
1262 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1263 ret = regulator_enable(priv->core_pwr);
1266 "Failed to enable core power: %d\n", ret);
1270 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1271 ret = regulator_enable(priv->io_pwr);
1273 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1279 /* Reset whole chip through gpio pin or memory-mapped registers for
1280 * different type of hardware
1283 reset_control_assert(priv->rstc);
1284 usleep_range(1000, 1100);
1285 reset_control_deassert(priv->rstc);
1287 gpiod_set_value_cansleep(priv->reset, 0);
1288 usleep_range(1000, 1100);
1289 gpiod_set_value_cansleep(priv->reset, 1);
1292 /* Waiting for MT7530 got to stable */
1293 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1294 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1297 dev_err(priv->dev, "reset timeout\n");
1301 id = mt7530_read(priv, MT7530_CREV);
1302 id >>= CHIP_NAME_SHIFT;
1303 if (id != MT7530_ID) {
1304 dev_err(priv->dev, "chip %x can't be supported\n", id);
1308 /* Reset the switch through internal reset */
1309 mt7530_write(priv, MT7530_SYS_CTRL,
1310 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1313 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1314 val = mt7530_read(priv, MT7530_MHWTRAP);
1315 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1316 val |= MHWTRAP_MANUAL;
1317 mt7530_write(priv, MT7530_MHWTRAP, val);
1319 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1321 /* Enable and reset MIB counters */
1322 mt7530_mib_reset(ds);
1324 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1326 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1327 /* Disable forwarding by default on all ports */
1328 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1331 if (dsa_is_cpu_port(ds, i))
1332 mt7530_cpu_port_enable(priv, i);
1334 mt7530_port_disable(ds, i);
1338 priv->p5_intf_sel = P5_DISABLED;
1339 interface = PHY_INTERFACE_MODE_NA;
1341 if (!dsa_is_unused_port(ds, 5)) {
1342 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1343 interface = of_get_phy_mode(dsa_to_port(ds, 5)->dn);
1345 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1346 for_each_child_of_node(dn, mac_np) {
1347 if (!of_device_is_compatible(mac_np,
1348 "mediatek,eth-mac"))
1351 ret = of_property_read_u32(mac_np, "reg", &id);
1352 if (ret < 0 || id != 1)
1355 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1356 if (phy_node->parent == priv->dev->of_node->parent) {
1357 interface = of_get_phy_mode(mac_np);
1358 id = of_mdio_parse_addr(ds->dev, phy_node);
1360 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1362 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1364 of_node_put(phy_node);
1369 mt7530_setup_port5(ds, interface);
1371 /* Flush the FDB table */
1372 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1379 static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
1381 const struct phylink_link_state *state)
1383 struct mt7530_priv *priv = ds->priv;
1384 u32 mcr_cur, mcr_new;
1387 case 0: /* Internal phy */
1392 if (state->interface != PHY_INTERFACE_MODE_GMII)
1395 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1396 if (priv->p5_interface == state->interface)
1398 if (!phy_interface_mode_is_rgmii(state->interface) &&
1399 state->interface != PHY_INTERFACE_MODE_MII &&
1400 state->interface != PHY_INTERFACE_MODE_GMII)
1403 mt7530_setup_port5(ds, state->interface);
1405 case 6: /* 1st cpu port */
1406 if (priv->p6_interface == state->interface)
1409 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1410 state->interface != PHY_INTERFACE_MODE_TRGMII)
1413 /* Setup TX circuit incluing relevant PAD and driving */
1414 mt7530_pad_clk_setup(ds, state->interface);
1416 if (priv->id == ID_MT7530) {
1417 /* Setup RX circuit, relevant PAD and driving on the
1418 * host which must be placed after the setup on the
1419 * device side is all finished.
1421 mt7623_pad_clk_setup(ds);
1424 priv->p6_interface = state->interface;
1427 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1431 if (phylink_autoneg_inband(mode)) {
1432 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1437 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
1439 mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
1440 PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
1441 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
1442 PMCR_BACKPR_EN | PMCR_FORCE_MODE | PMCR_FORCE_LNK;
1444 /* Are we connected to external phy */
1445 if (port == 5 && dsa_is_user_port(ds, 5))
1446 mcr_new |= PMCR_EXT_PHY;
1448 switch (state->speed) {
1450 mcr_new |= PMCR_FORCE_SPEED_1000;
1453 mcr_new |= PMCR_FORCE_SPEED_100;
1456 if (state->duplex == DUPLEX_FULL) {
1457 mcr_new |= PMCR_FORCE_FDX;
1458 if (state->pause & MLO_PAUSE_TX)
1459 mcr_new |= PMCR_TX_FC_EN;
1460 if (state->pause & MLO_PAUSE_RX)
1461 mcr_new |= PMCR_RX_FC_EN;
1464 if (mcr_new != mcr_cur)
1465 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
1468 static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
1470 phy_interface_t interface)
1472 struct mt7530_priv *priv = ds->priv;
1474 mt7530_port_set_status(priv, port, 0);
1477 static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
1479 phy_interface_t interface,
1480 struct phy_device *phydev)
1482 struct mt7530_priv *priv = ds->priv;
1484 mt7530_port_set_status(priv, port, 1);
1487 static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
1488 unsigned long *supported,
1489 struct phylink_link_state *state)
1491 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1494 case 0: /* Internal phy */
1499 if (state->interface != PHY_INTERFACE_MODE_NA &&
1500 state->interface != PHY_INTERFACE_MODE_GMII)
1503 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1504 if (state->interface != PHY_INTERFACE_MODE_NA &&
1505 !phy_interface_mode_is_rgmii(state->interface) &&
1506 state->interface != PHY_INTERFACE_MODE_MII &&
1507 state->interface != PHY_INTERFACE_MODE_GMII)
1510 case 6: /* 1st cpu port */
1511 if (state->interface != PHY_INTERFACE_MODE_NA &&
1512 state->interface != PHY_INTERFACE_MODE_RGMII &&
1513 state->interface != PHY_INTERFACE_MODE_TRGMII)
1517 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1519 linkmode_zero(supported);
1523 phylink_set_port_modes(mask);
1524 phylink_set(mask, Autoneg);
1526 if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
1527 phylink_set(mask, 1000baseT_Full);
1529 phylink_set(mask, 10baseT_Half);
1530 phylink_set(mask, 10baseT_Full);
1531 phylink_set(mask, 100baseT_Half);
1532 phylink_set(mask, 100baseT_Full);
1534 if (state->interface != PHY_INTERFACE_MODE_MII) {
1535 phylink_set(mask, 1000baseT_Half);
1536 phylink_set(mask, 1000baseT_Full);
1538 phylink_set(mask, 1000baseX_Full);
1542 phylink_set(mask, Pause);
1543 phylink_set(mask, Asym_Pause);
1545 linkmode_and(supported, supported, mask);
1546 linkmode_and(state->advertising, state->advertising, mask);
1550 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
1551 struct phylink_link_state *state)
1553 struct mt7530_priv *priv = ds->priv;
1556 if (port < 0 || port >= MT7530_NUM_PORTS)
1559 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
1561 state->link = (pmsr & PMSR_LINK);
1562 state->an_complete = state->link;
1563 state->duplex = !!(pmsr & PMSR_DPX);
1565 switch (pmsr & PMSR_SPEED_MASK) {
1567 state->speed = SPEED_10;
1569 case PMSR_SPEED_100:
1570 state->speed = SPEED_100;
1572 case PMSR_SPEED_1000:
1573 state->speed = SPEED_1000;
1576 state->speed = SPEED_UNKNOWN;
1580 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
1581 if (pmsr & PMSR_RX_FC)
1582 state->pause |= MLO_PAUSE_RX;
1583 if (pmsr & PMSR_TX_FC)
1584 state->pause |= MLO_PAUSE_TX;
1589 static const struct dsa_switch_ops mt7530_switch_ops = {
1590 .get_tag_protocol = mtk_get_tag_protocol,
1591 .setup = mt7530_setup,
1592 .get_strings = mt7530_get_strings,
1593 .phy_read = mt7530_phy_read,
1594 .phy_write = mt7530_phy_write,
1595 .get_ethtool_stats = mt7530_get_ethtool_stats,
1596 .get_sset_count = mt7530_get_sset_count,
1597 .port_enable = mt7530_port_enable,
1598 .port_disable = mt7530_port_disable,
1599 .port_stp_state_set = mt7530_stp_state_set,
1600 .port_bridge_join = mt7530_port_bridge_join,
1601 .port_bridge_leave = mt7530_port_bridge_leave,
1602 .port_fdb_add = mt7530_port_fdb_add,
1603 .port_fdb_del = mt7530_port_fdb_del,
1604 .port_fdb_dump = mt7530_port_fdb_dump,
1605 .port_vlan_filtering = mt7530_port_vlan_filtering,
1606 .port_vlan_prepare = mt7530_port_vlan_prepare,
1607 .port_vlan_add = mt7530_port_vlan_add,
1608 .port_vlan_del = mt7530_port_vlan_del,
1609 .phylink_validate = mt7530_phylink_validate,
1610 .phylink_mac_link_state = mt7530_phylink_mac_link_state,
1611 .phylink_mac_config = mt7530_phylink_mac_config,
1612 .phylink_mac_link_down = mt7530_phylink_mac_link_down,
1613 .phylink_mac_link_up = mt7530_phylink_mac_link_up,
1616 static const struct of_device_id mt7530_of_match[] = {
1617 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1618 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1621 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1624 mt7530_probe(struct mdio_device *mdiodev)
1626 struct mt7530_priv *priv;
1627 struct device_node *dn;
1629 dn = mdiodev->dev.of_node;
1631 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1635 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1639 priv->ds->dev = &mdiodev->dev;
1640 priv->ds->num_ports = DSA_MAX_PORTS;
1642 /* Use medatek,mcm property to distinguish hardware type that would
1643 * casues a little bit differences on power-on sequence.
1645 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1647 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1649 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1650 if (IS_ERR(priv->rstc)) {
1651 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1652 return PTR_ERR(priv->rstc);
1656 /* Get the hardware identifier from the devicetree node.
1657 * We will need it for some of the clock and regulator setup.
1659 priv->id = (unsigned int)(unsigned long)
1660 of_device_get_match_data(&mdiodev->dev);
1662 if (priv->id == ID_MT7530) {
1663 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1664 if (IS_ERR(priv->core_pwr))
1665 return PTR_ERR(priv->core_pwr);
1667 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1668 if (IS_ERR(priv->io_pwr))
1669 return PTR_ERR(priv->io_pwr);
1672 /* Not MCM that indicates switch works as the remote standalone
1673 * integrated circuit so the GPIO pin would be used to complete
1674 * the reset, otherwise memory-mapped register accessing used
1675 * through syscon provides in the case of MCM.
1678 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1680 if (IS_ERR(priv->reset)) {
1681 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1682 return PTR_ERR(priv->reset);
1686 priv->bus = mdiodev->bus;
1687 priv->dev = &mdiodev->dev;
1688 priv->ds->priv = priv;
1689 priv->ds->ops = &mt7530_switch_ops;
1690 mutex_init(&priv->reg_mutex);
1691 dev_set_drvdata(&mdiodev->dev, priv);
1693 return dsa_register_switch(priv->ds);
1697 mt7530_remove(struct mdio_device *mdiodev)
1699 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1702 ret = regulator_disable(priv->core_pwr);
1705 "Failed to disable core power: %d\n", ret);
1707 ret = regulator_disable(priv->io_pwr);
1709 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1712 dsa_unregister_switch(priv->ds);
1713 mutex_destroy(&priv->reg_mutex);
1716 static struct mdio_driver mt7530_mdio_driver = {
1717 .probe = mt7530_probe,
1718 .remove = mt7530_remove,
1721 .of_match_table = mt7530_of_match,
1725 mdio_module_driver(mt7530_mdio_driver);
1727 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1728 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1729 MODULE_LICENSE("GPL");