drivers/net/dsa/microchip/ksz_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/export.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_data/microchip-ksz.h>
  14 #include <linux/phy.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/if_bridge.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_net.h>
  19 #include <linux/micrel_phy.h>
  20 #include <net/dsa.h>
  21 #include <net/switchdev.h>
  22
  23 #include "ksz_common.h"
  24 #include "ksz8.h"
  25 #include "ksz9477.h"
  26 #include "lan937x.h"
  27
  28 #define MIB_COUNTER_NUM 0x20
  29
  30 struct ksz_stats_raw {
  31         u64 rx_hi;
  32         u64 rx_undersize;
  33         u64 rx_fragments;
  34         u64 rx_oversize;
  35         u64 rx_jabbers;
  36         u64 rx_symbol_err;
  37         u64 rx_crc_err;
  38         u64 rx_align_err;
  39         u64 rx_mac_ctrl;
  40         u64 rx_pause;
  41         u64 rx_bcast;
  42         u64 rx_mcast;
  43         u64 rx_ucast;
  44         u64 rx_64_or_less;
  45         u64 rx_65_127;
  46         u64 rx_128_255;
  47         u64 rx_256_511;
  48         u64 rx_512_1023;
  49         u64 rx_1024_1522;
  50         u64 rx_1523_2000;
  51         u64 rx_2001;
  52         u64 tx_hi;
  53         u64 tx_late_col;
  54         u64 tx_pause;
  55         u64 tx_bcast;
  56         u64 tx_mcast;
  57         u64 tx_ucast;
  58         u64 tx_deferred;
  59         u64 tx_total_col;
  60         u64 tx_exc_col;
  61         u64 tx_single_col;
  62         u64 tx_mult_col;
  63         u64 rx_total;
  64         u64 tx_total;
  65         u64 rx_discards;
  66         u64 tx_discards;
  67 };
  68
  69 static const struct ksz_mib_names ksz88xx_mib_names[] = {
  70         { 0x00, "rx" },
  71         { 0x01, "rx_hi" },
  72         { 0x02, "rx_undersize" },
  73         { 0x03, "rx_fragments" },
  74         { 0x04, "rx_oversize" },
  75         { 0x05, "rx_jabbers" },
  76         { 0x06, "rx_symbol_err" },
  77         { 0x07, "rx_crc_err" },
  78         { 0x08, "rx_align_err" },
  79         { 0x09, "rx_mac_ctrl" },
  80         { 0x0a, "rx_pause" },
  81         { 0x0b, "rx_bcast" },
  82         { 0x0c, "rx_mcast" },
  83         { 0x0d, "rx_ucast" },
  84         { 0x0e, "rx_64_or_less" },
  85         { 0x0f, "rx_65_127" },
  86         { 0x10, "rx_128_255" },
  87         { 0x11, "rx_256_511" },
  88         { 0x12, "rx_512_1023" },
  89         { 0x13, "rx_1024_1522" },
  90         { 0x14, "tx" },
  91         { 0x15, "tx_hi" },
  92         { 0x16, "tx_late_col" },
  93         { 0x17, "tx_pause" },
  94         { 0x18, "tx_bcast" },
  95         { 0x19, "tx_mcast" },
  96         { 0x1a, "tx_ucast" },
  97         { 0x1b, "tx_deferred" },
  98         { 0x1c, "tx_total_col" },
  99         { 0x1d, "tx_exc_col" },
 100         { 0x1e, "tx_single_col" },
 101         { 0x1f, "tx_mult_col" },
 102         { 0x100, "rx_discards" },
 103         { 0x101, "tx_discards" },
 104 };
 105
 106 static const struct ksz_mib_names ksz9477_mib_names[] = {
 107         { 0x00, "rx_hi" },
 108         { 0x01, "rx_undersize" },
 109         { 0x02, "rx_fragments" },
 110         { 0x03, "rx_oversize" },
 111         { 0x04, "rx_jabbers" },
 112         { 0x05, "rx_symbol_err" },
 113         { 0x06, "rx_crc_err" },
 114         { 0x07, "rx_align_err" },
 115         { 0x08, "rx_mac_ctrl" },
 116         { 0x09, "rx_pause" },
 117         { 0x0A, "rx_bcast" },
 118         { 0x0B, "rx_mcast" },
 119         { 0x0C, "rx_ucast" },
 120         { 0x0D, "rx_64_or_less" },
 121         { 0x0E, "rx_65_127" },
 122         { 0x0F, "rx_128_255" },
 123         { 0x10, "rx_256_511" },
 124         { 0x11, "rx_512_1023" },
 125         { 0x12, "rx_1024_1522" },
 126         { 0x13, "rx_1523_2000" },
 127         { 0x14, "rx_2001" },
 128         { 0x15, "tx_hi" },
 129         { 0x16, "tx_late_col" },
 130         { 0x17, "tx_pause" },
 131         { 0x18, "tx_bcast" },
 132         { 0x19, "tx_mcast" },
 133         { 0x1A, "tx_ucast" },
 134         { 0x1B, "tx_deferred" },
 135         { 0x1C, "tx_total_col" },
 136         { 0x1D, "tx_exc_col" },
 137         { 0x1E, "tx_single_col" },
 138         { 0x1F, "tx_mult_col" },
 139         { 0x80, "rx_total" },
 140         { 0x81, "tx_total" },
 141         { 0x82, "rx_discards" },
 142         { 0x83, "tx_discards" },
 143 };
 144
 145 static const struct ksz_dev_ops ksz8_dev_ops = {
 146         .setup = ksz8_setup,
 147         .get_port_addr = ksz8_get_port_addr,
 148         .cfg_port_member = ksz8_cfg_port_member,
 149         .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
 150         .port_setup = ksz8_port_setup,
 151         .r_phy = ksz8_r_phy,
 152         .w_phy = ksz8_w_phy,
 153         .r_mib_cnt = ksz8_r_mib_cnt,
 154         .r_mib_pkt = ksz8_r_mib_pkt,
 155         .freeze_mib = ksz8_freeze_mib,
 156         .port_init_cnt = ksz8_port_init_cnt,
 157         .fdb_dump = ksz8_fdb_dump,
 158         .mdb_add = ksz8_mdb_add,
 159         .mdb_del = ksz8_mdb_del,
 160         .vlan_filtering = ksz8_port_vlan_filtering,
 161         .vlan_add = ksz8_port_vlan_add,
 162         .vlan_del = ksz8_port_vlan_del,
 163         .mirror_add = ksz8_port_mirror_add,
 164         .mirror_del = ksz8_port_mirror_del,
 165         .get_caps = ksz8_get_caps,
 166         .config_cpu_port = ksz8_config_cpu_port,
 167         .enable_stp_addr = ksz8_enable_stp_addr,
 168         .reset = ksz8_reset_switch,
 169         .init = ksz8_switch_init,
 170         .exit = ksz8_switch_exit,
 171 };
 172
 173 static const struct ksz_dev_ops ksz9477_dev_ops = {
 174         .setup = ksz9477_setup,
 175         .get_port_addr = ksz9477_get_port_addr,
 176         .cfg_port_member = ksz9477_cfg_port_member,
 177         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 178         .port_setup = ksz9477_port_setup,
 179         .r_phy = ksz9477_r_phy,
 180         .w_phy = ksz9477_w_phy,
 181         .r_mib_cnt = ksz9477_r_mib_cnt,
 182         .r_mib_pkt = ksz9477_r_mib_pkt,
 183         .r_mib_stat64 = ksz_r_mib_stats64,
 184         .freeze_mib = ksz9477_freeze_mib,
 185         .port_init_cnt = ksz9477_port_init_cnt,
 186         .vlan_filtering = ksz9477_port_vlan_filtering,
 187         .vlan_add = ksz9477_port_vlan_add,
 188         .vlan_del = ksz9477_port_vlan_del,
 189         .mirror_add = ksz9477_port_mirror_add,
 190         .mirror_del = ksz9477_port_mirror_del,
 191         .get_caps = ksz9477_get_caps,
 192         .fdb_dump = ksz9477_fdb_dump,
 193         .fdb_add = ksz9477_fdb_add,
 194         .fdb_del = ksz9477_fdb_del,
 195         .mdb_add = ksz9477_mdb_add,
 196         .mdb_del = ksz9477_mdb_del,
 197         .change_mtu = ksz9477_change_mtu,
 198         .max_mtu = ksz9477_max_mtu,
 199         .config_cpu_port = ksz9477_config_cpu_port,
 200         .enable_stp_addr = ksz9477_enable_stp_addr,
 201         .reset = ksz9477_reset_switch,
 202         .init = ksz9477_switch_init,
 203         .exit = ksz9477_switch_exit,
 204 };
 205
 206 static const struct ksz_dev_ops lan937x_dev_ops = {
 207         .setup = lan937x_setup,
 208         .get_port_addr = ksz9477_get_port_addr,
 209         .cfg_port_member = ksz9477_cfg_port_member,
 210         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 211         .port_setup = lan937x_port_setup,
 212         .r_phy = lan937x_r_phy,
 213         .w_phy = lan937x_w_phy,
 214         .r_mib_cnt = ksz9477_r_mib_cnt,
 215         .r_mib_pkt = ksz9477_r_mib_pkt,
 216         .r_mib_stat64 = ksz_r_mib_stats64,
 217         .freeze_mib = ksz9477_freeze_mib,
 218         .port_init_cnt = ksz9477_port_init_cnt,
 219         .vlan_filtering = ksz9477_port_vlan_filtering,
 220         .vlan_add = ksz9477_port_vlan_add,
 221         .vlan_del = ksz9477_port_vlan_del,
 222         .mirror_add = ksz9477_port_mirror_add,
 223         .mirror_del = ksz9477_port_mirror_del,
 224         .get_caps = lan937x_phylink_get_caps,
 225         .phylink_mac_config = lan937x_phylink_mac_config,
 226         .setup_rgmii_delay = lan937x_setup_rgmii_delay,
 227         .fdb_dump = ksz9477_fdb_dump,
 228         .fdb_add = ksz9477_fdb_add,
 229         .fdb_del = ksz9477_fdb_del,
 230         .mdb_add = ksz9477_mdb_add,
 231         .mdb_del = ksz9477_mdb_del,
 232         .change_mtu = lan937x_change_mtu,
 233         .max_mtu = ksz9477_max_mtu,
 234         .config_cpu_port = lan937x_config_cpu_port,
 235         .enable_stp_addr = ksz9477_enable_stp_addr,
 236         .reset = lan937x_reset_switch,
 237         .init = lan937x_switch_init,
 238         .exit = lan937x_switch_exit,
 239 };
 240
 241 static const u16 ksz8795_regs[] = {
 242         [REG_IND_CTRL_0]                = 0x6E,
 243         [REG_IND_DATA_8]                = 0x70,
 244         [REG_IND_DATA_CHECK]            = 0x72,
 245         [REG_IND_DATA_HI]               = 0x71,
 246         [REG_IND_DATA_LO]               = 0x75,
 247         [REG_IND_MIB_CHECK]             = 0x74,
 248         [REG_IND_BYTE]                  = 0xA0,
 249         [P_FORCE_CTRL]                  = 0x0C,
 250         [P_LINK_STATUS]                 = 0x0E,
 251         [P_LOCAL_CTRL]                  = 0x07,
 252         [P_NEG_RESTART_CTRL]            = 0x0D,
 253         [P_REMOTE_STATUS]               = 0x08,
 254         [P_SPEED_STATUS]                = 0x09,
 255         [S_TAIL_TAG_CTRL]               = 0x0C,
 256         [P_STP_CTRL]                    = 0x02,
 257         [S_START_CTRL]                  = 0x01,
 258         [S_BROADCAST_CTRL]              = 0x06,
 259         [S_MULTICAST_CTRL]              = 0x04,
 260         [P_XMII_CTRL_0]                 = 0x06,
 261         [P_XMII_CTRL_1]                 = 0x56,
 262 };
 263
 264 static const u32 ksz8795_masks[] = {
 265         [PORT_802_1P_REMAPPING]         = BIT(7),
 266         [SW_TAIL_TAG_ENABLE]            = BIT(1),
 267         [MIB_COUNTER_OVERFLOW]          = BIT(6),
 268         [MIB_COUNTER_VALID]             = BIT(5),
 269         [VLAN_TABLE_FID]                = GENMASK(6, 0),
 270         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(11, 7),
 271         [VLAN_TABLE_VALID]              = BIT(12),
 272         [STATIC_MAC_TABLE_VALID]        = BIT(21),
 273         [STATIC_MAC_TABLE_USE_FID]      = BIT(23),
 274         [STATIC_MAC_TABLE_FID]          = GENMASK(30, 24),
 275         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(26),
 276         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(24, 20),
 277         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(6, 0),
 278         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(8),
 279         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 280         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 29),
 281         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(26, 20),
 282         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
 283         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
 284         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 285         [P_MII_RX_FLOW_CTRL]            = BIT(5),
 286 };
 287
 288 static const u8 ksz8795_xmii_ctrl0[] = {
 289         [P_MII_100MBIT]                 = 0,
 290         [P_MII_10MBIT]                  = 1,
 291         [P_MII_FULL_DUPLEX]             = 0,
 292         [P_MII_HALF_DUPLEX]             = 1,
 293 };
 294
 295 static const u8 ksz8795_xmii_ctrl1[] = {
 296         [P_RGMII_SEL]                   = 3,
 297         [P_GMII_SEL]                    = 2,
 298         [P_RMII_SEL]                    = 1,
 299         [P_MII_SEL]                     = 0,
 300         [P_GMII_1GBIT]                  = 1,
 301         [P_GMII_NOT_1GBIT]              = 0,
 302 };
 303
 304 static const u8 ksz8795_shifts[] = {
 305         [VLAN_TABLE_MEMBERSHIP_S]       = 7,
 306         [VLAN_TABLE]                    = 16,
 307         [STATIC_MAC_FWD_PORTS]          = 16,
 308         [STATIC_MAC_FID]                = 24,
 309         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 310         [DYNAMIC_MAC_ENTRIES]           = 29,
 311         [DYNAMIC_MAC_FID]               = 16,
 312         [DYNAMIC_MAC_TIMESTAMP]         = 27,
 313         [DYNAMIC_MAC_SRC_PORT]          = 24,
 314 };
 315
 316 static const u16 ksz8863_regs[] = {
 317         [REG_IND_CTRL_0]                = 0x79,
 318         [REG_IND_DATA_8]                = 0x7B,
 319         [REG_IND_DATA_CHECK]            = 0x7B,
 320         [REG_IND_DATA_HI]               = 0x7C,
 321         [REG_IND_DATA_LO]               = 0x80,
 322         [REG_IND_MIB_CHECK]             = 0x80,
 323         [P_FORCE_CTRL]                  = 0x0C,
 324         [P_LINK_STATUS]                 = 0x0E,
 325         [P_LOCAL_CTRL]                  = 0x0C,
 326         [P_NEG_RESTART_CTRL]            = 0x0D,
 327         [P_REMOTE_STATUS]               = 0x0E,
 328         [P_SPEED_STATUS]                = 0x0F,
 329         [S_TAIL_TAG_CTRL]               = 0x03,
 330         [P_STP_CTRL]                    = 0x02,
 331         [S_START_CTRL]                  = 0x01,
 332         [S_BROADCAST_CTRL]              = 0x06,
 333         [S_MULTICAST_CTRL]              = 0x04,
 334 };
 335
 336 static const u32 ksz8863_masks[] = {
 337         [PORT_802_1P_REMAPPING]         = BIT(3),
 338         [SW_TAIL_TAG_ENABLE]            = BIT(6),
 339         [MIB_COUNTER_OVERFLOW]          = BIT(7),
 340         [MIB_COUNTER_VALID]             = BIT(6),
 341         [VLAN_TABLE_FID]                = GENMASK(15, 12),
 342         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(18, 16),
 343         [VLAN_TABLE_VALID]              = BIT(19),
 344         [STATIC_MAC_TABLE_VALID]        = BIT(19),
 345         [STATIC_MAC_TABLE_USE_FID]      = BIT(21),
 346         [STATIC_MAC_TABLE_FID]          = GENMASK(29, 26),
 347         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(20),
 348         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(18, 16),
 349         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(5, 0),
 350         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(7),
 351         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 352         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 28),
 353         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(19, 16),
 354         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(21, 20),
 355         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(23, 22),
 356 };
 357
 358 static u8 ksz8863_shifts[] = {
 359         [VLAN_TABLE_MEMBERSHIP_S]       = 16,
 360         [STATIC_MAC_FWD_PORTS]          = 16,
 361         [STATIC_MAC_FID]                = 22,
 362         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 363         [DYNAMIC_MAC_ENTRIES]           = 24,
 364         [DYNAMIC_MAC_FID]               = 16,
 365         [DYNAMIC_MAC_TIMESTAMP]         = 24,
 366         [DYNAMIC_MAC_SRC_PORT]          = 20,
 367 };
 368
 369 static const u16 ksz9477_regs[] = {
 370         [P_STP_CTRL]                    = 0x0B04,
 371         [S_START_CTRL]                  = 0x0300,
 372         [S_BROADCAST_CTRL]              = 0x0332,
 373         [S_MULTICAST_CTRL]              = 0x0331,
 374         [P_XMII_CTRL_0]                 = 0x0300,
 375         [P_XMII_CTRL_1]                 = 0x0301,
 376 };
 377
 378 static const u32 ksz9477_masks[] = {
 379         [ALU_STAT_WRITE]                = 0,
 380         [ALU_STAT_READ]                 = 1,
 381         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 382         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 383 };
 384
 385 static const u8 ksz9477_shifts[] = {
 386         [ALU_STAT_INDEX]                = 16,
 387 };
 388
 389 static const u8 ksz9477_xmii_ctrl0[] = {
 390         [P_MII_100MBIT]                 = 1,
 391         [P_MII_10MBIT]                  = 0,
 392         [P_MII_FULL_DUPLEX]             = 1,
 393         [P_MII_HALF_DUPLEX]             = 0,
 394 };
 395
 396 static const u8 ksz9477_xmii_ctrl1[] = {
 397         [P_RGMII_SEL]                   = 0,
 398         [P_RMII_SEL]                    = 1,
 399         [P_GMII_SEL]                    = 2,
 400         [P_MII_SEL]                     = 3,
 401         [P_GMII_1GBIT]                  = 0,
 402         [P_GMII_NOT_1GBIT]              = 1,
 403 };
 404
 405 static const u32 lan937x_masks[] = {
 406         [ALU_STAT_WRITE]                = 1,
 407         [ALU_STAT_READ]                 = 2,
 408         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 409         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 410 };
 411
 412 static const u8 lan937x_shifts[] = {
 413         [ALU_STAT_INDEX]                = 8,
 414 };
 415
 416 const struct ksz_chip_data ksz_switch_chips[] = {
 417         [KSZ8795] = {
 418                 .chip_id = KSZ8795_CHIP_ID,
 419                 .dev_name = "KSZ8795",
 420                 .num_vlans = 4096,
 421                 .num_alus = 0,
 422                 .num_statics = 8,
 423                 .cpu_ports = 0x10,      /* can be configured as cpu port */
 424                 .port_cnt = 5,          /* total cpu and user ports */
 425                 .ops = &ksz8_dev_ops,
 426                 .ksz87xx_eee_link_erratum = true,
 427                 .mib_names = ksz9477_mib_names,
 428                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 429                 .reg_mib_cnt = MIB_COUNTER_NUM,
 430                 .regs = ksz8795_regs,
 431                 .masks = ksz8795_masks,
 432                 .shifts = ksz8795_shifts,
 433                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
 434                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
 435                 .supports_mii = {false, false, false, false, true},
 436                 .supports_rmii = {false, false, false, false, true},
 437                 .supports_rgmii = {false, false, false, false, true},
 438                 .internal_phy = {true, true, true, true, false},
 439         },
 440
 441         [KSZ8794] = {
 442                 /* WARNING
 443                  * =======
 444                  * KSZ8794 is similar to KSZ8795, except the port map
 445                  * contains a gap between external and CPU ports, the
 446                  * port map is NOT continuous. The per-port register
 447                  * map is shifted accordingly too, i.e. registers at
 448                  * offset 0x40 are NOT used on KSZ8794 and they ARE
 449                  * used on KSZ8795 for external port 3.
 450                  *           external  cpu
 451                  * KSZ8794   0,1,2      4
 452                  * KSZ8795   0,1,2,3    4
 453                  * KSZ8765   0,1,2,3    4
 454                  * port_cnt is configured as 5, even though it is 4
 455                  */
 456                 .chip_id = KSZ8794_CHIP_ID,
 457                 .dev_name = "KSZ8794",
 458                 .num_vlans = 4096,
 459                 .num_alus = 0,
 460                 .num_statics = 8,
 461                 .cpu_ports = 0x10,      /* can be configured as cpu port */
 462                 .port_cnt = 5,          /* total cpu and user ports */
 463                 .ops = &ksz8_dev_ops,
 464                 .ksz87xx_eee_link_erratum = true,
 465                 .mib_names = ksz9477_mib_names,
 466                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 467                 .reg_mib_cnt = MIB_COUNTER_NUM,
 468                 .regs = ksz8795_regs,
 469                 .masks = ksz8795_masks,
 470                 .shifts = ksz8795_shifts,
 471                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
 472                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
 473                 .supports_mii = {false, false, false, false, true},
 474                 .supports_rmii = {false, false, false, false, true},
 475                 .supports_rgmii = {false, false, false, false, true},
 476                 .internal_phy = {true, true, true, false, false},
 477         },
 478
 479         [KSZ8765] = {
 480                 .chip_id = KSZ8765_CHIP_ID,
 481                 .dev_name = "KSZ8765",
 482                 .num_vlans = 4096,
 483                 .num_alus = 0,
 484                 .num_statics = 8,
 485                 .cpu_ports = 0x10,      /* can be configured as cpu port */
 486                 .port_cnt = 5,          /* total cpu and user ports */
 487                 .ops = &ksz8_dev_ops,
 488                 .ksz87xx_eee_link_erratum = true,
 489                 .mib_names = ksz9477_mib_names,
 490                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 491                 .reg_mib_cnt = MIB_COUNTER_NUM,
 492                 .regs = ksz8795_regs,
 493                 .masks = ksz8795_masks,
 494                 .shifts = ksz8795_shifts,
 495                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
 496                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
 497                 .supports_mii = {false, false, false, false, true},
 498                 .supports_rmii = {false, false, false, false, true},
 499                 .supports_rgmii = {false, false, false, false, true},
 500                 .internal_phy = {true, true, true, true, false},
 501         },
 502
 503         [KSZ8830] = {
 504                 .chip_id = KSZ8830_CHIP_ID,
 505                 .dev_name = "KSZ8863/KSZ8873",
 506                 .num_vlans = 16,
 507                 .num_alus = 0,
 508                 .num_statics = 8,
 509                 .cpu_ports = 0x4,       /* can be configured as cpu port */
 510                 .port_cnt = 3,
 511                 .ops = &ksz8_dev_ops,
 512                 .mib_names = ksz88xx_mib_names,
 513                 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
 514                 .reg_mib_cnt = MIB_COUNTER_NUM,
 515                 .regs = ksz8863_regs,
 516                 .masks = ksz8863_masks,
 517                 .shifts = ksz8863_shifts,
 518                 .supports_mii = {false, false, true},
 519                 .supports_rmii = {false, false, true},
 520                 .internal_phy = {true, true, false},
 521         },
 522
 523         [KSZ9477] = {
 524                 .chip_id = KSZ9477_CHIP_ID,
 525                 .dev_name = "KSZ9477",
 526                 .num_vlans = 4096,
 527                 .num_alus = 4096,
 528                 .num_statics = 16,
 529                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
 530                 .port_cnt = 7,          /* total physical port count */
 531                 .ops = &ksz9477_dev_ops,
 532                 .phy_errata_9477 = true,
 533                 .mib_names = ksz9477_mib_names,
 534                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 535                 .reg_mib_cnt = MIB_COUNTER_NUM,
 536                 .regs = ksz9477_regs,
 537                 .masks = ksz9477_masks,
 538                 .shifts = ksz9477_shifts,
 539                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 540                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 541                 .supports_mii   = {false, false, false, false,
 542                                    false, true, false},
 543                 .supports_rmii  = {false, false, false, false,
 544                                    false, true, false},
 545                 .supports_rgmii = {false, false, false, false,
 546                                    false, true, false},
 547                 .internal_phy   = {true, true, true, true,
 548                                    true, false, false},
 549         },
 550
 551         [KSZ9897] = {
 552                 .chip_id = KSZ9897_CHIP_ID,
 553                 .dev_name = "KSZ9897",
 554                 .num_vlans = 4096,
 555                 .num_alus = 4096,
 556                 .num_statics = 16,
 557                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
 558                 .port_cnt = 7,          /* total physical port count */
 559                 .ops = &ksz9477_dev_ops,
 560                 .phy_errata_9477 = true,
 561                 .mib_names = ksz9477_mib_names,
 562                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 563                 .reg_mib_cnt = MIB_COUNTER_NUM,
 564                 .regs = ksz9477_regs,
 565                 .masks = ksz9477_masks,
 566                 .shifts = ksz9477_shifts,
 567                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 568                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 569                 .supports_mii   = {false, false, false, false,
 570                                    false, true, true},
 571                 .supports_rmii  = {false, false, false, false,
 572                                    false, true, true},
 573                 .supports_rgmii = {false, false, false, false,
 574                                    false, true, true},
 575                 .internal_phy   = {true, true, true, true,
 576                                    true, false, false},
 577         },
 578
 579         [KSZ9893] = {
 580                 .chip_id = KSZ9893_CHIP_ID,
 581                 .dev_name = "KSZ9893",
 582                 .num_vlans = 4096,
 583                 .num_alus = 4096,
 584                 .num_statics = 16,
 585                 .cpu_ports = 0x07,      /* can be configured as cpu port */
 586                 .port_cnt = 3,          /* total port count */
 587                 .ops = &ksz9477_dev_ops,
 588                 .mib_names = ksz9477_mib_names,
 589                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 590                 .reg_mib_cnt = MIB_COUNTER_NUM,
 591                 .regs = ksz9477_regs,
 592                 .masks = ksz9477_masks,
 593                 .shifts = ksz9477_shifts,
 594                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 595                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
 596                 .supports_mii = {false, false, true},
 597                 .supports_rmii = {false, false, true},
 598                 .supports_rgmii = {false, false, true},
 599                 .internal_phy = {true, true, false},
 600         },
 601
 602         [KSZ9567] = {
 603                 .chip_id = KSZ9567_CHIP_ID,
 604                 .dev_name = "KSZ9567",
 605                 .num_vlans = 4096,
 606                 .num_alus = 4096,
 607                 .num_statics = 16,
 608                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
 609                 .port_cnt = 7,          /* total physical port count */
 610                 .ops = &ksz9477_dev_ops,
 611                 .phy_errata_9477 = true,
 612                 .mib_names = ksz9477_mib_names,
 613                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 614                 .reg_mib_cnt = MIB_COUNTER_NUM,
 615                 .regs = ksz9477_regs,
 616                 .masks = ksz9477_masks,
 617                 .shifts = ksz9477_shifts,
 618                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 619                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 620                 .supports_mii   = {false, false, false, false,
 621                                    false, true, true},
 622                 .supports_rmii  = {false, false, false, false,
 623                                    false, true, true},
 624                 .supports_rgmii = {false, false, false, false,
 625                                    false, true, true},
 626                 .internal_phy   = {true, true, true, true,
 627                                    true, false, false},
 628         },
 629
 630         [LAN9370] = {
 631                 .chip_id = LAN9370_CHIP_ID,
 632                 .dev_name = "LAN9370",
 633                 .num_vlans = 4096,
 634                 .num_alus = 1024,
 635                 .num_statics = 256,
 636                 .cpu_ports = 0x10,      /* can be configured as cpu port */
 637                 .port_cnt = 5,          /* total physical port count */
 638                 .ops = &lan937x_dev_ops,
 639                 .mib_names = ksz9477_mib_names,
 640                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 641                 .reg_mib_cnt = MIB_COUNTER_NUM,
 642                 .regs = ksz9477_regs,
 643                 .masks = lan937x_masks,
 644                 .shifts = lan937x_shifts,
 645                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 646                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 647                 .supports_mii = {false, false, false, false, true},
 648                 .supports_rmii = {false, false, false, false, true},
 649                 .supports_rgmii = {false, false, false, false, true},
 650                 .internal_phy = {true, true, true, true, false},
 651         },
 652
 653         [LAN9371] = {
 654                 .chip_id = LAN9371_CHIP_ID,
 655                 .dev_name = "LAN9371",
 656                 .num_vlans = 4096,
 657                 .num_alus = 1024,
 658                 .num_statics = 256,
 659                 .cpu_ports = 0x30,      /* can be configured as cpu port */
 660                 .port_cnt = 6,          /* total physical port count */
 661                 .ops = &lan937x_dev_ops,
 662                 .mib_names = ksz9477_mib_names,
 663                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 664                 .reg_mib_cnt = MIB_COUNTER_NUM,
 665                 .regs = ksz9477_regs,
 666                 .masks = lan937x_masks,
 667                 .shifts = lan937x_shifts,
 668                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 669                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 670                 .supports_mii = {false, false, false, false, true, true},
 671                 .supports_rmii = {false, false, false, false, true, true},
 672                 .supports_rgmii = {false, false, false, false, true, true},
 673                 .internal_phy = {true, true, true, true, false, false},
 674         },
 675
 676         [LAN9372] = {
 677                 .chip_id = LAN9372_CHIP_ID,
 678                 .dev_name = "LAN9372",
 679                 .num_vlans = 4096,
 680                 .num_alus = 1024,
 681                 .num_statics = 256,
 682                 .cpu_ports = 0x30,      /* can be configured as cpu port */
 683                 .port_cnt = 8,          /* total physical port count */
 684                 .ops = &lan937x_dev_ops,
 685                 .mib_names = ksz9477_mib_names,
 686                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 687                 .reg_mib_cnt = MIB_COUNTER_NUM,
 688                 .regs = ksz9477_regs,
 689                 .masks = lan937x_masks,
 690                 .shifts = lan937x_shifts,
 691                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 692                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 693                 .supports_mii   = {false, false, false, false,
 694                                    true, true, false, false},
 695                 .supports_rmii  = {false, false, false, false,
 696                                    true, true, false, false},
 697                 .supports_rgmii = {false, false, false, false,
 698                                    true, true, false, false},
 699                 .internal_phy   = {true, true, true, true,
 700                                    false, false, true, true},
 701         },
 702
 703         [LAN9373] = {
 704                 .chip_id = LAN9373_CHIP_ID,
 705                 .dev_name = "LAN9373",
 706                 .num_vlans = 4096,
 707                 .num_alus = 1024,
 708                 .num_statics = 256,
 709                 .cpu_ports = 0x38,      /* can be configured as cpu port */
 710                 .port_cnt = 5,          /* total physical port count */
 711                 .ops = &lan937x_dev_ops,
 712                 .mib_names = ksz9477_mib_names,
 713                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 714                 .reg_mib_cnt = MIB_COUNTER_NUM,
 715                 .regs = ksz9477_regs,
 716                 .masks = lan937x_masks,
 717                 .shifts = lan937x_shifts,
 718                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 719                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 720                 .supports_mii   = {false, false, false, false,
 721                                    true, true, false, false},
 722                 .supports_rmii  = {false, false, false, false,
 723                                    true, true, false, false},
 724                 .supports_rgmii = {false, false, false, false,
 725                                    true, true, false, false},
 726                 .internal_phy   = {true, true, true, false,
 727                                    false, false, true, true},
 728         },
 729
 730         [LAN9374] = {
 731                 .chip_id = LAN9374_CHIP_ID,
 732                 .dev_name = "LAN9374",
 733                 .num_vlans = 4096,
 734                 .num_alus = 1024,
 735                 .num_statics = 256,
 736                 .cpu_ports = 0x30,      /* can be configured as cpu port */
 737                 .port_cnt = 8,          /* total physical port count */
 738                 .ops = &lan937x_dev_ops,
 739                 .mib_names = ksz9477_mib_names,
 740                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
 741                 .reg_mib_cnt = MIB_COUNTER_NUM,
 742                 .regs = ksz9477_regs,
 743                 .masks = lan937x_masks,
 744                 .shifts = lan937x_shifts,
 745                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
 746                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
 747                 .supports_mii   = {false, false, false, false,
 748                                    true, true, false, false},
 749                 .supports_rmii  = {false, false, false, false,
 750                                    true, true, false, false},
 751                 .supports_rgmii = {false, false, false, false,
 752                                    true, true, false, false},
 753                 .internal_phy   = {true, true, true, true,
 754                                    false, false, true, true},
 755         },
 756 };
 757 EXPORT_SYMBOL_GPL(ksz_switch_chips);
 758
 759 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
 760 {
 761         int i;
 762
 763         for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
 764                 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
 765
 766                 if (chip->chip_id == prod_num)
 767                         return chip;
 768         }
 769
 770         return NULL;
 771 }
 772
 773 static int ksz_check_device_id(struct ksz_device *dev)
 774 {
 775         const struct ksz_chip_data *dt_chip_data;
 776
 777         dt_chip_data = of_device_get_match_data(dev->dev);
 778
 779         /* Check for Device Tree and Chip ID */
 780         if (dt_chip_data->chip_id != dev->chip_id) {
 781                 dev_err(dev->dev,
 782                         "Device tree specifies chip %s but found %s, please fix it!\n",
 783                         dt_chip_data->dev_name, dev->info->dev_name);
 784                 return -ENODEV;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
 791                                  struct phylink_config *config)
 792 {
 793         struct ksz_device *dev = ds->priv;
 794
 795         config->legacy_pre_march2020 = false;
 796
 797         if (dev->info->supports_mii[port])
 798                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 799
 800         if (dev->info->supports_rmii[port])
 801                 __set_bit(PHY_INTERFACE_MODE_RMII,
 802                           config->supported_interfaces);
 803
 804         if (dev->info->supports_rgmii[port])
 805                 phy_interface_set_rgmii(config->supported_interfaces);
 806
 807         if (dev->info->internal_phy[port])
 808                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 809                           config->supported_interfaces);
 810
 811         if (dev->dev_ops->get_caps)
 812                 dev->dev_ops->get_caps(dev, port, config);
 813 }
 814
 815 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
 816 {
 817         struct ethtool_pause_stats *pstats;
 818         struct rtnl_link_stats64 *stats;
 819         struct ksz_stats_raw *raw;
 820         struct ksz_port_mib *mib;
 821
 822         mib = &dev->ports[port].mib;
 823         stats = &mib->stats64;
 824         pstats = &mib->pause_stats;
 825         raw = (struct ksz_stats_raw *)mib->counters;
 826
 827         spin_lock(&mib->stats64_lock);
 828
 829         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
 830                 raw->rx_pause;
 831         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
 832                 raw->tx_pause;
 833
 834         /* HW counters are counting bytes + FCS which is not acceptable
 835          * for rtnl_link_stats64 interface
 836          */
 837         stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
 838         stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
 839
 840         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
 841                 raw->rx_oversize;
 842
 843         stats->rx_crc_errors = raw->rx_crc_err;
 844         stats->rx_frame_errors = raw->rx_align_err;
 845         stats->rx_dropped = raw->rx_discards;
 846         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
 847                 stats->rx_frame_errors  + stats->rx_dropped;
 848
 849         stats->tx_window_errors = raw->tx_late_col;
 850         stats->tx_fifo_errors = raw->tx_discards;
 851         stats->tx_aborted_errors = raw->tx_exc_col;
 852         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
 853                 stats->tx_aborted_errors;
 854
 855         stats->multicast = raw->rx_mcast;
 856         stats->collisions = raw->tx_total_col;
 857
 858         pstats->tx_pause_frames = raw->tx_pause;
 859         pstats->rx_pause_frames = raw->rx_pause;
 860
 861         spin_unlock(&mib->stats64_lock);
 862 }
 863
 864 static void ksz_get_stats64(struct dsa_switch *ds, int port,
 865                             struct rtnl_link_stats64 *s)
 866 {
 867         struct ksz_device *dev = ds->priv;
 868         struct ksz_port_mib *mib;
 869
 870         mib = &dev->ports[port].mib;
 871
 872         spin_lock(&mib->stats64_lock);
 873         memcpy(s, &mib->stats64, sizeof(*s));
 874         spin_unlock(&mib->stats64_lock);
 875 }
 876
 877 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
 878                                 struct ethtool_pause_stats *pause_stats)
 879 {
 880         struct ksz_device *dev = ds->priv;
 881         struct ksz_port_mib *mib;
 882
 883         mib = &dev->ports[port].mib;
 884
 885         spin_lock(&mib->stats64_lock);
 886         memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
 887         spin_unlock(&mib->stats64_lock);
 888 }
 889
 890 static void ksz_get_strings(struct dsa_switch *ds, int port,
 891                             u32 stringset, uint8_t *buf)
 892 {
 893         struct ksz_device *dev = ds->priv;
 894         int i;
 895
 896         if (stringset != ETH_SS_STATS)
 897                 return;
 898
 899         for (i = 0; i < dev->info->mib_cnt; i++) {
 900                 memcpy(buf + i * ETH_GSTRING_LEN,
 901                        dev->info->mib_names[i].string, ETH_GSTRING_LEN);
 902         }
 903 }
 904
 905 static void ksz_update_port_member(struct ksz_device *dev, int port)
 906 {
 907         struct ksz_port *p = &dev->ports[port];
 908         struct dsa_switch *ds = dev->ds;
 909         u8 port_member = 0, cpu_port;
 910         const struct dsa_port *dp;
 911         int i, j;
 912
 913         if (!dsa_is_user_port(ds, port))
 914                 return;
 915
 916         dp = dsa_to_port(ds, port);
 917         cpu_port = BIT(dsa_upstream_port(ds, port));
 918
 919         for (i = 0; i < ds->num_ports; i++) {
 920                 const struct dsa_port *other_dp = dsa_to_port(ds, i);
 921                 struct ksz_port *other_p = &dev->ports[i];
 922                 u8 val = 0;
 923
 924                 if (!dsa_is_user_port(ds, i))
 925                         continue;
 926                 if (port == i)
 927                         continue;
 928                 if (!dsa_port_bridge_same(dp, other_dp))
 929                         continue;
 930                 if (other_p->stp_state != BR_STATE_FORWARDING)
 931                         continue;
 932
 933                 if (p->stp_state == BR_STATE_FORWARDING) {
 934                         val |= BIT(port);
 935                         port_member |= BIT(i);
 936                 }
 937
 938                 /* Retain port [i]'s relationship to other ports than [port] */
 939                 for (j = 0; j < ds->num_ports; j++) {
 940                         const struct dsa_port *third_dp;
 941                         struct ksz_port *third_p;
 942
 943                         if (j == i)
 944                                 continue;
 945                         if (j == port)
 946                                 continue;
 947                         if (!dsa_is_user_port(ds, j))
 948                                 continue;
 949                         third_p = &dev->ports[j];
 950                         if (third_p->stp_state != BR_STATE_FORWARDING)
 951                                 continue;
 952                         third_dp = dsa_to_port(ds, j);
 953                         if (dsa_port_bridge_same(other_dp, third_dp))
 954                                 val |= BIT(j);
 955                 }
 956
 957                 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
 958         }
 959
 960         dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
 961 }
 962
 963 static int ksz_setup(struct dsa_switch *ds)
 964 {
 965         struct ksz_device *dev = ds->priv;
 966         const u16 *regs;
 967         int ret;
 968
 969         regs = dev->info->regs;
 970
 971         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
 972                                        dev->info->num_vlans, GFP_KERNEL);
 973         if (!dev->vlan_cache)
 974                 return -ENOMEM;
 975
 976         ret = dev->dev_ops->reset(dev);
 977         if (ret) {
 978                 dev_err(ds->dev, "failed to reset switch\n");
 979                 return ret;
 980         }
 981
 982         /* set broadcast storm protection 10% rate */
 983         regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
 984                            BROADCAST_STORM_RATE,
 985                            (BROADCAST_STORM_VALUE *
 986                            BROADCAST_STORM_PROT_RATE) / 100);
 987
 988         dev->dev_ops->config_cpu_port(ds);
 989
 990         dev->dev_ops->enable_stp_addr(dev);
 991
 992         regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
 993                            MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
 994
 995         ksz_init_mib_timer(dev);
 996
 997         ds->configure_vlan_while_not_filtering = false;
 998
 999         if (dev->dev_ops->setup) {
1000                 ret = dev->dev_ops->setup(ds);
1001                 if (ret)
1002                         return ret;
1003         }
1004
1005         /* start switch */
1006         regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
1007                            SW_START, SW_START);
1008
1009         return 0;
1010 }
1011
1012 static void port_r_cnt(struct ksz_device *dev, int port)
1013 {
1014         struct ksz_port_mib *mib = &dev->ports[port].mib;
1015         u64 *dropped;
1016
1017         /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
1018         while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
1019                 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
1020                                         &mib->counters[mib->cnt_ptr]);
1021                 ++mib->cnt_ptr;
1022         }
1023
1024         /* last one in storage */
1025         dropped = &mib->counters[dev->info->mib_cnt];
1026
1027         /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
1028         while (mib->cnt_ptr < dev->info->mib_cnt) {
1029                 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
1030                                         dropped, &mib->counters[mib->cnt_ptr]);
1031                 ++mib->cnt_ptr;
1032         }
1033         mib->cnt_ptr = 0;
1034 }
1035
1036 static void ksz_mib_read_work(struct work_struct *work)
1037 {
1038         struct ksz_device *dev = container_of(work, struct ksz_device,
1039                                               mib_read.work);
1040         struct ksz_port_mib *mib;
1041         struct ksz_port *p;
1042         int i;
1043
1044         for (i = 0; i < dev->info->port_cnt; i++) {
1045                 if (dsa_is_unused_port(dev->ds, i))
1046                         continue;
1047
1048                 p = &dev->ports[i];
1049                 mib = &p->mib;
1050                 mutex_lock(&mib->cnt_mutex);
1051
1052                 /* Only read MIB counters when the port is told to do.
1053                  * If not, read only dropped counters when link is not up.
1054                  */
1055                 if (!p->read) {
1056                         const struct dsa_port *dp = dsa_to_port(dev->ds, i);
1057
1058                         if (!netif_carrier_ok(dp->slave))
1059                                 mib->cnt_ptr = dev->info->reg_mib_cnt;
1060                 }
1061                 port_r_cnt(dev, i);
1062                 p->read = false;
1063
1064                 if (dev->dev_ops->r_mib_stat64)
1065                         dev->dev_ops->r_mib_stat64(dev, i);
1066
1067                 mutex_unlock(&mib->cnt_mutex);
1068         }
1069
1070         schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
1071 }
1072
1073 void ksz_init_mib_timer(struct ksz_device *dev)
1074 {
1075         int i;
1076
1077         INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
1078
1079         for (i = 0; i < dev->info->port_cnt; i++) {
1080                 struct ksz_port_mib *mib = &dev->ports[i].mib;
1081
1082                 dev->dev_ops->port_init_cnt(dev, i);
1083
1084                 mib->cnt_ptr = 0;
1085                 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
1086         }
1087 }
1088
1089 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
1090 {
1091         struct ksz_device *dev = ds->priv;
1092         u16 val = 0xffff;
1093
1094         dev->dev_ops->r_phy(dev, addr, reg, &val);
1095
1096         return val;
1097 }
1098
1099 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
1100 {
1101         struct ksz_device *dev = ds->priv;
1102
1103         dev->dev_ops->w_phy(dev, addr, reg, val);
1104
1105         return 0;
1106 }
1107
1108 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
1109 {
1110         struct ksz_device *dev = ds->priv;
1111
1112         if (dev->chip_id == KSZ8830_CHIP_ID) {
1113                 /* Silicon Errata Sheet (DS80000830A):
1114                  * Port 1 does not work with LinkMD Cable-Testing.
1115                  * Port 1 does not respond to received PAUSE control frames.
1116                  */
1117                 if (!port)
1118                         return MICREL_KSZ8_P1_ERRATA;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
1125                               unsigned int mode, phy_interface_t interface)
1126 {
1127         struct ksz_device *dev = ds->priv;
1128         struct ksz_port *p = &dev->ports[port];
1129
1130         /* Read all MIB counters when the link is going down. */
1131         p->read = true;
1132         /* timer started */
1133         if (dev->mib_read_interval)
1134                 schedule_delayed_work(&dev->mib_read, 0);
1135 }
1136
1137 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
1138 {
1139         struct ksz_device *dev = ds->priv;
1140
1141         if (sset != ETH_SS_STATS)
1142                 return 0;
1143
1144         return dev->info->mib_cnt;
1145 }
1146
1147 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
1148                                   uint64_t *buf)
1149 {
1150         const struct dsa_port *dp = dsa_to_port(ds, port);
1151         struct ksz_device *dev = ds->priv;
1152         struct ksz_port_mib *mib;
1153
1154         mib = &dev->ports[port].mib;
1155         mutex_lock(&mib->cnt_mutex);
1156
1157         /* Only read dropped counters if no link. */
1158         if (!netif_carrier_ok(dp->slave))
1159                 mib->cnt_ptr = dev->info->reg_mib_cnt;
1160         port_r_cnt(dev, port);
1161         memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
1162         mutex_unlock(&mib->cnt_mutex);
1163 }
1164
1165 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
1166                                 struct dsa_bridge bridge,
1167                                 bool *tx_fwd_offload,
1168                                 struct netlink_ext_ack *extack)
1169 {
1170         /* port_stp_state_set() will be called after to put the port in
1171          * appropriate state so there is no need to do anything.
1172          */
1173
1174         return 0;
1175 }
1176
1177 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
1178                                   struct dsa_bridge bridge)
1179 {
1180         /* port_stp_state_set() will be called after to put the port in
1181          * forwarding state so there is no need to do anything.
1182          */
1183 }
1184
1185 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
1186 {
1187         struct ksz_device *dev = ds->priv;
1188
1189         dev->dev_ops->flush_dyn_mac_table(dev, port);
1190 }
1191
1192 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
1193                             const unsigned char *addr, u16 vid,
1194                             struct dsa_db db)
1195 {
1196         struct ksz_device *dev = ds->priv;
1197
1198         if (!dev->dev_ops->fdb_add)
1199                 return -EOPNOTSUPP;
1200
1201         return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
1202 }
1203
1204 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
1205                             const unsigned char *addr,
1206                             u16 vid, struct dsa_db db)
1207 {
1208         struct ksz_device *dev = ds->priv;
1209
1210         if (!dev->dev_ops->fdb_del)
1211                 return -EOPNOTSUPP;
1212
1213         return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
1214 }
1215
1216 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
1217                              dsa_fdb_dump_cb_t *cb, void *data)
1218 {
1219         struct ksz_device *dev = ds->priv;
1220
1221         if (!dev->dev_ops->fdb_dump)
1222                 return -EOPNOTSUPP;
1223
1224         return dev->dev_ops->fdb_dump(dev, port, cb, data);
1225 }
1226
1227 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
1228                             const struct switchdev_obj_port_mdb *mdb,
1229                             struct dsa_db db)
1230 {
1231         struct ksz_device *dev = ds->priv;
1232
1233         if (!dev->dev_ops->mdb_add)
1234                 return -EOPNOTSUPP;
1235
1236         return dev->dev_ops->mdb_add(dev, port, mdb, db);
1237 }
1238
1239 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
1240                             const struct switchdev_obj_port_mdb *mdb,
1241                             struct dsa_db db)
1242 {
1243         struct ksz_device *dev = ds->priv;
1244
1245         if (!dev->dev_ops->mdb_del)
1246                 return -EOPNOTSUPP;
1247
1248         return dev->dev_ops->mdb_del(dev, port, mdb, db);
1249 }
1250
1251 static int ksz_enable_port(struct dsa_switch *ds, int port,
1252                            struct phy_device *phy)
1253 {
1254         struct ksz_device *dev = ds->priv;
1255
1256         if (!dsa_is_user_port(ds, port))
1257                 return 0;
1258
1259         /* setup slave port */
1260         dev->dev_ops->port_setup(dev, port, false);
1261
1262         /* port_stp_state_set() will be called after to enable the port so
1263          * there is no need to do anything.
1264          */
1265
1266         return 0;
1267 }
1268
1269 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1270 {
1271         struct ksz_device *dev = ds->priv;
1272         struct ksz_port *p;
1273         const u16 *regs;
1274         u8 data;
1275
1276         regs = dev->info->regs;
1277
1278         ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
1279         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1280
1281         switch (state) {
1282         case BR_STATE_DISABLED:
1283                 data |= PORT_LEARN_DISABLE;
1284                 break;
1285         case BR_STATE_LISTENING:
1286                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1287                 break;
1288         case BR_STATE_LEARNING:
1289                 data |= PORT_RX_ENABLE;
1290                 break;
1291         case BR_STATE_FORWARDING:
1292                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
1293                 break;
1294         case BR_STATE_BLOCKING:
1295                 data |= PORT_LEARN_DISABLE;
1296                 break;
1297         default:
1298                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1299                 return;
1300         }
1301
1302         ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
1303
1304         p = &dev->ports[port];
1305         p->stp_state = state;
1306
1307         ksz_update_port_member(dev, port);
1308 }
1309
1310 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
1311                                                   int port,
1312                                                   enum dsa_tag_protocol mp)
1313 {
1314         struct ksz_device *dev = ds->priv;
1315         enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
1316
1317         if (dev->chip_id == KSZ8795_CHIP_ID ||
1318             dev->chip_id == KSZ8794_CHIP_ID ||
1319             dev->chip_id == KSZ8765_CHIP_ID)
1320                 proto = DSA_TAG_PROTO_KSZ8795;
1321
1322         if (dev->chip_id == KSZ8830_CHIP_ID ||
1323             dev->chip_id == KSZ9893_CHIP_ID)
1324                 proto = DSA_TAG_PROTO_KSZ9893;
1325
1326         if (dev->chip_id == KSZ9477_CHIP_ID ||
1327             dev->chip_id == KSZ9897_CHIP_ID ||
1328             dev->chip_id == KSZ9567_CHIP_ID)
1329                 proto = DSA_TAG_PROTO_KSZ9477;
1330
1331         if (is_lan937x(dev))
1332                 proto = DSA_TAG_PROTO_LAN937X_VALUE;
1333
1334         return proto;
1335 }
1336
1337 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
1338                                    bool flag, struct netlink_ext_ack *extack)
1339 {
1340         struct ksz_device *dev = ds->priv;
1341
1342         if (!dev->dev_ops->vlan_filtering)
1343                 return -EOPNOTSUPP;
1344
1345         return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
1346 }
1347
1348 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
1349                              const struct switchdev_obj_port_vlan *vlan,
1350                              struct netlink_ext_ack *extack)
1351 {
1352         struct ksz_device *dev = ds->priv;
1353
1354         if (!dev->dev_ops->vlan_add)
1355                 return -EOPNOTSUPP;
1356
1357         return dev->dev_ops->vlan_add(dev, port, vlan, extack);
1358 }
1359
1360 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
1361                              const struct switchdev_obj_port_vlan *vlan)
1362 {
1363         struct ksz_device *dev = ds->priv;
1364
1365         if (!dev->dev_ops->vlan_del)
1366                 return -EOPNOTSUPP;
1367
1368         return dev->dev_ops->vlan_del(dev, port, vlan);
1369 }
1370
1371 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
1372                                struct dsa_mall_mirror_tc_entry *mirror,
1373                                bool ingress, struct netlink_ext_ack *extack)
1374 {
1375         struct ksz_device *dev = ds->priv;
1376
1377         if (!dev->dev_ops->mirror_add)
1378                 return -EOPNOTSUPP;
1379
1380         return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
1381 }
1382
1383 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
1384                                 struct dsa_mall_mirror_tc_entry *mirror)
1385 {
1386         struct ksz_device *dev = ds->priv;
1387
1388         if (dev->dev_ops->mirror_del)
1389                 dev->dev_ops->mirror_del(dev, port, mirror);
1390 }
1391
1392 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
1393 {
1394         struct ksz_device *dev = ds->priv;
1395
1396         if (!dev->dev_ops->change_mtu)
1397                 return -EOPNOTSUPP;
1398
1399         return dev->dev_ops->change_mtu(dev, port, mtu);
1400 }
1401
1402 static int ksz_max_mtu(struct dsa_switch *ds, int port)
1403 {
1404         struct ksz_device *dev = ds->priv;
1405
1406         if (!dev->dev_ops->max_mtu)
1407                 return -EOPNOTSUPP;
1408
1409         return dev->dev_ops->max_mtu(dev, port);
1410 }
1411
1412 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
1413 {
1414         const u8 *bitval = dev->info->xmii_ctrl1;
1415         struct ksz_port *p = &dev->ports[port];
1416         const u16 *regs = dev->info->regs;
1417         u8 data8;
1418
1419         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1420
1421         data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
1422                    P_RGMII_ID_EG_ENABLE);
1423
1424         switch (interface) {
1425         case PHY_INTERFACE_MODE_MII:
1426                 data8 |= bitval[P_MII_SEL];
1427                 break;
1428         case PHY_INTERFACE_MODE_RMII:
1429                 data8 |= bitval[P_RMII_SEL];
1430                 break;
1431         case PHY_INTERFACE_MODE_GMII:
1432                 data8 |= bitval[P_GMII_SEL];
1433                 break;
1434         case PHY_INTERFACE_MODE_RGMII:
1435         case PHY_INTERFACE_MODE_RGMII_ID:
1436         case PHY_INTERFACE_MODE_RGMII_TXID:
1437         case PHY_INTERFACE_MODE_RGMII_RXID:
1438                 data8 |= bitval[P_RGMII_SEL];
1439                 break;
1440         default:
1441                 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
1442                         phy_modes(interface), port);
1443                 return;
1444         }
1445
1446         if (p->rgmii_tx_val)
1447                 data8 |= P_RGMII_ID_EG_ENABLE;
1448
1449         if (p->rgmii_rx_val)
1450                 data8 |= P_RGMII_ID_IG_ENABLE;
1451
1452         /* Write the updated value */
1453         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
1454 }
1455
1456 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
1457                                    unsigned int mode,
1458                                    const struct phylink_link_state *state)
1459 {
1460         struct ksz_device *dev = ds->priv;
1461
1462         if (dev->dev_ops->phylink_mac_config)
1463                 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
1464
1465         if (dev->dev_ops->setup_rgmii_delay)
1466                 dev->dev_ops->setup_rgmii_delay(dev, port);
1467 }
1468
1469 bool ksz_get_gbit(struct ksz_device *dev, int port)
1470 {
1471         const u8 *bitval = dev->info->xmii_ctrl1;
1472         const u16 *regs = dev->info->regs;
1473         bool gbit = false;
1474         u8 data8;
1475         bool val;
1476
1477         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1478
1479         val = FIELD_GET(P_GMII_1GBIT_M, data8);
1480
1481         if (val == bitval[P_GMII_1GBIT])
1482                 gbit = true;
1483
1484         return gbit;
1485 }
1486
1487 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
1488 {
1489         const u8 *bitval = dev->info->xmii_ctrl1;
1490         const u16 *regs = dev->info->regs;
1491         u8 data8;
1492
1493         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
1494
1495         data8 &= ~P_GMII_1GBIT_M;
1496
1497         if (gbit)
1498                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
1499         else
1500                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
1501
1502         /* Write the updated value */
1503         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
1504 }
1505
1506 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
1507 {
1508         const u8 *bitval = dev->info->xmii_ctrl0;
1509         const u16 *regs = dev->info->regs;
1510         u8 data8;
1511
1512         ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
1513
1514         data8 &= ~P_MII_100MBIT_M;
1515
1516         if (speed == SPEED_100)
1517                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
1518         else
1519                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
1520
1521         /* Write the updated value */
1522         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
1523 }
1524
1525 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
1526 {
1527         if (speed == SPEED_1000)
1528                 ksz_set_gbit(dev, port, true);
1529         else
1530                 ksz_set_gbit(dev, port, false);
1531
1532         if (speed == SPEED_100 || speed == SPEED_10)
1533                 ksz_set_100_10mbit(dev, port, speed);
1534 }
1535
1536 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
1537                                 bool tx_pause, bool rx_pause)
1538 {
1539         const u8 *bitval = dev->info->xmii_ctrl0;
1540         const u32 *masks = dev->info->masks;
1541         const u16 *regs = dev->info->regs;
1542         u8 mask;
1543         u8 val;
1544
1545         mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
1546                masks[P_MII_RX_FLOW_CTRL];
1547
1548         if (duplex == DUPLEX_FULL)
1549                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
1550         else
1551                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
1552
1553         if (tx_pause)
1554                 val |= masks[P_MII_TX_FLOW_CTRL];
1555
1556         if (rx_pause)
1557                 val |= masks[P_MII_RX_FLOW_CTRL];
1558
1559         ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
1560 }
1561
1562 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
1563                                     unsigned int mode,
1564                                     phy_interface_t interface,
1565                                     struct phy_device *phydev, int speed,
1566                                     int duplex, bool tx_pause, bool rx_pause)
1567 {
1568         struct ksz_device *dev = ds->priv;
1569         struct ksz_port *p;
1570
1571         p = &dev->ports[port];
1572
1573         /* Internal PHYs */
1574         if (dev->info->internal_phy[port])
1575                 return;
1576
1577         p->phydev.speed = speed;
1578
1579         ksz_port_set_xmii_speed(dev, port, speed);
1580
1581         ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
1582
1583         if (dev->dev_ops->phylink_mac_link_up)
1584                 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
1585                                                   phydev, speed, duplex,
1586                                                   tx_pause, rx_pause);
1587 }
1588
1589 static int ksz_switch_detect(struct ksz_device *dev)
1590 {
1591         u8 id1, id2;
1592         u16 id16;
1593         u32 id32;
1594         int ret;
1595
1596         /* read chip id */
1597         ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1598         if (ret)
1599                 return ret;
1600
1601         id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
1602         id2 = FIELD_GET(SW_CHIP_ID_M, id16);
1603
1604         switch (id1) {
1605         case KSZ87_FAMILY_ID:
1606                 if (id2 == KSZ87_CHIP_ID_95) {
1607                         u8 val;
1608
1609                         dev->chip_id = KSZ8795_CHIP_ID;
1610
1611                         ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
1612                         if (val & KSZ8_PORT_FIBER_MODE)
1613                                 dev->chip_id = KSZ8765_CHIP_ID;
1614                 } else if (id2 == KSZ87_CHIP_ID_94) {
1615                         dev->chip_id = KSZ8794_CHIP_ID;
1616                 } else {
1617                         return -ENODEV;
1618                 }
1619                 break;
1620         case KSZ88_FAMILY_ID:
1621                 if (id2 == KSZ88_CHIP_ID_63)
1622                         dev->chip_id = KSZ8830_CHIP_ID;
1623                 else
1624                         return -ENODEV;
1625                 break;
1626         default:
1627                 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
1628                 if (ret)
1629                         return ret;
1630
1631                 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
1632                 id32 &= ~0xFF;
1633
1634                 switch (id32) {
1635                 case KSZ9477_CHIP_ID:
1636                 case KSZ9897_CHIP_ID:
1637                 case KSZ9893_CHIP_ID:
1638                 case KSZ9567_CHIP_ID:
1639                 case LAN9370_CHIP_ID:
1640                 case LAN9371_CHIP_ID:
1641                 case LAN9372_CHIP_ID:
1642                 case LAN9373_CHIP_ID:
1643                 case LAN9374_CHIP_ID:
1644                         dev->chip_id = id32;
1645                         break;
1646                 default:
1647                         dev_err(dev->dev,
1648                                 "unsupported switch detected %x)\n", id32);
1649                         return -ENODEV;
1650                 }
1651         }
1652         return 0;
1653 }
1654
1655 static const struct dsa_switch_ops ksz_switch_ops = {
1656         .get_tag_protocol       = ksz_get_tag_protocol,
1657         .get_phy_flags          = ksz_get_phy_flags,
1658         .setup                  = ksz_setup,
1659         .phy_read               = ksz_phy_read16,
1660         .phy_write              = ksz_phy_write16,
1661         .phylink_get_caps       = ksz_phylink_get_caps,
1662         .phylink_mac_config     = ksz_phylink_mac_config,
1663         .phylink_mac_link_up    = ksz_phylink_mac_link_up,
1664         .phylink_mac_link_down  = ksz_mac_link_down,
1665         .port_enable            = ksz_enable_port,
1666         .get_strings            = ksz_get_strings,
1667         .get_ethtool_stats      = ksz_get_ethtool_stats,
1668         .get_sset_count         = ksz_sset_count,
1669         .port_bridge_join       = ksz_port_bridge_join,
1670         .port_bridge_leave      = ksz_port_bridge_leave,
1671         .port_stp_state_set     = ksz_port_stp_state_set,
1672         .port_fast_age          = ksz_port_fast_age,
1673         .port_vlan_filtering    = ksz_port_vlan_filtering,
1674         .port_vlan_add          = ksz_port_vlan_add,
1675         .port_vlan_del          = ksz_port_vlan_del,
1676         .port_fdb_dump          = ksz_port_fdb_dump,
1677         .port_fdb_add           = ksz_port_fdb_add,
1678         .port_fdb_del           = ksz_port_fdb_del,
1679         .port_mdb_add           = ksz_port_mdb_add,
1680         .port_mdb_del           = ksz_port_mdb_del,
1681         .port_mirror_add        = ksz_port_mirror_add,
1682         .port_mirror_del        = ksz_port_mirror_del,
1683         .get_stats64            = ksz_get_stats64,
1684         .get_pause_stats        = ksz_get_pause_stats,
1685         .port_change_mtu        = ksz_change_mtu,
1686         .port_max_mtu           = ksz_max_mtu,
1687 };
1688
1689 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
1690 {
1691         struct dsa_switch *ds;
1692         struct ksz_device *swdev;
1693
1694         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
1695         if (!ds)
1696                 return NULL;
1697
1698         ds->dev = base;
1699         ds->num_ports = DSA_MAX_PORTS;
1700         ds->ops = &ksz_switch_ops;
1701
1702         swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
1703         if (!swdev)
1704                 return NULL;
1705
1706         ds->priv = swdev;
1707         swdev->dev = base;
1708
1709         swdev->ds = ds;
1710         swdev->priv = priv;
1711
1712         return swdev;
1713 }
1714 EXPORT_SYMBOL(ksz_switch_alloc);
1715
1716 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
1717                                   struct device_node *port_dn)
1718 {
1719         phy_interface_t phy_mode = dev->ports[port_num].interface;
1720         int rx_delay = -1, tx_delay = -1;
1721
1722         if (!phy_interface_mode_is_rgmii(phy_mode))
1723                 return;
1724
1725         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1726         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1727
1728         if (rx_delay == -1 && tx_delay == -1) {
1729                 dev_warn(dev->dev,
1730                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1731                          "please update device tree to specify \"rx-internal-delay-ps\" and "
1732                          "\"tx-internal-delay-ps\"",
1733                          port_num);
1734
1735                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1736                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1737                         rx_delay = 2000;
1738
1739                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1740                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1741                         tx_delay = 2000;
1742         }
1743
1744         if (rx_delay < 0)
1745                 rx_delay = 0;
1746         if (tx_delay < 0)
1747                 tx_delay = 0;
1748
1749         dev->ports[port_num].rgmii_rx_val = rx_delay;
1750         dev->ports[port_num].rgmii_tx_val = tx_delay;
1751 }
1752
1753 int ksz_switch_register(struct ksz_device *dev)
1754 {
1755         const struct ksz_chip_data *info;
1756         struct device_node *port, *ports;
1757         phy_interface_t interface;
1758         unsigned int port_num;
1759         int ret;
1760         int i;
1761
1762         if (dev->pdata)
1763                 dev->chip_id = dev->pdata->chip_id;
1764
1765         dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
1766                                                   GPIOD_OUT_LOW);
1767         if (IS_ERR(dev->reset_gpio))
1768                 return PTR_ERR(dev->reset_gpio);
1769
1770         if (dev->reset_gpio) {
1771                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
1772                 usleep_range(10000, 12000);
1773                 gpiod_set_value_cansleep(dev->reset_gpio, 0);
1774                 msleep(100);
1775         }
1776
1777         mutex_init(&dev->dev_mutex);
1778         mutex_init(&dev->regmap_mutex);
1779         mutex_init(&dev->alu_mutex);
1780         mutex_init(&dev->vlan_mutex);
1781
1782         ret = ksz_switch_detect(dev);
1783         if (ret)
1784                 return ret;
1785
1786         info = ksz_lookup_info(dev->chip_id);
1787         if (!info)
1788                 return -ENODEV;
1789
1790         /* Update the compatible info with the probed one */
1791         dev->info = info;
1792
1793         dev_info(dev->dev, "found switch: %s, rev %i\n",
1794                  dev->info->dev_name, dev->chip_rev);
1795
1796         ret = ksz_check_device_id(dev);
1797         if (ret)
1798                 return ret;
1799
1800         dev->dev_ops = dev->info->ops;
1801
1802         ret = dev->dev_ops->init(dev);
1803         if (ret)
1804                 return ret;
1805
1806         dev->ports = devm_kzalloc(dev->dev,
1807                                   dev->info->port_cnt * sizeof(struct ksz_port),
1808                                   GFP_KERNEL);
1809         if (!dev->ports)
1810                 return -ENOMEM;
1811
1812         for (i = 0; i < dev->info->port_cnt; i++) {
1813                 spin_lock_init(&dev->ports[i].mib.stats64_lock);
1814                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1815                 dev->ports[i].mib.counters =
1816                         devm_kzalloc(dev->dev,
1817                                      sizeof(u64) * (dev->info->mib_cnt + 1),
1818                                      GFP_KERNEL);
1819                 if (!dev->ports[i].mib.counters)
1820                         return -ENOMEM;
1821         }
1822
1823         /* set the real number of ports */
1824         dev->ds->num_ports = dev->info->port_cnt;
1825
1826         /* Host port interface will be self detected, or specifically set in
1827          * device tree.
1828          */
1829         for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
1830                 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
1831         if (dev->dev->of_node) {
1832                 ret = of_get_phy_mode(dev->dev->of_node, &interface);
1833                 if (ret == 0)
1834                         dev->compat_interface = interface;
1835                 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
1836                 if (!ports)
1837                         ports = of_get_child_by_name(dev->dev->of_node, "ports");
1838                 if (ports) {
1839                         for_each_available_child_of_node(ports, port) {
1840                                 if (of_property_read_u32(port, "reg",
1841                                                          &port_num))
1842                                         continue;
1843                                 if (!(dev->port_mask & BIT(port_num))) {
1844                                         of_node_put(port);
1845                                         of_node_put(ports);
1846                                         return -EINVAL;
1847                                 }
1848                                 of_get_phy_mode(port,
1849                                                 &dev->ports[port_num].interface);
1850
1851                                 ksz_parse_rgmii_delay(dev, port_num, port);
1852                         }
1853                         of_node_put(ports);
1854                 }
1855                 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
1856                                                          "microchip,synclko-125");
1857                 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
1858                                                              "microchip,synclko-disable");
1859                 if (dev->synclko_125 && dev->synclko_disable) {
1860                         dev_err(dev->dev, "inconsistent synclko settings\n");
1861                         return -EINVAL;
1862                 }
1863         }
1864
1865         ret = dsa_register_switch(dev->ds);
1866         if (ret) {
1867                 dev->dev_ops->exit(dev);
1868                 return ret;
1869         }
1870
1871         /* Read MIB counters every 30 seconds to avoid overflow. */
1872         dev->mib_read_interval = msecs_to_jiffies(5000);
1873
1874         /* Start the MIB timer. */
1875         schedule_delayed_work(&dev->mib_read, 0);
1876
1877         return ret;
1878 }
1879 EXPORT_SYMBOL(ksz_switch_register);
1880
1881 void ksz_switch_remove(struct ksz_device *dev)
1882 {
1883         /* timer started */
1884         if (dev->mib_read_interval) {
1885                 dev->mib_read_interval = 0;
1886                 cancel_delayed_work_sync(&dev->mib_read);
1887         }
1888
1889         dev->dev_ops->exit(dev);
1890         dsa_unregister_switch(dev->ds);
1891
1892         if (dev->reset_gpio)
1893                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
1894
1895 }
1896 EXPORT_SYMBOL(ksz_switch_remove);
1897
1898 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1899 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
1900 MODULE_LICENSE("GPL");