drivers/net/dsa/microchip/ksz9477.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip KSZ9477 switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_data/microchip-ksz.h>
  12 #include <linux/phy.h>
  13 #include <linux/if_bridge.h>
  14 #include <net/dsa.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ksz9477_reg.h"
  18 #include "ksz_common.h"
  19
  20 /* Used with variable features to indicate capabilities. */
  21 #define GBIT_SUPPORT                    BIT(0)
  22 #define NEW_XMII                        BIT(1)
  23 #define IS_9893                         BIT(2)
  24
  25 static const struct {
  26         int index;
  27         char string[ETH_GSTRING_LEN];
  28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
  29         { 0x00, "rx_hi" },
  30         { 0x01, "rx_undersize" },
  31         { 0x02, "rx_fragments" },
  32         { 0x03, "rx_oversize" },
  33         { 0x04, "rx_jabbers" },
  34         { 0x05, "rx_symbol_err" },
  35         { 0x06, "rx_crc_err" },
  36         { 0x07, "rx_align_err" },
  37         { 0x08, "rx_mac_ctrl" },
  38         { 0x09, "rx_pause" },
  39         { 0x0A, "rx_bcast" },
  40         { 0x0B, "rx_mcast" },
  41         { 0x0C, "rx_ucast" },
  42         { 0x0D, "rx_64_or_less" },
  43         { 0x0E, "rx_65_127" },
  44         { 0x0F, "rx_128_255" },
  45         { 0x10, "rx_256_511" },
  46         { 0x11, "rx_512_1023" },
  47         { 0x12, "rx_1024_1522" },
  48         { 0x13, "rx_1523_2000" },
  49         { 0x14, "rx_2001" },
  50         { 0x15, "tx_hi" },
  51         { 0x16, "tx_late_col" },
  52         { 0x17, "tx_pause" },
  53         { 0x18, "tx_bcast" },
  54         { 0x19, "tx_mcast" },
  55         { 0x1A, "tx_ucast" },
  56         { 0x1B, "tx_deferred" },
  57         { 0x1C, "tx_total_col" },
  58         { 0x1D, "tx_exc_col" },
  59         { 0x1E, "tx_single_col" },
  60         { 0x1F, "tx_mult_col" },
  61         { 0x80, "rx_total" },
  62         { 0x81, "tx_total" },
  63         { 0x82, "rx_discards" },
  64         { 0x83, "tx_discards" },
  65 };
  66
  67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
  68 {
  69         regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
  70 }
  71
  72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
  73                          bool set)
  74 {
  75         regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
  76                            bits, set ? bits : 0);
  77 }
  78
  79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
  80 {
  81         regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
  82 }
  83
  84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
  85                                u32 bits, bool set)
  86 {
  87         regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
  88                            bits, set ? bits : 0);
  89 }
  90
  91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
  92 {
  93         unsigned int val;
  94
  95         return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
  96                                         val, !(val & VLAN_START), 10, 1000);
  97 }
  98
  99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
 100                                   u32 *vlan_table)
 101 {
 102         int ret;
 103
 104         mutex_lock(&dev->vlan_mutex);
 105
 106         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 107         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
 108
 109         /* wait to be cleared */
 110         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 111         if (ret) {
 112                 dev_dbg(dev->dev, "Failed to read vlan table\n");
 113                 goto exit;
 114         }
 115
 116         ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
 117         ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
 118         ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
 119
 120         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 121
 122 exit:
 123         mutex_unlock(&dev->vlan_mutex);
 124
 125         return ret;
 126 }
 127
 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
 129                                   u32 *vlan_table)
 130 {
 131         int ret;
 132
 133         mutex_lock(&dev->vlan_mutex);
 134
 135         ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
 136         ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
 137         ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
 138
 139         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 140         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
 141
 142         /* wait to be cleared */
 143         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 144         if (ret) {
 145                 dev_dbg(dev->dev, "Failed to write vlan table\n");
 146                 goto exit;
 147         }
 148
 149         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 150
 151         /* update vlan cache table */
 152         dev->vlan_cache[vid].table[0] = vlan_table[0];
 153         dev->vlan_cache[vid].table[1] = vlan_table[1];
 154         dev->vlan_cache[vid].table[2] = vlan_table[2];
 155
 156 exit:
 157         mutex_unlock(&dev->vlan_mutex);
 158
 159         return ret;
 160 }
 161
 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
 163 {
 164         ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
 165         ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
 166         ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
 167         ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
 168 }
 169
 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
 171 {
 172         ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
 173         ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
 174         ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
 175         ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
 176 }
 177
 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
 179 {
 180         unsigned int val;
 181
 182         return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
 183                                         val, !(val & ALU_START), 10, 1000);
 184 }
 185
 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
 187 {
 188         unsigned int val;
 189
 190         return regmap_read_poll_timeout(dev->regmap[2],
 191                                         REG_SW_ALU_STAT_CTRL__4,
 192                                         val, !(val & ALU_STAT_START),
 193                                         10, 1000);
 194 }
 195
 196 static int ksz9477_reset_switch(struct ksz_device *dev)
 197 {
 198         u8 data8;
 199         u32 data32;
 200
 201         /* reset switch */
 202         ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
 203
 204         /* turn off SPI DO Edge select */
 205         regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
 206                            SPI_AUTO_EDGE_DETECTION, 0);
 207
 208         /* default configuration */
 209         ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
 210         data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
 211               SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
 212         ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
 213
 214         /* disable interrupts */
 215         ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
 216         ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
 217         ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
 218
 219         /* set broadcast storm protection 10% rate */
 220         regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
 221                            BROADCAST_STORM_RATE,
 222                            (BROADCAST_STORM_VALUE *
 223                            BROADCAST_STORM_PROT_RATE) / 100);
 224
 225         if (dev->synclko_125)
 226                 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 227                            SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
 228
 229         return 0;
 230 }
 231
 232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
 233                               u64 *cnt)
 234 {
 235         struct ksz_port *p = &dev->ports[port];
 236         unsigned int val;
 237         u32 data;
 238         int ret;
 239
 240         /* retain the flush/freeze bit */
 241         data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 242         data |= MIB_COUNTER_READ;
 243         data |= (addr << MIB_COUNTER_INDEX_S);
 244         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
 245
 246         ret = regmap_read_poll_timeout(dev->regmap[2],
 247                         PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
 248                         val, !(val & MIB_COUNTER_READ), 10, 1000);
 249         /* failed to read MIB. get out of loop */
 250         if (ret) {
 251                 dev_dbg(dev->dev, "Failed to get MIB\n");
 252                 return;
 253         }
 254
 255         /* count resets upon read */
 256         ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
 257         *cnt += data;
 258 }
 259
 260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
 261                               u64 *dropped, u64 *cnt)
 262 {
 263         addr = ksz9477_mib_names[addr].index;
 264         ksz9477_r_mib_cnt(dev, port, addr, cnt);
 265 }
 266
 267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
 268 {
 269         u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 270         struct ksz_port *p = &dev->ports[port];
 271
 272         /* enable/disable the port for flush/freeze function */
 273         mutex_lock(&p->mib.cnt_mutex);
 274         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
 275
 276         /* used by MIB counter reading code to know freeze is enabled */
 277         p->freeze = freeze;
 278         mutex_unlock(&p->mib.cnt_mutex);
 279 }
 280
 281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
 282 {
 283         struct ksz_port_mib *mib = &dev->ports[port].mib;
 284
 285         /* flush all enabled port MIB counters */
 286         mutex_lock(&mib->cnt_mutex);
 287         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
 288                      MIB_COUNTER_FLUSH_FREEZE);
 289         ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
 290         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
 291         mutex_unlock(&mib->cnt_mutex);
 292
 293         mib->cnt_ptr = 0;
 294         memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
 295 }
 296
 297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
 298                                                       int port,
 299                                                       enum dsa_tag_protocol mp)
 300 {
 301         enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
 302         struct ksz_device *dev = ds->priv;
 303
 304         if (dev->features & IS_9893)
 305                 proto = DSA_TAG_PROTO_KSZ9893;
 306         return proto;
 307 }
 308
 309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
 310 {
 311         struct ksz_device *dev = ds->priv;
 312         u16 val = 0xffff;
 313
 314         /* No real PHY after this. Simulate the PHY.
 315          * A fixed PHY can be setup in the device tree, but this function is
 316          * still called for that port during initialization.
 317          * For RGMII PHY there is no way to access it so the fixed PHY should
 318          * be used.  For SGMII PHY the supporting code will be added later.
 319          */
 320         if (addr >= dev->phy_port_cnt) {
 321                 struct ksz_port *p = &dev->ports[addr];
 322
 323                 switch (reg) {
 324                 case MII_BMCR:
 325                         val = 0x1140;
 326                         break;
 327                 case MII_BMSR:
 328                         val = 0x796d;
 329                         break;
 330                 case MII_PHYSID1:
 331                         val = 0x0022;
 332                         break;
 333                 case MII_PHYSID2:
 334                         val = 0x1631;
 335                         break;
 336                 case MII_ADVERTISE:
 337                         val = 0x05e1;
 338                         break;
 339                 case MII_LPA:
 340                         val = 0xc5e1;
 341                         break;
 342                 case MII_CTRL1000:
 343                         val = 0x0700;
 344                         break;
 345                 case MII_STAT1000:
 346                         if (p->phydev.speed == SPEED_1000)
 347                                 val = 0x3800;
 348                         else
 349                                 val = 0;
 350                         break;
 351                 }
 352         } else {
 353                 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
 354         }
 355
 356         return val;
 357 }
 358
 359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
 360                                u16 val)
 361 {
 362         struct ksz_device *dev = ds->priv;
 363
 364         /* No real PHY after this. */
 365         if (addr >= dev->phy_port_cnt)
 366                 return 0;
 367
 368         /* No gigabit support.  Do not write to this register. */
 369         if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
 370                 return 0;
 371         ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
 372
 373         return 0;
 374 }
 375
 376 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
 377                                 u32 stringset, uint8_t *buf)
 378 {
 379         int i;
 380
 381         if (stringset != ETH_SS_STATS)
 382                 return;
 383
 384         for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
 385                 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
 386                        ETH_GSTRING_LEN);
 387         }
 388 }
 389
 390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
 391                                     u8 member)
 392 {
 393         ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
 394         dev->ports[port].member = member;
 395 }
 396
 397 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
 398                                        u8 state)
 399 {
 400         struct ksz_device *dev = ds->priv;
 401         struct ksz_port *p = &dev->ports[port];
 402         u8 data;
 403         int member = -1;
 404         int forward = dev->member;
 405
 406         ksz_pread8(dev, port, P_STP_CTRL, &data);
 407         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 408
 409         switch (state) {
 410         case BR_STATE_DISABLED:
 411                 data |= PORT_LEARN_DISABLE;
 412                 if (port != dev->cpu_port)
 413                         member = 0;
 414                 break;
 415         case BR_STATE_LISTENING:
 416                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 417                 if (port != dev->cpu_port &&
 418                     p->stp_state == BR_STATE_DISABLED)
 419                         member = dev->host_mask | p->vid_member;
 420                 break;
 421         case BR_STATE_LEARNING:
 422                 data |= PORT_RX_ENABLE;
 423                 break;
 424         case BR_STATE_FORWARDING:
 425                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
 426
 427                 /* This function is also used internally. */
 428                 if (port == dev->cpu_port)
 429                         break;
 430
 431                 member = dev->host_mask | p->vid_member;
 432                 mutex_lock(&dev->dev_mutex);
 433
 434                 /* Port is a member of a bridge. */
 435                 if (dev->br_member & (1 << port)) {
 436                         dev->member |= (1 << port);
 437                         member = dev->member;
 438                 }
 439                 mutex_unlock(&dev->dev_mutex);
 440                 break;
 441         case BR_STATE_BLOCKING:
 442                 data |= PORT_LEARN_DISABLE;
 443                 if (port != dev->cpu_port &&
 444                     p->stp_state == BR_STATE_DISABLED)
 445                         member = dev->host_mask | p->vid_member;
 446                 break;
 447         default:
 448                 dev_err(ds->dev, "invalid STP state: %d\n", state);
 449                 return;
 450         }
 451
 452         ksz_pwrite8(dev, port, P_STP_CTRL, data);
 453         p->stp_state = state;
 454         mutex_lock(&dev->dev_mutex);
 455         /* Port membership may share register with STP state. */
 456         if (member >= 0 && member != p->member)
 457                 ksz9477_cfg_port_member(dev, port, (u8)member);
 458
 459         /* Check if forwarding needs to be updated. */
 460         if (state != BR_STATE_FORWARDING) {
 461                 if (dev->br_member & (1 << port))
 462                         dev->member &= ~(1 << port);
 463         }
 464
 465         /* When topology has changed the function ksz_update_port_member
 466          * should be called to modify port forwarding behavior.
 467          */
 468         if (forward != dev->member)
 469                 ksz_update_port_member(dev, port);
 470         mutex_unlock(&dev->dev_mutex);
 471 }
 472
 473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
 474 {
 475         u8 data;
 476
 477         regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
 478                            SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
 479                            SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
 480
 481         if (port < dev->port_cnt) {
 482                 /* flush individual port */
 483                 ksz_pread8(dev, port, P_STP_CTRL, &data);
 484                 if (!(data & PORT_LEARN_DISABLE))
 485                         ksz_pwrite8(dev, port, P_STP_CTRL,
 486                                     data | PORT_LEARN_DISABLE);
 487                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
 488                 ksz_pwrite8(dev, port, P_STP_CTRL, data);
 489         } else {
 490                 /* flush all */
 491                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
 492         }
 493 }
 494
 495 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
 496                                        bool flag)
 497 {
 498         struct ksz_device *dev = ds->priv;
 499
 500         if (flag) {
 501                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 502                              PORT_VLAN_LOOKUP_VID_0, true);
 503                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
 504         } else {
 505                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
 506                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 507                              PORT_VLAN_LOOKUP_VID_0, false);
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
 514                                  const struct switchdev_obj_port_vlan *vlan)
 515 {
 516         struct ksz_device *dev = ds->priv;
 517         u32 vlan_table[3];
 518         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 519         int err;
 520
 521         err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table);
 522         if (err) {
 523                 dev_dbg(dev->dev, "Failed to get vlan table\n");
 524                 return err;
 525         }
 526
 527         vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M);
 528         if (untagged)
 529                 vlan_table[1] |= BIT(port);
 530         else
 531                 vlan_table[1] &= ~BIT(port);
 532         vlan_table[1] &= ~(BIT(dev->cpu_port));
 533
 534         vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
 535
 536         err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table);
 537         if (err) {
 538                 dev_dbg(dev->dev, "Failed to set vlan table\n");
 539                 return err;
 540         }
 541
 542         /* change PVID */
 543         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
 544                 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid);
 545
 546         return 0;
 547 }
 548
 549 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
 550                                  const struct switchdev_obj_port_vlan *vlan)
 551 {
 552         struct ksz_device *dev = ds->priv;
 553         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 554         u32 vlan_table[3];
 555         u16 pvid;
 556
 557         ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
 558         pvid = pvid & 0xFFF;
 559
 560         if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
 561                 dev_dbg(dev->dev, "Failed to get vlan table\n");
 562                 return -ETIMEDOUT;
 563         }
 564
 565         vlan_table[2] &= ~BIT(port);
 566
 567         if (pvid == vlan->vid)
 568                 pvid = 1;
 569
 570         if (untagged)
 571                 vlan_table[1] &= ~BIT(port);
 572
 573         if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
 574                 dev_dbg(dev->dev, "Failed to set vlan table\n");
 575                 return -ETIMEDOUT;
 576         }
 577
 578         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
 579
 580         return 0;
 581 }
 582
 583 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
 584                                 const unsigned char *addr, u16 vid)
 585 {
 586         struct ksz_device *dev = ds->priv;
 587         u32 alu_table[4];
 588         u32 data;
 589         int ret = 0;
 590
 591         mutex_lock(&dev->alu_mutex);
 592
 593         /* find any entry with mac & vid */
 594         data = vid << ALU_FID_INDEX_S;
 595         data |= ((addr[0] << 8) | addr[1]);
 596         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 597
 598         data = ((addr[2] << 24) | (addr[3] << 16));
 599         data |= ((addr[4] << 8) | addr[5]);
 600         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 601
 602         /* start read operation */
 603         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 604
 605         /* wait to be finished */
 606         ret = ksz9477_wait_alu_ready(dev);
 607         if (ret) {
 608                 dev_dbg(dev->dev, "Failed to read ALU\n");
 609                 goto exit;
 610         }
 611
 612         /* read ALU entry */
 613         ksz9477_read_table(dev, alu_table);
 614
 615         /* update ALU entry */
 616         alu_table[0] = ALU_V_STATIC_VALID;
 617         alu_table[1] |= BIT(port);
 618         if (vid)
 619                 alu_table[1] |= ALU_V_USE_FID;
 620         alu_table[2] = (vid << ALU_V_FID_S);
 621         alu_table[2] |= ((addr[0] << 8) | addr[1]);
 622         alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
 623         alu_table[3] |= ((addr[4] << 8) | addr[5]);
 624
 625         ksz9477_write_table(dev, alu_table);
 626
 627         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 628
 629         /* wait to be finished */
 630         ret = ksz9477_wait_alu_ready(dev);
 631         if (ret)
 632                 dev_dbg(dev->dev, "Failed to write ALU\n");
 633
 634 exit:
 635         mutex_unlock(&dev->alu_mutex);
 636
 637         return ret;
 638 }
 639
 640 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
 641                                 const unsigned char *addr, u16 vid)
 642 {
 643         struct ksz_device *dev = ds->priv;
 644         u32 alu_table[4];
 645         u32 data;
 646         int ret = 0;
 647
 648         mutex_lock(&dev->alu_mutex);
 649
 650         /* read any entry with mac & vid */
 651         data = vid << ALU_FID_INDEX_S;
 652         data |= ((addr[0] << 8) | addr[1]);
 653         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 654
 655         data = ((addr[2] << 24) | (addr[3] << 16));
 656         data |= ((addr[4] << 8) | addr[5]);
 657         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 658
 659         /* start read operation */
 660         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 661
 662         /* wait to be finished */
 663         ret = ksz9477_wait_alu_ready(dev);
 664         if (ret) {
 665                 dev_dbg(dev->dev, "Failed to read ALU\n");
 666                 goto exit;
 667         }
 668
 669         ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
 670         if (alu_table[0] & ALU_V_STATIC_VALID) {
 671                 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
 672                 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
 673                 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
 674
 675                 /* clear forwarding port */
 676                 alu_table[2] &= ~BIT(port);
 677
 678                 /* if there is no port to forward, clear table */
 679                 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
 680                         alu_table[0] = 0;
 681                         alu_table[1] = 0;
 682                         alu_table[2] = 0;
 683                         alu_table[3] = 0;
 684                 }
 685         } else {
 686                 alu_table[0] = 0;
 687                 alu_table[1] = 0;
 688                 alu_table[2] = 0;
 689                 alu_table[3] = 0;
 690         }
 691
 692         ksz9477_write_table(dev, alu_table);
 693
 694         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 695
 696         /* wait to be finished */
 697         ret = ksz9477_wait_alu_ready(dev);
 698         if (ret)
 699                 dev_dbg(dev->dev, "Failed to write ALU\n");
 700
 701 exit:
 702         mutex_unlock(&dev->alu_mutex);
 703
 704         return ret;
 705 }
 706
 707 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
 708 {
 709         alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
 710         alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
 711         alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
 712         alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
 713                         ALU_V_PRIO_AGE_CNT_M;
 714         alu->mstp = alu_table[0] & ALU_V_MSTP_M;
 715
 716         alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
 717         alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
 718         alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
 719
 720         alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
 721
 722         alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
 723         alu->mac[1] = alu_table[2] & 0xFF;
 724         alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
 725         alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
 726         alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
 727         alu->mac[5] = alu_table[3] & 0xFF;
 728 }
 729
 730 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
 731                                  dsa_fdb_dump_cb_t *cb, void *data)
 732 {
 733         struct ksz_device *dev = ds->priv;
 734         int ret = 0;
 735         u32 ksz_data;
 736         u32 alu_table[4];
 737         struct alu_struct alu;
 738         int timeout;
 739
 740         mutex_lock(&dev->alu_mutex);
 741
 742         /* start ALU search */
 743         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
 744
 745         do {
 746                 timeout = 1000;
 747                 do {
 748                         ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
 749                         if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
 750                                 break;
 751                         usleep_range(1, 10);
 752                 } while (timeout-- > 0);
 753
 754                 if (!timeout) {
 755                         dev_dbg(dev->dev, "Failed to search ALU\n");
 756                         ret = -ETIMEDOUT;
 757                         goto exit;
 758                 }
 759
 760                 /* read ALU table */
 761                 ksz9477_read_table(dev, alu_table);
 762
 763                 ksz9477_convert_alu(&alu, alu_table);
 764
 765                 if (alu.port_forward & BIT(port)) {
 766                         ret = cb(alu.mac, alu.fid, alu.is_static, data);
 767                         if (ret)
 768                                 goto exit;
 769                 }
 770         } while (ksz_data & ALU_START);
 771
 772 exit:
 773
 774         /* stop ALU search */
 775         ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
 776
 777         mutex_unlock(&dev->alu_mutex);
 778
 779         return ret;
 780 }
 781
 782 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
 783                                 const struct switchdev_obj_port_mdb *mdb)
 784 {
 785         struct ksz_device *dev = ds->priv;
 786         u32 static_table[4];
 787         u32 data;
 788         int index;
 789         u32 mac_hi, mac_lo;
 790         int err = 0;
 791
 792         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 793         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 794         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 795
 796         mutex_lock(&dev->alu_mutex);
 797
 798         for (index = 0; index < dev->num_statics; index++) {
 799                 /* find empty slot first */
 800                 data = (index << ALU_STAT_INDEX_S) |
 801                         ALU_STAT_READ | ALU_STAT_START;
 802                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 803
 804                 /* wait to be finished */
 805                 err = ksz9477_wait_alu_sta_ready(dev);
 806                 if (err) {
 807                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 808                         goto exit;
 809                 }
 810
 811                 /* read ALU static table */
 812                 ksz9477_read_table(dev, static_table);
 813
 814                 if (static_table[0] & ALU_V_STATIC_VALID) {
 815                         /* check this has same vid & mac address */
 816                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 817                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 818                             static_table[3] == mac_lo) {
 819                                 /* found matching one */
 820                                 break;
 821                         }
 822                 } else {
 823                         /* found empty one */
 824                         break;
 825                 }
 826         }
 827
 828         /* no available entry */
 829         if (index == dev->num_statics) {
 830                 err = -ENOSPC;
 831                 goto exit;
 832         }
 833
 834         /* add entry */
 835         static_table[0] = ALU_V_STATIC_VALID;
 836         static_table[1] |= BIT(port);
 837         if (mdb->vid)
 838                 static_table[1] |= ALU_V_USE_FID;
 839         static_table[2] = (mdb->vid << ALU_V_FID_S);
 840         static_table[2] |= mac_hi;
 841         static_table[3] = mac_lo;
 842
 843         ksz9477_write_table(dev, static_table);
 844
 845         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 846         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 847
 848         /* wait to be finished */
 849         if (ksz9477_wait_alu_sta_ready(dev))
 850                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 851
 852 exit:
 853         mutex_unlock(&dev->alu_mutex);
 854         return err;
 855 }
 856
 857 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
 858                                 const struct switchdev_obj_port_mdb *mdb)
 859 {
 860         struct ksz_device *dev = ds->priv;
 861         u32 static_table[4];
 862         u32 data;
 863         int index;
 864         int ret = 0;
 865         u32 mac_hi, mac_lo;
 866
 867         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 868         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 869         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 870
 871         mutex_lock(&dev->alu_mutex);
 872
 873         for (index = 0; index < dev->num_statics; index++) {
 874                 /* find empty slot first */
 875                 data = (index << ALU_STAT_INDEX_S) |
 876                         ALU_STAT_READ | ALU_STAT_START;
 877                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 878
 879                 /* wait to be finished */
 880                 ret = ksz9477_wait_alu_sta_ready(dev);
 881                 if (ret) {
 882                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 883                         goto exit;
 884                 }
 885
 886                 /* read ALU static table */
 887                 ksz9477_read_table(dev, static_table);
 888
 889                 if (static_table[0] & ALU_V_STATIC_VALID) {
 890                         /* check this has same vid & mac address */
 891
 892                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 893                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 894                             static_table[3] == mac_lo) {
 895                                 /* found matching one */
 896                                 break;
 897                         }
 898                 }
 899         }
 900
 901         /* no available entry */
 902         if (index == dev->num_statics)
 903                 goto exit;
 904
 905         /* clear port */
 906         static_table[1] &= ~BIT(port);
 907
 908         if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
 909                 /* delete entry */
 910                 static_table[0] = 0;
 911                 static_table[1] = 0;
 912                 static_table[2] = 0;
 913                 static_table[3] = 0;
 914         }
 915
 916         ksz9477_write_table(dev, static_table);
 917
 918         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 919         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 920
 921         /* wait to be finished */
 922         ret = ksz9477_wait_alu_sta_ready(dev);
 923         if (ret)
 924                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 925
 926 exit:
 927         mutex_unlock(&dev->alu_mutex);
 928
 929         return ret;
 930 }
 931
 932 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
 933                                    struct dsa_mall_mirror_tc_entry *mirror,
 934                                    bool ingress)
 935 {
 936         struct ksz_device *dev = ds->priv;
 937
 938         if (ingress)
 939                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
 940         else
 941                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
 942
 943         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
 944
 945         /* configure mirror port */
 946         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 947                      PORT_MIRROR_SNIFFER, true);
 948
 949         ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
 950
 951         return 0;
 952 }
 953
 954 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
 955                                     struct dsa_mall_mirror_tc_entry *mirror)
 956 {
 957         struct ksz_device *dev = ds->priv;
 958         u8 data;
 959
 960         if (mirror->ingress)
 961                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
 962         else
 963                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
 964
 965         ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
 966
 967         if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
 968                 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 969                              PORT_MIRROR_SNIFFER, false);
 970 }
 971
 972 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
 973 {
 974         bool gbit;
 975
 976         if (dev->features & NEW_XMII)
 977                 gbit = !(data & PORT_MII_NOT_1GBIT);
 978         else
 979                 gbit = !!(data & PORT_MII_1000MBIT_S1);
 980         return gbit;
 981 }
 982
 983 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
 984 {
 985         if (dev->features & NEW_XMII) {
 986                 if (gbit)
 987                         *data &= ~PORT_MII_NOT_1GBIT;
 988                 else
 989                         *data |= PORT_MII_NOT_1GBIT;
 990         } else {
 991                 if (gbit)
 992                         *data |= PORT_MII_1000MBIT_S1;
 993                 else
 994                         *data &= ~PORT_MII_1000MBIT_S1;
 995         }
 996 }
 997
 998 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
 999 {
1000         int mode;
1001
1002         if (dev->features & NEW_XMII) {
1003                 switch (data & PORT_MII_SEL_M) {
1004                 case PORT_MII_SEL:
1005                         mode = 0;
1006                         break;
1007                 case PORT_RMII_SEL:
1008                         mode = 1;
1009                         break;
1010                 case PORT_GMII_SEL:
1011                         mode = 2;
1012                         break;
1013                 default:
1014                         mode = 3;
1015                 }
1016         } else {
1017                 switch (data & PORT_MII_SEL_M) {
1018                 case PORT_MII_SEL_S1:
1019                         mode = 0;
1020                         break;
1021                 case PORT_RMII_SEL_S1:
1022                         mode = 1;
1023                         break;
1024                 case PORT_GMII_SEL_S1:
1025                         mode = 2;
1026                         break;
1027                 default:
1028                         mode = 3;
1029                 }
1030         }
1031         return mode;
1032 }
1033
1034 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1035 {
1036         u8 xmii;
1037
1038         if (dev->features & NEW_XMII) {
1039                 switch (mode) {
1040                 case 0:
1041                         xmii = PORT_MII_SEL;
1042                         break;
1043                 case 1:
1044                         xmii = PORT_RMII_SEL;
1045                         break;
1046                 case 2:
1047                         xmii = PORT_GMII_SEL;
1048                         break;
1049                 default:
1050                         xmii = PORT_RGMII_SEL;
1051                         break;
1052                 }
1053         } else {
1054                 switch (mode) {
1055                 case 0:
1056                         xmii = PORT_MII_SEL_S1;
1057                         break;
1058                 case 1:
1059                         xmii = PORT_RMII_SEL_S1;
1060                         break;
1061                 case 2:
1062                         xmii = PORT_GMII_SEL_S1;
1063                         break;
1064                 default:
1065                         xmii = PORT_RGMII_SEL_S1;
1066                         break;
1067                 }
1068         }
1069         *data &= ~PORT_MII_SEL_M;
1070         *data |= xmii;
1071 }
1072
1073 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1074 {
1075         phy_interface_t interface;
1076         bool gbit;
1077         int mode;
1078         u8 data8;
1079
1080         if (port < dev->phy_port_cnt)
1081                 return PHY_INTERFACE_MODE_NA;
1082         ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1083         gbit = ksz9477_get_gbit(dev, data8);
1084         mode = ksz9477_get_xmii(dev, data8);
1085         switch (mode) {
1086         case 2:
1087                 interface = PHY_INTERFACE_MODE_GMII;
1088                 if (gbit)
1089                         break;
1090                 fallthrough;
1091         case 0:
1092                 interface = PHY_INTERFACE_MODE_MII;
1093                 break;
1094         case 1:
1095                 interface = PHY_INTERFACE_MODE_RMII;
1096                 break;
1097         default:
1098                 interface = PHY_INTERFACE_MODE_RGMII;
1099                 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1100                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
1101                 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1102                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
1103                         if (data8 & PORT_RGMII_ID_EG_ENABLE)
1104                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1105                 }
1106                 break;
1107         }
1108         return interface;
1109 }
1110
1111 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1112                                    u8 dev_addr, u16 reg_addr, u16 val)
1113 {
1114         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1115                      MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1116         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1117         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1118                      MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1119         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1120 }
1121
1122 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1123 {
1124         /* Apply PHY settings to address errata listed in
1125          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1126          * Silicon Errata and Data Sheet Clarification documents:
1127          *
1128          * Register settings are needed to improve PHY receive performance
1129          */
1130         ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1131         ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1132         ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1133         ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1134         ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1135         ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1136         ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1137
1138         /* Transmit waveform amplitude can be improved
1139          * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1140          */
1141         ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1142
1143         /* Energy Efficient Ethernet (EEE) feature select must
1144          * be manually disabled (except on KSZ8565 which is 100Mbit)
1145          */
1146         if (dev->features & GBIT_SUPPORT)
1147                 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1148
1149         /* Register settings are required to meet data sheet
1150          * supply current specifications
1151          */
1152         ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1153         ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1154         ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1155         ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1156         ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1157         ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1158         ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1159         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1160         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1161         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1162         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1163         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1164         ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1165 }
1166
1167 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1168 {
1169         u8 data8;
1170         u8 member;
1171         u16 data16;
1172         struct ksz_port *p = &dev->ports[port];
1173
1174         /* enable tag tail for host port */
1175         if (cpu_port)
1176                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1177                              true);
1178
1179         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1180
1181         /* set back pressure */
1182         ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1183
1184         /* enable broadcast storm limit */
1185         ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1186
1187         /* disable DiffServ priority */
1188         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1189
1190         /* replace priority */
1191         ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1192                      false);
1193         ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1194                            MTI_PVID_REPLACE, false);
1195
1196         /* enable 802.1p priority */
1197         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1198
1199         if (port < dev->phy_port_cnt) {
1200                 /* do not force flow control */
1201                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1202                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1203                              false);
1204
1205                 if (dev->phy_errata_9477)
1206                         ksz9477_phy_errata_setup(dev, port);
1207         } else {
1208                 /* force flow control */
1209                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1210                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1211                              true);
1212
1213                 /* configure MAC to 1G & RGMII mode */
1214                 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1215                 switch (p->interface) {
1216                 case PHY_INTERFACE_MODE_MII:
1217                         ksz9477_set_xmii(dev, 0, &data8);
1218                         ksz9477_set_gbit(dev, false, &data8);
1219                         p->phydev.speed = SPEED_100;
1220                         break;
1221                 case PHY_INTERFACE_MODE_RMII:
1222                         ksz9477_set_xmii(dev, 1, &data8);
1223                         ksz9477_set_gbit(dev, false, &data8);
1224                         p->phydev.speed = SPEED_100;
1225                         break;
1226                 case PHY_INTERFACE_MODE_GMII:
1227                         ksz9477_set_xmii(dev, 2, &data8);
1228                         ksz9477_set_gbit(dev, true, &data8);
1229                         p->phydev.speed = SPEED_1000;
1230                         break;
1231                 default:
1232                         ksz9477_set_xmii(dev, 3, &data8);
1233                         ksz9477_set_gbit(dev, true, &data8);
1234                         data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1235                         data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1236                         if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1237                             p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1238                                 data8 |= PORT_RGMII_ID_IG_ENABLE;
1239                         if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1240                             p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1241                                 data8 |= PORT_RGMII_ID_EG_ENABLE;
1242                         /* On KSZ9893, disable RGMII in-band status support */
1243                         if (dev->features & IS_9893)
1244                                 data8 &= ~PORT_MII_MAC_MODE;
1245                         p->phydev.speed = SPEED_1000;
1246                         break;
1247                 }
1248                 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1249                 p->phydev.duplex = 1;
1250         }
1251         mutex_lock(&dev->dev_mutex);
1252         if (cpu_port)
1253                 member = dev->port_mask;
1254         else
1255                 member = dev->host_mask | p->vid_member;
1256         mutex_unlock(&dev->dev_mutex);
1257         ksz9477_cfg_port_member(dev, port, member);
1258
1259         /* clear pending interrupts */
1260         if (port < dev->phy_port_cnt)
1261                 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1262 }
1263
1264 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1265 {
1266         struct ksz_device *dev = ds->priv;
1267         struct ksz_port *p;
1268         int i;
1269
1270         for (i = 0; i < dev->port_cnt; i++) {
1271                 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1272                         phy_interface_t interface;
1273                         const char *prev_msg;
1274                         const char *prev_mode;
1275
1276                         dev->cpu_port = i;
1277                         dev->host_mask = (1 << dev->cpu_port);
1278                         dev->port_mask |= dev->host_mask;
1279                         p = &dev->ports[i];
1280
1281                         /* Read from XMII register to determine host port
1282                          * interface.  If set specifically in device tree
1283                          * note the difference to help debugging.
1284                          */
1285                         interface = ksz9477_get_interface(dev, i);
1286                         if (!p->interface) {
1287                                 if (dev->compat_interface) {
1288                                         dev_warn(dev->dev,
1289                                                  "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1290                                                  "Please update your device tree.\n",
1291                                                  i);
1292                                         p->interface = dev->compat_interface;
1293                                 } else {
1294                                         p->interface = interface;
1295                                 }
1296                         }
1297                         if (interface && interface != p->interface) {
1298                                 prev_msg = " instead of ";
1299                                 prev_mode = phy_modes(interface);
1300                         } else {
1301                                 prev_msg = "";
1302                                 prev_mode = "";
1303                         }
1304                         dev_info(dev->dev,
1305                                  "Port%d: using phy mode %s%s%s\n",
1306                                  i,
1307                                  phy_modes(p->interface),
1308                                  prev_msg,
1309                                  prev_mode);
1310
1311                         /* enable cpu port */
1312                         ksz9477_port_setup(dev, i, true);
1313                         p->vid_member = dev->port_mask;
1314                         p->on = 1;
1315                 }
1316         }
1317
1318         dev->member = dev->host_mask;
1319
1320         for (i = 0; i < dev->port_cnt; i++) {
1321                 if (i == dev->cpu_port)
1322                         continue;
1323                 p = &dev->ports[i];
1324
1325                 /* Initialize to non-zero so that ksz_cfg_port_member() will
1326                  * be called.
1327                  */
1328                 p->vid_member = (1 << i);
1329                 p->member = dev->port_mask;
1330                 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1331                 p->on = 1;
1332                 if (i < dev->phy_port_cnt)
1333                         p->phy = 1;
1334                 if (dev->chip_id == 0x00947700 && i == 6) {
1335                         p->sgmii = 1;
1336
1337                         /* SGMII PHY detection code is not implemented yet. */
1338                         p->phy = 0;
1339                 }
1340         }
1341 }
1342
1343 static int ksz9477_setup(struct dsa_switch *ds)
1344 {
1345         struct ksz_device *dev = ds->priv;
1346         int ret = 0;
1347
1348         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1349                                        dev->num_vlans, GFP_KERNEL);
1350         if (!dev->vlan_cache)
1351                 return -ENOMEM;
1352
1353         ret = ksz9477_reset_switch(dev);
1354         if (ret) {
1355                 dev_err(ds->dev, "failed to reset switch\n");
1356                 return ret;
1357         }
1358
1359         /* Required for port partitioning. */
1360         ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1361                       true);
1362
1363         /* Do not work correctly with tail tagging. */
1364         ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1365
1366         /* accept packet up to 2000bytes */
1367         ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1368
1369         ksz9477_config_cpu_port(ds);
1370
1371         ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1372
1373         /* queue based egress rate limit */
1374         ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1375
1376         /* enable global MIB counter freeze function */
1377         ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1378
1379         /* start switch */
1380         ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1381
1382         ksz_init_mib_timer(dev);
1383
1384         return 0;
1385 }
1386
1387 static const struct dsa_switch_ops ksz9477_switch_ops = {
1388         .get_tag_protocol       = ksz9477_get_tag_protocol,
1389         .setup                  = ksz9477_setup,
1390         .phy_read               = ksz9477_phy_read16,
1391         .phy_write              = ksz9477_phy_write16,
1392         .phylink_mac_link_down  = ksz_mac_link_down,
1393         .port_enable            = ksz_enable_port,
1394         .get_strings            = ksz9477_get_strings,
1395         .get_ethtool_stats      = ksz_get_ethtool_stats,
1396         .get_sset_count         = ksz_sset_count,
1397         .port_bridge_join       = ksz_port_bridge_join,
1398         .port_bridge_leave      = ksz_port_bridge_leave,
1399         .port_stp_state_set     = ksz9477_port_stp_state_set,
1400         .port_fast_age          = ksz_port_fast_age,
1401         .port_vlan_filtering    = ksz9477_port_vlan_filtering,
1402         .port_vlan_add          = ksz9477_port_vlan_add,
1403         .port_vlan_del          = ksz9477_port_vlan_del,
1404         .port_fdb_dump          = ksz9477_port_fdb_dump,
1405         .port_fdb_add           = ksz9477_port_fdb_add,
1406         .port_fdb_del           = ksz9477_port_fdb_del,
1407         .port_mdb_add           = ksz9477_port_mdb_add,
1408         .port_mdb_del           = ksz9477_port_mdb_del,
1409         .port_mirror_add        = ksz9477_port_mirror_add,
1410         .port_mirror_del        = ksz9477_port_mirror_del,
1411 };
1412
1413 static u32 ksz9477_get_port_addr(int port, int offset)
1414 {
1415         return PORT_CTRL_ADDR(port, offset);
1416 }
1417
1418 static int ksz9477_switch_detect(struct ksz_device *dev)
1419 {
1420         u8 data8;
1421         u8 id_hi;
1422         u8 id_lo;
1423         u32 id32;
1424         int ret;
1425
1426         /* turn off SPI DO Edge select */
1427         ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1428         if (ret)
1429                 return ret;
1430
1431         data8 &= ~SPI_AUTO_EDGE_DETECTION;
1432         ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1433         if (ret)
1434                 return ret;
1435
1436         /* read chip id */
1437         ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1438         if (ret)
1439                 return ret;
1440         ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1441         if (ret)
1442                 return ret;
1443
1444         /* Number of ports can be reduced depending on chip. */
1445         dev->phy_port_cnt = 5;
1446
1447         /* Default capability is gigabit capable. */
1448         dev->features = GBIT_SUPPORT;
1449
1450         dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8);
1451         id_hi = (u8)(id32 >> 16);
1452         id_lo = (u8)(id32 >> 8);
1453         if ((id_lo & 0xf) == 3) {
1454                 /* Chip is from KSZ9893 design. */
1455                 dev_info(dev->dev, "Found KSZ9893\n");
1456                 dev->features |= IS_9893;
1457
1458                 /* Chip does not support gigabit. */
1459                 if (data8 & SW_QW_ABLE)
1460                         dev->features &= ~GBIT_SUPPORT;
1461                 dev->phy_port_cnt = 2;
1462         } else {
1463                 dev_info(dev->dev, "Found KSZ9477 or compatible\n");
1464                 /* Chip uses new XMII register definitions. */
1465                 dev->features |= NEW_XMII;
1466
1467                 /* Chip does not support gigabit. */
1468                 if (!(data8 & SW_GIGABIT_ABLE))
1469                         dev->features &= ~GBIT_SUPPORT;
1470         }
1471
1472         /* Change chip id to known ones so it can be matched against them. */
1473         id32 = (id_hi << 16) | (id_lo << 8);
1474
1475         dev->chip_id = id32;
1476
1477         return 0;
1478 }
1479
1480 struct ksz_chip_data {
1481         u32 chip_id;
1482         const char *dev_name;
1483         int num_vlans;
1484         int num_alus;
1485         int num_statics;
1486         int cpu_ports;
1487         int port_cnt;
1488         bool phy_errata_9477;
1489 };
1490
1491 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1492         {
1493                 .chip_id = 0x00947700,
1494                 .dev_name = "KSZ9477",
1495                 .num_vlans = 4096,
1496                 .num_alus = 4096,
1497                 .num_statics = 16,
1498                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1499                 .port_cnt = 7,          /* total physical port count */
1500                 .phy_errata_9477 = true,
1501         },
1502         {
1503                 .chip_id = 0x00989700,
1504                 .dev_name = "KSZ9897",
1505                 .num_vlans = 4096,
1506                 .num_alus = 4096,
1507                 .num_statics = 16,
1508                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1509                 .port_cnt = 7,          /* total physical port count */
1510                 .phy_errata_9477 = true,
1511         },
1512         {
1513                 .chip_id = 0x00989300,
1514                 .dev_name = "KSZ9893",
1515                 .num_vlans = 4096,
1516                 .num_alus = 4096,
1517                 .num_statics = 16,
1518                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1519                 .port_cnt = 3,          /* total port count */
1520         },
1521         {
1522                 .chip_id = 0x00956700,
1523                 .dev_name = "KSZ9567",
1524                 .num_vlans = 4096,
1525                 .num_alus = 4096,
1526                 .num_statics = 16,
1527                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1528                 .port_cnt = 7,          /* total physical port count */
1529         },
1530 };
1531
1532 static int ksz9477_switch_init(struct ksz_device *dev)
1533 {
1534         int i;
1535
1536         dev->ds->ops = &ksz9477_switch_ops;
1537
1538         for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1539                 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1540
1541                 if (dev->chip_id == chip->chip_id) {
1542                         dev->name = chip->dev_name;
1543                         dev->num_vlans = chip->num_vlans;
1544                         dev->num_alus = chip->num_alus;
1545                         dev->num_statics = chip->num_statics;
1546                         dev->port_cnt = chip->port_cnt;
1547                         dev->cpu_ports = chip->cpu_ports;
1548                         dev->phy_errata_9477 = chip->phy_errata_9477;
1549
1550                         break;
1551                 }
1552         }
1553
1554         /* no switch found */
1555         if (!dev->port_cnt)
1556                 return -ENODEV;
1557
1558         dev->port_mask = (1 << dev->port_cnt) - 1;
1559
1560         dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1561         dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1562
1563         dev->ports = devm_kzalloc(dev->dev,
1564                                   dev->port_cnt * sizeof(struct ksz_port),
1565                                   GFP_KERNEL);
1566         if (!dev->ports)
1567                 return -ENOMEM;
1568         for (i = 0; i < dev->port_cnt; i++) {
1569                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1570                 dev->ports[i].mib.counters =
1571                         devm_kzalloc(dev->dev,
1572                                      sizeof(u64) *
1573                                      (TOTAL_SWITCH_COUNTER_NUM + 1),
1574                                      GFP_KERNEL);
1575                 if (!dev->ports[i].mib.counters)
1576                         return -ENOMEM;
1577         }
1578
1579         /* set the real number of ports */
1580         dev->ds->num_ports = dev->port_cnt;
1581
1582         return 0;
1583 }
1584
1585 static void ksz9477_switch_exit(struct ksz_device *dev)
1586 {
1587         ksz9477_reset_switch(dev);
1588 }
1589
1590 static const struct ksz_dev_ops ksz9477_dev_ops = {
1591         .get_port_addr = ksz9477_get_port_addr,
1592         .cfg_port_member = ksz9477_cfg_port_member,
1593         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1594         .port_setup = ksz9477_port_setup,
1595         .r_mib_cnt = ksz9477_r_mib_cnt,
1596         .r_mib_pkt = ksz9477_r_mib_pkt,
1597         .freeze_mib = ksz9477_freeze_mib,
1598         .port_init_cnt = ksz9477_port_init_cnt,
1599         .shutdown = ksz9477_reset_switch,
1600         .detect = ksz9477_switch_detect,
1601         .init = ksz9477_switch_init,
1602         .exit = ksz9477_switch_exit,
1603 };
1604
1605 int ksz9477_switch_register(struct ksz_device *dev)
1606 {
1607         int ret, i;
1608         struct phy_device *phydev;
1609
1610         ret = ksz_switch_register(dev, &ksz9477_dev_ops);
1611         if (ret)
1612                 return ret;
1613
1614         for (i = 0; i < dev->phy_port_cnt; ++i) {
1615                 if (!dsa_is_user_port(dev->ds, i))
1616                         continue;
1617
1618                 phydev = dsa_to_port(dev->ds, i)->slave->phydev;
1619
1620                 /* The MAC actually cannot run in 1000 half-duplex mode. */
1621                 phy_remove_link_mode(phydev,
1622                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1623
1624                 /* PHY does not support gigabit. */
1625                 if (!(dev->features & GBIT_SUPPORT))
1626                         phy_remove_link_mode(phydev,
1627                                              ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1628         }
1629         return ret;
1630 }
1631 EXPORT_SYMBOL(ksz9477_switch_register);
1632
1633 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1634 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1635 MODULE_LICENSE("GPL");