1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip KSZ9477 switch driver main logic
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/iopoll.h>
11 #include <linux/platform_data/microchip-ksz.h>
12 #include <linux/phy.h>
13 #include <linux/if_bridge.h>
15 #include <net/switchdev.h>
18 #include "ksz9477_reg.h"
19 #include "ksz_common.h"
21 /* Used with variable features to indicate capabilities. */
22 #define GBIT_SUPPORT BIT(0)
23 #define NEW_XMII BIT(1)
24 #define IS_9893 BIT(2)
28 char string[ETH_GSTRING_LEN];
29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
31 { 0x01, "rx_undersize" },
32 { 0x02, "rx_fragments" },
33 { 0x03, "rx_oversize" },
34 { 0x04, "rx_jabbers" },
35 { 0x05, "rx_symbol_err" },
36 { 0x06, "rx_crc_err" },
37 { 0x07, "rx_align_err" },
38 { 0x08, "rx_mac_ctrl" },
43 { 0x0D, "rx_64_or_less" },
44 { 0x0E, "rx_65_127" },
45 { 0x0F, "rx_128_255" },
46 { 0x10, "rx_256_511" },
47 { 0x11, "rx_512_1023" },
48 { 0x12, "rx_1024_1522" },
49 { 0x13, "rx_1523_2000" },
52 { 0x16, "tx_late_col" },
57 { 0x1B, "tx_deferred" },
58 { 0x1C, "tx_total_col" },
59 { 0x1D, "tx_exc_col" },
60 { 0x1E, "tx_single_col" },
61 { 0x1F, "tx_mult_col" },
64 { 0x82, "rx_discards" },
65 { 0x83, "tx_discards" },
68 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
70 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
73 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
76 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
77 bits, set ? bits : 0);
80 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
82 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
85 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
88 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
89 bits, set ? bits : 0);
92 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton,
98 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
102 } while (timeout-- > 0);
110 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
115 mutex_lock(&dev->vlan_mutex);
117 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
118 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
120 /* wait to be cleared */
121 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
123 dev_dbg(dev->dev, "Failed to read vlan table\n");
127 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
128 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
129 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
131 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
134 mutex_unlock(&dev->vlan_mutex);
139 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
144 mutex_lock(&dev->vlan_mutex);
146 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
147 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
148 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
150 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
151 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
153 /* wait to be cleared */
154 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
156 dev_dbg(dev->dev, "Failed to write vlan table\n");
160 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
162 /* update vlan cache table */
163 dev->vlan_cache[vid].table[0] = vlan_table[0];
164 dev->vlan_cache[vid].table[1] = vlan_table[1];
165 dev->vlan_cache[vid].table[2] = vlan_table[2];
168 mutex_unlock(&dev->vlan_mutex);
173 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
175 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
176 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
177 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
178 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
181 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
183 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
184 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
185 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
186 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
189 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton,
195 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
196 if (!(data & waiton))
199 } while (timeout-- > 0);
207 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton,
213 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
214 if (!(data & waiton))
217 } while (timeout-- > 0);
225 static int ksz9477_reset_switch(struct ksz_device *dev)
232 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
234 /* turn off SPI DO Edge select */
235 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
236 data8 &= ~SPI_AUTO_EDGE_DETECTION;
237 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
239 /* default configuration */
240 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
241 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
242 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
243 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
245 /* disable interrupts */
246 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
247 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
248 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
250 /* set broadcast storm protection 10% rate */
251 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
252 data16 &= ~BROADCAST_STORM_RATE;
253 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
254 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
256 if (dev->synclko_125)
257 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
258 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
263 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
266 struct ksz_poll_ctx ctx = {
269 .offset = REG_PORT_MIB_CTRL_STAT__4,
271 struct ksz_port *p = &dev->ports[port];
275 /* retain the flush/freeze bit */
276 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
277 data |= MIB_COUNTER_READ;
278 data |= (addr << MIB_COUNTER_INDEX_S);
279 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
281 ret = readx_poll_timeout(ksz_pread32_poll, &ctx, data,
282 !(data & MIB_COUNTER_READ), 10, 1000);
284 /* failed to read MIB. get out of loop */
286 dev_dbg(dev->dev, "Failed to get MIB\n");
290 /* count resets upon read */
291 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
295 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
296 u64 *dropped, u64 *cnt)
298 addr = ksz9477_mib_names[addr].index;
299 ksz9477_r_mib_cnt(dev, port, addr, cnt);
302 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
304 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
305 struct ksz_port *p = &dev->ports[port];
307 /* enable/disable the port for flush/freeze function */
308 mutex_lock(&p->mib.cnt_mutex);
309 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
311 /* used by MIB counter reading code to know freeze is enabled */
313 mutex_unlock(&p->mib.cnt_mutex);
316 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
318 struct ksz_port_mib *mib = &dev->ports[port].mib;
320 /* flush all enabled port MIB counters */
321 mutex_lock(&mib->cnt_mutex);
322 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
323 MIB_COUNTER_FLUSH_FREEZE);
324 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
325 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
326 mutex_unlock(&mib->cnt_mutex);
329 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
332 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
335 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
336 struct ksz_device *dev = ds->priv;
338 if (dev->features & IS_9893)
339 proto = DSA_TAG_PROTO_KSZ9893;
343 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
345 struct ksz_device *dev = ds->priv;
348 /* No real PHY after this. Simulate the PHY.
349 * A fixed PHY can be setup in the device tree, but this function is
350 * still called for that port during initialization.
351 * For RGMII PHY there is no way to access it so the fixed PHY should
352 * be used. For SGMII PHY the supporting code will be added later.
354 if (addr >= dev->phy_port_cnt) {
355 struct ksz_port *p = &dev->ports[addr];
380 if (p->phydev.speed == SPEED_1000)
387 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
393 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
396 struct ksz_device *dev = ds->priv;
398 /* No real PHY after this. */
399 if (addr >= dev->phy_port_cnt)
402 /* No gigabit support. Do not write to this register. */
403 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
405 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
410 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
411 u32 stringset, uint8_t *buf)
415 if (stringset != ETH_SS_STATS)
418 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
419 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
424 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
427 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
428 dev->ports[port].member = member;
431 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
434 struct ksz_device *dev = ds->priv;
435 struct ksz_port *p = &dev->ports[port];
438 int forward = dev->member;
440 ksz_pread8(dev, port, P_STP_CTRL, &data);
441 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
444 case BR_STATE_DISABLED:
445 data |= PORT_LEARN_DISABLE;
446 if (port != dev->cpu_port)
449 case BR_STATE_LISTENING:
450 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
451 if (port != dev->cpu_port &&
452 p->stp_state == BR_STATE_DISABLED)
453 member = dev->host_mask | p->vid_member;
455 case BR_STATE_LEARNING:
456 data |= PORT_RX_ENABLE;
458 case BR_STATE_FORWARDING:
459 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
461 /* This function is also used internally. */
462 if (port == dev->cpu_port)
465 member = dev->host_mask | p->vid_member;
466 mutex_lock(&dev->dev_mutex);
468 /* Port is a member of a bridge. */
469 if (dev->br_member & (1 << port)) {
470 dev->member |= (1 << port);
471 member = dev->member;
473 mutex_unlock(&dev->dev_mutex);
475 case BR_STATE_BLOCKING:
476 data |= PORT_LEARN_DISABLE;
477 if (port != dev->cpu_port &&
478 p->stp_state == BR_STATE_DISABLED)
479 member = dev->host_mask | p->vid_member;
482 dev_err(ds->dev, "invalid STP state: %d\n", state);
486 ksz_pwrite8(dev, port, P_STP_CTRL, data);
487 p->stp_state = state;
488 mutex_lock(&dev->dev_mutex);
489 if (data & PORT_RX_ENABLE)
490 dev->rx_ports |= (1 << port);
492 dev->rx_ports &= ~(1 << port);
493 if (data & PORT_TX_ENABLE)
494 dev->tx_ports |= (1 << port);
496 dev->tx_ports &= ~(1 << port);
498 /* Port membership may share register with STP state. */
499 if (member >= 0 && member != p->member)
500 ksz9477_cfg_port_member(dev, port, (u8)member);
502 /* Check if forwarding needs to be updated. */
503 if (state != BR_STATE_FORWARDING) {
504 if (dev->br_member & (1 << port))
505 dev->member &= ~(1 << port);
508 /* When topology has changed the function ksz_update_port_member
509 * should be called to modify port forwarding behavior.
511 if (forward != dev->member)
512 ksz_update_port_member(dev, port);
513 mutex_unlock(&dev->dev_mutex);
516 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
520 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data);
521 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S);
522 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
523 ksz_write8(dev, REG_SW_LUE_CTRL_2, data);
524 if (port < dev->mib_port_cnt) {
525 /* flush individual port */
526 ksz_pread8(dev, port, P_STP_CTRL, &data);
527 if (!(data & PORT_LEARN_DISABLE))
528 ksz_pwrite8(dev, port, P_STP_CTRL,
529 data | PORT_LEARN_DISABLE);
530 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
531 ksz_pwrite8(dev, port, P_STP_CTRL, data);
534 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
538 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
541 struct ksz_device *dev = ds->priv;
544 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
545 PORT_VLAN_LOOKUP_VID_0, true);
546 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
548 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
549 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
550 PORT_VLAN_LOOKUP_VID_0, false);
556 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
557 const struct switchdev_obj_port_vlan *vlan)
559 struct ksz_device *dev = ds->priv;
562 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
564 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
565 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
566 dev_dbg(dev->dev, "Failed to get vlan table\n");
570 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
572 vlan_table[1] |= BIT(port);
574 vlan_table[1] &= ~BIT(port);
575 vlan_table[1] &= ~(BIT(dev->cpu_port));
577 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
579 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
580 dev_dbg(dev->dev, "Failed to set vlan table\n");
585 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
586 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
590 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
591 const struct switchdev_obj_port_vlan *vlan)
593 struct ksz_device *dev = ds->priv;
594 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
599 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
602 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
603 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
604 dev_dbg(dev->dev, "Failed to get vlan table\n");
608 vlan_table[2] &= ~BIT(port);
614 vlan_table[1] &= ~BIT(port);
616 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
617 dev_dbg(dev->dev, "Failed to set vlan table\n");
622 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
627 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
628 const unsigned char *addr, u16 vid)
630 struct ksz_device *dev = ds->priv;
635 mutex_lock(&dev->alu_mutex);
637 /* find any entry with mac & vid */
638 data = vid << ALU_FID_INDEX_S;
639 data |= ((addr[0] << 8) | addr[1]);
640 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
642 data = ((addr[2] << 24) | (addr[3] << 16));
643 data |= ((addr[4] << 8) | addr[5]);
644 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
646 /* start read operation */
647 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
649 /* wait to be finished */
650 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
652 dev_dbg(dev->dev, "Failed to read ALU\n");
657 ksz9477_read_table(dev, alu_table);
659 /* update ALU entry */
660 alu_table[0] = ALU_V_STATIC_VALID;
661 alu_table[1] |= BIT(port);
663 alu_table[1] |= ALU_V_USE_FID;
664 alu_table[2] = (vid << ALU_V_FID_S);
665 alu_table[2] |= ((addr[0] << 8) | addr[1]);
666 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
667 alu_table[3] |= ((addr[4] << 8) | addr[5]);
669 ksz9477_write_table(dev, alu_table);
671 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
673 /* wait to be finished */
674 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
676 dev_dbg(dev->dev, "Failed to write ALU\n");
679 mutex_unlock(&dev->alu_mutex);
684 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
685 const unsigned char *addr, u16 vid)
687 struct ksz_device *dev = ds->priv;
692 mutex_lock(&dev->alu_mutex);
694 /* read any entry with mac & vid */
695 data = vid << ALU_FID_INDEX_S;
696 data |= ((addr[0] << 8) | addr[1]);
697 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
699 data = ((addr[2] << 24) | (addr[3] << 16));
700 data |= ((addr[4] << 8) | addr[5]);
701 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
703 /* start read operation */
704 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
706 /* wait to be finished */
707 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
709 dev_dbg(dev->dev, "Failed to read ALU\n");
713 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
714 if (alu_table[0] & ALU_V_STATIC_VALID) {
715 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
716 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
717 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
719 /* clear forwarding port */
720 alu_table[2] &= ~BIT(port);
722 /* if there is no port to forward, clear table */
723 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
736 ksz9477_write_table(dev, alu_table);
738 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
740 /* wait to be finished */
741 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
743 dev_dbg(dev->dev, "Failed to write ALU\n");
746 mutex_unlock(&dev->alu_mutex);
751 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
753 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
754 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
755 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
756 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
757 ALU_V_PRIO_AGE_CNT_M;
758 alu->mstp = alu_table[0] & ALU_V_MSTP_M;
760 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
761 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
762 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
764 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
766 alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
767 alu->mac[1] = alu_table[2] & 0xFF;
768 alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
769 alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
770 alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
771 alu->mac[5] = alu_table[3] & 0xFF;
774 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
775 dsa_fdb_dump_cb_t *cb, void *data)
777 struct ksz_device *dev = ds->priv;
781 struct alu_struct alu;
784 mutex_lock(&dev->alu_mutex);
786 /* start ALU search */
787 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
792 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
793 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
796 } while (timeout-- > 0);
799 dev_dbg(dev->dev, "Failed to search ALU\n");
805 ksz9477_read_table(dev, alu_table);
807 ksz9477_convert_alu(&alu, alu_table);
809 if (alu.port_forward & BIT(port)) {
810 ret = cb(alu.mac, alu.fid, alu.is_static, data);
814 } while (ksz_data & ALU_START);
818 /* stop ALU search */
819 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
821 mutex_unlock(&dev->alu_mutex);
826 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
827 const struct switchdev_obj_port_mdb *mdb)
829 struct ksz_device *dev = ds->priv;
835 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
836 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
837 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
839 mutex_lock(&dev->alu_mutex);
841 for (index = 0; index < dev->num_statics; index++) {
842 /* find empty slot first */
843 data = (index << ALU_STAT_INDEX_S) |
844 ALU_STAT_READ | ALU_STAT_START;
845 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
847 /* wait to be finished */
848 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
849 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
853 /* read ALU static table */
854 ksz9477_read_table(dev, static_table);
856 if (static_table[0] & ALU_V_STATIC_VALID) {
857 /* check this has same vid & mac address */
858 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
859 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
860 static_table[3] == mac_lo) {
861 /* found matching one */
865 /* found empty one */
870 /* no available entry */
871 if (index == dev->num_statics)
875 static_table[0] = ALU_V_STATIC_VALID;
876 static_table[1] |= BIT(port);
878 static_table[1] |= ALU_V_USE_FID;
879 static_table[2] = (mdb->vid << ALU_V_FID_S);
880 static_table[2] |= mac_hi;
881 static_table[3] = mac_lo;
883 ksz9477_write_table(dev, static_table);
885 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
886 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
888 /* wait to be finished */
889 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
890 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
893 mutex_unlock(&dev->alu_mutex);
896 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
897 const struct switchdev_obj_port_mdb *mdb)
899 struct ksz_device *dev = ds->priv;
906 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
907 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
908 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
910 mutex_lock(&dev->alu_mutex);
912 for (index = 0; index < dev->num_statics; index++) {
913 /* find empty slot first */
914 data = (index << ALU_STAT_INDEX_S) |
915 ALU_STAT_READ | ALU_STAT_START;
916 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
918 /* wait to be finished */
919 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
921 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
925 /* read ALU static table */
926 ksz9477_read_table(dev, static_table);
928 if (static_table[0] & ALU_V_STATIC_VALID) {
929 /* check this has same vid & mac address */
931 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
932 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
933 static_table[3] == mac_lo) {
934 /* found matching one */
940 /* no available entry */
941 if (index == dev->num_statics)
945 static_table[1] &= ~BIT(port);
947 if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
955 ksz9477_write_table(dev, static_table);
957 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
958 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
960 /* wait to be finished */
961 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
963 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
966 mutex_unlock(&dev->alu_mutex);
971 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
972 struct dsa_mall_mirror_tc_entry *mirror,
975 struct ksz_device *dev = ds->priv;
978 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
980 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
982 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
984 /* configure mirror port */
985 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
986 PORT_MIRROR_SNIFFER, true);
988 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
993 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
994 struct dsa_mall_mirror_tc_entry *mirror)
996 struct ksz_device *dev = ds->priv;
1000 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1002 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1004 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1006 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1007 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1008 PORT_MIRROR_SNIFFER, false);
1011 static void ksz9477_phy_setup(struct ksz_device *dev, int port,
1012 struct phy_device *phy)
1014 /* Only apply to port with PHY. */
1015 if (port >= dev->phy_port_cnt)
1018 /* The MAC actually cannot run in 1000 half-duplex mode. */
1019 phy_remove_link_mode(phy,
1020 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1022 /* PHY does not support gigabit. */
1023 if (!(dev->features & GBIT_SUPPORT))
1024 phy_remove_link_mode(phy,
1025 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1028 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
1032 if (dev->features & NEW_XMII)
1033 gbit = !(data & PORT_MII_NOT_1GBIT);
1035 gbit = !!(data & PORT_MII_1000MBIT_S1);
1039 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
1041 if (dev->features & NEW_XMII) {
1043 *data &= ~PORT_MII_NOT_1GBIT;
1045 *data |= PORT_MII_NOT_1GBIT;
1048 *data |= PORT_MII_1000MBIT_S1;
1050 *data &= ~PORT_MII_1000MBIT_S1;
1054 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
1058 if (dev->features & NEW_XMII) {
1059 switch (data & PORT_MII_SEL_M) {
1073 switch (data & PORT_MII_SEL_M) {
1074 case PORT_MII_SEL_S1:
1077 case PORT_RMII_SEL_S1:
1080 case PORT_GMII_SEL_S1:
1090 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1094 if (dev->features & NEW_XMII) {
1097 xmii = PORT_MII_SEL;
1100 xmii = PORT_RMII_SEL;
1103 xmii = PORT_GMII_SEL;
1106 xmii = PORT_RGMII_SEL;
1112 xmii = PORT_MII_SEL_S1;
1115 xmii = PORT_RMII_SEL_S1;
1118 xmii = PORT_GMII_SEL_S1;
1121 xmii = PORT_RGMII_SEL_S1;
1125 *data &= ~PORT_MII_SEL_M;
1129 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1131 phy_interface_t interface;
1136 if (port < dev->phy_port_cnt)
1137 return PHY_INTERFACE_MODE_NA;
1138 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1139 gbit = ksz9477_get_gbit(dev, data8);
1140 mode = ksz9477_get_xmii(dev, data8);
1143 interface = PHY_INTERFACE_MODE_GMII;
1148 interface = PHY_INTERFACE_MODE_MII;
1151 interface = PHY_INTERFACE_MODE_RMII;
1154 interface = PHY_INTERFACE_MODE_RGMII;
1155 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1156 interface = PHY_INTERFACE_MODE_RGMII_TXID;
1157 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1158 interface = PHY_INTERFACE_MODE_RGMII_RXID;
1159 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1160 interface = PHY_INTERFACE_MODE_RGMII_ID;
1167 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1168 u8 dev_addr, u16 reg_addr, u16 val)
1170 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1171 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1172 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1173 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1174 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1175 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1178 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1180 /* Apply PHY settings to address errata listed in
1181 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1182 * Silicon Errata and Data Sheet Clarification documents:
1184 * Register settings are needed to improve PHY receive performance
1186 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1187 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1188 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1189 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1190 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1191 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1192 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1194 /* Transmit waveform amplitude can be improved
1195 * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1197 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1199 /* Energy Efficient Ethernet (EEE) feature select must
1200 * be manually disabled (except on KSZ8565 which is 100Mbit)
1202 if (dev->features & GBIT_SUPPORT)
1203 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1205 /* Register settings are required to meet data sheet
1206 * supply current specifications
1208 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1209 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1210 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1211 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1212 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1213 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1214 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1215 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1216 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1217 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1218 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1219 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1220 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1223 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1228 struct ksz_port *p = &dev->ports[port];
1230 /* enable tag tail for host port */
1232 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1235 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1237 /* set back pressure */
1238 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1240 /* enable broadcast storm limit */
1241 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1243 /* disable DiffServ priority */
1244 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1246 /* replace priority */
1247 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1249 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1250 MTI_PVID_REPLACE, false);
1252 /* enable 802.1p priority */
1253 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1255 if (port < dev->phy_port_cnt) {
1256 /* do not force flow control */
1257 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1258 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1261 if (dev->phy_errata_9477)
1262 ksz9477_phy_errata_setup(dev, port);
1264 /* force flow control */
1265 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1266 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1269 /* configure MAC to 1G & RGMII mode */
1270 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1271 switch (dev->interface) {
1272 case PHY_INTERFACE_MODE_MII:
1273 ksz9477_set_xmii(dev, 0, &data8);
1274 ksz9477_set_gbit(dev, false, &data8);
1275 p->phydev.speed = SPEED_100;
1277 case PHY_INTERFACE_MODE_RMII:
1278 ksz9477_set_xmii(dev, 1, &data8);
1279 ksz9477_set_gbit(dev, false, &data8);
1280 p->phydev.speed = SPEED_100;
1282 case PHY_INTERFACE_MODE_GMII:
1283 ksz9477_set_xmii(dev, 2, &data8);
1284 ksz9477_set_gbit(dev, true, &data8);
1285 p->phydev.speed = SPEED_1000;
1288 ksz9477_set_xmii(dev, 3, &data8);
1289 ksz9477_set_gbit(dev, true, &data8);
1290 data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1291 data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1292 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1293 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1294 data8 |= PORT_RGMII_ID_IG_ENABLE;
1295 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1296 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1297 data8 |= PORT_RGMII_ID_EG_ENABLE;
1298 p->phydev.speed = SPEED_1000;
1301 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1302 p->phydev.duplex = 1;
1304 mutex_lock(&dev->dev_mutex);
1306 member = dev->port_mask;
1307 dev->on_ports = dev->host_mask;
1308 dev->live_ports = dev->host_mask;
1310 member = dev->host_mask | p->vid_member;
1311 dev->on_ports |= (1 << port);
1313 /* Link was detected before port is enabled. */
1315 dev->live_ports |= (1 << port);
1317 mutex_unlock(&dev->dev_mutex);
1318 ksz9477_cfg_port_member(dev, port, member);
1320 /* clear pending interrupts */
1321 if (port < dev->phy_port_cnt)
1322 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1325 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1327 struct ksz_device *dev = ds->priv;
1331 ds->num_ports = dev->port_cnt;
1333 for (i = 0; i < dev->port_cnt; i++) {
1334 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1335 phy_interface_t interface;
1338 dev->host_mask = (1 << dev->cpu_port);
1339 dev->port_mask |= dev->host_mask;
1341 /* Read from XMII register to determine host port
1342 * interface. If set specifically in device tree
1343 * note the difference to help debugging.
1345 interface = ksz9477_get_interface(dev, i);
1346 if (!dev->interface)
1347 dev->interface = interface;
1348 if (interface && interface != dev->interface)
1350 "use %s instead of %s\n",
1351 phy_modes(dev->interface),
1352 phy_modes(interface));
1354 /* enable cpu port */
1355 ksz9477_port_setup(dev, i, true);
1356 p = &dev->ports[dev->cpu_port];
1357 p->vid_member = dev->port_mask;
1362 dev->member = dev->host_mask;
1364 for (i = 0; i < dev->mib_port_cnt; i++) {
1365 if (i == dev->cpu_port)
1369 /* Initialize to non-zero so that ksz_cfg_port_member() will
1372 p->vid_member = (1 << i);
1373 p->member = dev->port_mask;
1374 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1376 if (i < dev->phy_port_cnt)
1378 if (dev->chip_id == 0x00947700 && i == 6) {
1381 /* SGMII PHY detection code is not implemented yet. */
1387 static int ksz9477_setup(struct dsa_switch *ds)
1389 struct ksz_device *dev = ds->priv;
1392 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1393 dev->num_vlans, GFP_KERNEL);
1394 if (!dev->vlan_cache)
1397 ret = ksz9477_reset_switch(dev);
1399 dev_err(ds->dev, "failed to reset switch\n");
1403 /* Required for port partitioning. */
1404 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1407 /* Do not work correctly with tail tagging. */
1408 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1410 /* accept packet up to 2000bytes */
1411 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1413 ksz9477_config_cpu_port(ds);
1415 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1417 /* queue based egress rate limit */
1418 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1420 /* enable global MIB counter freeze function */
1421 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1424 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1426 ksz_init_mib_timer(dev);
1431 static const struct dsa_switch_ops ksz9477_switch_ops = {
1432 .get_tag_protocol = ksz9477_get_tag_protocol,
1433 .setup = ksz9477_setup,
1434 .phy_read = ksz9477_phy_read16,
1435 .phy_write = ksz9477_phy_write16,
1436 .adjust_link = ksz_adjust_link,
1437 .port_enable = ksz_enable_port,
1438 .port_disable = ksz_disable_port,
1439 .get_strings = ksz9477_get_strings,
1440 .get_ethtool_stats = ksz_get_ethtool_stats,
1441 .get_sset_count = ksz_sset_count,
1442 .port_bridge_join = ksz_port_bridge_join,
1443 .port_bridge_leave = ksz_port_bridge_leave,
1444 .port_stp_state_set = ksz9477_port_stp_state_set,
1445 .port_fast_age = ksz_port_fast_age,
1446 .port_vlan_filtering = ksz9477_port_vlan_filtering,
1447 .port_vlan_prepare = ksz_port_vlan_prepare,
1448 .port_vlan_add = ksz9477_port_vlan_add,
1449 .port_vlan_del = ksz9477_port_vlan_del,
1450 .port_fdb_dump = ksz9477_port_fdb_dump,
1451 .port_fdb_add = ksz9477_port_fdb_add,
1452 .port_fdb_del = ksz9477_port_fdb_del,
1453 .port_mdb_prepare = ksz_port_mdb_prepare,
1454 .port_mdb_add = ksz9477_port_mdb_add,
1455 .port_mdb_del = ksz9477_port_mdb_del,
1456 .port_mirror_add = ksz9477_port_mirror_add,
1457 .port_mirror_del = ksz9477_port_mirror_del,
1460 static u32 ksz9477_get_port_addr(int port, int offset)
1462 return PORT_CTRL_ADDR(port, offset);
1465 static int ksz9477_switch_detect(struct ksz_device *dev)
1473 /* turn off SPI DO Edge select */
1474 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1478 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1479 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1484 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1487 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1491 /* Number of ports can be reduced depending on chip. */
1492 dev->mib_port_cnt = TOTAL_PORT_NUM;
1493 dev->phy_port_cnt = 5;
1495 /* Default capability is gigabit capable. */
1496 dev->features = GBIT_SUPPORT;
1498 id_hi = (u8)(id32 >> 16);
1499 id_lo = (u8)(id32 >> 8);
1500 if ((id_lo & 0xf) == 3) {
1501 /* Chip is from KSZ9893 design. */
1502 dev->features |= IS_9893;
1504 /* Chip does not support gigabit. */
1505 if (data8 & SW_QW_ABLE)
1506 dev->features &= ~GBIT_SUPPORT;
1507 dev->mib_port_cnt = 3;
1508 dev->phy_port_cnt = 2;
1510 /* Chip uses new XMII register definitions. */
1511 dev->features |= NEW_XMII;
1513 /* Chip does not support gigabit. */
1514 if (!(data8 & SW_GIGABIT_ABLE))
1515 dev->features &= ~GBIT_SUPPORT;
1518 /* Change chip id to known ones so it can be matched against them. */
1519 id32 = (id_hi << 16) | (id_lo << 8);
1521 dev->chip_id = id32;
1526 struct ksz_chip_data {
1528 const char *dev_name;
1534 bool phy_errata_9477;
1537 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1539 .chip_id = 0x00947700,
1540 .dev_name = "KSZ9477",
1544 .cpu_ports = 0x7F, /* can be configured as cpu port */
1545 .port_cnt = 7, /* total physical port count */
1546 .phy_errata_9477 = true,
1549 .chip_id = 0x00989700,
1550 .dev_name = "KSZ9897",
1554 .cpu_ports = 0x7F, /* can be configured as cpu port */
1555 .port_cnt = 7, /* total physical port count */
1556 .phy_errata_9477 = true,
1559 .chip_id = 0x00989300,
1560 .dev_name = "KSZ9893",
1564 .cpu_ports = 0x07, /* can be configured as cpu port */
1565 .port_cnt = 3, /* total port count */
1569 static int ksz9477_switch_init(struct ksz_device *dev)
1573 dev->ds->ops = &ksz9477_switch_ops;
1575 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1576 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1578 if (dev->chip_id == chip->chip_id) {
1579 dev->name = chip->dev_name;
1580 dev->num_vlans = chip->num_vlans;
1581 dev->num_alus = chip->num_alus;
1582 dev->num_statics = chip->num_statics;
1583 dev->port_cnt = chip->port_cnt;
1584 dev->cpu_ports = chip->cpu_ports;
1585 dev->phy_errata_9477 = chip->phy_errata_9477;
1591 /* no switch found */
1595 dev->port_mask = (1 << dev->port_cnt) - 1;
1597 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1598 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1600 i = dev->mib_port_cnt;
1601 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1605 for (i = 0; i < dev->mib_port_cnt; i++) {
1606 mutex_init(&dev->ports[i].mib.cnt_mutex);
1607 dev->ports[i].mib.counters =
1608 devm_kzalloc(dev->dev,
1610 (TOTAL_SWITCH_COUNTER_NUM + 1),
1612 if (!dev->ports[i].mib.counters)
1619 static void ksz9477_switch_exit(struct ksz_device *dev)
1621 ksz9477_reset_switch(dev);
1624 static const struct ksz_dev_ops ksz9477_dev_ops = {
1625 .get_port_addr = ksz9477_get_port_addr,
1626 .cfg_port_member = ksz9477_cfg_port_member,
1627 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1628 .phy_setup = ksz9477_phy_setup,
1629 .port_setup = ksz9477_port_setup,
1630 .r_mib_cnt = ksz9477_r_mib_cnt,
1631 .r_mib_pkt = ksz9477_r_mib_pkt,
1632 .freeze_mib = ksz9477_freeze_mib,
1633 .port_init_cnt = ksz9477_port_init_cnt,
1634 .shutdown = ksz9477_reset_switch,
1635 .detect = ksz9477_switch_detect,
1636 .init = ksz9477_switch_init,
1637 .exit = ksz9477_switch_exit,
1640 int ksz9477_switch_register(struct ksz_device *dev)
1642 return ksz_switch_register(dev, &ksz9477_dev_ops);
1644 EXPORT_SYMBOL(ksz9477_switch_register);
1646 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1647 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1648 MODULE_LICENSE("GPL");