drivers/net/dsa/microchip/ksz9477.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip KSZ9477 switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_data/microchip-ksz.h>
  12 #include <linux/phy.h>
  13 #include <linux/if_bridge.h>
  14 #include <net/dsa.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ksz9477_reg.h"
  18 #include "ksz_common.h"
  19
  20 /* Used with variable features to indicate capabilities. */
  21 #define GBIT_SUPPORT                    BIT(0)
  22 #define NEW_XMII                        BIT(1)
  23 #define IS_9893                         BIT(2)
  24
  25 static const struct {
  26         int index;
  27         char string[ETH_GSTRING_LEN];
  28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
  29         { 0x00, "rx_hi" },
  30         { 0x01, "rx_undersize" },
  31         { 0x02, "rx_fragments" },
  32         { 0x03, "rx_oversize" },
  33         { 0x04, "rx_jabbers" },
  34         { 0x05, "rx_symbol_err" },
  35         { 0x06, "rx_crc_err" },
  36         { 0x07, "rx_align_err" },
  37         { 0x08, "rx_mac_ctrl" },
  38         { 0x09, "rx_pause" },
  39         { 0x0A, "rx_bcast" },
  40         { 0x0B, "rx_mcast" },
  41         { 0x0C, "rx_ucast" },
  42         { 0x0D, "rx_64_or_less" },
  43         { 0x0E, "rx_65_127" },
  44         { 0x0F, "rx_128_255" },
  45         { 0x10, "rx_256_511" },
  46         { 0x11, "rx_512_1023" },
  47         { 0x12, "rx_1024_1522" },
  48         { 0x13, "rx_1523_2000" },
  49         { 0x14, "rx_2001" },
  50         { 0x15, "tx_hi" },
  51         { 0x16, "tx_late_col" },
  52         { 0x17, "tx_pause" },
  53         { 0x18, "tx_bcast" },
  54         { 0x19, "tx_mcast" },
  55         { 0x1A, "tx_ucast" },
  56         { 0x1B, "tx_deferred" },
  57         { 0x1C, "tx_total_col" },
  58         { 0x1D, "tx_exc_col" },
  59         { 0x1E, "tx_single_col" },
  60         { 0x1F, "tx_mult_col" },
  61         { 0x80, "rx_total" },
  62         { 0x81, "tx_total" },
  63         { 0x82, "rx_discards" },
  64         { 0x83, "tx_discards" },
  65 };
  66
  67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
  68 {
  69         regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
  70 }
  71
  72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
  73                          bool set)
  74 {
  75         regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
  76                            bits, set ? bits : 0);
  77 }
  78
  79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
  80 {
  81         regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
  82 }
  83
  84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
  85                                u32 bits, bool set)
  86 {
  87         regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
  88                            bits, set ? bits : 0);
  89 }
  90
  91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
  92 {
  93         unsigned int val;
  94
  95         return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
  96                                         val, !(val & VLAN_START), 10, 1000);
  97 }
  98
  99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
 100                                   u32 *vlan_table)
 101 {
 102         int ret;
 103
 104         mutex_lock(&dev->vlan_mutex);
 105
 106         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 107         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
 108
 109         /* wait to be cleared */
 110         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 111         if (ret) {
 112                 dev_dbg(dev->dev, "Failed to read vlan table\n");
 113                 goto exit;
 114         }
 115
 116         ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
 117         ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
 118         ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
 119
 120         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 121
 122 exit:
 123         mutex_unlock(&dev->vlan_mutex);
 124
 125         return ret;
 126 }
 127
 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
 129                                   u32 *vlan_table)
 130 {
 131         int ret;
 132
 133         mutex_lock(&dev->vlan_mutex);
 134
 135         ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
 136         ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
 137         ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
 138
 139         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 140         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
 141
 142         /* wait to be cleared */
 143         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 144         if (ret) {
 145                 dev_dbg(dev->dev, "Failed to write vlan table\n");
 146                 goto exit;
 147         }
 148
 149         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 150
 151         /* update vlan cache table */
 152         dev->vlan_cache[vid].table[0] = vlan_table[0];
 153         dev->vlan_cache[vid].table[1] = vlan_table[1];
 154         dev->vlan_cache[vid].table[2] = vlan_table[2];
 155
 156 exit:
 157         mutex_unlock(&dev->vlan_mutex);
 158
 159         return ret;
 160 }
 161
 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
 163 {
 164         ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
 165         ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
 166         ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
 167         ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
 168 }
 169
 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
 171 {
 172         ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
 173         ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
 174         ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
 175         ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
 176 }
 177
 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
 179 {
 180         unsigned int val;
 181
 182         return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
 183                                         val, !(val & ALU_START), 10, 1000);
 184 }
 185
 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
 187 {
 188         unsigned int val;
 189
 190         return regmap_read_poll_timeout(dev->regmap[2],
 191                                         REG_SW_ALU_STAT_CTRL__4,
 192                                         val, !(val & ALU_STAT_START),
 193                                         10, 1000);
 194 }
 195
 196 static int ksz9477_reset_switch(struct ksz_device *dev)
 197 {
 198         u8 data8;
 199         u32 data32;
 200
 201         /* reset switch */
 202         ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
 203
 204         /* turn off SPI DO Edge select */
 205         regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
 206                            SPI_AUTO_EDGE_DETECTION, 0);
 207
 208         /* default configuration */
 209         ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
 210         data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
 211               SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
 212         ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
 213
 214         /* disable interrupts */
 215         ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
 216         ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
 217         ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
 218
 219         /* set broadcast storm protection 10% rate */
 220         regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
 221                            BROADCAST_STORM_RATE,
 222                            (BROADCAST_STORM_VALUE *
 223                            BROADCAST_STORM_PROT_RATE) / 100);
 224
 225         if (dev->synclko_125)
 226                 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 227                            SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
 228
 229         return 0;
 230 }
 231
 232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
 233                               u64 *cnt)
 234 {
 235         struct ksz_port *p = &dev->ports[port];
 236         unsigned int val;
 237         u32 data;
 238         int ret;
 239
 240         /* retain the flush/freeze bit */
 241         data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 242         data |= MIB_COUNTER_READ;
 243         data |= (addr << MIB_COUNTER_INDEX_S);
 244         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
 245
 246         ret = regmap_read_poll_timeout(dev->regmap[2],
 247                         PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
 248                         val, !(val & MIB_COUNTER_READ), 10, 1000);
 249         /* failed to read MIB. get out of loop */
 250         if (ret) {
 251                 dev_dbg(dev->dev, "Failed to get MIB\n");
 252                 return;
 253         }
 254
 255         /* count resets upon read */
 256         ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
 257         *cnt += data;
 258 }
 259
 260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
 261                               u64 *dropped, u64 *cnt)
 262 {
 263         addr = ksz9477_mib_names[addr].index;
 264         ksz9477_r_mib_cnt(dev, port, addr, cnt);
 265 }
 266
 267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
 268 {
 269         u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 270         struct ksz_port *p = &dev->ports[port];
 271
 272         /* enable/disable the port for flush/freeze function */
 273         mutex_lock(&p->mib.cnt_mutex);
 274         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
 275
 276         /* used by MIB counter reading code to know freeze is enabled */
 277         p->freeze = freeze;
 278         mutex_unlock(&p->mib.cnt_mutex);
 279 }
 280
 281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
 282 {
 283         struct ksz_port_mib *mib = &dev->ports[port].mib;
 284
 285         /* flush all enabled port MIB counters */
 286         mutex_lock(&mib->cnt_mutex);
 287         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
 288                      MIB_COUNTER_FLUSH_FREEZE);
 289         ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
 290         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
 291         mutex_unlock(&mib->cnt_mutex);
 292
 293         mib->cnt_ptr = 0;
 294         memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
 295 }
 296
 297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
 298                                                       int port,
 299                                                       enum dsa_tag_protocol mp)
 300 {
 301         enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
 302         struct ksz_device *dev = ds->priv;
 303
 304         if (dev->features & IS_9893)
 305                 proto = DSA_TAG_PROTO_KSZ9893;
 306         return proto;
 307 }
 308
 309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
 310 {
 311         struct ksz_device *dev = ds->priv;
 312         u16 val = 0xffff;
 313
 314         /* No real PHY after this. Simulate the PHY.
 315          * A fixed PHY can be setup in the device tree, but this function is
 316          * still called for that port during initialization.
 317          * For RGMII PHY there is no way to access it so the fixed PHY should
 318          * be used.  For SGMII PHY the supporting code will be added later.
 319          */
 320         if (addr >= dev->phy_port_cnt) {
 321                 struct ksz_port *p = &dev->ports[addr];
 322
 323                 switch (reg) {
 324                 case MII_BMCR:
 325                         val = 0x1140;
 326                         break;
 327                 case MII_BMSR:
 328                         val = 0x796d;
 329                         break;
 330                 case MII_PHYSID1:
 331                         val = 0x0022;
 332                         break;
 333                 case MII_PHYSID2:
 334                         val = 0x1631;
 335                         break;
 336                 case MII_ADVERTISE:
 337                         val = 0x05e1;
 338                         break;
 339                 case MII_LPA:
 340                         val = 0xc5e1;
 341                         break;
 342                 case MII_CTRL1000:
 343                         val = 0x0700;
 344                         break;
 345                 case MII_STAT1000:
 346                         if (p->phydev.speed == SPEED_1000)
 347                                 val = 0x3800;
 348                         else
 349                                 val = 0;
 350                         break;
 351                 }
 352         } else {
 353                 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
 354         }
 355
 356         return val;
 357 }
 358
 359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
 360                                u16 val)
 361 {
 362         struct ksz_device *dev = ds->priv;
 363
 364         /* No real PHY after this. */
 365         if (addr >= dev->phy_port_cnt)
 366                 return 0;
 367
 368         /* No gigabit support.  Do not write to this register. */
 369         if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
 370                 return 0;
 371         ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
 372
 373         return 0;
 374 }
 375
 376 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
 377                                 u32 stringset, uint8_t *buf)
 378 {
 379         int i;
 380
 381         if (stringset != ETH_SS_STATS)
 382                 return;
 383
 384         for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
 385                 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
 386                        ETH_GSTRING_LEN);
 387         }
 388 }
 389
 390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
 391                                     u8 member)
 392 {
 393         ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
 394         dev->ports[port].member = member;
 395 }
 396
 397 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
 398                                        u8 state)
 399 {
 400         struct ksz_device *dev = ds->priv;
 401         struct ksz_port *p = &dev->ports[port];
 402         u8 data;
 403         int member = -1;
 404         int forward = dev->member;
 405
 406         ksz_pread8(dev, port, P_STP_CTRL, &data);
 407         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 408
 409         switch (state) {
 410         case BR_STATE_DISABLED:
 411                 data |= PORT_LEARN_DISABLE;
 412                 if (port != dev->cpu_port)
 413                         member = 0;
 414                 break;
 415         case BR_STATE_LISTENING:
 416                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 417                 if (port != dev->cpu_port &&
 418                     p->stp_state == BR_STATE_DISABLED)
 419                         member = dev->host_mask | p->vid_member;
 420                 break;
 421         case BR_STATE_LEARNING:
 422                 data |= PORT_RX_ENABLE;
 423                 break;
 424         case BR_STATE_FORWARDING:
 425                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
 426
 427                 /* This function is also used internally. */
 428                 if (port == dev->cpu_port)
 429                         break;
 430
 431                 member = dev->host_mask | p->vid_member;
 432                 mutex_lock(&dev->dev_mutex);
 433
 434                 /* Port is a member of a bridge. */
 435                 if (dev->br_member & (1 << port)) {
 436                         dev->member |= (1 << port);
 437                         member = dev->member;
 438                 }
 439                 mutex_unlock(&dev->dev_mutex);
 440                 break;
 441         case BR_STATE_BLOCKING:
 442                 data |= PORT_LEARN_DISABLE;
 443                 if (port != dev->cpu_port &&
 444                     p->stp_state == BR_STATE_DISABLED)
 445                         member = dev->host_mask | p->vid_member;
 446                 break;
 447         default:
 448                 dev_err(ds->dev, "invalid STP state: %d\n", state);
 449                 return;
 450         }
 451
 452         ksz_pwrite8(dev, port, P_STP_CTRL, data);
 453         p->stp_state = state;
 454         mutex_lock(&dev->dev_mutex);
 455         /* Port membership may share register with STP state. */
 456         if (member >= 0 && member != p->member)
 457                 ksz9477_cfg_port_member(dev, port, (u8)member);
 458
 459         /* Check if forwarding needs to be updated. */
 460         if (state != BR_STATE_FORWARDING) {
 461                 if (dev->br_member & (1 << port))
 462                         dev->member &= ~(1 << port);
 463         }
 464
 465         /* When topology has changed the function ksz_update_port_member
 466          * should be called to modify port forwarding behavior.
 467          */
 468         if (forward != dev->member)
 469                 ksz_update_port_member(dev, port);
 470         mutex_unlock(&dev->dev_mutex);
 471 }
 472
 473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
 474 {
 475         u8 data;
 476
 477         regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
 478                            SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
 479                            SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
 480
 481         if (port < dev->port_cnt) {
 482                 /* flush individual port */
 483                 ksz_pread8(dev, port, P_STP_CTRL, &data);
 484                 if (!(data & PORT_LEARN_DISABLE))
 485                         ksz_pwrite8(dev, port, P_STP_CTRL,
 486                                     data | PORT_LEARN_DISABLE);
 487                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
 488                 ksz_pwrite8(dev, port, P_STP_CTRL, data);
 489         } else {
 490                 /* flush all */
 491                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
 492         }
 493 }
 494
 495 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
 496                                        bool flag,
 497                                        struct switchdev_trans *trans)
 498 {
 499         struct ksz_device *dev = ds->priv;
 500
 501         if (switchdev_trans_ph_prepare(trans))
 502                 return 0;
 503
 504         if (flag) {
 505                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 506                              PORT_VLAN_LOOKUP_VID_0, true);
 507                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
 508         } else {
 509                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
 510                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 511                              PORT_VLAN_LOOKUP_VID_0, false);
 512         }
 513
 514         return 0;
 515 }
 516
 517 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
 518                                   const struct switchdev_obj_port_vlan *vlan)
 519 {
 520         struct ksz_device *dev = ds->priv;
 521         u32 vlan_table[3];
 522         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 523
 524         if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
 525                 dev_dbg(dev->dev, "Failed to get vlan table\n");
 526                 return;
 527         }
 528
 529         vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M);
 530         if (untagged)
 531                 vlan_table[1] |= BIT(port);
 532         else
 533                 vlan_table[1] &= ~BIT(port);
 534         vlan_table[1] &= ~(BIT(dev->cpu_port));
 535
 536         vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
 537
 538         if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
 539                 dev_dbg(dev->dev, "Failed to set vlan table\n");
 540                 return;
 541         }
 542
 543         /* change PVID */
 544         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
 545                 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid);
 546 }
 547
 548 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
 549                                  const struct switchdev_obj_port_vlan *vlan)
 550 {
 551         struct ksz_device *dev = ds->priv;
 552         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 553         u32 vlan_table[3];
 554         u16 pvid;
 555
 556         ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
 557         pvid = pvid & 0xFFF;
 558
 559         if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
 560                 dev_dbg(dev->dev, "Failed to get vlan table\n");
 561                 return -ETIMEDOUT;
 562         }
 563
 564         vlan_table[2] &= ~BIT(port);
 565
 566         if (pvid == vlan->vid)
 567                 pvid = 1;
 568
 569         if (untagged)
 570                 vlan_table[1] &= ~BIT(port);
 571
 572         if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
 573                 dev_dbg(dev->dev, "Failed to set vlan table\n");
 574                 return -ETIMEDOUT;
 575         }
 576
 577         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
 578
 579         return 0;
 580 }
 581
 582 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
 583                                 const unsigned char *addr, u16 vid)
 584 {
 585         struct ksz_device *dev = ds->priv;
 586         u32 alu_table[4];
 587         u32 data;
 588         int ret = 0;
 589
 590         mutex_lock(&dev->alu_mutex);
 591
 592         /* find any entry with mac & vid */
 593         data = vid << ALU_FID_INDEX_S;
 594         data |= ((addr[0] << 8) | addr[1]);
 595         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 596
 597         data = ((addr[2] << 24) | (addr[3] << 16));
 598         data |= ((addr[4] << 8) | addr[5]);
 599         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 600
 601         /* start read operation */
 602         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 603
 604         /* wait to be finished */
 605         ret = ksz9477_wait_alu_ready(dev);
 606         if (ret) {
 607                 dev_dbg(dev->dev, "Failed to read ALU\n");
 608                 goto exit;
 609         }
 610
 611         /* read ALU entry */
 612         ksz9477_read_table(dev, alu_table);
 613
 614         /* update ALU entry */
 615         alu_table[0] = ALU_V_STATIC_VALID;
 616         alu_table[1] |= BIT(port);
 617         if (vid)
 618                 alu_table[1] |= ALU_V_USE_FID;
 619         alu_table[2] = (vid << ALU_V_FID_S);
 620         alu_table[2] |= ((addr[0] << 8) | addr[1]);
 621         alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
 622         alu_table[3] |= ((addr[4] << 8) | addr[5]);
 623
 624         ksz9477_write_table(dev, alu_table);
 625
 626         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 627
 628         /* wait to be finished */
 629         ret = ksz9477_wait_alu_ready(dev);
 630         if (ret)
 631                 dev_dbg(dev->dev, "Failed to write ALU\n");
 632
 633 exit:
 634         mutex_unlock(&dev->alu_mutex);
 635
 636         return ret;
 637 }
 638
 639 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
 640                                 const unsigned char *addr, u16 vid)
 641 {
 642         struct ksz_device *dev = ds->priv;
 643         u32 alu_table[4];
 644         u32 data;
 645         int ret = 0;
 646
 647         mutex_lock(&dev->alu_mutex);
 648
 649         /* read any entry with mac & vid */
 650         data = vid << ALU_FID_INDEX_S;
 651         data |= ((addr[0] << 8) | addr[1]);
 652         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 653
 654         data = ((addr[2] << 24) | (addr[3] << 16));
 655         data |= ((addr[4] << 8) | addr[5]);
 656         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 657
 658         /* start read operation */
 659         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 660
 661         /* wait to be finished */
 662         ret = ksz9477_wait_alu_ready(dev);
 663         if (ret) {
 664                 dev_dbg(dev->dev, "Failed to read ALU\n");
 665                 goto exit;
 666         }
 667
 668         ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
 669         if (alu_table[0] & ALU_V_STATIC_VALID) {
 670                 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
 671                 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
 672                 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
 673
 674                 /* clear forwarding port */
 675                 alu_table[2] &= ~BIT(port);
 676
 677                 /* if there is no port to forward, clear table */
 678                 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
 679                         alu_table[0] = 0;
 680                         alu_table[1] = 0;
 681                         alu_table[2] = 0;
 682                         alu_table[3] = 0;
 683                 }
 684         } else {
 685                 alu_table[0] = 0;
 686                 alu_table[1] = 0;
 687                 alu_table[2] = 0;
 688                 alu_table[3] = 0;
 689         }
 690
 691         ksz9477_write_table(dev, alu_table);
 692
 693         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 694
 695         /* wait to be finished */
 696         ret = ksz9477_wait_alu_ready(dev);
 697         if (ret)
 698                 dev_dbg(dev->dev, "Failed to write ALU\n");
 699
 700 exit:
 701         mutex_unlock(&dev->alu_mutex);
 702
 703         return ret;
 704 }
 705
 706 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
 707 {
 708         alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
 709         alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
 710         alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
 711         alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
 712                         ALU_V_PRIO_AGE_CNT_M;
 713         alu->mstp = alu_table[0] & ALU_V_MSTP_M;
 714
 715         alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
 716         alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
 717         alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
 718
 719         alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
 720
 721         alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
 722         alu->mac[1] = alu_table[2] & 0xFF;
 723         alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
 724         alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
 725         alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
 726         alu->mac[5] = alu_table[3] & 0xFF;
 727 }
 728
 729 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
 730                                  dsa_fdb_dump_cb_t *cb, void *data)
 731 {
 732         struct ksz_device *dev = ds->priv;
 733         int ret = 0;
 734         u32 ksz_data;
 735         u32 alu_table[4];
 736         struct alu_struct alu;
 737         int timeout;
 738
 739         mutex_lock(&dev->alu_mutex);
 740
 741         /* start ALU search */
 742         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
 743
 744         do {
 745                 timeout = 1000;
 746                 do {
 747                         ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
 748                         if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
 749                                 break;
 750                         usleep_range(1, 10);
 751                 } while (timeout-- > 0);
 752
 753                 if (!timeout) {
 754                         dev_dbg(dev->dev, "Failed to search ALU\n");
 755                         ret = -ETIMEDOUT;
 756                         goto exit;
 757                 }
 758
 759                 /* read ALU table */
 760                 ksz9477_read_table(dev, alu_table);
 761
 762                 ksz9477_convert_alu(&alu, alu_table);
 763
 764                 if (alu.port_forward & BIT(port)) {
 765                         ret = cb(alu.mac, alu.fid, alu.is_static, data);
 766                         if (ret)
 767                                 goto exit;
 768                 }
 769         } while (ksz_data & ALU_START);
 770
 771 exit:
 772
 773         /* stop ALU search */
 774         ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
 775
 776         mutex_unlock(&dev->alu_mutex);
 777
 778         return ret;
 779 }
 780
 781 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
 782                                  const struct switchdev_obj_port_mdb *mdb)
 783 {
 784         struct ksz_device *dev = ds->priv;
 785         u32 static_table[4];
 786         u32 data;
 787         int index;
 788         u32 mac_hi, mac_lo;
 789
 790         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 791         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 792         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 793
 794         mutex_lock(&dev->alu_mutex);
 795
 796         for (index = 0; index < dev->num_statics; index++) {
 797                 /* find empty slot first */
 798                 data = (index << ALU_STAT_INDEX_S) |
 799                         ALU_STAT_READ | ALU_STAT_START;
 800                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 801
 802                 /* wait to be finished */
 803                 if (ksz9477_wait_alu_sta_ready(dev)) {
 804                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 805                         goto exit;
 806                 }
 807
 808                 /* read ALU static table */
 809                 ksz9477_read_table(dev, static_table);
 810
 811                 if (static_table[0] & ALU_V_STATIC_VALID) {
 812                         /* check this has same vid & mac address */
 813                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 814                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 815                             static_table[3] == mac_lo) {
 816                                 /* found matching one */
 817                                 break;
 818                         }
 819                 } else {
 820                         /* found empty one */
 821                         break;
 822                 }
 823         }
 824
 825         /* no available entry */
 826         if (index == dev->num_statics)
 827                 goto exit;
 828
 829         /* add entry */
 830         static_table[0] = ALU_V_STATIC_VALID;
 831         static_table[1] |= BIT(port);
 832         if (mdb->vid)
 833                 static_table[1] |= ALU_V_USE_FID;
 834         static_table[2] = (mdb->vid << ALU_V_FID_S);
 835         static_table[2] |= mac_hi;
 836         static_table[3] = mac_lo;
 837
 838         ksz9477_write_table(dev, static_table);
 839
 840         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 841         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 842
 843         /* wait to be finished */
 844         if (ksz9477_wait_alu_sta_ready(dev))
 845                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 846
 847 exit:
 848         mutex_unlock(&dev->alu_mutex);
 849 }
 850
 851 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
 852                                 const struct switchdev_obj_port_mdb *mdb)
 853 {
 854         struct ksz_device *dev = ds->priv;
 855         u32 static_table[4];
 856         u32 data;
 857         int index;
 858         int ret = 0;
 859         u32 mac_hi, mac_lo;
 860
 861         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 862         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 863         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 864
 865         mutex_lock(&dev->alu_mutex);
 866
 867         for (index = 0; index < dev->num_statics; index++) {
 868                 /* find empty slot first */
 869                 data = (index << ALU_STAT_INDEX_S) |
 870                         ALU_STAT_READ | ALU_STAT_START;
 871                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 872
 873                 /* wait to be finished */
 874                 ret = ksz9477_wait_alu_sta_ready(dev);
 875                 if (ret) {
 876                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 877                         goto exit;
 878                 }
 879
 880                 /* read ALU static table */
 881                 ksz9477_read_table(dev, static_table);
 882
 883                 if (static_table[0] & ALU_V_STATIC_VALID) {
 884                         /* check this has same vid & mac address */
 885
 886                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 887                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 888                             static_table[3] == mac_lo) {
 889                                 /* found matching one */
 890                                 break;
 891                         }
 892                 }
 893         }
 894
 895         /* no available entry */
 896         if (index == dev->num_statics)
 897                 goto exit;
 898
 899         /* clear port */
 900         static_table[1] &= ~BIT(port);
 901
 902         if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
 903                 /* delete entry */
 904                 static_table[0] = 0;
 905                 static_table[1] = 0;
 906                 static_table[2] = 0;
 907                 static_table[3] = 0;
 908         }
 909
 910         ksz9477_write_table(dev, static_table);
 911
 912         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 913         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 914
 915         /* wait to be finished */
 916         ret = ksz9477_wait_alu_sta_ready(dev);
 917         if (ret)
 918                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 919
 920 exit:
 921         mutex_unlock(&dev->alu_mutex);
 922
 923         return ret;
 924 }
 925
 926 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
 927                                    struct dsa_mall_mirror_tc_entry *mirror,
 928                                    bool ingress)
 929 {
 930         struct ksz_device *dev = ds->priv;
 931
 932         if (ingress)
 933                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
 934         else
 935                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
 936
 937         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
 938
 939         /* configure mirror port */
 940         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 941                      PORT_MIRROR_SNIFFER, true);
 942
 943         ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
 944
 945         return 0;
 946 }
 947
 948 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
 949                                     struct dsa_mall_mirror_tc_entry *mirror)
 950 {
 951         struct ksz_device *dev = ds->priv;
 952         u8 data;
 953
 954         if (mirror->ingress)
 955                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
 956         else
 957                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
 958
 959         ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
 960
 961         if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
 962                 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 963                              PORT_MIRROR_SNIFFER, false);
 964 }
 965
 966 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
 967 {
 968         bool gbit;
 969
 970         if (dev->features & NEW_XMII)
 971                 gbit = !(data & PORT_MII_NOT_1GBIT);
 972         else
 973                 gbit = !!(data & PORT_MII_1000MBIT_S1);
 974         return gbit;
 975 }
 976
 977 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
 978 {
 979         if (dev->features & NEW_XMII) {
 980                 if (gbit)
 981                         *data &= ~PORT_MII_NOT_1GBIT;
 982                 else
 983                         *data |= PORT_MII_NOT_1GBIT;
 984         } else {
 985                 if (gbit)
 986                         *data |= PORT_MII_1000MBIT_S1;
 987                 else
 988                         *data &= ~PORT_MII_1000MBIT_S1;
 989         }
 990 }
 991
 992 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
 993 {
 994         int mode;
 995
 996         if (dev->features & NEW_XMII) {
 997                 switch (data & PORT_MII_SEL_M) {
 998                 case PORT_MII_SEL:
 999                         mode = 0;
1000                         break;
1001                 case PORT_RMII_SEL:
1002                         mode = 1;
1003                         break;
1004                 case PORT_GMII_SEL:
1005                         mode = 2;
1006                         break;
1007                 default:
1008                         mode = 3;
1009                 }
1010         } else {
1011                 switch (data & PORT_MII_SEL_M) {
1012                 case PORT_MII_SEL_S1:
1013                         mode = 0;
1014                         break;
1015                 case PORT_RMII_SEL_S1:
1016                         mode = 1;
1017                         break;
1018                 case PORT_GMII_SEL_S1:
1019                         mode = 2;
1020                         break;
1021                 default:
1022                         mode = 3;
1023                 }
1024         }
1025         return mode;
1026 }
1027
1028 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1029 {
1030         u8 xmii;
1031
1032         if (dev->features & NEW_XMII) {
1033                 switch (mode) {
1034                 case 0:
1035                         xmii = PORT_MII_SEL;
1036                         break;
1037                 case 1:
1038                         xmii = PORT_RMII_SEL;
1039                         break;
1040                 case 2:
1041                         xmii = PORT_GMII_SEL;
1042                         break;
1043                 default:
1044                         xmii = PORT_RGMII_SEL;
1045                         break;
1046                 }
1047         } else {
1048                 switch (mode) {
1049                 case 0:
1050                         xmii = PORT_MII_SEL_S1;
1051                         break;
1052                 case 1:
1053                         xmii = PORT_RMII_SEL_S1;
1054                         break;
1055                 case 2:
1056                         xmii = PORT_GMII_SEL_S1;
1057                         break;
1058                 default:
1059                         xmii = PORT_RGMII_SEL_S1;
1060                         break;
1061                 }
1062         }
1063         *data &= ~PORT_MII_SEL_M;
1064         *data |= xmii;
1065 }
1066
1067 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1068 {
1069         phy_interface_t interface;
1070         bool gbit;
1071         int mode;
1072         u8 data8;
1073
1074         if (port < dev->phy_port_cnt)
1075                 return PHY_INTERFACE_MODE_NA;
1076         ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1077         gbit = ksz9477_get_gbit(dev, data8);
1078         mode = ksz9477_get_xmii(dev, data8);
1079         switch (mode) {
1080         case 2:
1081                 interface = PHY_INTERFACE_MODE_GMII;
1082                 if (gbit)
1083                         break;
1084                 fallthrough;
1085         case 0:
1086                 interface = PHY_INTERFACE_MODE_MII;
1087                 break;
1088         case 1:
1089                 interface = PHY_INTERFACE_MODE_RMII;
1090                 break;
1091         default:
1092                 interface = PHY_INTERFACE_MODE_RGMII;
1093                 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1094                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
1095                 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1096                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
1097                         if (data8 & PORT_RGMII_ID_EG_ENABLE)
1098                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1099                 }
1100                 break;
1101         }
1102         return interface;
1103 }
1104
1105 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1106                                    u8 dev_addr, u16 reg_addr, u16 val)
1107 {
1108         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1109                      MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1110         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1111         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1112                      MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1113         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1114 }
1115
1116 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1117 {
1118         /* Apply PHY settings to address errata listed in
1119          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1120          * Silicon Errata and Data Sheet Clarification documents:
1121          *
1122          * Register settings are needed to improve PHY receive performance
1123          */
1124         ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1125         ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1126         ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1127         ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1128         ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1129         ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1130         ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1131
1132         /* Transmit waveform amplitude can be improved
1133          * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1134          */
1135         ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1136
1137         /* Energy Efficient Ethernet (EEE) feature select must
1138          * be manually disabled (except on KSZ8565 which is 100Mbit)
1139          */
1140         if (dev->features & GBIT_SUPPORT)
1141                 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1142
1143         /* Register settings are required to meet data sheet
1144          * supply current specifications
1145          */
1146         ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1147         ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1148         ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1149         ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1150         ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1151         ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1152         ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1153         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1154         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1155         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1156         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1157         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1158         ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1159 }
1160
1161 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1162 {
1163         u8 data8;
1164         u8 member;
1165         u16 data16;
1166         struct ksz_port *p = &dev->ports[port];
1167
1168         /* enable tag tail for host port */
1169         if (cpu_port)
1170                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1171                              true);
1172
1173         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1174
1175         /* set back pressure */
1176         ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1177
1178         /* enable broadcast storm limit */
1179         ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1180
1181         /* disable DiffServ priority */
1182         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1183
1184         /* replace priority */
1185         ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1186                      false);
1187         ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1188                            MTI_PVID_REPLACE, false);
1189
1190         /* enable 802.1p priority */
1191         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1192
1193         if (port < dev->phy_port_cnt) {
1194                 /* do not force flow control */
1195                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1196                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1197                              false);
1198
1199                 if (dev->phy_errata_9477)
1200                         ksz9477_phy_errata_setup(dev, port);
1201         } else {
1202                 /* force flow control */
1203                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1204                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1205                              true);
1206
1207                 /* configure MAC to 1G & RGMII mode */
1208                 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1209                 switch (p->interface) {
1210                 case PHY_INTERFACE_MODE_MII:
1211                         ksz9477_set_xmii(dev, 0, &data8);
1212                         ksz9477_set_gbit(dev, false, &data8);
1213                         p->phydev.speed = SPEED_100;
1214                         break;
1215                 case PHY_INTERFACE_MODE_RMII:
1216                         ksz9477_set_xmii(dev, 1, &data8);
1217                         ksz9477_set_gbit(dev, false, &data8);
1218                         p->phydev.speed = SPEED_100;
1219                         break;
1220                 case PHY_INTERFACE_MODE_GMII:
1221                         ksz9477_set_xmii(dev, 2, &data8);
1222                         ksz9477_set_gbit(dev, true, &data8);
1223                         p->phydev.speed = SPEED_1000;
1224                         break;
1225                 default:
1226                         ksz9477_set_xmii(dev, 3, &data8);
1227                         ksz9477_set_gbit(dev, true, &data8);
1228                         data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1229                         data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1230                         if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1231                             p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1232                                 data8 |= PORT_RGMII_ID_IG_ENABLE;
1233                         if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1234                             p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1235                                 data8 |= PORT_RGMII_ID_EG_ENABLE;
1236                         /* On KSZ9893, disable RGMII in-band status support */
1237                         if (dev->features & IS_9893)
1238                                 data8 &= ~PORT_MII_MAC_MODE;
1239                         p->phydev.speed = SPEED_1000;
1240                         break;
1241                 }
1242                 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1243                 p->phydev.duplex = 1;
1244         }
1245         mutex_lock(&dev->dev_mutex);
1246         if (cpu_port)
1247                 member = dev->port_mask;
1248         else
1249                 member = dev->host_mask | p->vid_member;
1250         mutex_unlock(&dev->dev_mutex);
1251         ksz9477_cfg_port_member(dev, port, member);
1252
1253         /* clear pending interrupts */
1254         if (port < dev->phy_port_cnt)
1255                 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1256 }
1257
1258 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1259 {
1260         struct ksz_device *dev = ds->priv;
1261         struct ksz_port *p;
1262         int i;
1263
1264         for (i = 0; i < dev->port_cnt; i++) {
1265                 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1266                         phy_interface_t interface;
1267                         const char *prev_msg;
1268                         const char *prev_mode;
1269
1270                         dev->cpu_port = i;
1271                         dev->host_mask = (1 << dev->cpu_port);
1272                         dev->port_mask |= dev->host_mask;
1273                         p = &dev->ports[i];
1274
1275                         /* Read from XMII register to determine host port
1276                          * interface.  If set specifically in device tree
1277                          * note the difference to help debugging.
1278                          */
1279                         interface = ksz9477_get_interface(dev, i);
1280                         if (!p->interface) {
1281                                 if (dev->compat_interface) {
1282                                         dev_warn(dev->dev,
1283                                                  "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1284                                                  "Please update your device tree.\n",
1285                                                  i);
1286                                         p->interface = dev->compat_interface;
1287                                 } else {
1288                                         p->interface = interface;
1289                                 }
1290                         }
1291                         if (interface && interface != p->interface) {
1292                                 prev_msg = " instead of ";
1293                                 prev_mode = phy_modes(interface);
1294                         } else {
1295                                 prev_msg = "";
1296                                 prev_mode = "";
1297                         }
1298                         dev_info(dev->dev,
1299                                  "Port%d: using phy mode %s%s%s\n",
1300                                  i,
1301                                  phy_modes(p->interface),
1302                                  prev_msg,
1303                                  prev_mode);
1304
1305                         /* enable cpu port */
1306                         ksz9477_port_setup(dev, i, true);
1307                         p->vid_member = dev->port_mask;
1308                         p->on = 1;
1309                 }
1310         }
1311
1312         dev->member = dev->host_mask;
1313
1314         for (i = 0; i < dev->port_cnt; i++) {
1315                 if (i == dev->cpu_port)
1316                         continue;
1317                 p = &dev->ports[i];
1318
1319                 /* Initialize to non-zero so that ksz_cfg_port_member() will
1320                  * be called.
1321                  */
1322                 p->vid_member = (1 << i);
1323                 p->member = dev->port_mask;
1324                 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1325                 p->on = 1;
1326                 if (i < dev->phy_port_cnt)
1327                         p->phy = 1;
1328                 if (dev->chip_id == 0x00947700 && i == 6) {
1329                         p->sgmii = 1;
1330
1331                         /* SGMII PHY detection code is not implemented yet. */
1332                         p->phy = 0;
1333                 }
1334         }
1335 }
1336
1337 static int ksz9477_setup(struct dsa_switch *ds)
1338 {
1339         struct ksz_device *dev = ds->priv;
1340         int ret = 0;
1341
1342         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1343                                        dev->num_vlans, GFP_KERNEL);
1344         if (!dev->vlan_cache)
1345                 return -ENOMEM;
1346
1347         ret = ksz9477_reset_switch(dev);
1348         if (ret) {
1349                 dev_err(ds->dev, "failed to reset switch\n");
1350                 return ret;
1351         }
1352
1353         /* Required for port partitioning. */
1354         ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1355                       true);
1356
1357         /* Do not work correctly with tail tagging. */
1358         ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1359
1360         /* accept packet up to 2000bytes */
1361         ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1362
1363         ksz9477_config_cpu_port(ds);
1364
1365         ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1366
1367         /* queue based egress rate limit */
1368         ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1369
1370         /* enable global MIB counter freeze function */
1371         ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1372
1373         /* start switch */
1374         ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1375
1376         ksz_init_mib_timer(dev);
1377
1378         return 0;
1379 }
1380
1381 static const struct dsa_switch_ops ksz9477_switch_ops = {
1382         .get_tag_protocol       = ksz9477_get_tag_protocol,
1383         .setup                  = ksz9477_setup,
1384         .phy_read               = ksz9477_phy_read16,
1385         .phy_write              = ksz9477_phy_write16,
1386         .phylink_mac_link_down  = ksz_mac_link_down,
1387         .port_enable            = ksz_enable_port,
1388         .get_strings            = ksz9477_get_strings,
1389         .get_ethtool_stats      = ksz_get_ethtool_stats,
1390         .get_sset_count         = ksz_sset_count,
1391         .port_bridge_join       = ksz_port_bridge_join,
1392         .port_bridge_leave      = ksz_port_bridge_leave,
1393         .port_stp_state_set     = ksz9477_port_stp_state_set,
1394         .port_fast_age          = ksz_port_fast_age,
1395         .port_vlan_filtering    = ksz9477_port_vlan_filtering,
1396         .port_vlan_prepare      = ksz_port_vlan_prepare,
1397         .port_vlan_add          = ksz9477_port_vlan_add,
1398         .port_vlan_del          = ksz9477_port_vlan_del,
1399         .port_fdb_dump          = ksz9477_port_fdb_dump,
1400         .port_fdb_add           = ksz9477_port_fdb_add,
1401         .port_fdb_del           = ksz9477_port_fdb_del,
1402         .port_mdb_prepare       = ksz_port_mdb_prepare,
1403         .port_mdb_add           = ksz9477_port_mdb_add,
1404         .port_mdb_del           = ksz9477_port_mdb_del,
1405         .port_mirror_add        = ksz9477_port_mirror_add,
1406         .port_mirror_del        = ksz9477_port_mirror_del,
1407 };
1408
1409 static u32 ksz9477_get_port_addr(int port, int offset)
1410 {
1411         return PORT_CTRL_ADDR(port, offset);
1412 }
1413
1414 static int ksz9477_switch_detect(struct ksz_device *dev)
1415 {
1416         u8 data8;
1417         u8 id_hi;
1418         u8 id_lo;
1419         u32 id32;
1420         int ret;
1421
1422         /* turn off SPI DO Edge select */
1423         ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1424         if (ret)
1425                 return ret;
1426
1427         data8 &= ~SPI_AUTO_EDGE_DETECTION;
1428         ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1429         if (ret)
1430                 return ret;
1431
1432         /* read chip id */
1433         ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1434         if (ret)
1435                 return ret;
1436         ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1437         if (ret)
1438                 return ret;
1439
1440         /* Number of ports can be reduced depending on chip. */
1441         dev->phy_port_cnt = 5;
1442
1443         /* Default capability is gigabit capable. */
1444         dev->features = GBIT_SUPPORT;
1445
1446         dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8);
1447         id_hi = (u8)(id32 >> 16);
1448         id_lo = (u8)(id32 >> 8);
1449         if ((id_lo & 0xf) == 3) {
1450                 /* Chip is from KSZ9893 design. */
1451                 dev_info(dev->dev, "Found KSZ9893\n");
1452                 dev->features |= IS_9893;
1453
1454                 /* Chip does not support gigabit. */
1455                 if (data8 & SW_QW_ABLE)
1456                         dev->features &= ~GBIT_SUPPORT;
1457                 dev->phy_port_cnt = 2;
1458         } else {
1459                 dev_info(dev->dev, "Found KSZ9477 or compatible\n");
1460                 /* Chip uses new XMII register definitions. */
1461                 dev->features |= NEW_XMII;
1462
1463                 /* Chip does not support gigabit. */
1464                 if (!(data8 & SW_GIGABIT_ABLE))
1465                         dev->features &= ~GBIT_SUPPORT;
1466         }
1467
1468         /* Change chip id to known ones so it can be matched against them. */
1469         id32 = (id_hi << 16) | (id_lo << 8);
1470
1471         dev->chip_id = id32;
1472
1473         return 0;
1474 }
1475
1476 struct ksz_chip_data {
1477         u32 chip_id;
1478         const char *dev_name;
1479         int num_vlans;
1480         int num_alus;
1481         int num_statics;
1482         int cpu_ports;
1483         int port_cnt;
1484         bool phy_errata_9477;
1485 };
1486
1487 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1488         {
1489                 .chip_id = 0x00947700,
1490                 .dev_name = "KSZ9477",
1491                 .num_vlans = 4096,
1492                 .num_alus = 4096,
1493                 .num_statics = 16,
1494                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1495                 .port_cnt = 7,          /* total physical port count */
1496                 .phy_errata_9477 = true,
1497         },
1498         {
1499                 .chip_id = 0x00989700,
1500                 .dev_name = "KSZ9897",
1501                 .num_vlans = 4096,
1502                 .num_alus = 4096,
1503                 .num_statics = 16,
1504                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1505                 .port_cnt = 7,          /* total physical port count */
1506                 .phy_errata_9477 = true,
1507         },
1508         {
1509                 .chip_id = 0x00989300,
1510                 .dev_name = "KSZ9893",
1511                 .num_vlans = 4096,
1512                 .num_alus = 4096,
1513                 .num_statics = 16,
1514                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1515                 .port_cnt = 3,          /* total port count */
1516         },
1517         {
1518                 .chip_id = 0x00956700,
1519                 .dev_name = "KSZ9567",
1520                 .num_vlans = 4096,
1521                 .num_alus = 4096,
1522                 .num_statics = 16,
1523                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1524                 .port_cnt = 7,          /* total physical port count */
1525         },
1526 };
1527
1528 static int ksz9477_switch_init(struct ksz_device *dev)
1529 {
1530         int i;
1531
1532         dev->ds->ops = &ksz9477_switch_ops;
1533
1534         for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1535                 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1536
1537                 if (dev->chip_id == chip->chip_id) {
1538                         dev->name = chip->dev_name;
1539                         dev->num_vlans = chip->num_vlans;
1540                         dev->num_alus = chip->num_alus;
1541                         dev->num_statics = chip->num_statics;
1542                         dev->port_cnt = chip->port_cnt;
1543                         dev->cpu_ports = chip->cpu_ports;
1544                         dev->phy_errata_9477 = chip->phy_errata_9477;
1545
1546                         break;
1547                 }
1548         }
1549
1550         /* no switch found */
1551         if (!dev->port_cnt)
1552                 return -ENODEV;
1553
1554         dev->port_mask = (1 << dev->port_cnt) - 1;
1555
1556         dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1557         dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1558
1559         dev->ports = devm_kzalloc(dev->dev,
1560                                   dev->port_cnt * sizeof(struct ksz_port),
1561                                   GFP_KERNEL);
1562         if (!dev->ports)
1563                 return -ENOMEM;
1564         for (i = 0; i < dev->port_cnt; i++) {
1565                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1566                 dev->ports[i].mib.counters =
1567                         devm_kzalloc(dev->dev,
1568                                      sizeof(u64) *
1569                                      (TOTAL_SWITCH_COUNTER_NUM + 1),
1570                                      GFP_KERNEL);
1571                 if (!dev->ports[i].mib.counters)
1572                         return -ENOMEM;
1573         }
1574
1575         /* set the real number of ports */
1576         dev->ds->num_ports = dev->port_cnt;
1577
1578         return 0;
1579 }
1580
1581 static void ksz9477_switch_exit(struct ksz_device *dev)
1582 {
1583         ksz9477_reset_switch(dev);
1584 }
1585
1586 static const struct ksz_dev_ops ksz9477_dev_ops = {
1587         .get_port_addr = ksz9477_get_port_addr,
1588         .cfg_port_member = ksz9477_cfg_port_member,
1589         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1590         .port_setup = ksz9477_port_setup,
1591         .r_mib_cnt = ksz9477_r_mib_cnt,
1592         .r_mib_pkt = ksz9477_r_mib_pkt,
1593         .freeze_mib = ksz9477_freeze_mib,
1594         .port_init_cnt = ksz9477_port_init_cnt,
1595         .shutdown = ksz9477_reset_switch,
1596         .detect = ksz9477_switch_detect,
1597         .init = ksz9477_switch_init,
1598         .exit = ksz9477_switch_exit,
1599 };
1600
1601 int ksz9477_switch_register(struct ksz_device *dev)
1602 {
1603         int ret, i;
1604         struct phy_device *phydev;
1605
1606         ret = ksz_switch_register(dev, &ksz9477_dev_ops);
1607         if (ret)
1608                 return ret;
1609
1610         for (i = 0; i < dev->phy_port_cnt; ++i) {
1611                 if (!dsa_is_user_port(dev->ds, i))
1612                         continue;
1613
1614                 phydev = dsa_to_port(dev->ds, i)->slave->phydev;
1615
1616                 /* The MAC actually cannot run in 1000 half-duplex mode. */
1617                 phy_remove_link_mode(phydev,
1618                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1619
1620                 /* PHY does not support gigabit. */
1621                 if (!(dev->features & GBIT_SUPPORT))
1622                         phy_remove_link_mode(phydev,
1623                                              ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1624         }
1625         return ret;
1626 }
1627 EXPORT_SYMBOL(ksz9477_switch_register);
1628
1629 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1630 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1631 MODULE_LICENSE("GPL");