drivers/net/dsa/microchip/ksz9477.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip KSZ9477 switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_data/microchip-ksz.h>
  12 #include <linux/phy.h>
  13 #include <linux/if_bridge.h>
  14 #include <net/dsa.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ksz_priv.h"
  18 #include "ksz9477_reg.h"
  19 #include "ksz_common.h"
  20
  21 /* Used with variable features to indicate capabilities. */
  22 #define GBIT_SUPPORT                    BIT(0)
  23 #define NEW_XMII                        BIT(1)
  24 #define IS_9893                         BIT(2)
  25
  26 static const struct {
  27         int index;
  28         char string[ETH_GSTRING_LEN];
  29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
  30         { 0x00, "rx_hi" },
  31         { 0x01, "rx_undersize" },
  32         { 0x02, "rx_fragments" },
  33         { 0x03, "rx_oversize" },
  34         { 0x04, "rx_jabbers" },
  35         { 0x05, "rx_symbol_err" },
  36         { 0x06, "rx_crc_err" },
  37         { 0x07, "rx_align_err" },
  38         { 0x08, "rx_mac_ctrl" },
  39         { 0x09, "rx_pause" },
  40         { 0x0A, "rx_bcast" },
  41         { 0x0B, "rx_mcast" },
  42         { 0x0C, "rx_ucast" },
  43         { 0x0D, "rx_64_or_less" },
  44         { 0x0E, "rx_65_127" },
  45         { 0x0F, "rx_128_255" },
  46         { 0x10, "rx_256_511" },
  47         { 0x11, "rx_512_1023" },
  48         { 0x12, "rx_1024_1522" },
  49         { 0x13, "rx_1523_2000" },
  50         { 0x14, "rx_2001" },
  51         { 0x15, "tx_hi" },
  52         { 0x16, "tx_late_col" },
  53         { 0x17, "tx_pause" },
  54         { 0x18, "tx_bcast" },
  55         { 0x19, "tx_mcast" },
  56         { 0x1A, "tx_ucast" },
  57         { 0x1B, "tx_deferred" },
  58         { 0x1C, "tx_total_col" },
  59         { 0x1D, "tx_exc_col" },
  60         { 0x1E, "tx_single_col" },
  61         { 0x1F, "tx_mult_col" },
  62         { 0x80, "rx_total" },
  63         { 0x81, "tx_total" },
  64         { 0x82, "rx_discards" },
  65         { 0x83, "tx_discards" },
  66 };
  67
  68 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
  69 {
  70         regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
  71 }
  72
  73 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
  74                          bool set)
  75 {
  76         regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
  77                            bits, set ? bits : 0);
  78 }
  79
  80 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
  81 {
  82         regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
  83 }
  84
  85 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
  86                                u32 bits, bool set)
  87 {
  88         regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
  89                            bits, set ? bits : 0);
  90 }
  91
  92 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton,
  93                                         int timeout)
  94 {
  95         u8 data;
  96
  97         do {
  98                 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
  99                 if (!(data & waiton))
 100                         break;
 101                 usleep_range(1, 10);
 102         } while (timeout-- > 0);
 103
 104         if (timeout <= 0)
 105                 return -ETIMEDOUT;
 106
 107         return 0;
 108 }
 109
 110 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
 111                                   u32 *vlan_table)
 112 {
 113         int ret;
 114
 115         mutex_lock(&dev->vlan_mutex);
 116
 117         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 118         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
 119
 120         /* wait to be cleared */
 121         ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
 122         if (ret < 0) {
 123                 dev_dbg(dev->dev, "Failed to read vlan table\n");
 124                 goto exit;
 125         }
 126
 127         ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
 128         ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
 129         ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
 130
 131         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 132
 133 exit:
 134         mutex_unlock(&dev->vlan_mutex);
 135
 136         return ret;
 137 }
 138
 139 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
 140                                   u32 *vlan_table)
 141 {
 142         int ret;
 143
 144         mutex_lock(&dev->vlan_mutex);
 145
 146         ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
 147         ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
 148         ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
 149
 150         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 151         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
 152
 153         /* wait to be cleared */
 154         ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
 155         if (ret < 0) {
 156                 dev_dbg(dev->dev, "Failed to write vlan table\n");
 157                 goto exit;
 158         }
 159
 160         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 161
 162         /* update vlan cache table */
 163         dev->vlan_cache[vid].table[0] = vlan_table[0];
 164         dev->vlan_cache[vid].table[1] = vlan_table[1];
 165         dev->vlan_cache[vid].table[2] = vlan_table[2];
 166
 167 exit:
 168         mutex_unlock(&dev->vlan_mutex);
 169
 170         return ret;
 171 }
 172
 173 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
 174 {
 175         ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
 176         ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
 177         ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
 178         ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
 179 }
 180
 181 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
 182 {
 183         ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
 184         ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
 185         ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
 186         ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
 187 }
 188
 189 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton,
 190                                   int timeout)
 191 {
 192         u32 data;
 193
 194         do {
 195                 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
 196                 if (!(data & waiton))
 197                         break;
 198                 usleep_range(1, 10);
 199         } while (timeout-- > 0);
 200
 201         if (timeout <= 0)
 202                 return -ETIMEDOUT;
 203
 204         return 0;
 205 }
 206
 207 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton,
 208                                       int timeout)
 209 {
 210         u32 data;
 211
 212         do {
 213                 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
 214                 if (!(data & waiton))
 215                         break;
 216                 usleep_range(1, 10);
 217         } while (timeout-- > 0);
 218
 219         if (timeout <= 0)
 220                 return -ETIMEDOUT;
 221
 222         return 0;
 223 }
 224
 225 static int ksz9477_reset_switch(struct ksz_device *dev)
 226 {
 227         u8 data8;
 228         u16 data16;
 229         u32 data32;
 230
 231         /* reset switch */
 232         ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
 233
 234         /* turn off SPI DO Edge select */
 235         ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
 236         data8 &= ~SPI_AUTO_EDGE_DETECTION;
 237         ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
 238
 239         /* default configuration */
 240         ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
 241         data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
 242               SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
 243         ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
 244
 245         /* disable interrupts */
 246         ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
 247         ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
 248         ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
 249
 250         /* set broadcast storm protection 10% rate */
 251         ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
 252         data16 &= ~BROADCAST_STORM_RATE;
 253         data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
 254         ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
 255
 256         if (dev->synclko_125)
 257                 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 258                            SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
 259
 260         return 0;
 261 }
 262
 263 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
 264                               u64 *cnt)
 265 {
 266         struct ksz_port *p = &dev->ports[port];
 267         unsigned int val;
 268         u32 data;
 269         int ret;
 270
 271         /* retain the flush/freeze bit */
 272         data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 273         data |= MIB_COUNTER_READ;
 274         data |= (addr << MIB_COUNTER_INDEX_S);
 275         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
 276
 277         ret = regmap_read_poll_timeout(dev->regmap[2],
 278                         PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
 279                         val, !(val & MIB_COUNTER_READ), 10, 1000);
 280         /* failed to read MIB. get out of loop */
 281         if (ret) {
 282                 dev_dbg(dev->dev, "Failed to get MIB\n");
 283                 return;
 284         }
 285
 286         /* count resets upon read */
 287         ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
 288         *cnt += data;
 289 }
 290
 291 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
 292                               u64 *dropped, u64 *cnt)
 293 {
 294         addr = ksz9477_mib_names[addr].index;
 295         ksz9477_r_mib_cnt(dev, port, addr, cnt);
 296 }
 297
 298 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
 299 {
 300         u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 301         struct ksz_port *p = &dev->ports[port];
 302
 303         /* enable/disable the port for flush/freeze function */
 304         mutex_lock(&p->mib.cnt_mutex);
 305         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
 306
 307         /* used by MIB counter reading code to know freeze is enabled */
 308         p->freeze = freeze;
 309         mutex_unlock(&p->mib.cnt_mutex);
 310 }
 311
 312 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
 313 {
 314         struct ksz_port_mib *mib = &dev->ports[port].mib;
 315
 316         /* flush all enabled port MIB counters */
 317         mutex_lock(&mib->cnt_mutex);
 318         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
 319                      MIB_COUNTER_FLUSH_FREEZE);
 320         ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
 321         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
 322         mutex_unlock(&mib->cnt_mutex);
 323
 324         mib->cnt_ptr = 0;
 325         memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
 326 }
 327
 328 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
 329                                                       int port)
 330 {
 331         enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
 332         struct ksz_device *dev = ds->priv;
 333
 334         if (dev->features & IS_9893)
 335                 proto = DSA_TAG_PROTO_KSZ9893;
 336         return proto;
 337 }
 338
 339 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
 340 {
 341         struct ksz_device *dev = ds->priv;
 342         u16 val = 0xffff;
 343
 344         /* No real PHY after this. Simulate the PHY.
 345          * A fixed PHY can be setup in the device tree, but this function is
 346          * still called for that port during initialization.
 347          * For RGMII PHY there is no way to access it so the fixed PHY should
 348          * be used.  For SGMII PHY the supporting code will be added later.
 349          */
 350         if (addr >= dev->phy_port_cnt) {
 351                 struct ksz_port *p = &dev->ports[addr];
 352
 353                 switch (reg) {
 354                 case MII_BMCR:
 355                         val = 0x1140;
 356                         break;
 357                 case MII_BMSR:
 358                         val = 0x796d;
 359                         break;
 360                 case MII_PHYSID1:
 361                         val = 0x0022;
 362                         break;
 363                 case MII_PHYSID2:
 364                         val = 0x1631;
 365                         break;
 366                 case MII_ADVERTISE:
 367                         val = 0x05e1;
 368                         break;
 369                 case MII_LPA:
 370                         val = 0xc5e1;
 371                         break;
 372                 case MII_CTRL1000:
 373                         val = 0x0700;
 374                         break;
 375                 case MII_STAT1000:
 376                         if (p->phydev.speed == SPEED_1000)
 377                                 val = 0x3800;
 378                         else
 379                                 val = 0;
 380                         break;
 381                 }
 382         } else {
 383                 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
 384         }
 385
 386         return val;
 387 }
 388
 389 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
 390                                u16 val)
 391 {
 392         struct ksz_device *dev = ds->priv;
 393
 394         /* No real PHY after this. */
 395         if (addr >= dev->phy_port_cnt)
 396                 return 0;
 397
 398         /* No gigabit support.  Do not write to this register. */
 399         if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
 400                 return 0;
 401         ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
 402
 403         return 0;
 404 }
 405
 406 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
 407                                 u32 stringset, uint8_t *buf)
 408 {
 409         int i;
 410
 411         if (stringset != ETH_SS_STATS)
 412                 return;
 413
 414         for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
 415                 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
 416                        ETH_GSTRING_LEN);
 417         }
 418 }
 419
 420 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
 421                                     u8 member)
 422 {
 423         ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
 424         dev->ports[port].member = member;
 425 }
 426
 427 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
 428                                        u8 state)
 429 {
 430         struct ksz_device *dev = ds->priv;
 431         struct ksz_port *p = &dev->ports[port];
 432         u8 data;
 433         int member = -1;
 434         int forward = dev->member;
 435
 436         ksz_pread8(dev, port, P_STP_CTRL, &data);
 437         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 438
 439         switch (state) {
 440         case BR_STATE_DISABLED:
 441                 data |= PORT_LEARN_DISABLE;
 442                 if (port != dev->cpu_port)
 443                         member = 0;
 444                 break;
 445         case BR_STATE_LISTENING:
 446                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 447                 if (port != dev->cpu_port &&
 448                     p->stp_state == BR_STATE_DISABLED)
 449                         member = dev->host_mask | p->vid_member;
 450                 break;
 451         case BR_STATE_LEARNING:
 452                 data |= PORT_RX_ENABLE;
 453                 break;
 454         case BR_STATE_FORWARDING:
 455                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
 456
 457                 /* This function is also used internally. */
 458                 if (port == dev->cpu_port)
 459                         break;
 460
 461                 member = dev->host_mask | p->vid_member;
 462                 mutex_lock(&dev->dev_mutex);
 463
 464                 /* Port is a member of a bridge. */
 465                 if (dev->br_member & (1 << port)) {
 466                         dev->member |= (1 << port);
 467                         member = dev->member;
 468                 }
 469                 mutex_unlock(&dev->dev_mutex);
 470                 break;
 471         case BR_STATE_BLOCKING:
 472                 data |= PORT_LEARN_DISABLE;
 473                 if (port != dev->cpu_port &&
 474                     p->stp_state == BR_STATE_DISABLED)
 475                         member = dev->host_mask | p->vid_member;
 476                 break;
 477         default:
 478                 dev_err(ds->dev, "invalid STP state: %d\n", state);
 479                 return;
 480         }
 481
 482         ksz_pwrite8(dev, port, P_STP_CTRL, data);
 483         p->stp_state = state;
 484         mutex_lock(&dev->dev_mutex);
 485         if (data & PORT_RX_ENABLE)
 486                 dev->rx_ports |= (1 << port);
 487         else
 488                 dev->rx_ports &= ~(1 << port);
 489         if (data & PORT_TX_ENABLE)
 490                 dev->tx_ports |= (1 << port);
 491         else
 492                 dev->tx_ports &= ~(1 << port);
 493
 494         /* Port membership may share register with STP state. */
 495         if (member >= 0 && member != p->member)
 496                 ksz9477_cfg_port_member(dev, port, (u8)member);
 497
 498         /* Check if forwarding needs to be updated. */
 499         if (state != BR_STATE_FORWARDING) {
 500                 if (dev->br_member & (1 << port))
 501                         dev->member &= ~(1 << port);
 502         }
 503
 504         /* When topology has changed the function ksz_update_port_member
 505          * should be called to modify port forwarding behavior.
 506          */
 507         if (forward != dev->member)
 508                 ksz_update_port_member(dev, port);
 509         mutex_unlock(&dev->dev_mutex);
 510 }
 511
 512 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
 513 {
 514         u8 data;
 515
 516         ksz_read8(dev, REG_SW_LUE_CTRL_2, &data);
 517         data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S);
 518         data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
 519         ksz_write8(dev, REG_SW_LUE_CTRL_2, data);
 520         if (port < dev->mib_port_cnt) {
 521                 /* flush individual port */
 522                 ksz_pread8(dev, port, P_STP_CTRL, &data);
 523                 if (!(data & PORT_LEARN_DISABLE))
 524                         ksz_pwrite8(dev, port, P_STP_CTRL,
 525                                     data | PORT_LEARN_DISABLE);
 526                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
 527                 ksz_pwrite8(dev, port, P_STP_CTRL, data);
 528         } else {
 529                 /* flush all */
 530                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
 531         }
 532 }
 533
 534 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
 535                                        bool flag)
 536 {
 537         struct ksz_device *dev = ds->priv;
 538
 539         if (flag) {
 540                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 541                              PORT_VLAN_LOOKUP_VID_0, true);
 542                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
 543         } else {
 544                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
 545                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 546                              PORT_VLAN_LOOKUP_VID_0, false);
 547         }
 548
 549         return 0;
 550 }
 551
 552 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
 553                                   const struct switchdev_obj_port_vlan *vlan)
 554 {
 555         struct ksz_device *dev = ds->priv;
 556         u32 vlan_table[3];
 557         u16 vid;
 558         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 559
 560         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 561                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 562                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 563                         return;
 564                 }
 565
 566                 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
 567                 if (untagged)
 568                         vlan_table[1] |= BIT(port);
 569                 else
 570                         vlan_table[1] &= ~BIT(port);
 571                 vlan_table[1] &= ~(BIT(dev->cpu_port));
 572
 573                 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
 574
 575                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 576                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 577                         return;
 578                 }
 579
 580                 /* change PVID */
 581                 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
 582                         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
 583         }
 584 }
 585
 586 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
 587                                  const struct switchdev_obj_port_vlan *vlan)
 588 {
 589         struct ksz_device *dev = ds->priv;
 590         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 591         u32 vlan_table[3];
 592         u16 vid;
 593         u16 pvid;
 594
 595         ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
 596         pvid = pvid & 0xFFF;
 597
 598         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 599                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 600                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 601                         return -ETIMEDOUT;
 602                 }
 603
 604                 vlan_table[2] &= ~BIT(port);
 605
 606                 if (pvid == vid)
 607                         pvid = 1;
 608
 609                 if (untagged)
 610                         vlan_table[1] &= ~BIT(port);
 611
 612                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 613                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 614                         return -ETIMEDOUT;
 615                 }
 616         }
 617
 618         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
 619
 620         return 0;
 621 }
 622
 623 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
 624                                 const unsigned char *addr, u16 vid)
 625 {
 626         struct ksz_device *dev = ds->priv;
 627         u32 alu_table[4];
 628         u32 data;
 629         int ret = 0;
 630
 631         mutex_lock(&dev->alu_mutex);
 632
 633         /* find any entry with mac & vid */
 634         data = vid << ALU_FID_INDEX_S;
 635         data |= ((addr[0] << 8) | addr[1]);
 636         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 637
 638         data = ((addr[2] << 24) | (addr[3] << 16));
 639         data |= ((addr[4] << 8) | addr[5]);
 640         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 641
 642         /* start read operation */
 643         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 644
 645         /* wait to be finished */
 646         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 647         if (ret < 0) {
 648                 dev_dbg(dev->dev, "Failed to read ALU\n");
 649                 goto exit;
 650         }
 651
 652         /* read ALU entry */
 653         ksz9477_read_table(dev, alu_table);
 654
 655         /* update ALU entry */
 656         alu_table[0] = ALU_V_STATIC_VALID;
 657         alu_table[1] |= BIT(port);
 658         if (vid)
 659                 alu_table[1] |= ALU_V_USE_FID;
 660         alu_table[2] = (vid << ALU_V_FID_S);
 661         alu_table[2] |= ((addr[0] << 8) | addr[1]);
 662         alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
 663         alu_table[3] |= ((addr[4] << 8) | addr[5]);
 664
 665         ksz9477_write_table(dev, alu_table);
 666
 667         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 668
 669         /* wait to be finished */
 670         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 671         if (ret < 0)
 672                 dev_dbg(dev->dev, "Failed to write ALU\n");
 673
 674 exit:
 675         mutex_unlock(&dev->alu_mutex);
 676
 677         return ret;
 678 }
 679
 680 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
 681                                 const unsigned char *addr, u16 vid)
 682 {
 683         struct ksz_device *dev = ds->priv;
 684         u32 alu_table[4];
 685         u32 data;
 686         int ret = 0;
 687
 688         mutex_lock(&dev->alu_mutex);
 689
 690         /* read any entry with mac & vid */
 691         data = vid << ALU_FID_INDEX_S;
 692         data |= ((addr[0] << 8) | addr[1]);
 693         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 694
 695         data = ((addr[2] << 24) | (addr[3] << 16));
 696         data |= ((addr[4] << 8) | addr[5]);
 697         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 698
 699         /* start read operation */
 700         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 701
 702         /* wait to be finished */
 703         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 704         if (ret < 0) {
 705                 dev_dbg(dev->dev, "Failed to read ALU\n");
 706                 goto exit;
 707         }
 708
 709         ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
 710         if (alu_table[0] & ALU_V_STATIC_VALID) {
 711                 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
 712                 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
 713                 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
 714
 715                 /* clear forwarding port */
 716                 alu_table[2] &= ~BIT(port);
 717
 718                 /* if there is no port to forward, clear table */
 719                 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
 720                         alu_table[0] = 0;
 721                         alu_table[1] = 0;
 722                         alu_table[2] = 0;
 723                         alu_table[3] = 0;
 724                 }
 725         } else {
 726                 alu_table[0] = 0;
 727                 alu_table[1] = 0;
 728                 alu_table[2] = 0;
 729                 alu_table[3] = 0;
 730         }
 731
 732         ksz9477_write_table(dev, alu_table);
 733
 734         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 735
 736         /* wait to be finished */
 737         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 738         if (ret < 0)
 739                 dev_dbg(dev->dev, "Failed to write ALU\n");
 740
 741 exit:
 742         mutex_unlock(&dev->alu_mutex);
 743
 744         return ret;
 745 }
 746
 747 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
 748 {
 749         alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
 750         alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
 751         alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
 752         alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
 753                         ALU_V_PRIO_AGE_CNT_M;
 754         alu->mstp = alu_table[0] & ALU_V_MSTP_M;
 755
 756         alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
 757         alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
 758         alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
 759
 760         alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
 761
 762         alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
 763         alu->mac[1] = alu_table[2] & 0xFF;
 764         alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
 765         alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
 766         alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
 767         alu->mac[5] = alu_table[3] & 0xFF;
 768 }
 769
 770 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
 771                                  dsa_fdb_dump_cb_t *cb, void *data)
 772 {
 773         struct ksz_device *dev = ds->priv;
 774         int ret = 0;
 775         u32 ksz_data;
 776         u32 alu_table[4];
 777         struct alu_struct alu;
 778         int timeout;
 779
 780         mutex_lock(&dev->alu_mutex);
 781
 782         /* start ALU search */
 783         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
 784
 785         do {
 786                 timeout = 1000;
 787                 do {
 788                         ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
 789                         if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
 790                                 break;
 791                         usleep_range(1, 10);
 792                 } while (timeout-- > 0);
 793
 794                 if (!timeout) {
 795                         dev_dbg(dev->dev, "Failed to search ALU\n");
 796                         ret = -ETIMEDOUT;
 797                         goto exit;
 798                 }
 799
 800                 /* read ALU table */
 801                 ksz9477_read_table(dev, alu_table);
 802
 803                 ksz9477_convert_alu(&alu, alu_table);
 804
 805                 if (alu.port_forward & BIT(port)) {
 806                         ret = cb(alu.mac, alu.fid, alu.is_static, data);
 807                         if (ret)
 808                                 goto exit;
 809                 }
 810         } while (ksz_data & ALU_START);
 811
 812 exit:
 813
 814         /* stop ALU search */
 815         ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
 816
 817         mutex_unlock(&dev->alu_mutex);
 818
 819         return ret;
 820 }
 821
 822 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
 823                                  const struct switchdev_obj_port_mdb *mdb)
 824 {
 825         struct ksz_device *dev = ds->priv;
 826         u32 static_table[4];
 827         u32 data;
 828         int index;
 829         u32 mac_hi, mac_lo;
 830
 831         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 832         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 833         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 834
 835         mutex_lock(&dev->alu_mutex);
 836
 837         for (index = 0; index < dev->num_statics; index++) {
 838                 /* find empty slot first */
 839                 data = (index << ALU_STAT_INDEX_S) |
 840                         ALU_STAT_READ | ALU_STAT_START;
 841                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 842
 843                 /* wait to be finished */
 844                 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
 845                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 846                         goto exit;
 847                 }
 848
 849                 /* read ALU static table */
 850                 ksz9477_read_table(dev, static_table);
 851
 852                 if (static_table[0] & ALU_V_STATIC_VALID) {
 853                         /* check this has same vid & mac address */
 854                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 855                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 856                             static_table[3] == mac_lo) {
 857                                 /* found matching one */
 858                                 break;
 859                         }
 860                 } else {
 861                         /* found empty one */
 862                         break;
 863                 }
 864         }
 865
 866         /* no available entry */
 867         if (index == dev->num_statics)
 868                 goto exit;
 869
 870         /* add entry */
 871         static_table[0] = ALU_V_STATIC_VALID;
 872         static_table[1] |= BIT(port);
 873         if (mdb->vid)
 874                 static_table[1] |= ALU_V_USE_FID;
 875         static_table[2] = (mdb->vid << ALU_V_FID_S);
 876         static_table[2] |= mac_hi;
 877         static_table[3] = mac_lo;
 878
 879         ksz9477_write_table(dev, static_table);
 880
 881         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 882         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 883
 884         /* wait to be finished */
 885         if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
 886                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 887
 888 exit:
 889         mutex_unlock(&dev->alu_mutex);
 890 }
 891
 892 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
 893                                 const struct switchdev_obj_port_mdb *mdb)
 894 {
 895         struct ksz_device *dev = ds->priv;
 896         u32 static_table[4];
 897         u32 data;
 898         int index;
 899         int ret = 0;
 900         u32 mac_hi, mac_lo;
 901
 902         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 903         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 904         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 905
 906         mutex_lock(&dev->alu_mutex);
 907
 908         for (index = 0; index < dev->num_statics; index++) {
 909                 /* find empty slot first */
 910                 data = (index << ALU_STAT_INDEX_S) |
 911                         ALU_STAT_READ | ALU_STAT_START;
 912                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 913
 914                 /* wait to be finished */
 915                 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
 916                 if (ret < 0) {
 917                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 918                         goto exit;
 919                 }
 920
 921                 /* read ALU static table */
 922                 ksz9477_read_table(dev, static_table);
 923
 924                 if (static_table[0] & ALU_V_STATIC_VALID) {
 925                         /* check this has same vid & mac address */
 926
 927                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 928                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 929                             static_table[3] == mac_lo) {
 930                                 /* found matching one */
 931                                 break;
 932                         }
 933                 }
 934         }
 935
 936         /* no available entry */
 937         if (index == dev->num_statics)
 938                 goto exit;
 939
 940         /* clear port */
 941         static_table[1] &= ~BIT(port);
 942
 943         if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
 944                 /* delete entry */
 945                 static_table[0] = 0;
 946                 static_table[1] = 0;
 947                 static_table[2] = 0;
 948                 static_table[3] = 0;
 949         }
 950
 951         ksz9477_write_table(dev, static_table);
 952
 953         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 954         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 955
 956         /* wait to be finished */
 957         ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
 958         if (ret < 0)
 959                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 960
 961 exit:
 962         mutex_unlock(&dev->alu_mutex);
 963
 964         return ret;
 965 }
 966
 967 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
 968                                    struct dsa_mall_mirror_tc_entry *mirror,
 969                                    bool ingress)
 970 {
 971         struct ksz_device *dev = ds->priv;
 972
 973         if (ingress)
 974                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
 975         else
 976                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
 977
 978         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
 979
 980         /* configure mirror port */
 981         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 982                      PORT_MIRROR_SNIFFER, true);
 983
 984         ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
 985
 986         return 0;
 987 }
 988
 989 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
 990                                     struct dsa_mall_mirror_tc_entry *mirror)
 991 {
 992         struct ksz_device *dev = ds->priv;
 993         u8 data;
 994
 995         if (mirror->ingress)
 996                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
 997         else
 998                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
 999
1000         ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1001
1002         if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1003                 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1004                              PORT_MIRROR_SNIFFER, false);
1005 }
1006
1007 static void ksz9477_phy_setup(struct ksz_device *dev, int port,
1008                               struct phy_device *phy)
1009 {
1010         /* Only apply to port with PHY. */
1011         if (port >= dev->phy_port_cnt)
1012                 return;
1013
1014         /* The MAC actually cannot run in 1000 half-duplex mode. */
1015         phy_remove_link_mode(phy,
1016                              ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1017
1018         /* PHY does not support gigabit. */
1019         if (!(dev->features & GBIT_SUPPORT))
1020                 phy_remove_link_mode(phy,
1021                                      ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1022 }
1023
1024 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
1025 {
1026         bool gbit;
1027
1028         if (dev->features & NEW_XMII)
1029                 gbit = !(data & PORT_MII_NOT_1GBIT);
1030         else
1031                 gbit = !!(data & PORT_MII_1000MBIT_S1);
1032         return gbit;
1033 }
1034
1035 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
1036 {
1037         if (dev->features & NEW_XMII) {
1038                 if (gbit)
1039                         *data &= ~PORT_MII_NOT_1GBIT;
1040                 else
1041                         *data |= PORT_MII_NOT_1GBIT;
1042         } else {
1043                 if (gbit)
1044                         *data |= PORT_MII_1000MBIT_S1;
1045                 else
1046                         *data &= ~PORT_MII_1000MBIT_S1;
1047         }
1048 }
1049
1050 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
1051 {
1052         int mode;
1053
1054         if (dev->features & NEW_XMII) {
1055                 switch (data & PORT_MII_SEL_M) {
1056                 case PORT_MII_SEL:
1057                         mode = 0;
1058                         break;
1059                 case PORT_RMII_SEL:
1060                         mode = 1;
1061                         break;
1062                 case PORT_GMII_SEL:
1063                         mode = 2;
1064                         break;
1065                 default:
1066                         mode = 3;
1067                 }
1068         } else {
1069                 switch (data & PORT_MII_SEL_M) {
1070                 case PORT_MII_SEL_S1:
1071                         mode = 0;
1072                         break;
1073                 case PORT_RMII_SEL_S1:
1074                         mode = 1;
1075                         break;
1076                 case PORT_GMII_SEL_S1:
1077                         mode = 2;
1078                         break;
1079                 default:
1080                         mode = 3;
1081                 }
1082         }
1083         return mode;
1084 }
1085
1086 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1087 {
1088         u8 xmii;
1089
1090         if (dev->features & NEW_XMII) {
1091                 switch (mode) {
1092                 case 0:
1093                         xmii = PORT_MII_SEL;
1094                         break;
1095                 case 1:
1096                         xmii = PORT_RMII_SEL;
1097                         break;
1098                 case 2:
1099                         xmii = PORT_GMII_SEL;
1100                         break;
1101                 default:
1102                         xmii = PORT_RGMII_SEL;
1103                         break;
1104                 }
1105         } else {
1106                 switch (mode) {
1107                 case 0:
1108                         xmii = PORT_MII_SEL_S1;
1109                         break;
1110                 case 1:
1111                         xmii = PORT_RMII_SEL_S1;
1112                         break;
1113                 case 2:
1114                         xmii = PORT_GMII_SEL_S1;
1115                         break;
1116                 default:
1117                         xmii = PORT_RGMII_SEL_S1;
1118                         break;
1119                 }
1120         }
1121         *data &= ~PORT_MII_SEL_M;
1122         *data |= xmii;
1123 }
1124
1125 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1126 {
1127         phy_interface_t interface;
1128         bool gbit;
1129         int mode;
1130         u8 data8;
1131
1132         if (port < dev->phy_port_cnt)
1133                 return PHY_INTERFACE_MODE_NA;
1134         ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1135         gbit = ksz9477_get_gbit(dev, data8);
1136         mode = ksz9477_get_xmii(dev, data8);
1137         switch (mode) {
1138         case 2:
1139                 interface = PHY_INTERFACE_MODE_GMII;
1140                 if (gbit)
1141                         break;
1142                 /* fall through */
1143         case 0:
1144                 interface = PHY_INTERFACE_MODE_MII;
1145                 break;
1146         case 1:
1147                 interface = PHY_INTERFACE_MODE_RMII;
1148                 break;
1149         default:
1150                 interface = PHY_INTERFACE_MODE_RGMII;
1151                 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1152                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
1153                 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1154                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
1155                         if (data8 & PORT_RGMII_ID_EG_ENABLE)
1156                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1157                 }
1158                 break;
1159         }
1160         return interface;
1161 }
1162
1163 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1164                                    u8 dev_addr, u16 reg_addr, u16 val)
1165 {
1166         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1167                      MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1168         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1169         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1170                      MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1171         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1172 }
1173
1174 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1175 {
1176         /* Apply PHY settings to address errata listed in
1177          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1178          * Silicon Errata and Data Sheet Clarification documents:
1179          *
1180          * Register settings are needed to improve PHY receive performance
1181          */
1182         ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1183         ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1184         ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1185         ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1186         ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1187         ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1188         ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1189
1190         /* Transmit waveform amplitude can be improved
1191          * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1192          */
1193         ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1194
1195         /* Energy Efficient Ethernet (EEE) feature select must
1196          * be manually disabled (except on KSZ8565 which is 100Mbit)
1197          */
1198         if (dev->features & GBIT_SUPPORT)
1199                 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1200
1201         /* Register settings are required to meet data sheet
1202          * supply current specifications
1203          */
1204         ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1205         ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1206         ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1207         ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1208         ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1209         ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1210         ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1211         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1212         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1213         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1214         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1215         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1216         ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1217 }
1218
1219 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1220 {
1221         u8 data8;
1222         u8 member;
1223         u16 data16;
1224         struct ksz_port *p = &dev->ports[port];
1225
1226         /* enable tag tail for host port */
1227         if (cpu_port)
1228                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1229                              true);
1230
1231         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1232
1233         /* set back pressure */
1234         ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1235
1236         /* enable broadcast storm limit */
1237         ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1238
1239         /* disable DiffServ priority */
1240         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1241
1242         /* replace priority */
1243         ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1244                      false);
1245         ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1246                            MTI_PVID_REPLACE, false);
1247
1248         /* enable 802.1p priority */
1249         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1250
1251         if (port < dev->phy_port_cnt) {
1252                 /* do not force flow control */
1253                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1254                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1255                              false);
1256
1257                 if (dev->phy_errata_9477)
1258                         ksz9477_phy_errata_setup(dev, port);
1259         } else {
1260                 /* force flow control */
1261                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1262                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1263                              true);
1264
1265                 /* configure MAC to 1G & RGMII mode */
1266                 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1267                 switch (dev->interface) {
1268                 case PHY_INTERFACE_MODE_MII:
1269                         ksz9477_set_xmii(dev, 0, &data8);
1270                         ksz9477_set_gbit(dev, false, &data8);
1271                         p->phydev.speed = SPEED_100;
1272                         break;
1273                 case PHY_INTERFACE_MODE_RMII:
1274                         ksz9477_set_xmii(dev, 1, &data8);
1275                         ksz9477_set_gbit(dev, false, &data8);
1276                         p->phydev.speed = SPEED_100;
1277                         break;
1278                 case PHY_INTERFACE_MODE_GMII:
1279                         ksz9477_set_xmii(dev, 2, &data8);
1280                         ksz9477_set_gbit(dev, true, &data8);
1281                         p->phydev.speed = SPEED_1000;
1282                         break;
1283                 default:
1284                         ksz9477_set_xmii(dev, 3, &data8);
1285                         ksz9477_set_gbit(dev, true, &data8);
1286                         data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1287                         data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1288                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1289                             dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1290                                 data8 |= PORT_RGMII_ID_IG_ENABLE;
1291                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1292                             dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1293                                 data8 |= PORT_RGMII_ID_EG_ENABLE;
1294                         p->phydev.speed = SPEED_1000;
1295                         break;
1296                 }
1297                 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1298                 p->phydev.duplex = 1;
1299         }
1300         mutex_lock(&dev->dev_mutex);
1301         if (cpu_port) {
1302                 member = dev->port_mask;
1303                 dev->on_ports = dev->host_mask;
1304                 dev->live_ports = dev->host_mask;
1305         } else {
1306                 member = dev->host_mask | p->vid_member;
1307                 dev->on_ports |= (1 << port);
1308
1309                 /* Link was detected before port is enabled. */
1310                 if (p->phydev.link)
1311                         dev->live_ports |= (1 << port);
1312         }
1313         mutex_unlock(&dev->dev_mutex);
1314         ksz9477_cfg_port_member(dev, port, member);
1315
1316         /* clear pending interrupts */
1317         if (port < dev->phy_port_cnt)
1318                 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1319 }
1320
1321 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1322 {
1323         struct ksz_device *dev = ds->priv;
1324         struct ksz_port *p;
1325         int i;
1326
1327         ds->num_ports = dev->port_cnt;
1328
1329         for (i = 0; i < dev->port_cnt; i++) {
1330                 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1331                         phy_interface_t interface;
1332
1333                         dev->cpu_port = i;
1334                         dev->host_mask = (1 << dev->cpu_port);
1335                         dev->port_mask |= dev->host_mask;
1336
1337                         /* Read from XMII register to determine host port
1338                          * interface.  If set specifically in device tree
1339                          * note the difference to help debugging.
1340                          */
1341                         interface = ksz9477_get_interface(dev, i);
1342                         if (!dev->interface)
1343                                 dev->interface = interface;
1344                         if (interface && interface != dev->interface)
1345                                 dev_info(dev->dev,
1346                                          "use %s instead of %s\n",
1347                                           phy_modes(dev->interface),
1348                                           phy_modes(interface));
1349
1350                         /* enable cpu port */
1351                         ksz9477_port_setup(dev, i, true);
1352                         p = &dev->ports[dev->cpu_port];
1353                         p->vid_member = dev->port_mask;
1354                         p->on = 1;
1355                 }
1356         }
1357
1358         dev->member = dev->host_mask;
1359
1360         for (i = 0; i < dev->mib_port_cnt; i++) {
1361                 if (i == dev->cpu_port)
1362                         continue;
1363                 p = &dev->ports[i];
1364
1365                 /* Initialize to non-zero so that ksz_cfg_port_member() will
1366                  * be called.
1367                  */
1368                 p->vid_member = (1 << i);
1369                 p->member = dev->port_mask;
1370                 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1371                 p->on = 1;
1372                 if (i < dev->phy_port_cnt)
1373                         p->phy = 1;
1374                 if (dev->chip_id == 0x00947700 && i == 6) {
1375                         p->sgmii = 1;
1376
1377                         /* SGMII PHY detection code is not implemented yet. */
1378                         p->phy = 0;
1379                 }
1380         }
1381 }
1382
1383 static int ksz9477_setup(struct dsa_switch *ds)
1384 {
1385         struct ksz_device *dev = ds->priv;
1386         int ret = 0;
1387
1388         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1389                                        dev->num_vlans, GFP_KERNEL);
1390         if (!dev->vlan_cache)
1391                 return -ENOMEM;
1392
1393         ret = ksz9477_reset_switch(dev);
1394         if (ret) {
1395                 dev_err(ds->dev, "failed to reset switch\n");
1396                 return ret;
1397         }
1398
1399         /* Required for port partitioning. */
1400         ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1401                       true);
1402
1403         /* Do not work correctly with tail tagging. */
1404         ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1405
1406         /* accept packet up to 2000bytes */
1407         ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1408
1409         ksz9477_config_cpu_port(ds);
1410
1411         ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1412
1413         /* queue based egress rate limit */
1414         ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1415
1416         /* enable global MIB counter freeze function */
1417         ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1418
1419         /* start switch */
1420         ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1421
1422         ksz_init_mib_timer(dev);
1423
1424         return 0;
1425 }
1426
1427 static const struct dsa_switch_ops ksz9477_switch_ops = {
1428         .get_tag_protocol       = ksz9477_get_tag_protocol,
1429         .setup                  = ksz9477_setup,
1430         .phy_read               = ksz9477_phy_read16,
1431         .phy_write              = ksz9477_phy_write16,
1432         .adjust_link            = ksz_adjust_link,
1433         .port_enable            = ksz_enable_port,
1434         .port_disable           = ksz_disable_port,
1435         .get_strings            = ksz9477_get_strings,
1436         .get_ethtool_stats      = ksz_get_ethtool_stats,
1437         .get_sset_count         = ksz_sset_count,
1438         .port_bridge_join       = ksz_port_bridge_join,
1439         .port_bridge_leave      = ksz_port_bridge_leave,
1440         .port_stp_state_set     = ksz9477_port_stp_state_set,
1441         .port_fast_age          = ksz_port_fast_age,
1442         .port_vlan_filtering    = ksz9477_port_vlan_filtering,
1443         .port_vlan_prepare      = ksz_port_vlan_prepare,
1444         .port_vlan_add          = ksz9477_port_vlan_add,
1445         .port_vlan_del          = ksz9477_port_vlan_del,
1446         .port_fdb_dump          = ksz9477_port_fdb_dump,
1447         .port_fdb_add           = ksz9477_port_fdb_add,
1448         .port_fdb_del           = ksz9477_port_fdb_del,
1449         .port_mdb_prepare       = ksz_port_mdb_prepare,
1450         .port_mdb_add           = ksz9477_port_mdb_add,
1451         .port_mdb_del           = ksz9477_port_mdb_del,
1452         .port_mirror_add        = ksz9477_port_mirror_add,
1453         .port_mirror_del        = ksz9477_port_mirror_del,
1454 };
1455
1456 static u32 ksz9477_get_port_addr(int port, int offset)
1457 {
1458         return PORT_CTRL_ADDR(port, offset);
1459 }
1460
1461 static int ksz9477_switch_detect(struct ksz_device *dev)
1462 {
1463         u8 data8;
1464         u8 id_hi;
1465         u8 id_lo;
1466         u32 id32;
1467         int ret;
1468
1469         /* turn off SPI DO Edge select */
1470         ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1471         if (ret)
1472                 return ret;
1473
1474         data8 &= ~SPI_AUTO_EDGE_DETECTION;
1475         ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1476         if (ret)
1477                 return ret;
1478
1479         /* read chip id */
1480         ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1481         if (ret)
1482                 return ret;
1483         ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1484         if (ret)
1485                 return ret;
1486
1487         /* Number of ports can be reduced depending on chip. */
1488         dev->mib_port_cnt = TOTAL_PORT_NUM;
1489         dev->phy_port_cnt = 5;
1490
1491         /* Default capability is gigabit capable. */
1492         dev->features = GBIT_SUPPORT;
1493
1494         id_hi = (u8)(id32 >> 16);
1495         id_lo = (u8)(id32 >> 8);
1496         if ((id_lo & 0xf) == 3) {
1497                 /* Chip is from KSZ9893 design. */
1498                 dev->features |= IS_9893;
1499
1500                 /* Chip does not support gigabit. */
1501                 if (data8 & SW_QW_ABLE)
1502                         dev->features &= ~GBIT_SUPPORT;
1503                 dev->mib_port_cnt = 3;
1504                 dev->phy_port_cnt = 2;
1505         } else {
1506                 /* Chip uses new XMII register definitions. */
1507                 dev->features |= NEW_XMII;
1508
1509                 /* Chip does not support gigabit. */
1510                 if (!(data8 & SW_GIGABIT_ABLE))
1511                         dev->features &= ~GBIT_SUPPORT;
1512         }
1513
1514         /* Change chip id to known ones so it can be matched against them. */
1515         id32 = (id_hi << 16) | (id_lo << 8);
1516
1517         dev->chip_id = id32;
1518
1519         return 0;
1520 }
1521
1522 struct ksz_chip_data {
1523         u32 chip_id;
1524         const char *dev_name;
1525         int num_vlans;
1526         int num_alus;
1527         int num_statics;
1528         int cpu_ports;
1529         int port_cnt;
1530         bool phy_errata_9477;
1531 };
1532
1533 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1534         {
1535                 .chip_id = 0x00947700,
1536                 .dev_name = "KSZ9477",
1537                 .num_vlans = 4096,
1538                 .num_alus = 4096,
1539                 .num_statics = 16,
1540                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1541                 .port_cnt = 7,          /* total physical port count */
1542                 .phy_errata_9477 = true,
1543         },
1544         {
1545                 .chip_id = 0x00989700,
1546                 .dev_name = "KSZ9897",
1547                 .num_vlans = 4096,
1548                 .num_alus = 4096,
1549                 .num_statics = 16,
1550                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1551                 .port_cnt = 7,          /* total physical port count */
1552                 .phy_errata_9477 = true,
1553         },
1554         {
1555                 .chip_id = 0x00989300,
1556                 .dev_name = "KSZ9893",
1557                 .num_vlans = 4096,
1558                 .num_alus = 4096,
1559                 .num_statics = 16,
1560                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1561                 .port_cnt = 3,          /* total port count */
1562         },
1563 };
1564
1565 static int ksz9477_switch_init(struct ksz_device *dev)
1566 {
1567         int i;
1568
1569         dev->ds->ops = &ksz9477_switch_ops;
1570
1571         for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1572                 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1573
1574                 if (dev->chip_id == chip->chip_id) {
1575                         dev->name = chip->dev_name;
1576                         dev->num_vlans = chip->num_vlans;
1577                         dev->num_alus = chip->num_alus;
1578                         dev->num_statics = chip->num_statics;
1579                         dev->port_cnt = chip->port_cnt;
1580                         dev->cpu_ports = chip->cpu_ports;
1581                         dev->phy_errata_9477 = chip->phy_errata_9477;
1582
1583                         break;
1584                 }
1585         }
1586
1587         /* no switch found */
1588         if (!dev->port_cnt)
1589                 return -ENODEV;
1590
1591         dev->port_mask = (1 << dev->port_cnt) - 1;
1592
1593         dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1594         dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1595
1596         i = dev->mib_port_cnt;
1597         dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1598                                   GFP_KERNEL);
1599         if (!dev->ports)
1600                 return -ENOMEM;
1601         for (i = 0; i < dev->mib_port_cnt; i++) {
1602                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1603                 dev->ports[i].mib.counters =
1604                         devm_kzalloc(dev->dev,
1605                                      sizeof(u64) *
1606                                      (TOTAL_SWITCH_COUNTER_NUM + 1),
1607                                      GFP_KERNEL);
1608                 if (!dev->ports[i].mib.counters)
1609                         return -ENOMEM;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static void ksz9477_switch_exit(struct ksz_device *dev)
1616 {
1617         ksz9477_reset_switch(dev);
1618 }
1619
1620 static const struct ksz_dev_ops ksz9477_dev_ops = {
1621         .get_port_addr = ksz9477_get_port_addr,
1622         .cfg_port_member = ksz9477_cfg_port_member,
1623         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1624         .phy_setup = ksz9477_phy_setup,
1625         .port_setup = ksz9477_port_setup,
1626         .r_mib_cnt = ksz9477_r_mib_cnt,
1627         .r_mib_pkt = ksz9477_r_mib_pkt,
1628         .freeze_mib = ksz9477_freeze_mib,
1629         .port_init_cnt = ksz9477_port_init_cnt,
1630         .shutdown = ksz9477_reset_switch,
1631         .detect = ksz9477_switch_detect,
1632         .init = ksz9477_switch_init,
1633         .exit = ksz9477_switch_exit,
1634 };
1635
1636 int ksz9477_switch_register(struct ksz_device *dev)
1637 {
1638         return ksz_switch_register(dev, &ksz9477_dev_ops);
1639 }
1640 EXPORT_SYMBOL(ksz9477_switch_register);
1641
1642 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1643 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1644 MODULE_LICENSE("GPL");