drivers/net/dsa/microchip/ksz9477.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip KSZ9477 switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_data/microchip-ksz.h>
  12 #include <linux/phy.h>
  13 #include <linux/if_bridge.h>
  14 #include <net/dsa.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ksz_priv.h"
  18 #include "ksz9477_reg.h"
  19 #include "ksz_common.h"
  20
  21 /* Used with variable features to indicate capabilities. */
  22 #define GBIT_SUPPORT                    BIT(0)
  23 #define NEW_XMII                        BIT(1)
  24 #define IS_9893                         BIT(2)
  25
  26 static const struct {
  27         int index;
  28         char string[ETH_GSTRING_LEN];
  29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
  30         { 0x00, "rx_hi" },
  31         { 0x01, "rx_undersize" },
  32         { 0x02, "rx_fragments" },
  33         { 0x03, "rx_oversize" },
  34         { 0x04, "rx_jabbers" },
  35         { 0x05, "rx_symbol_err" },
  36         { 0x06, "rx_crc_err" },
  37         { 0x07, "rx_align_err" },
  38         { 0x08, "rx_mac_ctrl" },
  39         { 0x09, "rx_pause" },
  40         { 0x0A, "rx_bcast" },
  41         { 0x0B, "rx_mcast" },
  42         { 0x0C, "rx_ucast" },
  43         { 0x0D, "rx_64_or_less" },
  44         { 0x0E, "rx_65_127" },
  45         { 0x0F, "rx_128_255" },
  46         { 0x10, "rx_256_511" },
  47         { 0x11, "rx_512_1023" },
  48         { 0x12, "rx_1024_1522" },
  49         { 0x13, "rx_1523_2000" },
  50         { 0x14, "rx_2001" },
  51         { 0x15, "tx_hi" },
  52         { 0x16, "tx_late_col" },
  53         { 0x17, "tx_pause" },
  54         { 0x18, "tx_bcast" },
  55         { 0x19, "tx_mcast" },
  56         { 0x1A, "tx_ucast" },
  57         { 0x1B, "tx_deferred" },
  58         { 0x1C, "tx_total_col" },
  59         { 0x1D, "tx_exc_col" },
  60         { 0x1E, "tx_single_col" },
  61         { 0x1F, "tx_mult_col" },
  62         { 0x80, "rx_total" },
  63         { 0x81, "tx_total" },
  64         { 0x82, "rx_discards" },
  65         { 0x83, "tx_discards" },
  66 };
  67
  68 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
  69 {
  70         regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
  71 }
  72
  73 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
  74                          bool set)
  75 {
  76         regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
  77                            bits, set ? bits : 0);
  78 }
  79
  80 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
  81 {
  82         regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
  83 }
  84
  85 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
  86                                u32 bits, bool set)
  87 {
  88         regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
  89                            bits, set ? bits : 0);
  90 }
  91
  92 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton,
  93                                         int timeout)
  94 {
  95         u8 data;
  96
  97         do {
  98                 ksz_read8(dev, REG_SW_VLAN_CTRL, &data);
  99                 if (!(data & waiton))
 100                         break;
 101                 usleep_range(1, 10);
 102         } while (timeout-- > 0);
 103
 104         if (timeout <= 0)
 105                 return -ETIMEDOUT;
 106
 107         return 0;
 108 }
 109
 110 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
 111                                   u32 *vlan_table)
 112 {
 113         int ret;
 114
 115         mutex_lock(&dev->vlan_mutex);
 116
 117         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 118         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
 119
 120         /* wait to be cleared */
 121         ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
 122         if (ret < 0) {
 123                 dev_dbg(dev->dev, "Failed to read vlan table\n");
 124                 goto exit;
 125         }
 126
 127         ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
 128         ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
 129         ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
 130
 131         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 132
 133 exit:
 134         mutex_unlock(&dev->vlan_mutex);
 135
 136         return ret;
 137 }
 138
 139 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
 140                                   u32 *vlan_table)
 141 {
 142         int ret;
 143
 144         mutex_lock(&dev->vlan_mutex);
 145
 146         ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
 147         ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
 148         ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
 149
 150         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 151         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
 152
 153         /* wait to be cleared */
 154         ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000);
 155         if (ret < 0) {
 156                 dev_dbg(dev->dev, "Failed to write vlan table\n");
 157                 goto exit;
 158         }
 159
 160         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 161
 162         /* update vlan cache table */
 163         dev->vlan_cache[vid].table[0] = vlan_table[0];
 164         dev->vlan_cache[vid].table[1] = vlan_table[1];
 165         dev->vlan_cache[vid].table[2] = vlan_table[2];
 166
 167 exit:
 168         mutex_unlock(&dev->vlan_mutex);
 169
 170         return ret;
 171 }
 172
 173 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
 174 {
 175         ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
 176         ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
 177         ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
 178         ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
 179 }
 180
 181 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
 182 {
 183         ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
 184         ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
 185         ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
 186         ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
 187 }
 188
 189 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton,
 190                                   int timeout)
 191 {
 192         u32 data;
 193
 194         do {
 195                 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data);
 196                 if (!(data & waiton))
 197                         break;
 198                 usleep_range(1, 10);
 199         } while (timeout-- > 0);
 200
 201         if (timeout <= 0)
 202                 return -ETIMEDOUT;
 203
 204         return 0;
 205 }
 206
 207 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton,
 208                                       int timeout)
 209 {
 210         u32 data;
 211
 212         do {
 213                 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data);
 214                 if (!(data & waiton))
 215                         break;
 216                 usleep_range(1, 10);
 217         } while (timeout-- > 0);
 218
 219         if (timeout <= 0)
 220                 return -ETIMEDOUT;
 221
 222         return 0;
 223 }
 224
 225 static int ksz9477_reset_switch(struct ksz_device *dev)
 226 {
 227         u8 data8;
 228         u16 data16;
 229         u32 data32;
 230
 231         /* reset switch */
 232         ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
 233
 234         /* turn off SPI DO Edge select */
 235         ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
 236         data8 &= ~SPI_AUTO_EDGE_DETECTION;
 237         ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
 238
 239         /* default configuration */
 240         ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
 241         data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
 242               SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
 243         ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
 244
 245         /* disable interrupts */
 246         ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
 247         ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
 248         ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
 249
 250         /* set broadcast storm protection 10% rate */
 251         ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16);
 252         data16 &= ~BROADCAST_STORM_RATE;
 253         data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
 254         ksz_write16(dev, REG_SW_MAC_CTRL_2, data16);
 255
 256         if (dev->synclko_125)
 257                 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 258                            SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
 259
 260         return 0;
 261 }
 262
 263 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
 264                               u64 *cnt)
 265 {
 266         struct ksz_poll_ctx ctx = {
 267                 .dev = dev,
 268                 .port = port,
 269                 .offset = REG_PORT_MIB_CTRL_STAT__4,
 270         };
 271         struct ksz_port *p = &dev->ports[port];
 272         u32 data;
 273         int ret;
 274
 275         /* retain the flush/freeze bit */
 276         data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 277         data |= MIB_COUNTER_READ;
 278         data |= (addr << MIB_COUNTER_INDEX_S);
 279         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
 280
 281         ret = readx_poll_timeout(ksz_pread32_poll, &ctx, data,
 282                                  !(data & MIB_COUNTER_READ), 10, 1000);
 283
 284         /* failed to read MIB. get out of loop */
 285         if (ret < 0) {
 286                 dev_dbg(dev->dev, "Failed to get MIB\n");
 287                 return;
 288         }
 289
 290         /* count resets upon read */
 291         ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
 292         *cnt += data;
 293 }
 294
 295 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
 296                               u64 *dropped, u64 *cnt)
 297 {
 298         addr = ksz9477_mib_names[addr].index;
 299         ksz9477_r_mib_cnt(dev, port, addr, cnt);
 300 }
 301
 302 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
 303 {
 304         u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 305         struct ksz_port *p = &dev->ports[port];
 306
 307         /* enable/disable the port for flush/freeze function */
 308         mutex_lock(&p->mib.cnt_mutex);
 309         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
 310
 311         /* used by MIB counter reading code to know freeze is enabled */
 312         p->freeze = freeze;
 313         mutex_unlock(&p->mib.cnt_mutex);
 314 }
 315
 316 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
 317 {
 318         struct ksz_port_mib *mib = &dev->ports[port].mib;
 319
 320         /* flush all enabled port MIB counters */
 321         mutex_lock(&mib->cnt_mutex);
 322         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
 323                      MIB_COUNTER_FLUSH_FREEZE);
 324         ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
 325         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
 326         mutex_unlock(&mib->cnt_mutex);
 327
 328         mib->cnt_ptr = 0;
 329         memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
 330 }
 331
 332 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
 333                                                       int port)
 334 {
 335         enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
 336         struct ksz_device *dev = ds->priv;
 337
 338         if (dev->features & IS_9893)
 339                 proto = DSA_TAG_PROTO_KSZ9893;
 340         return proto;
 341 }
 342
 343 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
 344 {
 345         struct ksz_device *dev = ds->priv;
 346         u16 val = 0xffff;
 347
 348         /* No real PHY after this. Simulate the PHY.
 349          * A fixed PHY can be setup in the device tree, but this function is
 350          * still called for that port during initialization.
 351          * For RGMII PHY there is no way to access it so the fixed PHY should
 352          * be used.  For SGMII PHY the supporting code will be added later.
 353          */
 354         if (addr >= dev->phy_port_cnt) {
 355                 struct ksz_port *p = &dev->ports[addr];
 356
 357                 switch (reg) {
 358                 case MII_BMCR:
 359                         val = 0x1140;
 360                         break;
 361                 case MII_BMSR:
 362                         val = 0x796d;
 363                         break;
 364                 case MII_PHYSID1:
 365                         val = 0x0022;
 366                         break;
 367                 case MII_PHYSID2:
 368                         val = 0x1631;
 369                         break;
 370                 case MII_ADVERTISE:
 371                         val = 0x05e1;
 372                         break;
 373                 case MII_LPA:
 374                         val = 0xc5e1;
 375                         break;
 376                 case MII_CTRL1000:
 377                         val = 0x0700;
 378                         break;
 379                 case MII_STAT1000:
 380                         if (p->phydev.speed == SPEED_1000)
 381                                 val = 0x3800;
 382                         else
 383                                 val = 0;
 384                         break;
 385                 }
 386         } else {
 387                 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
 388         }
 389
 390         return val;
 391 }
 392
 393 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
 394                                u16 val)
 395 {
 396         struct ksz_device *dev = ds->priv;
 397
 398         /* No real PHY after this. */
 399         if (addr >= dev->phy_port_cnt)
 400                 return 0;
 401
 402         /* No gigabit support.  Do not write to this register. */
 403         if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
 404                 return 0;
 405         ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
 406
 407         return 0;
 408 }
 409
 410 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
 411                                 u32 stringset, uint8_t *buf)
 412 {
 413         int i;
 414
 415         if (stringset != ETH_SS_STATS)
 416                 return;
 417
 418         for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
 419                 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
 420                        ETH_GSTRING_LEN);
 421         }
 422 }
 423
 424 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
 425                                     u8 member)
 426 {
 427         ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
 428         dev->ports[port].member = member;
 429 }
 430
 431 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
 432                                        u8 state)
 433 {
 434         struct ksz_device *dev = ds->priv;
 435         struct ksz_port *p = &dev->ports[port];
 436         u8 data;
 437         int member = -1;
 438         int forward = dev->member;
 439
 440         ksz_pread8(dev, port, P_STP_CTRL, &data);
 441         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 442
 443         switch (state) {
 444         case BR_STATE_DISABLED:
 445                 data |= PORT_LEARN_DISABLE;
 446                 if (port != dev->cpu_port)
 447                         member = 0;
 448                 break;
 449         case BR_STATE_LISTENING:
 450                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 451                 if (port != dev->cpu_port &&
 452                     p->stp_state == BR_STATE_DISABLED)
 453                         member = dev->host_mask | p->vid_member;
 454                 break;
 455         case BR_STATE_LEARNING:
 456                 data |= PORT_RX_ENABLE;
 457                 break;
 458         case BR_STATE_FORWARDING:
 459                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
 460
 461                 /* This function is also used internally. */
 462                 if (port == dev->cpu_port)
 463                         break;
 464
 465                 member = dev->host_mask | p->vid_member;
 466                 mutex_lock(&dev->dev_mutex);
 467
 468                 /* Port is a member of a bridge. */
 469                 if (dev->br_member & (1 << port)) {
 470                         dev->member |= (1 << port);
 471                         member = dev->member;
 472                 }
 473                 mutex_unlock(&dev->dev_mutex);
 474                 break;
 475         case BR_STATE_BLOCKING:
 476                 data |= PORT_LEARN_DISABLE;
 477                 if (port != dev->cpu_port &&
 478                     p->stp_state == BR_STATE_DISABLED)
 479                         member = dev->host_mask | p->vid_member;
 480                 break;
 481         default:
 482                 dev_err(ds->dev, "invalid STP state: %d\n", state);
 483                 return;
 484         }
 485
 486         ksz_pwrite8(dev, port, P_STP_CTRL, data);
 487         p->stp_state = state;
 488         mutex_lock(&dev->dev_mutex);
 489         if (data & PORT_RX_ENABLE)
 490                 dev->rx_ports |= (1 << port);
 491         else
 492                 dev->rx_ports &= ~(1 << port);
 493         if (data & PORT_TX_ENABLE)
 494                 dev->tx_ports |= (1 << port);
 495         else
 496                 dev->tx_ports &= ~(1 << port);
 497
 498         /* Port membership may share register with STP state. */
 499         if (member >= 0 && member != p->member)
 500                 ksz9477_cfg_port_member(dev, port, (u8)member);
 501
 502         /* Check if forwarding needs to be updated. */
 503         if (state != BR_STATE_FORWARDING) {
 504                 if (dev->br_member & (1 << port))
 505                         dev->member &= ~(1 << port);
 506         }
 507
 508         /* When topology has changed the function ksz_update_port_member
 509          * should be called to modify port forwarding behavior.
 510          */
 511         if (forward != dev->member)
 512                 ksz_update_port_member(dev, port);
 513         mutex_unlock(&dev->dev_mutex);
 514 }
 515
 516 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
 517 {
 518         u8 data;
 519
 520         ksz_read8(dev, REG_SW_LUE_CTRL_2, &data);
 521         data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S);
 522         data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
 523         ksz_write8(dev, REG_SW_LUE_CTRL_2, data);
 524         if (port < dev->mib_port_cnt) {
 525                 /* flush individual port */
 526                 ksz_pread8(dev, port, P_STP_CTRL, &data);
 527                 if (!(data & PORT_LEARN_DISABLE))
 528                         ksz_pwrite8(dev, port, P_STP_CTRL,
 529                                     data | PORT_LEARN_DISABLE);
 530                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
 531                 ksz_pwrite8(dev, port, P_STP_CTRL, data);
 532         } else {
 533                 /* flush all */
 534                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
 535         }
 536 }
 537
 538 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
 539                                        bool flag)
 540 {
 541         struct ksz_device *dev = ds->priv;
 542
 543         if (flag) {
 544                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 545                              PORT_VLAN_LOOKUP_VID_0, true);
 546                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
 547         } else {
 548                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
 549                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 550                              PORT_VLAN_LOOKUP_VID_0, false);
 551         }
 552
 553         return 0;
 554 }
 555
 556 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
 557                                   const struct switchdev_obj_port_vlan *vlan)
 558 {
 559         struct ksz_device *dev = ds->priv;
 560         u32 vlan_table[3];
 561         u16 vid;
 562         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 563
 564         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 565                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 566                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 567                         return;
 568                 }
 569
 570                 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
 571                 if (untagged)
 572                         vlan_table[1] |= BIT(port);
 573                 else
 574                         vlan_table[1] &= ~BIT(port);
 575                 vlan_table[1] &= ~(BIT(dev->cpu_port));
 576
 577                 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
 578
 579                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 580                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 581                         return;
 582                 }
 583
 584                 /* change PVID */
 585                 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
 586                         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
 587         }
 588 }
 589
 590 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
 591                                  const struct switchdev_obj_port_vlan *vlan)
 592 {
 593         struct ksz_device *dev = ds->priv;
 594         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 595         u32 vlan_table[3];
 596         u16 vid;
 597         u16 pvid;
 598
 599         ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
 600         pvid = pvid & 0xFFF;
 601
 602         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 603                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 604                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 605                         return -ETIMEDOUT;
 606                 }
 607
 608                 vlan_table[2] &= ~BIT(port);
 609
 610                 if (pvid == vid)
 611                         pvid = 1;
 612
 613                 if (untagged)
 614                         vlan_table[1] &= ~BIT(port);
 615
 616                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 617                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 618                         return -ETIMEDOUT;
 619                 }
 620         }
 621
 622         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
 623
 624         return 0;
 625 }
 626
 627 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
 628                                 const unsigned char *addr, u16 vid)
 629 {
 630         struct ksz_device *dev = ds->priv;
 631         u32 alu_table[4];
 632         u32 data;
 633         int ret = 0;
 634
 635         mutex_lock(&dev->alu_mutex);
 636
 637         /* find any entry with mac & vid */
 638         data = vid << ALU_FID_INDEX_S;
 639         data |= ((addr[0] << 8) | addr[1]);
 640         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 641
 642         data = ((addr[2] << 24) | (addr[3] << 16));
 643         data |= ((addr[4] << 8) | addr[5]);
 644         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 645
 646         /* start read operation */
 647         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 648
 649         /* wait to be finished */
 650         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 651         if (ret < 0) {
 652                 dev_dbg(dev->dev, "Failed to read ALU\n");
 653                 goto exit;
 654         }
 655
 656         /* read ALU entry */
 657         ksz9477_read_table(dev, alu_table);
 658
 659         /* update ALU entry */
 660         alu_table[0] = ALU_V_STATIC_VALID;
 661         alu_table[1] |= BIT(port);
 662         if (vid)
 663                 alu_table[1] |= ALU_V_USE_FID;
 664         alu_table[2] = (vid << ALU_V_FID_S);
 665         alu_table[2] |= ((addr[0] << 8) | addr[1]);
 666         alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
 667         alu_table[3] |= ((addr[4] << 8) | addr[5]);
 668
 669         ksz9477_write_table(dev, alu_table);
 670
 671         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 672
 673         /* wait to be finished */
 674         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 675         if (ret < 0)
 676                 dev_dbg(dev->dev, "Failed to write ALU\n");
 677
 678 exit:
 679         mutex_unlock(&dev->alu_mutex);
 680
 681         return ret;
 682 }
 683
 684 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
 685                                 const unsigned char *addr, u16 vid)
 686 {
 687         struct ksz_device *dev = ds->priv;
 688         u32 alu_table[4];
 689         u32 data;
 690         int ret = 0;
 691
 692         mutex_lock(&dev->alu_mutex);
 693
 694         /* read any entry with mac & vid */
 695         data = vid << ALU_FID_INDEX_S;
 696         data |= ((addr[0] << 8) | addr[1]);
 697         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 698
 699         data = ((addr[2] << 24) | (addr[3] << 16));
 700         data |= ((addr[4] << 8) | addr[5]);
 701         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 702
 703         /* start read operation */
 704         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 705
 706         /* wait to be finished */
 707         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 708         if (ret < 0) {
 709                 dev_dbg(dev->dev, "Failed to read ALU\n");
 710                 goto exit;
 711         }
 712
 713         ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
 714         if (alu_table[0] & ALU_V_STATIC_VALID) {
 715                 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
 716                 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
 717                 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
 718
 719                 /* clear forwarding port */
 720                 alu_table[2] &= ~BIT(port);
 721
 722                 /* if there is no port to forward, clear table */
 723                 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
 724                         alu_table[0] = 0;
 725                         alu_table[1] = 0;
 726                         alu_table[2] = 0;
 727                         alu_table[3] = 0;
 728                 }
 729         } else {
 730                 alu_table[0] = 0;
 731                 alu_table[1] = 0;
 732                 alu_table[2] = 0;
 733                 alu_table[3] = 0;
 734         }
 735
 736         ksz9477_write_table(dev, alu_table);
 737
 738         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 739
 740         /* wait to be finished */
 741         ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000);
 742         if (ret < 0)
 743                 dev_dbg(dev->dev, "Failed to write ALU\n");
 744
 745 exit:
 746         mutex_unlock(&dev->alu_mutex);
 747
 748         return ret;
 749 }
 750
 751 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
 752 {
 753         alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
 754         alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
 755         alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
 756         alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
 757                         ALU_V_PRIO_AGE_CNT_M;
 758         alu->mstp = alu_table[0] & ALU_V_MSTP_M;
 759
 760         alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
 761         alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
 762         alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
 763
 764         alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
 765
 766         alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
 767         alu->mac[1] = alu_table[2] & 0xFF;
 768         alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
 769         alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
 770         alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
 771         alu->mac[5] = alu_table[3] & 0xFF;
 772 }
 773
 774 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
 775                                  dsa_fdb_dump_cb_t *cb, void *data)
 776 {
 777         struct ksz_device *dev = ds->priv;
 778         int ret = 0;
 779         u32 ksz_data;
 780         u32 alu_table[4];
 781         struct alu_struct alu;
 782         int timeout;
 783
 784         mutex_lock(&dev->alu_mutex);
 785
 786         /* start ALU search */
 787         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
 788
 789         do {
 790                 timeout = 1000;
 791                 do {
 792                         ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
 793                         if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
 794                                 break;
 795                         usleep_range(1, 10);
 796                 } while (timeout-- > 0);
 797
 798                 if (!timeout) {
 799                         dev_dbg(dev->dev, "Failed to search ALU\n");
 800                         ret = -ETIMEDOUT;
 801                         goto exit;
 802                 }
 803
 804                 /* read ALU table */
 805                 ksz9477_read_table(dev, alu_table);
 806
 807                 ksz9477_convert_alu(&alu, alu_table);
 808
 809                 if (alu.port_forward & BIT(port)) {
 810                         ret = cb(alu.mac, alu.fid, alu.is_static, data);
 811                         if (ret)
 812                                 goto exit;
 813                 }
 814         } while (ksz_data & ALU_START);
 815
 816 exit:
 817
 818         /* stop ALU search */
 819         ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
 820
 821         mutex_unlock(&dev->alu_mutex);
 822
 823         return ret;
 824 }
 825
 826 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
 827                                  const struct switchdev_obj_port_mdb *mdb)
 828 {
 829         struct ksz_device *dev = ds->priv;
 830         u32 static_table[4];
 831         u32 data;
 832         int index;
 833         u32 mac_hi, mac_lo;
 834
 835         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 836         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 837         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 838
 839         mutex_lock(&dev->alu_mutex);
 840
 841         for (index = 0; index < dev->num_statics; index++) {
 842                 /* find empty slot first */
 843                 data = (index << ALU_STAT_INDEX_S) |
 844                         ALU_STAT_READ | ALU_STAT_START;
 845                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 846
 847                 /* wait to be finished */
 848                 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) {
 849                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 850                         goto exit;
 851                 }
 852
 853                 /* read ALU static table */
 854                 ksz9477_read_table(dev, static_table);
 855
 856                 if (static_table[0] & ALU_V_STATIC_VALID) {
 857                         /* check this has same vid & mac address */
 858                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 859                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 860                             static_table[3] == mac_lo) {
 861                                 /* found matching one */
 862                                 break;
 863                         }
 864                 } else {
 865                         /* found empty one */
 866                         break;
 867                 }
 868         }
 869
 870         /* no available entry */
 871         if (index == dev->num_statics)
 872                 goto exit;
 873
 874         /* add entry */
 875         static_table[0] = ALU_V_STATIC_VALID;
 876         static_table[1] |= BIT(port);
 877         if (mdb->vid)
 878                 static_table[1] |= ALU_V_USE_FID;
 879         static_table[2] = (mdb->vid << ALU_V_FID_S);
 880         static_table[2] |= mac_hi;
 881         static_table[3] = mac_lo;
 882
 883         ksz9477_write_table(dev, static_table);
 884
 885         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 886         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 887
 888         /* wait to be finished */
 889         if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0)
 890                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 891
 892 exit:
 893         mutex_unlock(&dev->alu_mutex);
 894 }
 895
 896 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
 897                                 const struct switchdev_obj_port_mdb *mdb)
 898 {
 899         struct ksz_device *dev = ds->priv;
 900         u32 static_table[4];
 901         u32 data;
 902         int index;
 903         int ret = 0;
 904         u32 mac_hi, mac_lo;
 905
 906         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 907         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 908         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 909
 910         mutex_lock(&dev->alu_mutex);
 911
 912         for (index = 0; index < dev->num_statics; index++) {
 913                 /* find empty slot first */
 914                 data = (index << ALU_STAT_INDEX_S) |
 915                         ALU_STAT_READ | ALU_STAT_START;
 916                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 917
 918                 /* wait to be finished */
 919                 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
 920                 if (ret < 0) {
 921                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 922                         goto exit;
 923                 }
 924
 925                 /* read ALU static table */
 926                 ksz9477_read_table(dev, static_table);
 927
 928                 if (static_table[0] & ALU_V_STATIC_VALID) {
 929                         /* check this has same vid & mac address */
 930
 931                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 932                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 933                             static_table[3] == mac_lo) {
 934                                 /* found matching one */
 935                                 break;
 936                         }
 937                 }
 938         }
 939
 940         /* no available entry */
 941         if (index == dev->num_statics)
 942                 goto exit;
 943
 944         /* clear port */
 945         static_table[1] &= ~BIT(port);
 946
 947         if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
 948                 /* delete entry */
 949                 static_table[0] = 0;
 950                 static_table[1] = 0;
 951                 static_table[2] = 0;
 952                 static_table[3] = 0;
 953         }
 954
 955         ksz9477_write_table(dev, static_table);
 956
 957         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 958         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 959
 960         /* wait to be finished */
 961         ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000);
 962         if (ret < 0)
 963                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 964
 965 exit:
 966         mutex_unlock(&dev->alu_mutex);
 967
 968         return ret;
 969 }
 970
 971 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
 972                                    struct dsa_mall_mirror_tc_entry *mirror,
 973                                    bool ingress)
 974 {
 975         struct ksz_device *dev = ds->priv;
 976
 977         if (ingress)
 978                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
 979         else
 980                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
 981
 982         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
 983
 984         /* configure mirror port */
 985         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 986                      PORT_MIRROR_SNIFFER, true);
 987
 988         ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
 989
 990         return 0;
 991 }
 992
 993 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
 994                                     struct dsa_mall_mirror_tc_entry *mirror)
 995 {
 996         struct ksz_device *dev = ds->priv;
 997         u8 data;
 998
 999         if (mirror->ingress)
1000                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1001         else
1002                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1003
1004         ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1005
1006         if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
1007                 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1008                              PORT_MIRROR_SNIFFER, false);
1009 }
1010
1011 static void ksz9477_phy_setup(struct ksz_device *dev, int port,
1012                               struct phy_device *phy)
1013 {
1014         /* Only apply to port with PHY. */
1015         if (port >= dev->phy_port_cnt)
1016                 return;
1017
1018         /* The MAC actually cannot run in 1000 half-duplex mode. */
1019         phy_remove_link_mode(phy,
1020                              ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1021
1022         /* PHY does not support gigabit. */
1023         if (!(dev->features & GBIT_SUPPORT))
1024                 phy_remove_link_mode(phy,
1025                                      ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1026 }
1027
1028 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
1029 {
1030         bool gbit;
1031
1032         if (dev->features & NEW_XMII)
1033                 gbit = !(data & PORT_MII_NOT_1GBIT);
1034         else
1035                 gbit = !!(data & PORT_MII_1000MBIT_S1);
1036         return gbit;
1037 }
1038
1039 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
1040 {
1041         if (dev->features & NEW_XMII) {
1042                 if (gbit)
1043                         *data &= ~PORT_MII_NOT_1GBIT;
1044                 else
1045                         *data |= PORT_MII_NOT_1GBIT;
1046         } else {
1047                 if (gbit)
1048                         *data |= PORT_MII_1000MBIT_S1;
1049                 else
1050                         *data &= ~PORT_MII_1000MBIT_S1;
1051         }
1052 }
1053
1054 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
1055 {
1056         int mode;
1057
1058         if (dev->features & NEW_XMII) {
1059                 switch (data & PORT_MII_SEL_M) {
1060                 case PORT_MII_SEL:
1061                         mode = 0;
1062                         break;
1063                 case PORT_RMII_SEL:
1064                         mode = 1;
1065                         break;
1066                 case PORT_GMII_SEL:
1067                         mode = 2;
1068                         break;
1069                 default:
1070                         mode = 3;
1071                 }
1072         } else {
1073                 switch (data & PORT_MII_SEL_M) {
1074                 case PORT_MII_SEL_S1:
1075                         mode = 0;
1076                         break;
1077                 case PORT_RMII_SEL_S1:
1078                         mode = 1;
1079                         break;
1080                 case PORT_GMII_SEL_S1:
1081                         mode = 2;
1082                         break;
1083                 default:
1084                         mode = 3;
1085                 }
1086         }
1087         return mode;
1088 }
1089
1090 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1091 {
1092         u8 xmii;
1093
1094         if (dev->features & NEW_XMII) {
1095                 switch (mode) {
1096                 case 0:
1097                         xmii = PORT_MII_SEL;
1098                         break;
1099                 case 1:
1100                         xmii = PORT_RMII_SEL;
1101                         break;
1102                 case 2:
1103                         xmii = PORT_GMII_SEL;
1104                         break;
1105                 default:
1106                         xmii = PORT_RGMII_SEL;
1107                         break;
1108                 }
1109         } else {
1110                 switch (mode) {
1111                 case 0:
1112                         xmii = PORT_MII_SEL_S1;
1113                         break;
1114                 case 1:
1115                         xmii = PORT_RMII_SEL_S1;
1116                         break;
1117                 case 2:
1118                         xmii = PORT_GMII_SEL_S1;
1119                         break;
1120                 default:
1121                         xmii = PORT_RGMII_SEL_S1;
1122                         break;
1123                 }
1124         }
1125         *data &= ~PORT_MII_SEL_M;
1126         *data |= xmii;
1127 }
1128
1129 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1130 {
1131         phy_interface_t interface;
1132         bool gbit;
1133         int mode;
1134         u8 data8;
1135
1136         if (port < dev->phy_port_cnt)
1137                 return PHY_INTERFACE_MODE_NA;
1138         ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1139         gbit = ksz9477_get_gbit(dev, data8);
1140         mode = ksz9477_get_xmii(dev, data8);
1141         switch (mode) {
1142         case 2:
1143                 interface = PHY_INTERFACE_MODE_GMII;
1144                 if (gbit)
1145                         break;
1146                 /* fall through */
1147         case 0:
1148                 interface = PHY_INTERFACE_MODE_MII;
1149                 break;
1150         case 1:
1151                 interface = PHY_INTERFACE_MODE_RMII;
1152                 break;
1153         default:
1154                 interface = PHY_INTERFACE_MODE_RGMII;
1155                 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1156                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
1157                 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1158                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
1159                         if (data8 & PORT_RGMII_ID_EG_ENABLE)
1160                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1161                 }
1162                 break;
1163         }
1164         return interface;
1165 }
1166
1167 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1168                                    u8 dev_addr, u16 reg_addr, u16 val)
1169 {
1170         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1171                      MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1172         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1173         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1174                      MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1175         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1176 }
1177
1178 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1179 {
1180         /* Apply PHY settings to address errata listed in
1181          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1182          * Silicon Errata and Data Sheet Clarification documents:
1183          *
1184          * Register settings are needed to improve PHY receive performance
1185          */
1186         ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1187         ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1188         ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1189         ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1190         ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1191         ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1192         ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1193
1194         /* Transmit waveform amplitude can be improved
1195          * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1196          */
1197         ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1198
1199         /* Energy Efficient Ethernet (EEE) feature select must
1200          * be manually disabled (except on KSZ8565 which is 100Mbit)
1201          */
1202         if (dev->features & GBIT_SUPPORT)
1203                 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1204
1205         /* Register settings are required to meet data sheet
1206          * supply current specifications
1207          */
1208         ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1209         ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1210         ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1211         ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1212         ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1213         ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1214         ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1215         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1216         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1217         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1218         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1219         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1220         ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1221 }
1222
1223 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1224 {
1225         u8 data8;
1226         u8 member;
1227         u16 data16;
1228         struct ksz_port *p = &dev->ports[port];
1229
1230         /* enable tag tail for host port */
1231         if (cpu_port)
1232                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1233                              true);
1234
1235         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1236
1237         /* set back pressure */
1238         ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1239
1240         /* enable broadcast storm limit */
1241         ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1242
1243         /* disable DiffServ priority */
1244         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1245
1246         /* replace priority */
1247         ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1248                      false);
1249         ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1250                            MTI_PVID_REPLACE, false);
1251
1252         /* enable 802.1p priority */
1253         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1254
1255         if (port < dev->phy_port_cnt) {
1256                 /* do not force flow control */
1257                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1258                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1259                              false);
1260
1261                 if (dev->phy_errata_9477)
1262                         ksz9477_phy_errata_setup(dev, port);
1263         } else {
1264                 /* force flow control */
1265                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1266                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1267                              true);
1268
1269                 /* configure MAC to 1G & RGMII mode */
1270                 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1271                 switch (dev->interface) {
1272                 case PHY_INTERFACE_MODE_MII:
1273                         ksz9477_set_xmii(dev, 0, &data8);
1274                         ksz9477_set_gbit(dev, false, &data8);
1275                         p->phydev.speed = SPEED_100;
1276                         break;
1277                 case PHY_INTERFACE_MODE_RMII:
1278                         ksz9477_set_xmii(dev, 1, &data8);
1279                         ksz9477_set_gbit(dev, false, &data8);
1280                         p->phydev.speed = SPEED_100;
1281                         break;
1282                 case PHY_INTERFACE_MODE_GMII:
1283                         ksz9477_set_xmii(dev, 2, &data8);
1284                         ksz9477_set_gbit(dev, true, &data8);
1285                         p->phydev.speed = SPEED_1000;
1286                         break;
1287                 default:
1288                         ksz9477_set_xmii(dev, 3, &data8);
1289                         ksz9477_set_gbit(dev, true, &data8);
1290                         data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1291                         data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1292                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1293                             dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1294                                 data8 |= PORT_RGMII_ID_IG_ENABLE;
1295                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1296                             dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1297                                 data8 |= PORT_RGMII_ID_EG_ENABLE;
1298                         p->phydev.speed = SPEED_1000;
1299                         break;
1300                 }
1301                 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1302                 p->phydev.duplex = 1;
1303         }
1304         mutex_lock(&dev->dev_mutex);
1305         if (cpu_port) {
1306                 member = dev->port_mask;
1307                 dev->on_ports = dev->host_mask;
1308                 dev->live_ports = dev->host_mask;
1309         } else {
1310                 member = dev->host_mask | p->vid_member;
1311                 dev->on_ports |= (1 << port);
1312
1313                 /* Link was detected before port is enabled. */
1314                 if (p->phydev.link)
1315                         dev->live_ports |= (1 << port);
1316         }
1317         mutex_unlock(&dev->dev_mutex);
1318         ksz9477_cfg_port_member(dev, port, member);
1319
1320         /* clear pending interrupts */
1321         if (port < dev->phy_port_cnt)
1322                 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1323 }
1324
1325 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1326 {
1327         struct ksz_device *dev = ds->priv;
1328         struct ksz_port *p;
1329         int i;
1330
1331         ds->num_ports = dev->port_cnt;
1332
1333         for (i = 0; i < dev->port_cnt; i++) {
1334                 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1335                         phy_interface_t interface;
1336
1337                         dev->cpu_port = i;
1338                         dev->host_mask = (1 << dev->cpu_port);
1339                         dev->port_mask |= dev->host_mask;
1340
1341                         /* Read from XMII register to determine host port
1342                          * interface.  If set specifically in device tree
1343                          * note the difference to help debugging.
1344                          */
1345                         interface = ksz9477_get_interface(dev, i);
1346                         if (!dev->interface)
1347                                 dev->interface = interface;
1348                         if (interface && interface != dev->interface)
1349                                 dev_info(dev->dev,
1350                                          "use %s instead of %s\n",
1351                                           phy_modes(dev->interface),
1352                                           phy_modes(interface));
1353
1354                         /* enable cpu port */
1355                         ksz9477_port_setup(dev, i, true);
1356                         p = &dev->ports[dev->cpu_port];
1357                         p->vid_member = dev->port_mask;
1358                         p->on = 1;
1359                 }
1360         }
1361
1362         dev->member = dev->host_mask;
1363
1364         for (i = 0; i < dev->mib_port_cnt; i++) {
1365                 if (i == dev->cpu_port)
1366                         continue;
1367                 p = &dev->ports[i];
1368
1369                 /* Initialize to non-zero so that ksz_cfg_port_member() will
1370                  * be called.
1371                  */
1372                 p->vid_member = (1 << i);
1373                 p->member = dev->port_mask;
1374                 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1375                 p->on = 1;
1376                 if (i < dev->phy_port_cnt)
1377                         p->phy = 1;
1378                 if (dev->chip_id == 0x00947700 && i == 6) {
1379                         p->sgmii = 1;
1380
1381                         /* SGMII PHY detection code is not implemented yet. */
1382                         p->phy = 0;
1383                 }
1384         }
1385 }
1386
1387 static int ksz9477_setup(struct dsa_switch *ds)
1388 {
1389         struct ksz_device *dev = ds->priv;
1390         int ret = 0;
1391
1392         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1393                                        dev->num_vlans, GFP_KERNEL);
1394         if (!dev->vlan_cache)
1395                 return -ENOMEM;
1396
1397         ret = ksz9477_reset_switch(dev);
1398         if (ret) {
1399                 dev_err(ds->dev, "failed to reset switch\n");
1400                 return ret;
1401         }
1402
1403         /* Required for port partitioning. */
1404         ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1405                       true);
1406
1407         /* Do not work correctly with tail tagging. */
1408         ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1409
1410         /* accept packet up to 2000bytes */
1411         ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1412
1413         ksz9477_config_cpu_port(ds);
1414
1415         ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1416
1417         /* queue based egress rate limit */
1418         ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1419
1420         /* enable global MIB counter freeze function */
1421         ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1422
1423         /* start switch */
1424         ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1425
1426         ksz_init_mib_timer(dev);
1427
1428         return 0;
1429 }
1430
1431 static const struct dsa_switch_ops ksz9477_switch_ops = {
1432         .get_tag_protocol       = ksz9477_get_tag_protocol,
1433         .setup                  = ksz9477_setup,
1434         .phy_read               = ksz9477_phy_read16,
1435         .phy_write              = ksz9477_phy_write16,
1436         .adjust_link            = ksz_adjust_link,
1437         .port_enable            = ksz_enable_port,
1438         .port_disable           = ksz_disable_port,
1439         .get_strings            = ksz9477_get_strings,
1440         .get_ethtool_stats      = ksz_get_ethtool_stats,
1441         .get_sset_count         = ksz_sset_count,
1442         .port_bridge_join       = ksz_port_bridge_join,
1443         .port_bridge_leave      = ksz_port_bridge_leave,
1444         .port_stp_state_set     = ksz9477_port_stp_state_set,
1445         .port_fast_age          = ksz_port_fast_age,
1446         .port_vlan_filtering    = ksz9477_port_vlan_filtering,
1447         .port_vlan_prepare      = ksz_port_vlan_prepare,
1448         .port_vlan_add          = ksz9477_port_vlan_add,
1449         .port_vlan_del          = ksz9477_port_vlan_del,
1450         .port_fdb_dump          = ksz9477_port_fdb_dump,
1451         .port_fdb_add           = ksz9477_port_fdb_add,
1452         .port_fdb_del           = ksz9477_port_fdb_del,
1453         .port_mdb_prepare       = ksz_port_mdb_prepare,
1454         .port_mdb_add           = ksz9477_port_mdb_add,
1455         .port_mdb_del           = ksz9477_port_mdb_del,
1456         .port_mirror_add        = ksz9477_port_mirror_add,
1457         .port_mirror_del        = ksz9477_port_mirror_del,
1458 };
1459
1460 static u32 ksz9477_get_port_addr(int port, int offset)
1461 {
1462         return PORT_CTRL_ADDR(port, offset);
1463 }
1464
1465 static int ksz9477_switch_detect(struct ksz_device *dev)
1466 {
1467         u8 data8;
1468         u8 id_hi;
1469         u8 id_lo;
1470         u32 id32;
1471         int ret;
1472
1473         /* turn off SPI DO Edge select */
1474         ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1475         if (ret)
1476                 return ret;
1477
1478         data8 &= ~SPI_AUTO_EDGE_DETECTION;
1479         ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1480         if (ret)
1481                 return ret;
1482
1483         /* read chip id */
1484         ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1485         if (ret)
1486                 return ret;
1487         ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1488         if (ret)
1489                 return ret;
1490
1491         /* Number of ports can be reduced depending on chip. */
1492         dev->mib_port_cnt = TOTAL_PORT_NUM;
1493         dev->phy_port_cnt = 5;
1494
1495         /* Default capability is gigabit capable. */
1496         dev->features = GBIT_SUPPORT;
1497
1498         id_hi = (u8)(id32 >> 16);
1499         id_lo = (u8)(id32 >> 8);
1500         if ((id_lo & 0xf) == 3) {
1501                 /* Chip is from KSZ9893 design. */
1502                 dev->features |= IS_9893;
1503
1504                 /* Chip does not support gigabit. */
1505                 if (data8 & SW_QW_ABLE)
1506                         dev->features &= ~GBIT_SUPPORT;
1507                 dev->mib_port_cnt = 3;
1508                 dev->phy_port_cnt = 2;
1509         } else {
1510                 /* Chip uses new XMII register definitions. */
1511                 dev->features |= NEW_XMII;
1512
1513                 /* Chip does not support gigabit. */
1514                 if (!(data8 & SW_GIGABIT_ABLE))
1515                         dev->features &= ~GBIT_SUPPORT;
1516         }
1517
1518         /* Change chip id to known ones so it can be matched against them. */
1519         id32 = (id_hi << 16) | (id_lo << 8);
1520
1521         dev->chip_id = id32;
1522
1523         return 0;
1524 }
1525
1526 struct ksz_chip_data {
1527         u32 chip_id;
1528         const char *dev_name;
1529         int num_vlans;
1530         int num_alus;
1531         int num_statics;
1532         int cpu_ports;
1533         int port_cnt;
1534         bool phy_errata_9477;
1535 };
1536
1537 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1538         {
1539                 .chip_id = 0x00947700,
1540                 .dev_name = "KSZ9477",
1541                 .num_vlans = 4096,
1542                 .num_alus = 4096,
1543                 .num_statics = 16,
1544                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1545                 .port_cnt = 7,          /* total physical port count */
1546                 .phy_errata_9477 = true,
1547         },
1548         {
1549                 .chip_id = 0x00989700,
1550                 .dev_name = "KSZ9897",
1551                 .num_vlans = 4096,
1552                 .num_alus = 4096,
1553                 .num_statics = 16,
1554                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1555                 .port_cnt = 7,          /* total physical port count */
1556                 .phy_errata_9477 = true,
1557         },
1558         {
1559                 .chip_id = 0x00989300,
1560                 .dev_name = "KSZ9893",
1561                 .num_vlans = 4096,
1562                 .num_alus = 4096,
1563                 .num_statics = 16,
1564                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1565                 .port_cnt = 3,          /* total port count */
1566         },
1567 };
1568
1569 static int ksz9477_switch_init(struct ksz_device *dev)
1570 {
1571         int i;
1572
1573         dev->ds->ops = &ksz9477_switch_ops;
1574
1575         for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1576                 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1577
1578                 if (dev->chip_id == chip->chip_id) {
1579                         dev->name = chip->dev_name;
1580                         dev->num_vlans = chip->num_vlans;
1581                         dev->num_alus = chip->num_alus;
1582                         dev->num_statics = chip->num_statics;
1583                         dev->port_cnt = chip->port_cnt;
1584                         dev->cpu_ports = chip->cpu_ports;
1585                         dev->phy_errata_9477 = chip->phy_errata_9477;
1586
1587                         break;
1588                 }
1589         }
1590
1591         /* no switch found */
1592         if (!dev->port_cnt)
1593                 return -ENODEV;
1594
1595         dev->port_mask = (1 << dev->port_cnt) - 1;
1596
1597         dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1598         dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1599
1600         i = dev->mib_port_cnt;
1601         dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1602                                   GFP_KERNEL);
1603         if (!dev->ports)
1604                 return -ENOMEM;
1605         for (i = 0; i < dev->mib_port_cnt; i++) {
1606                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1607                 dev->ports[i].mib.counters =
1608                         devm_kzalloc(dev->dev,
1609                                      sizeof(u64) *
1610                                      (TOTAL_SWITCH_COUNTER_NUM + 1),
1611                                      GFP_KERNEL);
1612                 if (!dev->ports[i].mib.counters)
1613                         return -ENOMEM;
1614         }
1615
1616         return 0;
1617 }
1618
1619 static void ksz9477_switch_exit(struct ksz_device *dev)
1620 {
1621         ksz9477_reset_switch(dev);
1622 }
1623
1624 static const struct ksz_dev_ops ksz9477_dev_ops = {
1625         .get_port_addr = ksz9477_get_port_addr,
1626         .cfg_port_member = ksz9477_cfg_port_member,
1627         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1628         .phy_setup = ksz9477_phy_setup,
1629         .port_setup = ksz9477_port_setup,
1630         .r_mib_cnt = ksz9477_r_mib_cnt,
1631         .r_mib_pkt = ksz9477_r_mib_pkt,
1632         .freeze_mib = ksz9477_freeze_mib,
1633         .port_init_cnt = ksz9477_port_init_cnt,
1634         .shutdown = ksz9477_reset_switch,
1635         .detect = ksz9477_switch_detect,
1636         .init = ksz9477_switch_init,
1637         .exit = ksz9477_switch_exit,
1638 };
1639
1640 int ksz9477_switch_register(struct ksz_device *dev)
1641 {
1642         return ksz_switch_register(dev, &ksz9477_dev_ops);
1643 }
1644 EXPORT_SYMBOL(ksz9477_switch_register);
1645
1646 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1647 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1648 MODULE_LICENSE("GPL");