1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip KSZ8795 switch driver
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/export.h>
12 #include <linux/gpio.h>
13 #include <linux/if_vlan.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_data/microchip-ksz.h>
17 #include <linux/phy.h>
18 #include <linux/etherdevice.h>
19 #include <linux/if_bridge.h>
20 #include <linux/micrel_phy.h>
22 #include <net/switchdev.h>
23 #include <linux/phylink.h>
25 #include "ksz_common.h"
26 #include "ksz8795_reg.h"
29 static const u8 ksz8795_regs[] = {
30 [REG_IND_CTRL_0] = 0x6E,
31 [REG_IND_DATA_8] = 0x70,
32 [REG_IND_DATA_CHECK] = 0x72,
33 [REG_IND_DATA_HI] = 0x71,
34 [REG_IND_DATA_LO] = 0x75,
35 [REG_IND_MIB_CHECK] = 0x74,
36 [P_FORCE_CTRL] = 0x0C,
37 [P_LINK_STATUS] = 0x0E,
38 [P_LOCAL_CTRL] = 0x07,
39 [P_NEG_RESTART_CTRL] = 0x0D,
40 [P_REMOTE_STATUS] = 0x08,
41 [P_SPEED_STATUS] = 0x09,
42 [S_TAIL_TAG_CTRL] = 0x0C,
45 static const u32 ksz8795_masks[] = {
46 [PORT_802_1P_REMAPPING] = BIT(7),
47 [SW_TAIL_TAG_ENABLE] = BIT(1),
48 [MIB_COUNTER_OVERFLOW] = BIT(6),
49 [MIB_COUNTER_VALID] = BIT(5),
50 [VLAN_TABLE_FID] = GENMASK(6, 0),
51 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
52 [VLAN_TABLE_VALID] = BIT(12),
53 [STATIC_MAC_TABLE_VALID] = BIT(21),
54 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
55 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
56 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
57 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
58 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
59 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
60 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
61 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
62 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
63 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
64 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
67 static const u8 ksz8795_shifts[] = {
68 [VLAN_TABLE_MEMBERSHIP_S] = 7,
70 [STATIC_MAC_FWD_PORTS] = 16,
71 [STATIC_MAC_FID] = 24,
72 [DYNAMIC_MAC_ENTRIES_H] = 3,
73 [DYNAMIC_MAC_ENTRIES] = 29,
74 [DYNAMIC_MAC_FID] = 16,
75 [DYNAMIC_MAC_TIMESTAMP] = 27,
76 [DYNAMIC_MAC_SRC_PORT] = 24,
79 static const u8 ksz8863_regs[] = {
80 [REG_IND_CTRL_0] = 0x79,
81 [REG_IND_DATA_8] = 0x7B,
82 [REG_IND_DATA_CHECK] = 0x7B,
83 [REG_IND_DATA_HI] = 0x7C,
84 [REG_IND_DATA_LO] = 0x80,
85 [REG_IND_MIB_CHECK] = 0x80,
86 [P_FORCE_CTRL] = 0x0C,
87 [P_LINK_STATUS] = 0x0E,
88 [P_LOCAL_CTRL] = 0x0C,
89 [P_NEG_RESTART_CTRL] = 0x0D,
90 [P_REMOTE_STATUS] = 0x0E,
91 [P_SPEED_STATUS] = 0x0F,
92 [S_TAIL_TAG_CTRL] = 0x03,
95 static const u32 ksz8863_masks[] = {
96 [PORT_802_1P_REMAPPING] = BIT(3),
97 [SW_TAIL_TAG_ENABLE] = BIT(6),
98 [MIB_COUNTER_OVERFLOW] = BIT(7),
99 [MIB_COUNTER_VALID] = BIT(6),
100 [VLAN_TABLE_FID] = GENMASK(15, 12),
101 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
102 [VLAN_TABLE_VALID] = BIT(19),
103 [STATIC_MAC_TABLE_VALID] = BIT(19),
104 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
105 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
106 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
107 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
108 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
109 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
110 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
111 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
112 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
113 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
114 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
117 static u8 ksz8863_shifts[] = {
118 [VLAN_TABLE_MEMBERSHIP_S] = 16,
119 [STATIC_MAC_FWD_PORTS] = 16,
120 [STATIC_MAC_FID] = 22,
121 [DYNAMIC_MAC_ENTRIES_H] = 3,
122 [DYNAMIC_MAC_ENTRIES] = 24,
123 [DYNAMIC_MAC_FID] = 16,
124 [DYNAMIC_MAC_TIMESTAMP] = 24,
125 [DYNAMIC_MAC_SRC_PORT] = 20,
129 char string[ETH_GSTRING_LEN];
132 static const struct mib_names ksz87xx_mib_names[] = {
171 static const struct mib_names ksz88xx_mib_names[] = {
208 static bool ksz_is_ksz88x3(struct ksz_device *dev)
210 return dev->chip_id == 0x8830;
213 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
215 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
218 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
221 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
222 bits, set ? bits : 0);
225 static int ksz8_reset_switch(struct ksz_device *dev)
227 if (ksz_is_ksz88x3(dev)) {
229 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
230 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
231 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
232 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
235 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
236 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
237 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
243 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
247 /* Number of queues can only be 1, 2, or 4. */
251 queue = PORT_QUEUE_SPLIT_4;
254 queue = PORT_QUEUE_SPLIT_2;
257 queue = PORT_QUEUE_SPLIT_1;
259 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
260 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
261 lo &= ~PORT_QUEUE_SPLIT_L;
262 if (queue & PORT_QUEUE_SPLIT_2)
263 lo |= PORT_QUEUE_SPLIT_L;
264 hi &= ~PORT_QUEUE_SPLIT_H;
265 if (queue & PORT_QUEUE_SPLIT_4)
266 hi |= PORT_QUEUE_SPLIT_H;
267 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
268 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
270 /* Default is port based for egress rate limit. */
271 if (queue != PORT_QUEUE_SPLIT_1)
272 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
276 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
278 struct ksz8 *ksz8 = dev->priv;
289 ctrl_addr = addr + dev->reg_mib_cnt * port;
290 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
292 mutex_lock(&dev->alu_mutex);
293 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
295 /* It is almost guaranteed to always read the valid bit because of
298 for (loop = 2; loop > 0; loop--) {
299 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
301 if (check & masks[MIB_COUNTER_VALID]) {
302 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
303 if (check & masks[MIB_COUNTER_OVERFLOW])
304 *cnt += MIB_COUNTER_VALUE + 1;
305 *cnt += data & MIB_COUNTER_VALUE;
309 mutex_unlock(&dev->alu_mutex);
312 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
313 u64 *dropped, u64 *cnt)
315 struct ksz8 *ksz8 = dev->priv;
326 addr -= dev->reg_mib_cnt;
327 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
328 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
329 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
331 mutex_lock(&dev->alu_mutex);
332 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
334 /* It is almost guaranteed to always read the valid bit because of
337 for (loop = 2; loop > 0; loop--) {
338 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
340 if (check & masks[MIB_COUNTER_VALID]) {
341 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
345 total = check & MIB_TOTAL_BYTES_H;
349 if (check & masks[MIB_COUNTER_OVERFLOW]) {
350 total = MIB_TOTAL_BYTES_H + 1;
355 if (check & masks[MIB_COUNTER_OVERFLOW])
356 *cnt += MIB_PACKET_DROPPED + 1;
357 *cnt += data & MIB_PACKET_DROPPED;
362 mutex_unlock(&dev->alu_mutex);
365 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
366 u64 *dropped, u64 *cnt)
368 struct ksz8 *ksz8 = dev->priv;
369 const u8 *regs = ksz8->regs;
370 u32 *last = (u32 *)dropped;
375 addr -= dev->reg_mib_cnt;
376 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
377 KSZ8863_MIB_PACKET_DROPPED_RX_0;
379 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
381 mutex_lock(&dev->alu_mutex);
382 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
383 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
384 mutex_unlock(&dev->alu_mutex);
386 data &= MIB_PACKET_DROPPED;
391 data += MIB_PACKET_DROPPED + 1;
397 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
398 u64 *dropped, u64 *cnt)
400 if (ksz_is_ksz88x3(dev))
401 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
403 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
406 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
408 if (ksz_is_ksz88x3(dev))
411 /* enable the port for flush/freeze function */
413 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
414 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
416 /* disable the port after freeze is done */
418 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
421 static void ksz8_port_init_cnt(struct ksz_device *dev, int port)
423 struct ksz_port_mib *mib = &dev->ports[port].mib;
426 if (!ksz_is_ksz88x3(dev)) {
427 /* flush all enabled port MIB counters */
428 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
429 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
430 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
435 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
436 while (mib->cnt_ptr < dev->reg_mib_cnt) {
437 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
438 &mib->counters[mib->cnt_ptr]);
442 /* last one in storage */
443 dropped = &mib->counters[dev->mib_cnt];
445 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
446 while (mib->cnt_ptr < dev->mib_cnt) {
447 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
448 dropped, &mib->counters[mib->cnt_ptr]);
452 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
455 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
457 struct ksz8 *ksz8 = dev->priv;
458 const u8 *regs = ksz8->regs;
461 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
463 mutex_lock(&dev->alu_mutex);
464 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
465 ksz_read64(dev, regs[REG_IND_DATA_HI], data);
466 mutex_unlock(&dev->alu_mutex);
469 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
471 struct ksz8 *ksz8 = dev->priv;
472 const u8 *regs = ksz8->regs;
475 ctrl_addr = IND_ACC_TABLE(table) | addr;
477 mutex_lock(&dev->alu_mutex);
478 ksz_write64(dev, regs[REG_IND_DATA_HI], data);
479 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
480 mutex_unlock(&dev->alu_mutex);
483 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
485 struct ksz8 *ksz8 = dev->priv;
494 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
496 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
498 /* Entry is not ready for accessing. */
499 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
501 /* Entry is ready for accessing. */
503 ksz_read8(dev, regs[REG_IND_DATA_8], data);
505 /* There is no valid entry in the table. */
506 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
512 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
513 u8 *mac_addr, u8 *fid, u8 *src_port,
514 u8 *timestamp, u16 *entries)
516 struct ksz8 *ksz8 = dev->priv;
517 u32 data_hi, data_lo;
525 shifts = ksz8->shifts;
529 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
531 mutex_lock(&dev->alu_mutex);
532 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
534 rc = ksz8_valid_dyn_entry(dev, &data);
538 } else if (rc == -ENXIO) {
540 /* At least one valid entry in the table. */
545 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
546 data_hi = (u32)(buf >> 32);
549 /* Check out how many valid entry in the table. */
550 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
551 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
552 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
553 shifts[DYNAMIC_MAC_ENTRIES];
556 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
557 shifts[DYNAMIC_MAC_FID];
558 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
559 shifts[DYNAMIC_MAC_SRC_PORT];
560 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
561 shifts[DYNAMIC_MAC_TIMESTAMP];
563 mac_addr[5] = (u8)data_lo;
564 mac_addr[4] = (u8)(data_lo >> 8);
565 mac_addr[3] = (u8)(data_lo >> 16);
566 mac_addr[2] = (u8)(data_lo >> 24);
568 mac_addr[1] = (u8)data_hi;
569 mac_addr[0] = (u8)(data_hi >> 8);
572 mutex_unlock(&dev->alu_mutex);
577 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
578 struct alu_struct *alu)
580 struct ksz8 *ksz8 = dev->priv;
581 u32 data_hi, data_lo;
586 shifts = ksz8->shifts;
589 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
590 data_hi = data >> 32;
592 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] |
593 masks[STATIC_MAC_TABLE_OVERRIDE])) {
594 alu->mac[5] = (u8)data_lo;
595 alu->mac[4] = (u8)(data_lo >> 8);
596 alu->mac[3] = (u8)(data_lo >> 16);
597 alu->mac[2] = (u8)(data_lo >> 24);
598 alu->mac[1] = (u8)data_hi;
599 alu->mac[0] = (u8)(data_hi >> 8);
601 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
602 shifts[STATIC_MAC_FWD_PORTS];
604 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
606 alu->is_static = true;
608 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
609 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
610 shifts[STATIC_MAC_FID];
616 static void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
617 struct alu_struct *alu)
619 struct ksz8 *ksz8 = dev->priv;
620 u32 data_hi, data_lo;
625 shifts = ksz8->shifts;
628 data_lo = ((u32)alu->mac[2] << 24) |
629 ((u32)alu->mac[3] << 16) |
630 ((u32)alu->mac[4] << 8) | alu->mac[5];
631 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
632 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
634 if (alu->is_override)
635 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
636 if (alu->is_use_fid) {
637 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
638 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
641 data_hi |= masks[STATIC_MAC_TABLE_VALID];
643 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
645 data = (u64)data_hi << 32 | data_lo;
646 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
649 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
650 u8 *member, u8 *valid)
652 struct ksz8 *ksz8 = dev->priv;
656 shifts = ksz8->shifts;
659 *fid = vlan & masks[VLAN_TABLE_FID];
660 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
661 shifts[VLAN_TABLE_MEMBERSHIP_S];
662 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
665 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
668 struct ksz8 *ksz8 = dev->priv;
672 shifts = ksz8->shifts;
676 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
678 *vlan |= masks[VLAN_TABLE_VALID];
681 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
683 struct ksz8 *ksz8 = dev->priv;
688 shifts = ksz8->shifts;
690 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
692 for (i = 0; i < 4; i++) {
693 dev->vlan_cache[addr + i].table[0] = (u16)data;
694 data >>= shifts[VLAN_TABLE];
698 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
708 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
712 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
722 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
724 dev->vlan_cache[vid].table[0] = vlan;
725 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
728 static void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
730 struct ksz8 *ksz8 = dev->priv;
731 u8 restart, speed, ctrl, link;
732 const u8 *regs = ksz8->regs;
733 int processed = true;
740 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
741 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
742 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
743 if (restart & PORT_PHY_LOOPBACK)
744 data |= BMCR_LOOPBACK;
745 if (ctrl & PORT_FORCE_100_MBIT)
746 data |= BMCR_SPEED100;
747 if (ksz_is_ksz88x3(dev)) {
748 if ((ctrl & PORT_AUTO_NEG_ENABLE))
749 data |= BMCR_ANENABLE;
751 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
752 data |= BMCR_ANENABLE;
754 if (restart & PORT_POWER_DOWN)
756 if (restart & PORT_AUTO_NEG_RESTART)
757 data |= BMCR_ANRESTART;
758 if (ctrl & PORT_FORCE_FULL_DUPLEX)
759 data |= BMCR_FULLDPLX;
760 if (speed & PORT_HP_MDIX)
761 data |= KSZ886X_BMCR_HP_MDIX;
762 if (restart & PORT_FORCE_MDIX)
763 data |= KSZ886X_BMCR_FORCE_MDI;
764 if (restart & PORT_AUTO_MDIX_DISABLE)
765 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
766 if (restart & PORT_TX_DISABLE)
767 data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
768 if (restart & PORT_LED_OFF)
769 data |= KSZ886X_BMCR_DISABLE_LED;
772 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
773 data = BMSR_100FULL |
778 if (link & PORT_AUTO_NEG_COMPLETE)
779 data |= BMSR_ANEGCOMPLETE;
780 if (link & PORT_STAT_LINK_GOOD)
781 data |= BMSR_LSTATUS;
784 data = KSZ8795_ID_HI;
787 if (ksz_is_ksz88x3(dev))
788 data = KSZ8863_ID_LO;
790 data = KSZ8795_ID_LO;
793 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
794 data = ADVERTISE_CSMA;
795 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
796 data |= ADVERTISE_PAUSE_CAP;
797 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
798 data |= ADVERTISE_100FULL;
799 if (ctrl & PORT_AUTO_NEG_100BTX)
800 data |= ADVERTISE_100HALF;
801 if (ctrl & PORT_AUTO_NEG_10BT_FD)
802 data |= ADVERTISE_10FULL;
803 if (ctrl & PORT_AUTO_NEG_10BT)
804 data |= ADVERTISE_10HALF;
807 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
809 if (link & PORT_REMOTE_SYM_PAUSE)
810 data |= LPA_PAUSE_CAP;
811 if (link & PORT_REMOTE_100BTX_FD)
813 if (link & PORT_REMOTE_100BTX)
815 if (link & PORT_REMOTE_10BT_FD)
817 if (link & PORT_REMOTE_10BT)
819 if (data & ~LPA_SLCT)
822 case PHY_REG_LINK_MD:
823 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
824 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
825 if (val1 & PORT_START_CABLE_DIAG)
826 data |= PHY_START_CABLE_DIAG;
828 if (val1 & PORT_CABLE_10M_SHORT)
829 data |= PHY_CABLE_10M_SHORT;
831 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
832 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
834 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
835 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
836 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
838 case PHY_REG_PHY_CTRL:
839 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
840 if (link & PORT_MDIX_STATUS)
841 data |= KSZ886X_CTRL_MDIX_STAT;
851 static void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
853 struct ksz8 *ksz8 = dev->priv;
854 u8 restart, speed, ctrl, data;
855 const u8 *regs = ksz8->regs;
861 /* Do not support PHY reset function. */
862 if (val & BMCR_RESET)
864 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
866 if (val & KSZ886X_BMCR_HP_MDIX)
867 data |= PORT_HP_MDIX;
869 data &= ~PORT_HP_MDIX;
871 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
872 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
874 if (ksz_is_ksz88x3(dev)) {
875 if ((val & BMCR_ANENABLE))
876 data |= PORT_AUTO_NEG_ENABLE;
878 data &= ~PORT_AUTO_NEG_ENABLE;
880 if (!(val & BMCR_ANENABLE))
881 data |= PORT_AUTO_NEG_DISABLE;
883 data &= ~PORT_AUTO_NEG_DISABLE;
885 /* Fiber port does not support auto-negotiation. */
886 if (dev->ports[p].fiber)
887 data |= PORT_AUTO_NEG_DISABLE;
890 if (val & BMCR_SPEED100)
891 data |= PORT_FORCE_100_MBIT;
893 data &= ~PORT_FORCE_100_MBIT;
894 if (val & BMCR_FULLDPLX)
895 data |= PORT_FORCE_FULL_DUPLEX;
897 data &= ~PORT_FORCE_FULL_DUPLEX;
899 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
900 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
902 if (val & KSZ886X_BMCR_DISABLE_LED)
903 data |= PORT_LED_OFF;
905 data &= ~PORT_LED_OFF;
906 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
907 data |= PORT_TX_DISABLE;
909 data &= ~PORT_TX_DISABLE;
910 if (val & BMCR_ANRESTART)
911 data |= PORT_AUTO_NEG_RESTART;
913 data &= ~(PORT_AUTO_NEG_RESTART);
914 if (val & BMCR_PDOWN)
915 data |= PORT_POWER_DOWN;
917 data &= ~PORT_POWER_DOWN;
918 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
919 data |= PORT_AUTO_MDIX_DISABLE;
921 data &= ~PORT_AUTO_MDIX_DISABLE;
922 if (val & KSZ886X_BMCR_FORCE_MDI)
923 data |= PORT_FORCE_MDIX;
925 data &= ~PORT_FORCE_MDIX;
926 if (val & BMCR_LOOPBACK)
927 data |= PORT_PHY_LOOPBACK;
929 data &= ~PORT_PHY_LOOPBACK;
931 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data);
934 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
936 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
937 PORT_AUTO_NEG_100BTX_FD |
938 PORT_AUTO_NEG_100BTX |
939 PORT_AUTO_NEG_10BT_FD |
941 if (val & ADVERTISE_PAUSE_CAP)
942 data |= PORT_AUTO_NEG_SYM_PAUSE;
943 if (val & ADVERTISE_100FULL)
944 data |= PORT_AUTO_NEG_100BTX_FD;
945 if (val & ADVERTISE_100HALF)
946 data |= PORT_AUTO_NEG_100BTX;
947 if (val & ADVERTISE_10FULL)
948 data |= PORT_AUTO_NEG_10BT_FD;
949 if (val & ADVERTISE_10HALF)
950 data |= PORT_AUTO_NEG_10BT;
952 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
954 case PHY_REG_LINK_MD:
955 if (val & PHY_START_CABLE_DIAG)
956 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
963 static enum dsa_tag_protocol ksz8_get_tag_protocol(struct dsa_switch *ds,
965 enum dsa_tag_protocol mp)
967 struct ksz_device *dev = ds->priv;
969 /* ksz88x3 uses the same tag schema as KSZ9893 */
970 return ksz_is_ksz88x3(dev) ?
971 DSA_TAG_PROTO_KSZ9893 : DSA_TAG_PROTO_KSZ8795;
974 static u32 ksz8_sw_get_phy_flags(struct dsa_switch *ds, int port)
976 /* Silicon Errata Sheet (DS80000830A):
977 * Port 1 does not work with LinkMD Cable-Testing.
978 * Port 1 does not respond to received PAUSE control frames.
981 return MICREL_KSZ8_P1_ERRATA;
986 static void ksz8_get_strings(struct dsa_switch *ds, int port,
987 u32 stringset, uint8_t *buf)
989 struct ksz_device *dev = ds->priv;
992 for (i = 0; i < dev->mib_cnt; i++) {
993 memcpy(buf + i * ETH_GSTRING_LEN,
994 dev->mib_names[i].string, ETH_GSTRING_LEN);
998 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1002 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1003 data &= ~PORT_VLAN_MEMBERSHIP;
1004 data |= (member & dev->port_mask);
1005 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1008 static void ksz8_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1010 struct ksz_device *dev = ds->priv;
1014 ksz_pread8(dev, port, P_STP_CTRL, &data);
1015 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1018 case BR_STATE_DISABLED:
1019 data |= PORT_LEARN_DISABLE;
1021 case BR_STATE_LISTENING:
1022 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1024 case BR_STATE_LEARNING:
1025 data |= PORT_RX_ENABLE;
1027 case BR_STATE_FORWARDING:
1028 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
1030 case BR_STATE_BLOCKING:
1031 data |= PORT_LEARN_DISABLE;
1034 dev_err(ds->dev, "invalid STP state: %d\n", state);
1038 ksz_pwrite8(dev, port, P_STP_CTRL, data);
1040 p = &dev->ports[port];
1041 p->stp_state = state;
1043 ksz_update_port_member(dev, port);
1046 static void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1048 u8 learn[DSA_MAX_PORTS];
1049 int first, index, cnt;
1052 if ((uint)port < dev->port_cnt) {
1056 /* Flush all ports. */
1058 cnt = dev->port_cnt;
1060 for (index = first; index < cnt; index++) {
1061 p = &dev->ports[index];
1064 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
1065 if (!(learn[index] & PORT_LEARN_DISABLE))
1066 ksz_pwrite8(dev, index, P_STP_CTRL,
1067 learn[index] | PORT_LEARN_DISABLE);
1069 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1070 for (index = first; index < cnt; index++) {
1071 p = &dev->ports[index];
1074 if (!(learn[index] & PORT_LEARN_DISABLE))
1075 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
1079 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag,
1080 struct netlink_ext_ack *extack)
1082 struct ksz_device *dev = ds->priv;
1084 if (ksz_is_ksz88x3(dev))
1087 /* Discard packets with VID not enabled on the switch */
1088 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1090 /* Discard packets with VID not enabled on the ingress port */
1091 for (port = 0; port < dev->phy_port_cnt; ++port)
1092 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1098 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1100 if (ksz_is_ksz88x3(dev)) {
1101 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1102 0x03 << (4 - 2 * port), state);
1104 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1108 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port,
1109 const struct switchdev_obj_port_vlan *vlan,
1110 struct netlink_ext_ack *extack)
1112 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1113 struct ksz_device *dev = ds->priv;
1114 struct ksz_port *p = &dev->ports[port];
1115 u16 data, new_pvid = 0;
1116 u8 fid, member, valid;
1118 if (ksz_is_ksz88x3(dev))
1121 /* If a VLAN is added with untagged flag different from the
1122 * port's Remove Tag flag, we need to change the latter.
1123 * Ignore VID 0, which is always untagged.
1124 * Ignore CPU port, which will always be tagged.
1126 if (untagged != p->remove_tag && vlan->vid != 0 &&
1127 port != dev->cpu_port) {
1130 /* Reject attempts to add a VLAN that requires the
1131 * Remove Tag flag to be changed, unless there are no
1132 * other VLANs currently configured.
1134 for (vid = 1; vid < dev->num_vlans; ++vid) {
1135 /* Skip the VID we are going to add or reconfigure */
1136 if (vid == vlan->vid)
1139 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1140 &fid, &member, &valid);
1141 if (valid && (member & BIT(port)))
1145 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1146 p->remove_tag = untagged;
1149 ksz8_r_vlan_table(dev, vlan->vid, &data);
1150 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1152 /* First time to setup the VLAN entry. */
1154 /* Need to find a way to map VID to FID. */
1158 member |= BIT(port);
1160 ksz8_to_vlan(dev, fid, member, valid, &data);
1161 ksz8_w_vlan_table(dev, vlan->vid, data);
1164 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1165 new_pvid = vlan->vid;
1170 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1171 vid &= ~VLAN_VID_MASK;
1173 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1175 ksz8_port_enable_pvid(dev, port, true);
1181 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port,
1182 const struct switchdev_obj_port_vlan *vlan)
1184 struct ksz_device *dev = ds->priv;
1186 u8 fid, member, valid;
1188 if (ksz_is_ksz88x3(dev))
1191 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1192 pvid = pvid & 0xFFF;
1194 ksz8_r_vlan_table(dev, vlan->vid, &data);
1195 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1197 member &= ~BIT(port);
1199 /* Invalidate the entry if no more member. */
1205 ksz8_to_vlan(dev, fid, member, valid, &data);
1206 ksz8_w_vlan_table(dev, vlan->vid, data);
1208 if (pvid == vlan->vid)
1209 ksz8_port_enable_pvid(dev, port, false);
1214 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port,
1215 struct dsa_mall_mirror_tc_entry *mirror,
1218 struct ksz_device *dev = ds->priv;
1221 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1222 dev->mirror_rx |= BIT(port);
1224 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1225 dev->mirror_tx |= BIT(port);
1228 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1230 /* configure mirror port */
1231 if (dev->mirror_rx || dev->mirror_tx)
1232 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1233 PORT_MIRROR_SNIFFER, true);
1238 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port,
1239 struct dsa_mall_mirror_tc_entry *mirror)
1241 struct ksz_device *dev = ds->priv;
1244 if (mirror->ingress) {
1245 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1246 dev->mirror_rx &= ~BIT(port);
1248 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1249 dev->mirror_tx &= ~BIT(port);
1252 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1254 if (!dev->mirror_rx && !dev->mirror_tx)
1255 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1256 PORT_MIRROR_SNIFFER, false);
1259 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1261 struct ksz_port *p = &dev->ports[port];
1264 if (!p->interface && dev->compat_interface) {
1266 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1267 "Please update your device tree.\n",
1269 p->interface = dev->compat_interface;
1272 /* Configure MII interface for proper network communication. */
1273 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
1274 data8 &= ~PORT_INTERFACE_TYPE;
1275 data8 &= ~PORT_GMII_1GPS_MODE;
1276 switch (p->interface) {
1277 case PHY_INTERFACE_MODE_MII:
1278 p->phydev.speed = SPEED_100;
1280 case PHY_INTERFACE_MODE_RMII:
1281 data8 |= PORT_INTERFACE_RMII;
1282 p->phydev.speed = SPEED_100;
1284 case PHY_INTERFACE_MODE_GMII:
1285 data8 |= PORT_GMII_1GPS_MODE;
1286 data8 |= PORT_INTERFACE_GMII;
1287 p->phydev.speed = SPEED_1000;
1290 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
1291 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
1292 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1293 p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1294 data8 |= PORT_RGMII_ID_IN_ENABLE;
1295 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1296 p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1297 data8 |= PORT_RGMII_ID_OUT_ENABLE;
1298 data8 |= PORT_GMII_1GPS_MODE;
1299 data8 |= PORT_INTERFACE_RGMII;
1300 p->phydev.speed = SPEED_1000;
1303 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
1304 p->phydev.duplex = 1;
1307 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1309 struct dsa_switch *ds = dev->ds;
1310 struct ksz8 *ksz8 = dev->priv;
1314 masks = ksz8->masks;
1316 /* enable broadcast storm limit */
1317 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1319 if (!ksz_is_ksz88x3(dev))
1320 ksz8795_set_prio_queue(dev, port, 4);
1322 /* disable DiffServ priority */
1323 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1325 /* replace priority */
1326 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1327 masks[PORT_802_1P_REMAPPING], false);
1329 /* enable 802.1p priority */
1330 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1333 if (!ksz_is_ksz88x3(dev))
1334 ksz8795_cpu_interface_select(dev, port);
1336 member = dsa_user_ports(ds);
1338 member = BIT(dsa_upstream_port(ds, port));
1341 ksz8_cfg_port_member(dev, port, member);
1344 static void ksz8_config_cpu_port(struct dsa_switch *ds)
1346 struct ksz_device *dev = ds->priv;
1347 struct ksz8 *ksz8 = dev->priv;
1348 const u8 *regs = ksz8->regs;
1354 masks = ksz8->masks;
1356 /* Switch marks the maximum frame with extra byte as oversize. */
1357 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1358 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1360 p = &dev->ports[dev->cpu_port];
1363 ksz8_port_setup(dev, dev->cpu_port, true);
1365 for (i = 0; i < dev->phy_port_cnt; i++) {
1368 ksz8_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1370 /* Last port may be disabled. */
1371 if (i == dev->phy_port_cnt)
1376 for (i = 0; i < dev->phy_port_cnt; i++) {
1380 if (!ksz_is_ksz88x3(dev)) {
1381 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1382 if (remote & PORT_FIBER_MODE)
1386 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1389 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1394 static int ksz8_setup(struct dsa_switch *ds)
1396 struct ksz_device *dev = ds->priv;
1397 struct alu_struct alu;
1400 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1401 dev->num_vlans, GFP_KERNEL);
1402 if (!dev->vlan_cache)
1405 ret = ksz8_reset_switch(dev);
1407 dev_err(ds->dev, "failed to reset switch\n");
1411 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1413 /* Enable automatic fast aging when link changed detected. */
1414 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1416 /* Enable aggressive back off algorithm in half duplex mode. */
1417 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1418 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1421 * Make sure unicast VLAN boundary is set as default and
1422 * enable no excessive collision drop.
1424 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1425 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1426 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1428 ksz8_config_cpu_port(ds);
1430 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1432 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1434 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1436 if (!ksz_is_ksz88x3(dev))
1437 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1439 /* set broadcast storm protection 10% rate */
1440 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1441 BROADCAST_STORM_RATE,
1442 (BROADCAST_STORM_VALUE *
1443 BROADCAST_STORM_PROT_RATE) / 100);
1445 for (i = 0; i < (dev->num_vlans / 4); i++)
1446 ksz8_r_vlan_entries(dev, i);
1448 /* Setup STP address for STP operation. */
1449 memset(&alu, 0, sizeof(alu));
1450 ether_addr_copy(alu.mac, eth_stp_addr);
1451 alu.is_static = true;
1452 alu.is_override = true;
1453 alu.port_forward = dev->host_mask;
1455 ksz8_w_sta_mac_table(dev, 0, &alu);
1457 ksz_init_mib_timer(dev);
1459 ds->configure_vlan_while_not_filtering = false;
1464 static void ksz8_validate(struct dsa_switch *ds, int port,
1465 unsigned long *supported,
1466 struct phylink_link_state *state)
1468 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1469 struct ksz_device *dev = ds->priv;
1471 if (port == dev->cpu_port) {
1472 if (state->interface != PHY_INTERFACE_MODE_RMII &&
1473 state->interface != PHY_INTERFACE_MODE_MII &&
1474 state->interface != PHY_INTERFACE_MODE_NA)
1477 if (state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1478 state->interface != PHY_INTERFACE_MODE_NA)
1482 /* Allow all the expected bits */
1483 phylink_set_port_modes(mask);
1484 phylink_set(mask, Autoneg);
1486 /* Silicon Errata Sheet (DS80000830A):
1487 * "Port 1 does not respond to received flow control PAUSE frames"
1488 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1491 if (!ksz_is_ksz88x3(dev) || port)
1492 phylink_set(mask, Pause);
1494 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1495 if (!ksz_is_ksz88x3(dev))
1496 phylink_set(mask, Asym_Pause);
1498 /* 10M and 100M are only supported */
1499 phylink_set(mask, 10baseT_Half);
1500 phylink_set(mask, 10baseT_Full);
1501 phylink_set(mask, 100baseT_Half);
1502 phylink_set(mask, 100baseT_Full);
1504 linkmode_and(supported, supported, mask);
1505 linkmode_and(state->advertising, state->advertising, mask);
1510 linkmode_zero(supported);
1511 dev_err(ds->dev, "Unsupported interface: %s, port: %d\n",
1512 phy_modes(state->interface), port);
1515 static const struct dsa_switch_ops ksz8_switch_ops = {
1516 .get_tag_protocol = ksz8_get_tag_protocol,
1517 .get_phy_flags = ksz8_sw_get_phy_flags,
1518 .setup = ksz8_setup,
1519 .phy_read = ksz_phy_read16,
1520 .phy_write = ksz_phy_write16,
1521 .phylink_validate = ksz8_validate,
1522 .phylink_mac_link_down = ksz_mac_link_down,
1523 .port_enable = ksz_enable_port,
1524 .get_strings = ksz8_get_strings,
1525 .get_ethtool_stats = ksz_get_ethtool_stats,
1526 .get_sset_count = ksz_sset_count,
1527 .port_bridge_join = ksz_port_bridge_join,
1528 .port_bridge_leave = ksz_port_bridge_leave,
1529 .port_stp_state_set = ksz8_port_stp_state_set,
1530 .port_fast_age = ksz_port_fast_age,
1531 .port_vlan_filtering = ksz8_port_vlan_filtering,
1532 .port_vlan_add = ksz8_port_vlan_add,
1533 .port_vlan_del = ksz8_port_vlan_del,
1534 .port_fdb_dump = ksz_port_fdb_dump,
1535 .port_mdb_add = ksz_port_mdb_add,
1536 .port_mdb_del = ksz_port_mdb_del,
1537 .port_mirror_add = ksz8_port_mirror_add,
1538 .port_mirror_del = ksz8_port_mirror_del,
1541 static u32 ksz8_get_port_addr(int port, int offset)
1543 return PORT_CTRL_ADDR(port, offset);
1546 static int ksz8_switch_detect(struct ksz_device *dev)
1553 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1558 id2 = id16 & SW_CHIP_ID_M;
1561 case KSZ87_FAMILY_ID:
1562 if ((id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1565 if (id2 == CHIP_ID_95) {
1569 ksz_read8(dev, REG_PORT_STATUS_0, &val);
1570 if (val & PORT_FIBER_MODE)
1572 } else if (id2 == CHIP_ID_94) {
1576 case KSZ88_FAMILY_ID:
1577 if (id2 != CHIP_ID_63)
1581 dev_err(dev->dev, "invalid family id: %d\n", id1);
1586 dev->chip_id = id16;
1591 struct ksz_chip_data {
1593 const char *dev_name;
1601 static const struct ksz_chip_data ksz8_switch_chips[] = {
1604 .dev_name = "KSZ8795",
1608 .cpu_ports = 0x10, /* can be configured as cpu port */
1609 .port_cnt = 5, /* total cpu and user ports */
1615 * KSZ8794 is similar to KSZ8795, except the port map
1616 * contains a gap between external and CPU ports, the
1617 * port map is NOT continuous. The per-port register
1618 * map is shifted accordingly too, i.e. registers at
1619 * offset 0x40 are NOT used on KSZ8794 and they ARE
1620 * used on KSZ8795 for external port 3.
1627 .dev_name = "KSZ8794",
1631 .cpu_ports = 0x10, /* can be configured as cpu port */
1632 .port_cnt = 4, /* total cpu and user ports */
1636 .dev_name = "KSZ8765",
1640 .cpu_ports = 0x10, /* can be configured as cpu port */
1641 .port_cnt = 5, /* total cpu and user ports */
1645 .dev_name = "KSZ8863/KSZ8873",
1649 .cpu_ports = 0x4, /* can be configured as cpu port */
1654 static int ksz8_switch_init(struct ksz_device *dev)
1656 struct ksz8 *ksz8 = dev->priv;
1659 dev->ds->ops = &ksz8_switch_ops;
1661 for (i = 0; i < ARRAY_SIZE(ksz8_switch_chips); i++) {
1662 const struct ksz_chip_data *chip = &ksz8_switch_chips[i];
1664 if (dev->chip_id == chip->chip_id) {
1665 dev->name = chip->dev_name;
1666 dev->num_vlans = chip->num_vlans;
1667 dev->num_alus = chip->num_alus;
1668 dev->num_statics = chip->num_statics;
1669 dev->port_cnt = fls(chip->cpu_ports);
1670 dev->cpu_port = fls(chip->cpu_ports) - 1;
1671 dev->phy_port_cnt = dev->port_cnt - 1;
1672 dev->cpu_ports = chip->cpu_ports;
1673 dev->host_mask = chip->cpu_ports;
1674 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) |
1680 /* no switch found */
1681 if (!dev->cpu_ports)
1684 if (ksz_is_ksz88x3(dev)) {
1685 ksz8->regs = ksz8863_regs;
1686 ksz8->masks = ksz8863_masks;
1687 ksz8->shifts = ksz8863_shifts;
1688 dev->mib_cnt = ARRAY_SIZE(ksz88xx_mib_names);
1689 dev->mib_names = ksz88xx_mib_names;
1691 ksz8->regs = ksz8795_regs;
1692 ksz8->masks = ksz8795_masks;
1693 ksz8->shifts = ksz8795_shifts;
1694 dev->mib_cnt = ARRAY_SIZE(ksz87xx_mib_names);
1695 dev->mib_names = ksz87xx_mib_names;
1698 dev->reg_mib_cnt = MIB_COUNTER_NUM;
1700 dev->ports = devm_kzalloc(dev->dev,
1701 dev->port_cnt * sizeof(struct ksz_port),
1705 for (i = 0; i < dev->port_cnt; i++) {
1706 mutex_init(&dev->ports[i].mib.cnt_mutex);
1707 dev->ports[i].mib.counters =
1708 devm_kzalloc(dev->dev,
1712 if (!dev->ports[i].mib.counters)
1716 /* set the real number of ports */
1717 dev->ds->num_ports = dev->port_cnt;
1719 /* We rely on software untagging on the CPU port, so that we
1720 * can support both tagged and untagged VLANs
1722 dev->ds->untag_bridge_pvid = true;
1724 /* VLAN filtering is partly controlled by the global VLAN
1727 dev->ds->vlan_filtering_is_global = true;
1732 static void ksz8_switch_exit(struct ksz_device *dev)
1734 ksz8_reset_switch(dev);
1737 static const struct ksz_dev_ops ksz8_dev_ops = {
1738 .get_port_addr = ksz8_get_port_addr,
1739 .cfg_port_member = ksz8_cfg_port_member,
1740 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
1741 .port_setup = ksz8_port_setup,
1742 .r_phy = ksz8_r_phy,
1743 .w_phy = ksz8_w_phy,
1744 .r_dyn_mac_table = ksz8_r_dyn_mac_table,
1745 .r_sta_mac_table = ksz8_r_sta_mac_table,
1746 .w_sta_mac_table = ksz8_w_sta_mac_table,
1747 .r_mib_cnt = ksz8_r_mib_cnt,
1748 .r_mib_pkt = ksz8_r_mib_pkt,
1749 .freeze_mib = ksz8_freeze_mib,
1750 .port_init_cnt = ksz8_port_init_cnt,
1751 .shutdown = ksz8_reset_switch,
1752 .detect = ksz8_switch_detect,
1753 .init = ksz8_switch_init,
1754 .exit = ksz8_switch_exit,
1757 int ksz8_switch_register(struct ksz_device *dev)
1759 return ksz_switch_register(dev, &ksz8_dev_ops);
1761 EXPORT_SYMBOL(ksz8_switch_register);
1763 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1764 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1765 MODULE_LICENSE("GPL");