1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/regmap.h>
9 #include <linux/mutex.h>
10 #include <linux/mii.h>
11 #include <linux/phy.h>
12 #include <linux/if_bridge.h>
13 #include <linux/if_vlan.h>
14 #include <linux/etherdevice.h>
18 /* For the LAN9303 and LAN9354, only port 0 is an XMII port. */
19 #define IS_PORT_XMII(port) ((port) == 0)
21 #define LAN9303_NUM_PORTS 3
23 /* 13.2 System Control and Status Registers
24 * Multiply register number by 4 to get address offset.
26 #define LAN9303_CHIP_REV 0x14
27 # define LAN9303_CHIP_ID 0x9303
28 # define LAN9352_CHIP_ID 0x9352
29 # define LAN9353_CHIP_ID 0x9353
30 # define LAN9354_CHIP_ID 0x9354
31 # define LAN9355_CHIP_ID 0x9355
32 #define LAN9303_IRQ_CFG 0x15
33 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
34 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
35 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
36 #define LAN9303_INT_STS 0x16
37 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
38 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
39 #define LAN9303_INT_EN 0x17
40 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
41 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
42 #define LAN9303_BYTE_ORDER 0x19
43 #define LAN9303_HW_CFG 0x1D
44 # define LAN9303_HW_CFG_READY BIT(27)
45 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
46 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
47 #define LAN9303_PMI_DATA 0x29
48 #define LAN9303_PMI_ACCESS 0x2A
49 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
50 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
51 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
52 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
53 #define LAN9303_MANUAL_FC_1 0x68
54 #define LAN9303_MANUAL_FC_2 0x69
55 #define LAN9303_MANUAL_FC_0 0x6a
56 # define LAN9303_BP_EN BIT(6)
57 # define LAN9303_RX_FC_EN BIT(2)
58 # define LAN9303_TX_FC_EN BIT(1)
59 #define LAN9303_SWITCH_CSR_DATA 0x6b
60 #define LAN9303_SWITCH_CSR_CMD 0x6c
61 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
62 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
63 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
64 #define LAN9303_VIRT_PHY_BASE 0x70
65 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
66 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
68 /*13.4 Switch Fabric Control and Status Registers
69 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
71 #define LAN9303_SW_DEV_ID 0x0000
72 #define LAN9303_SW_RESET 0x0001
73 #define LAN9303_SW_RESET_RESET BIT(0)
74 #define LAN9303_SW_IMR 0x0004
75 #define LAN9303_SW_IPR 0x0005
76 #define LAN9303_MAC_VER_ID_0 0x0400
77 #define LAN9303_MAC_RX_CFG_0 0x0401
78 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
79 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
80 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
81 #define LAN9303_MAC_RX_64_CNT_0 0x0411
82 #define LAN9303_MAC_RX_127_CNT_0 0x0412
83 #define LAN9303_MAC_RX_255_CNT_0 0x413
84 #define LAN9303_MAC_RX_511_CNT_0 0x0414
85 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
86 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
87 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
88 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
89 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
90 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
91 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
92 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
93 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
94 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
95 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
96 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
97 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
98 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
99 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
101 #define LAN9303_MAC_TX_CFG_0 0x0440
102 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
103 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
104 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
105 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
106 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
107 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
108 #define LAN9303_MAC_TX_64_CNT_0 0x0454
109 #define LAN9303_MAC_TX_127_CNT_0 0x0455
110 #define LAN9303_MAC_TX_255_CNT_0 0x0456
111 #define LAN9303_MAC_TX_511_CNT_0 0x0457
112 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
113 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
114 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
115 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
116 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
117 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
118 #define LAN9303_MAC_TX_LATECOL_0 0x045f
119 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
120 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
121 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
122 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
124 #define LAN9303_MAC_VER_ID_1 0x0800
125 #define LAN9303_MAC_RX_CFG_1 0x0801
126 #define LAN9303_MAC_TX_CFG_1 0x0840
127 #define LAN9303_MAC_VER_ID_2 0x0c00
128 #define LAN9303_MAC_RX_CFG_2 0x0c01
129 #define LAN9303_MAC_TX_CFG_2 0x0c40
130 #define LAN9303_SWE_ALR_CMD 0x1800
131 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
132 # define LAN9303_ALR_CMD_GET_FIRST BIT(1)
133 # define LAN9303_ALR_CMD_GET_NEXT BIT(0)
134 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
135 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
136 # define LAN9303_ALR_DAT1_VALID BIT(26)
137 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
138 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
139 # define LAN9303_ALR_DAT1_STATIC BIT(24)
140 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16
141 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
142 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
143 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
144 #define LAN9303_SWE_ALR_CMD_STS 0x1808
145 # define ALR_STS_MAKE_PEND BIT(0)
146 #define LAN9303_SWE_VLAN_CMD 0x180b
147 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
148 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
149 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
150 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
151 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
152 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
153 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
154 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
155 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
156 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
157 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
158 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
159 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
160 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
161 #define LAN9303_SWE_PORT_STATE 0x1843
162 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
163 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
164 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
165 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
166 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
167 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
168 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
169 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
170 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
171 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
172 #define LAN9303_SWE_PORT_MIRROR 0x1846
173 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
174 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
175 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
176 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
177 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
178 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
179 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
180 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
181 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
182 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
183 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
184 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
185 #define LAN9303_BM_CFG 0x1c00
186 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
187 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
188 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
189 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
191 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
193 /* the built-in PHYs are of type LAN911X */
194 #define MII_LAN911X_SPECIAL_MODES 0x12
195 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
197 static const struct regmap_range lan9303_valid_regs[] = {
198 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
199 regmap_reg_range(0x19, 0x19), /* endian test */
200 regmap_reg_range(0x1d, 0x1d), /* hardware config */
201 regmap_reg_range(0x23, 0x24), /* general purpose timer */
202 regmap_reg_range(0x27, 0x27), /* counter */
203 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
204 regmap_reg_range(0x68, 0x6a), /* flow control */
205 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
206 regmap_reg_range(0x6d, 0x6f), /* misc */
207 regmap_reg_range(0x70, 0x77), /* virtual phy */
208 regmap_reg_range(0x78, 0x7a), /* GPIO */
209 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
210 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
213 static const struct regmap_range lan9303_reserved_ranges[] = {
214 regmap_reg_range(0x00, 0x13),
215 regmap_reg_range(0x18, 0x18),
216 regmap_reg_range(0x1a, 0x1c),
217 regmap_reg_range(0x1e, 0x22),
218 regmap_reg_range(0x25, 0x26),
219 regmap_reg_range(0x28, 0x28),
220 regmap_reg_range(0x2b, 0x67),
221 regmap_reg_range(0x7b, 0x7b),
222 regmap_reg_range(0x7f, 0x7f),
223 regmap_reg_range(0xb8, 0xff),
226 const struct regmap_access_table lan9303_register_set = {
227 .yes_ranges = lan9303_valid_regs,
228 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
229 .no_ranges = lan9303_reserved_ranges,
230 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
232 EXPORT_SYMBOL(lan9303_register_set);
234 /* Flow Control registers indexed by port number */
235 static unsigned int flow_ctl_reg[] = {
241 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
245 /* we can lose arbitration for the I2C case, because the device
246 * tries to detect and read an external EEPROM after reset and acts as
247 * a master on the shared I2C bus itself. This conflicts with our
248 * attempts to access the device as a slave at the same moment.
250 for (i = 0; i < 5; i++) {
251 ret = regmap_read(regmap, offset, reg);
262 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
266 for (i = 0; i < 25; i++) {
270 ret = lan9303_read(chip->regmap, offset, ®);
272 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
273 __func__, offset, ret);
278 usleep_range(1000, 2000);
284 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
289 if (regnum > MII_EXPANSION)
292 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
299 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
301 if (regnum > MII_EXPANSION)
304 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
307 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
309 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
310 LAN9303_PMI_ACCESS_MII_BUSY);
313 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
318 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
319 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
321 mutex_lock(&chip->indirect_mutex);
323 ret = lan9303_indirect_phy_wait_for_completion(chip);
327 /* start the MII read cycle */
328 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
332 ret = lan9303_indirect_phy_wait_for_completion(chip);
336 /* read the result of this operation */
337 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
341 mutex_unlock(&chip->indirect_mutex);
346 mutex_unlock(&chip->indirect_mutex);
350 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
356 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
357 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
358 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
360 mutex_lock(&chip->indirect_mutex);
362 ret = lan9303_indirect_phy_wait_for_completion(chip);
366 /* write the data first... */
367 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
371 /* ...then start the MII write cycle */
372 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
375 mutex_unlock(&chip->indirect_mutex);
379 const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
380 .phy_read = lan9303_indirect_phy_read,
381 .phy_write = lan9303_indirect_phy_write,
383 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
385 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
387 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
388 LAN9303_SWITCH_CSR_CMD_BUSY);
391 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
397 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
398 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
400 mutex_lock(&chip->indirect_mutex);
402 ret = lan9303_switch_wait_for_completion(chip);
406 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
408 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
413 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
415 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
419 mutex_unlock(&chip->indirect_mutex);
423 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
429 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
430 reg |= LAN9303_SWITCH_CSR_CMD_RW;
431 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
433 mutex_lock(&chip->indirect_mutex);
435 ret = lan9303_switch_wait_for_completion(chip);
440 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
442 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
447 ret = lan9303_switch_wait_for_completion(chip);
451 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
453 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
455 mutex_unlock(&chip->indirect_mutex);
459 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
465 ret = lan9303_read_switch_reg(chip, regnum, ®);
469 reg = (reg & ~mask) | val;
471 return lan9303_write_switch_reg(chip, regnum, reg);
474 static int lan9303_write_switch_port(struct lan9303 *chip, int port,
477 return lan9303_write_switch_reg(
478 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
481 static int lan9303_read_switch_port(struct lan9303 *chip, int port,
482 u16 regnum, u32 *val)
484 return lan9303_read_switch_reg(
485 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
488 static int lan9303_detect_phy_setup(struct lan9303 *chip)
492 /* Calculate chip->phy_addr_base:
493 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
494 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
495 * 'phy_addr_sel_strap' setting directly, so we need a test, which
496 * configuration is active:
497 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
498 * and the IDs are 0-1-2, else it contains something different from
499 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
500 * 0xffff is returned on MDIO read with no response.
502 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
504 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
508 chip->phy_addr_base = reg != 0 && reg != 0xffff;
510 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
511 chip->phy_addr_base ? "1-2-3" : "0-1-2");
516 /* Map ALR-port bits to port bitmap, and back */
517 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
518 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
520 /* Return pointer to first free ALR cache entry, return NULL if none */
521 static struct lan9303_alr_cache_entry *
522 lan9303_alr_cache_find_free(struct lan9303 *chip)
525 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
527 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
528 if (entr->port_map == 0)
534 /* Return pointer to ALR cache entry matching MAC address */
535 static struct lan9303_alr_cache_entry *
536 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
539 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
541 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
542 "ether_addr_equal require u16 alignment");
544 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
545 if (ether_addr_equal(entr->mac_addr, mac_addr))
551 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
555 for (i = 0; i < 25; i++) {
558 lan9303_read_switch_reg(chip, regno, ®);
561 usleep_range(1000, 2000);
567 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
569 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
570 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
571 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
572 LAN9303_ALR_CMD_MAKE_ENTRY);
573 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
574 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
579 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
580 int portmap, void *ctx);
582 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
586 mutex_lock(&chip->alr_mutex);
587 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
588 LAN9303_ALR_CMD_GET_FIRST);
589 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
591 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
593 int alrport, portmap;
595 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
596 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
597 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
600 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
601 LAN9303_ALR_DAT1_PORT_BITOFFS;
602 portmap = alrport_2_portmap[alrport];
604 ret = cb(chip, dat0, dat1, portmap, ctx);
608 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
609 LAN9303_ALR_CMD_GET_NEXT);
610 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
612 mutex_unlock(&chip->alr_mutex);
617 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
619 mac[0] = (dat0 >> 0) & 0xff;
620 mac[1] = (dat0 >> 8) & 0xff;
621 mac[2] = (dat0 >> 16) & 0xff;
622 mac[3] = (dat0 >> 24) & 0xff;
623 mac[4] = (dat1 >> 0) & 0xff;
624 mac[5] = (dat1 >> 8) & 0xff;
627 struct del_port_learned_ctx {
631 /* Clear learned (non-static) entry on given port */
632 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
633 u32 dat1, int portmap, void *ctx)
635 struct del_port_learned_ctx *del_ctx = ctx;
636 int port = del_ctx->port;
638 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
641 /* learned entries has only one port, we can just delete */
642 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
643 lan9303_alr_make_entry_raw(chip, dat0, dat1);
648 struct port_fdb_dump_ctx {
651 dsa_fdb_dump_cb_t *cb;
654 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
655 u32 dat1, int portmap, void *ctx)
657 struct port_fdb_dump_ctx *dump_ctx = ctx;
661 if ((BIT(dump_ctx->port) & portmap) == 0)
664 alr_reg_to_mac(dat0, dat1, mac);
665 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
666 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
669 /* Set a static ALR entry. Delete entry if port_map is zero */
670 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
671 u8 port_map, bool stp_override)
673 u32 dat0, dat1, alr_port;
675 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
676 dat1 = LAN9303_ALR_DAT1_STATIC;
678 dat1 |= LAN9303_ALR_DAT1_VALID;
679 /* otherwise no ports: delete entry */
681 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
683 alr_port = portmap_2_alrport[port_map & 7];
684 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
685 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
688 dat0 |= (mac[0] << 0);
689 dat0 |= (mac[1] << 8);
690 dat0 |= (mac[2] << 16);
691 dat0 |= (mac[3] << 24);
693 dat1 |= (mac[4] << 0);
694 dat1 |= (mac[5] << 8);
696 lan9303_alr_make_entry_raw(chip, dat0, dat1);
699 /* Add port to static ALR entry, create new static entry if needed */
700 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
703 struct lan9303_alr_cache_entry *entr;
705 mutex_lock(&chip->alr_mutex);
706 entr = lan9303_alr_cache_find_mac(chip, mac);
707 if (!entr) { /*New entry */
708 entr = lan9303_alr_cache_find_free(chip);
710 mutex_unlock(&chip->alr_mutex);
713 ether_addr_copy(entr->mac_addr, mac);
715 entr->port_map |= BIT(port);
716 entr->stp_override = stp_override;
717 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
718 mutex_unlock(&chip->alr_mutex);
723 /* Delete static port from ALR entry, delete entry if last port */
724 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
726 struct lan9303_alr_cache_entry *entr;
728 mutex_lock(&chip->alr_mutex);
729 entr = lan9303_alr_cache_find_mac(chip, mac);
731 goto out; /* no static entry found */
733 entr->port_map &= ~BIT(port);
734 if (entr->port_map == 0) /* zero means its free again */
735 eth_zero_addr(entr->mac_addr);
736 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
739 mutex_unlock(&chip->alr_mutex);
743 static int lan9303_disable_processing_port(struct lan9303 *chip,
748 /* disable RX, but keep register reset default values else */
749 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
750 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
754 /* disable TX, but keep register reset default values else */
755 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
756 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
757 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
760 static int lan9303_enable_processing_port(struct lan9303 *chip,
765 /* enable RX and keep register reset default values else */
766 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
767 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
768 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
772 /* enable TX and keep register reset default values else */
773 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
774 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
775 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
776 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
779 /* forward special tagged packets from port 0 to port 1 *or* port 2 */
780 static int lan9303_setup_tagging(struct lan9303 *chip)
784 /* enable defining the destination port via special VLAN tagging
787 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
788 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
792 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
793 * able to discover their source port
795 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
796 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
799 /* We want a special working switch:
800 * - do not forward packets between port 1 and 2
801 * - forward everything from port 1 to port 0
802 * - forward everything from port 2 to port 0
804 static int lan9303_separate_ports(struct lan9303 *chip)
808 lan9303_alr_del_port(chip, eth_stp_addr, 0);
809 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
810 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
811 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
812 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
813 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
814 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
818 /* prevent port 1 and 2 from forwarding packets by their own */
819 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
820 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
821 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
822 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
825 static void lan9303_bridge_ports(struct lan9303 *chip)
827 /* ports bridged: remove mirroring */
828 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
829 LAN9303_SWE_PORT_MIRROR_DISABLED);
831 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
832 chip->swe_port_state);
833 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
836 static void lan9303_handle_reset(struct lan9303 *chip)
838 if (!chip->reset_gpio)
841 if (chip->reset_duration != 0)
842 msleep(chip->reset_duration);
844 /* release (deassert) reset and activate the device */
845 gpiod_set_value_cansleep(chip->reset_gpio, 0);
848 /* stop processing packets for all ports */
849 static int lan9303_disable_processing(struct lan9303 *chip)
853 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
854 int ret = lan9303_disable_processing_port(chip, p);
863 static int lan9303_check_device(struct lan9303 *chip)
868 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
870 dev_err(chip->dev, "failed to read chip revision register: %d\n",
875 if (((reg >> 16) != LAN9303_CHIP_ID) &&
876 ((reg >> 16) != LAN9354_CHIP_ID)) {
877 dev_err(chip->dev, "unexpected device found: LAN%4.4X\n",
882 /* The default state of the LAN9303 device is to forward packets between
883 * all ports (if not configured differently by an external EEPROM).
884 * The initial state of a DSA device must be forwarding packets only
885 * between the external and the internal ports and no forwarding
886 * between the external ports. In preparation we stop packet handling
887 * at all for now until the LAN9303 device is re-programmed accordingly.
889 ret = lan9303_disable_processing(chip);
891 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
893 dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff);
895 ret = lan9303_detect_phy_setup(chip);
898 "failed to discover phy bootstrap setup: %d\n", ret);
905 /* ---------------------------- DSA -----------------------------------*/
907 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
909 enum dsa_tag_protocol mp)
911 return DSA_TAG_PROTO_LAN9303;
914 static int lan9303_setup(struct dsa_switch *ds)
916 struct lan9303 *chip = ds->priv;
920 /* Make sure that port 0 is the cpu port */
921 if (!dsa_is_cpu_port(ds, 0)) {
922 dev_err(chip->dev, "port 0 is not the CPU port\n");
926 /* Virtual Phy: Remove Turbo 200Mbit mode */
927 ret = lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ®);
931 /* Clear the TURBO Mode bit if it was set. */
932 if (reg & LAN9303_VIRT_SPECIAL_TURBO) {
933 reg &= ~LAN9303_VIRT_SPECIAL_TURBO;
934 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, reg);
937 ret = lan9303_setup_tagging(chip);
939 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
941 ret = lan9303_separate_ports(chip);
943 dev_err(chip->dev, "failed to separate ports %d\n", ret);
945 ret = lan9303_enable_processing_port(chip, 0);
947 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
949 /* Trap IGMP to port 0 */
950 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
951 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
952 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
953 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
954 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
956 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
961 struct lan9303_mib_desc {
962 unsigned int offset; /* offset of first MAC */
966 static const struct lan9303_mib_desc lan9303_mib[] = {
967 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
968 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
969 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
970 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
971 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
972 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
973 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
974 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
975 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
976 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
977 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
978 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
979 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
980 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
981 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
982 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
983 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
984 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
985 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
986 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
987 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
988 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
989 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "RxShort", },
990 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
991 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
992 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
993 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
994 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
995 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
996 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
997 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
998 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
999 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
1000 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
1001 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
1002 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
1003 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
1006 static void lan9303_get_strings(struct dsa_switch *ds, int port,
1007 u32 stringset, uint8_t *data)
1011 if (stringset != ETH_SS_STATS)
1014 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1015 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
1020 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
1023 struct lan9303 *chip = ds->priv;
1026 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1030 ret = lan9303_read_switch_port(
1031 chip, port, lan9303_mib[u].offset, ®);
1034 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1035 port, lan9303_mib[u].offset);
1042 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
1044 if (sset != ETH_SS_STATS)
1047 return ARRAY_SIZE(lan9303_mib);
1050 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
1052 struct lan9303 *chip = ds->priv;
1053 int phy_base = chip->phy_addr_base;
1055 if (phy == phy_base)
1056 return lan9303_virt_phy_reg_read(chip, regnum);
1057 if (phy > phy_base + 2)
1060 return chip->ops->phy_read(chip, phy, regnum);
1063 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
1066 struct lan9303 *chip = ds->priv;
1067 int phy_base = chip->phy_addr_base;
1069 if (phy == phy_base)
1070 return lan9303_virt_phy_reg_write(chip, regnum, val);
1071 if (phy > phy_base + 2)
1074 return chip->ops->phy_write(chip, phy, regnum, val);
1077 static int lan9303_port_enable(struct dsa_switch *ds, int port,
1078 struct phy_device *phy)
1080 struct dsa_port *dp = dsa_to_port(ds, port);
1081 struct lan9303 *chip = ds->priv;
1083 if (!dsa_port_is_user(dp))
1086 vlan_vid_add(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1088 return lan9303_enable_processing_port(chip, port);
1091 static void lan9303_port_disable(struct dsa_switch *ds, int port)
1093 struct dsa_port *dp = dsa_to_port(ds, port);
1094 struct lan9303 *chip = ds->priv;
1096 if (!dsa_port_is_user(dp))
1099 vlan_vid_del(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1101 lan9303_disable_processing_port(chip, port);
1102 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
1105 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1106 struct dsa_bridge bridge,
1107 bool *tx_fwd_offload,
1108 struct netlink_ext_ack *extack)
1110 struct lan9303 *chip = ds->priv;
1112 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1113 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) {
1114 lan9303_bridge_ports(chip);
1115 chip->is_bridged = true; /* unleash stp_state_set() */
1121 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1122 struct dsa_bridge bridge)
1124 struct lan9303 *chip = ds->priv;
1126 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1127 if (chip->is_bridged) {
1128 lan9303_separate_ports(chip);
1129 chip->is_bridged = false;
1133 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1136 int portmask, portstate;
1137 struct lan9303 *chip = ds->priv;
1139 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1140 __func__, port, state);
1143 case BR_STATE_DISABLED:
1144 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1146 case BR_STATE_BLOCKING:
1147 case BR_STATE_LISTENING:
1148 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1150 case BR_STATE_LEARNING:
1151 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1153 case BR_STATE_FORWARDING:
1154 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1157 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1158 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1162 portmask = 0x3 << (port * 2);
1163 portstate <<= (port * 2);
1165 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1167 if (chip->is_bridged)
1168 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1169 chip->swe_port_state);
1170 /* else: touching SWE_PORT_STATE would break port separation */
1173 static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1175 struct lan9303 *chip = ds->priv;
1176 struct del_port_learned_ctx del_ctx = {
1180 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1181 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1184 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1185 const unsigned char *addr, u16 vid,
1188 struct lan9303 *chip = ds->priv;
1190 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1194 return lan9303_alr_add_port(chip, addr, port, false);
1197 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1198 const unsigned char *addr, u16 vid,
1201 struct lan9303 *chip = ds->priv;
1203 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1206 lan9303_alr_del_port(chip, addr, port);
1211 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1212 dsa_fdb_dump_cb_t *cb, void *data)
1214 struct lan9303 *chip = ds->priv;
1215 struct port_fdb_dump_ctx dump_ctx = {
1221 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1222 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1225 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1226 const struct switchdev_obj_port_mdb *mdb)
1228 struct lan9303 *chip = ds->priv;
1230 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1234 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1236 if (!lan9303_alr_cache_find_free(chip))
1242 static int lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1243 const struct switchdev_obj_port_mdb *mdb,
1246 struct lan9303 *chip = ds->priv;
1249 err = lan9303_port_mdb_prepare(ds, port, mdb);
1253 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1255 return lan9303_alr_add_port(chip, mdb->addr, port, false);
1258 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1259 const struct switchdev_obj_port_mdb *mdb,
1262 struct lan9303 *chip = ds->priv;
1264 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1268 lan9303_alr_del_port(chip, mdb->addr, port);
1273 static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port,
1274 struct phylink_config *config)
1276 struct lan9303 *chip = ds->priv;
1278 dev_dbg(chip->dev, "%s(%d) entered.", __func__, port);
1280 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
1284 __set_bit(PHY_INTERFACE_MODE_RMII,
1285 config->supported_interfaces);
1286 __set_bit(PHY_INTERFACE_MODE_MII,
1287 config->supported_interfaces);
1289 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1290 config->supported_interfaces);
1291 /* Compatibility for phylib's default interface type when the
1292 * phy-mode property is absent
1294 __set_bit(PHY_INTERFACE_MODE_GMII,
1295 config->supported_interfaces);
1298 /* This driver does not make use of the speed, duplex, pause or the
1299 * advertisement in its mac_config, so it is safe to mark this driver
1302 config->legacy_pre_march2020 = false;
1305 static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int port,
1307 phy_interface_t interface,
1308 struct phy_device *phydev, int speed,
1309 int duplex, bool tx_pause,
1312 struct lan9303 *chip = ds->priv;
1316 /* On this device, we are only interested in doing something here if
1317 * this is the xMII port. All other ports are 10/100 phys using MDIO
1318 * to control there link settings.
1320 if (!IS_PORT_XMII(port))
1323 /* Disable auto-negotiation and force the speed/duplex settings. */
1324 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1325 ctl &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1326 if (speed == SPEED_100)
1327 ctl |= BMCR_SPEED100;
1328 if (duplex == DUPLEX_FULL)
1329 ctl |= BMCR_FULLDPLX;
1330 lan9303_phy_write(ds, port, MII_BMCR, ctl);
1332 /* Force the flow control settings. */
1333 lan9303_read(chip->regmap, flow_ctl_reg[port], ®);
1334 reg &= ~(LAN9303_BP_EN | LAN9303_RX_FC_EN | LAN9303_TX_FC_EN);
1336 reg |= (LAN9303_RX_FC_EN | LAN9303_BP_EN);
1338 reg |= LAN9303_TX_FC_EN;
1339 regmap_write(chip->regmap, flow_ctl_reg[port], reg);
1342 static const struct dsa_switch_ops lan9303_switch_ops = {
1343 .get_tag_protocol = lan9303_get_tag_protocol,
1344 .setup = lan9303_setup,
1345 .get_strings = lan9303_get_strings,
1346 .phy_read = lan9303_phy_read,
1347 .phy_write = lan9303_phy_write,
1348 .phylink_get_caps = lan9303_phylink_get_caps,
1349 .phylink_mac_link_up = lan9303_phylink_mac_link_up,
1350 .get_ethtool_stats = lan9303_get_ethtool_stats,
1351 .get_sset_count = lan9303_get_sset_count,
1352 .port_enable = lan9303_port_enable,
1353 .port_disable = lan9303_port_disable,
1354 .port_bridge_join = lan9303_port_bridge_join,
1355 .port_bridge_leave = lan9303_port_bridge_leave,
1356 .port_stp_state_set = lan9303_port_stp_state_set,
1357 .port_fast_age = lan9303_port_fast_age,
1358 .port_fdb_add = lan9303_port_fdb_add,
1359 .port_fdb_del = lan9303_port_fdb_del,
1360 .port_fdb_dump = lan9303_port_fdb_dump,
1361 .port_mdb_add = lan9303_port_mdb_add,
1362 .port_mdb_del = lan9303_port_mdb_del,
1365 static int lan9303_register_switch(struct lan9303 *chip)
1369 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL);
1373 chip->ds->dev = chip->dev;
1374 chip->ds->num_ports = LAN9303_NUM_PORTS;
1375 chip->ds->priv = chip;
1376 chip->ds->ops = &lan9303_switch_ops;
1377 base = chip->phy_addr_base;
1378 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
1380 return dsa_register_switch(chip->ds);
1383 static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1384 struct device_node *np)
1386 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1388 if (IS_ERR(chip->reset_gpio))
1389 return PTR_ERR(chip->reset_gpio);
1391 if (!chip->reset_gpio) {
1392 dev_dbg(chip->dev, "No reset GPIO defined\n");
1396 chip->reset_duration = 200;
1399 of_property_read_u32(np, "reset-duration",
1400 &chip->reset_duration);
1402 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1405 /* A sane reset duration should not be longer than 1s */
1406 if (chip->reset_duration > 1000)
1407 chip->reset_duration = 1000;
1412 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1417 mutex_init(&chip->indirect_mutex);
1418 mutex_init(&chip->alr_mutex);
1420 ret = lan9303_probe_reset_gpio(chip, np);
1424 lan9303_handle_reset(chip);
1426 /* First read to the device. This is a Dummy read to ensure MDIO */
1427 /* access is in 32-bit sync. */
1428 ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, ®);
1430 dev_err(chip->dev, "failed to access the device: %d\n",
1432 if (!chip->reset_gpio) {
1434 "hint: maybe failed due to missing reset GPIO\n");
1439 ret = lan9303_check_device(chip);
1443 ret = lan9303_register_switch(chip);
1445 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1451 EXPORT_SYMBOL(lan9303_probe);
1453 int lan9303_remove(struct lan9303 *chip)
1457 rc = lan9303_disable_processing(chip);
1459 dev_warn(chip->dev, "shutting down failed\n");
1461 dsa_unregister_switch(chip->ds);
1463 /* assert reset to the whole device to prevent it from doing anything */
1464 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1465 gpiod_unexport(chip->reset_gpio);
1469 EXPORT_SYMBOL(lan9303_remove);
1471 void lan9303_shutdown(struct lan9303 *chip)
1473 dsa_switch_shutdown(chip->ds);
1475 EXPORT_SYMBOL(lan9303_shutdown);
1477 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1478 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1479 MODULE_LICENSE("GPL v2");