drivers/net/dsa/hirschmann/hellcreek.h

   1 /* SPDX-License-Identifier: (GPL-2.0 or MIT) */
   2 /*
   3  * DSA driver for:
   4  * Hirschmann Hellcreek TSN switch.
   5  *
   6  * Copyright (C) 2019-2021 Linutronix GmbH
   7  * Author Kurt Kanzenbach <kurt@linutronix.de>
   8  */
   9
  10 #ifndef _HELLCREEK_H_
  11 #define _HELLCREEK_H_
  12
  13 #include <linux/bitmap.h>
  14 #include <linux/bitops.h>
  15 #include <linux/device.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mutex.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/leds.h>
  20 #include <linux/platform_data/hirschmann-hellcreek.h>
  21 #include <linux/ptp_clock_kernel.h>
  22 #include <linux/timecounter.h>
  23 #include <net/dsa.h>
  24 #include <net/pkt_sched.h>
  25
  26 /* Ports:
  27  *  - 0: CPU
  28  *  - 1: Tunnel
  29  *  - 2: TSN front port 1
  30  *  - 3: TSN front port 2
  31  *  - ...
  32  */
  33 #define CPU_PORT                        0
  34 #define TUNNEL_PORT                     1
  35
  36 #define HELLCREEK_VLAN_NO_MEMBER        0x0
  37 #define HELLCREEK_VLAN_UNTAGGED_MEMBER  0x1
  38 #define HELLCREEK_VLAN_TAGGED_MEMBER    0x3
  39 #define HELLCREEK_NUM_EGRESS_QUEUES     8
  40
  41 /* Register definitions */
  42 #define HR_MODID_C                      (0 * 2)
  43 #define HR_REL_L_C                      (1 * 2)
  44 #define HR_REL_H_C                      (2 * 2)
  45 #define HR_BLD_L_C                      (3 * 2)
  46 #define HR_BLD_H_C                      (4 * 2)
  47 #define HR_CTRL_C                       (5 * 2)
  48 #define HR_CTRL_C_READY                 BIT(14)
  49 #define HR_CTRL_C_TRANSITION            BIT(13)
  50 #define HR_CTRL_C_ENABLE                BIT(0)
  51
  52 #define HR_PSEL                         (0xa6 * 2)
  53 #define HR_PSEL_PTWSEL_SHIFT            4
  54 #define HR_PSEL_PTWSEL_MASK             GENMASK(5, 4)
  55 #define HR_PSEL_PRTCWSEL_SHIFT          0
  56 #define HR_PSEL_PRTCWSEL_MASK           GENMASK(2, 0)
  57
  58 #define HR_PTCFG                        (0xa7 * 2)
  59 #define HR_PTCFG_MLIMIT_EN              BIT(13)
  60 #define HR_PTCFG_UMC_FLT                BIT(10)
  61 #define HR_PTCFG_UUC_FLT                BIT(9)
  62 #define HR_PTCFG_UNTRUST                BIT(8)
  63 #define HR_PTCFG_TAG_REQUIRED           BIT(7)
  64 #define HR_PTCFG_PPRIO_SHIFT            4
  65 #define HR_PTCFG_PPRIO_MASK             GENMASK(6, 4)
  66 #define HR_PTCFG_INGRESSFLT             BIT(3)
  67 #define HR_PTCFG_BLOCKED                BIT(2)
  68 #define HR_PTCFG_LEARNING_EN            BIT(1)
  69 #define HR_PTCFG_ADMIN_EN               BIT(0)
  70
  71 #define HR_PRTCCFG                      (0xa8 * 2)
  72 #define HR_PRTCCFG_PCP_TC_MAP_SHIFT     0
  73 #define HR_PRTCCFG_PCP_TC_MAP_MASK      GENMASK(2, 0)
  74
  75 #define HR_CSEL                         (0x8d * 2)
  76 #define HR_CSEL_SHIFT                   0
  77 #define HR_CSEL_MASK                    GENMASK(7, 0)
  78 #define HR_CRDL                         (0x8e * 2)
  79 #define HR_CRDH                         (0x8f * 2)
  80
  81 #define HR_SWTRC_CFG                    (0x90 * 2)
  82 #define HR_SWTRC0                       (0x91 * 2)
  83 #define HR_SWTRC1                       (0x92 * 2)
  84 #define HR_PFREE                        (0x93 * 2)
  85 #define HR_MFREE                        (0x94 * 2)
  86
  87 #define HR_FDBAGE                       (0x97 * 2)
  88 #define HR_FDBMAX                       (0x98 * 2)
  89 #define HR_FDBRDL                       (0x99 * 2)
  90 #define HR_FDBRDM                       (0x9a * 2)
  91 #define HR_FDBRDH                       (0x9b * 2)
  92
  93 #define HR_FDBMDRD                      (0x9c * 2)
  94 #define HR_FDBMDRD_PORTMASK_SHIFT       0
  95 #define HR_FDBMDRD_PORTMASK_MASK        GENMASK(3, 0)
  96 #define HR_FDBMDRD_AGE_SHIFT            4
  97 #define HR_FDBMDRD_AGE_MASK             GENMASK(7, 4)
  98 #define HR_FDBMDRD_OBT                  BIT(8)
  99 #define HR_FDBMDRD_PASS_BLOCKED         BIT(9)
 100 #define HR_FDBMDRD_STATIC               BIT(11)
 101 #define HR_FDBMDRD_REPRIO_TC_SHIFT      12
 102 #define HR_FDBMDRD_REPRIO_TC_MASK       GENMASK(14, 12)
 103 #define HR_FDBMDRD_REPRIO_EN            BIT(15)
 104
 105 #define HR_FDBWDL                       (0x9d * 2)
 106 #define HR_FDBWDM                       (0x9e * 2)
 107 #define HR_FDBWDH                       (0x9f * 2)
 108 #define HR_FDBWRM0                      (0xa0 * 2)
 109 #define HR_FDBWRM0_PORTMASK_SHIFT       0
 110 #define HR_FDBWRM0_PORTMASK_MASK        GENMASK(3, 0)
 111 #define HR_FDBWRM0_OBT                  BIT(8)
 112 #define HR_FDBWRM0_PASS_BLOCKED         BIT(9)
 113 #define HR_FDBWRM0_REPRIO_TC_SHIFT      12
 114 #define HR_FDBWRM0_REPRIO_TC_MASK       GENMASK(14, 12)
 115 #define HR_FDBWRM0_REPRIO_EN            BIT(15)
 116 #define HR_FDBWRM1                      (0xa1 * 2)
 117
 118 #define HR_FDBWRCMD                     (0xa2 * 2)
 119 #define HR_FDBWRCMD_FDBDEL              BIT(9)
 120
 121 #define HR_SWCFG                        (0xa3 * 2)
 122 #define HR_SWCFG_GM_STATEMD             BIT(15)
 123 #define HR_SWCFG_LAS_MODE_SHIFT         12
 124 #define HR_SWCFG_LAS_MODE_MASK          GENMASK(13, 12)
 125 #define HR_SWCFG_LAS_OFF                (0x00)
 126 #define HR_SWCFG_LAS_ON                 (0x01)
 127 #define HR_SWCFG_LAS_STATIC             (0x10)
 128 #define HR_SWCFG_CT_EN                  BIT(11)
 129 #define HR_SWCFG_VLAN_UNAWARE           BIT(10)
 130 #define HR_SWCFG_ALWAYS_OBT             BIT(9)
 131 #define HR_SWCFG_FDBAGE_EN              BIT(5)
 132 #define HR_SWCFG_FDBLRN_EN              BIT(4)
 133
 134 #define HR_SWSTAT                       (0xa4 * 2)
 135 #define HR_SWSTAT_FAIL                  BIT(4)
 136 #define HR_SWSTAT_BUSY                  BIT(0)
 137
 138 #define HR_SWCMD                        (0xa5 * 2)
 139 #define HW_SWCMD_FLUSH                  BIT(0)
 140
 141 #define HR_VIDCFG                       (0xaa * 2)
 142 #define HR_VIDCFG_VID_SHIFT             0
 143 #define HR_VIDCFG_VID_MASK              GENMASK(11, 0)
 144 #define HR_VIDCFG_PVID                  BIT(12)
 145
 146 #define HR_VIDMBRCFG                    (0xab * 2)
 147 #define HR_VIDMBRCFG_P0MBR_SHIFT        0
 148 #define HR_VIDMBRCFG_P0MBR_MASK         GENMASK(1, 0)
 149 #define HR_VIDMBRCFG_P1MBR_SHIFT        2
 150 #define HR_VIDMBRCFG_P1MBR_MASK         GENMASK(3, 2)
 151 #define HR_VIDMBRCFG_P2MBR_SHIFT        4
 152 #define HR_VIDMBRCFG_P2MBR_MASK         GENMASK(5, 4)
 153 #define HR_VIDMBRCFG_P3MBR_SHIFT        6
 154 #define HR_VIDMBRCFG_P3MBR_MASK         GENMASK(7, 6)
 155
 156 #define HR_FEABITS0                     (0xac * 2)
 157 #define HR_FEABITS0_FDBBINS_SHIFT       4
 158 #define HR_FEABITS0_FDBBINS_MASK        GENMASK(7, 4)
 159 #define HR_FEABITS0_PCNT_SHIFT          8
 160 #define HR_FEABITS0_PCNT_MASK           GENMASK(11, 8)
 161 #define HR_FEABITS0_MCNT_SHIFT          12
 162 #define HR_FEABITS0_MCNT_MASK           GENMASK(15, 12)
 163
 164 #define TR_QTRACK                       (0xb1 * 2)
 165 #define TR_TGDVER                       (0xb3 * 2)
 166 #define TR_TGDVER_REV_MIN_MASK          GENMASK(7, 0)
 167 #define TR_TGDVER_REV_MIN_SHIFT         0
 168 #define TR_TGDVER_REV_MAJ_MASK          GENMASK(15, 8)
 169 #define TR_TGDVER_REV_MAJ_SHIFT         8
 170 #define TR_TGDSEL                       (0xb4 * 2)
 171 #define TR_TGDSEL_TDGSEL_MASK           GENMASK(1, 0)
 172 #define TR_TGDSEL_TDGSEL_SHIFT          0
 173 #define TR_TGDCTRL                      (0xb5 * 2)
 174 #define TR_TGDCTRL_GATE_EN              BIT(0)
 175 #define TR_TGDCTRL_CYC_SNAP             BIT(4)
 176 #define TR_TGDCTRL_SNAP_EST             BIT(5)
 177 #define TR_TGDCTRL_ADMINGATESTATES_MASK GENMASK(15, 8)
 178 #define TR_TGDCTRL_ADMINGATESTATES_SHIFT        8
 179 #define TR_TGDSTAT0                     (0xb6 * 2)
 180 #define TR_TGDSTAT1                     (0xb7 * 2)
 181 #define TR_ESTWRL                       (0xb8 * 2)
 182 #define TR_ESTWRH                       (0xb9 * 2)
 183 #define TR_ESTCMD                       (0xba * 2)
 184 #define TR_ESTCMD_ESTSEC_MASK           GENMASK(2, 0)
 185 #define TR_ESTCMD_ESTSEC_SHIFT          0
 186 #define TR_ESTCMD_ESTARM                BIT(4)
 187 #define TR_ESTCMD_ESTSWCFG              BIT(5)
 188 #define TR_EETWRL                       (0xbb * 2)
 189 #define TR_EETWRH                       (0xbc * 2)
 190 #define TR_EETCMD                       (0xbd * 2)
 191 #define TR_EETCMD_EETSEC_MASK           GEMASK(2, 0)
 192 #define TR_EETCMD_EETSEC_SHIFT          0
 193 #define TR_EETCMD_EETARM                BIT(4)
 194 #define TR_CTWRL                        (0xbe * 2)
 195 #define TR_CTWRH                        (0xbf * 2)
 196 #define TR_LCNSL                        (0xc1 * 2)
 197 #define TR_LCNSH                        (0xc2 * 2)
 198 #define TR_LCS                          (0xc3 * 2)
 199 #define TR_GCLDAT                       (0xc4 * 2)
 200 #define TR_GCLDAT_GCLWRGATES_MASK       GENMASK(7, 0)
 201 #define TR_GCLDAT_GCLWRGATES_SHIFT      0
 202 #define TR_GCLDAT_GCLWRLAST             BIT(8)
 203 #define TR_GCLDAT_GCLOVRI               BIT(9)
 204 #define TR_GCLTIL                       (0xc5 * 2)
 205 #define TR_GCLTIH                       (0xc6 * 2)
 206 #define TR_GCLCMD                       (0xc7 * 2)
 207 #define TR_GCLCMD_GCLWRADR_MASK         GENMASK(7, 0)
 208 #define TR_GCLCMD_GCLWRADR_SHIFT        0
 209 #define TR_GCLCMD_INIT_GATE_STATES_MASK GENMASK(15, 8)
 210 #define TR_GCLCMD_INIT_GATE_STATES_SHIFT        8
 211
 212 struct hellcreek_counter {
 213         u8 offset;
 214         const char *name;
 215 };
 216
 217 struct hellcreek;
 218
 219 /* State flags for hellcreek_port_hwtstamp::state */
 220 enum {
 221         HELLCREEK_HWTSTAMP_ENABLED,
 222         HELLCREEK_HWTSTAMP_TX_IN_PROGRESS,
 223 };
 224
 225 /* A structure to hold hardware timestamping information per port */
 226 struct hellcreek_port_hwtstamp {
 227         /* Timestamping state */
 228         unsigned long state;
 229
 230         /* Resources for receive timestamping */
 231         struct sk_buff_head rx_queue; /* For synchronization messages */
 232
 233         /* Resources for transmit timestamping */
 234         unsigned long tx_tstamp_start;
 235         struct sk_buff *tx_skb;
 236
 237         /* Current timestamp configuration */
 238         struct hwtstamp_config tstamp_config;
 239 };
 240
 241 struct hellcreek_port {
 242         struct hellcreek *hellcreek;
 243         unsigned long *vlan_dev_bitmap;
 244         int port;
 245         u16 ptcfg;              /* ptcfg shadow */
 246         u64 *counter_values;
 247
 248         /* Per-port timestamping resources */
 249         struct hellcreek_port_hwtstamp port_hwtstamp;
 250
 251         /* Per-port Qbv schedule information */
 252         struct tc_taprio_qopt_offload *current_schedule;
 253         struct delayed_work schedule_work;
 254 };
 255
 256 struct hellcreek_fdb_entry {
 257         size_t idx;
 258         unsigned char mac[ETH_ALEN];
 259         u8 portmask;
 260         u8 age;
 261         u8 is_obt;
 262         u8 pass_blocked;
 263         u8 is_static;
 264         u8 reprio_tc;
 265         u8 reprio_en;
 266 };
 267
 268 struct hellcreek {
 269         const struct hellcreek_platform_data *pdata;
 270         struct device *dev;
 271         struct dsa_switch *ds;
 272         struct ptp_clock *ptp_clock;
 273         struct ptp_clock_info ptp_clock_info;
 274         struct hellcreek_port *ports;
 275         struct delayed_work overflow_work;
 276         struct led_classdev led_is_gm;
 277         struct led_classdev led_sync_good;
 278         struct mutex reg_lock;  /* Switch IP register lock */
 279         struct mutex vlan_lock; /* VLAN bitmaps lock */
 280         struct mutex ptp_lock;  /* PTP IP register lock */
 281         struct devlink_region *vlan_region;
 282         struct devlink_region *fdb_region;
 283         void __iomem *base;
 284         void __iomem *ptp_base;
 285         u16 swcfg;              /* swcfg shadow */
 286         u8 *vidmbrcfg;          /* vidmbrcfg shadow */
 287         u64 seconds;            /* PTP seconds */
 288         u64 last_ts;            /* Used for overflow detection */
 289         u16 status_out;         /* ptp.status_out shadow */
 290         size_t fdb_entries;
 291 };
 292
 293 /* A Qbv schedule can only started up to 8 seconds in the future. If the delta
 294  * between the base time and the current ptp time is larger than 8 seconds, then
 295  * use periodic work to check for the schedule to be started. The delayed work
 296  * cannot be armed directly to $base_time - 8 + X, because for large deltas the
 297  * PTP frequency matters.
 298  */
 299 #define HELLCREEK_SCHEDULE_PERIOD       (2 * HZ)
 300 #define dw_to_hellcreek_port(dw)                                \
 301         container_of(dw, struct hellcreek_port, schedule_work)
 302
 303 /* Devlink resources */
 304 enum hellcreek_devlink_resource_id {
 305         HELLCREEK_DEVLINK_PARAM_ID_VLAN_TABLE,
 306         HELLCREEK_DEVLINK_PARAM_ID_FDB_TABLE,
 307 };
 308
 309 struct hellcreek_devlink_vlan_entry {
 310         u16 vid;
 311         u16 member;
 312 };
 313
 314 #endif /* _HELLCREEK_H_ */