1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom Starfighter 2 DSA switch driver
5 * Copyright (C) 2014, Broadcom Corporation
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/of_net.h>
21 #include <linux/of_mdio.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_bridge.h>
25 #include <linux/brcmphy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/platform_data/b53.h>
30 #include "bcm_sf2_regs.h"
31 #include "b53/b53_priv.h"
32 #include "b53/b53_regs.h"
34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
40 if (priv->type == BCM7445_DEVICE_ID)
41 offset = CORE_STS_OVERRIDE_IMP;
43 offset = CORE_STS_OVERRIDE_IMP2;
45 /* Enable the port memories */
46 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
47 reg &= ~P_TXQ_PSM_VDD(port);
48 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
50 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
51 reg = core_readl(priv, CORE_IMP_CTL);
52 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
53 reg &= ~(RX_DIS | TX_DIS);
54 core_writel(priv, reg, CORE_IMP_CTL);
56 /* Enable forwarding */
57 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
59 /* Enable IMP port in dumb mode */
60 reg = core_readl(priv, CORE_SWITCH_CTRL);
61 reg |= MII_DUMB_FWDG_EN;
62 core_writel(priv, reg, CORE_SWITCH_CTRL);
64 /* Configure Traffic Class to QoS mapping, allow each priority to map
65 * to a different queue number
67 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
68 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
69 reg |= i << (PRT_TO_QID_SHIFT * i);
70 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
72 b53_brcm_hdr_setup(ds, port);
74 /* Force link status for IMP port */
75 reg = core_readl(priv, offset);
76 reg |= (MII_SW_OR | LINK_STS);
77 core_writel(priv, reg, offset);
80 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
82 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
85 reg = reg_readl(priv, REG_SPHY_CNTRL);
88 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
89 reg_writel(priv, reg, REG_SPHY_CNTRL);
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
94 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
99 reg_writel(priv, reg, REG_SPHY_CNTRL);
101 /* Use PHY-driven LED signaling */
103 reg = reg_readl(priv, REG_LED_CNTRL(0));
104 reg |= SPDLNK_SRC_SEL;
105 reg_writel(priv, reg, REG_LED_CNTRL(0));
109 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
119 /* Port 0 interrupts are located on the first bank */
120 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
123 off = P_IRQ_OFF(port);
127 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
130 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
140 /* Port 0 interrupts are located on the first bank */
141 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
142 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
145 off = P_IRQ_OFF(port);
149 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
150 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
153 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
154 struct phy_device *phy)
156 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
160 /* Clear the memory power down */
161 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
162 reg &= ~P_TXQ_PSM_VDD(port);
163 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
165 /* Enable learning */
166 reg = core_readl(priv, CORE_DIS_LEARN);
168 core_writel(priv, reg, CORE_DIS_LEARN);
170 /* Enable Broadcom tags for that port if requested */
171 if (priv->brcm_tag_mask & BIT(port))
172 b53_brcm_hdr_setup(ds, port);
174 /* Configure Traffic Class to QoS mapping, allow each priority to map
175 * to a different queue number
177 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
178 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
179 reg |= i << (PRT_TO_QID_SHIFT * i);
180 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
182 /* Re-enable the GPHY and re-apply workarounds */
183 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
184 bcm_sf2_gphy_enable_set(ds, true);
186 /* if phy_stop() has been called before, phy
187 * will be in halted state, and phy_start()
190 * the resume path does not configure back
191 * autoneg settings, and since we hard reset
192 * the phy manually here, we need to reset the
193 * state machine also.
195 phy->state = PHY_READY;
200 /* Enable MoCA port interrupts to get notified */
201 if (port == priv->moca_port)
202 bcm_sf2_port_intr_enable(priv, port);
204 /* Set per-queue pause threshold to 32 */
205 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
207 /* Set ACB threshold to 24 */
208 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
209 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
210 SF2_NUM_EGRESS_QUEUES + i));
211 reg &= ~XOFF_THRESHOLD_MASK;
213 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
214 SF2_NUM_EGRESS_QUEUES + i));
217 return b53_enable_port(ds, port, phy);
220 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
222 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
225 /* Disable learning while in WoL mode */
226 if (priv->wol_ports_mask & (1 << port)) {
227 reg = core_readl(priv, CORE_DIS_LEARN);
229 core_writel(priv, reg, CORE_DIS_LEARN);
233 if (port == priv->moca_port)
234 bcm_sf2_port_intr_disable(priv, port);
236 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
237 bcm_sf2_gphy_enable_set(ds, false);
239 b53_disable_port(ds, port);
241 /* Power down the port memory */
242 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
243 reg |= P_TXQ_PSM_VDD(port);
244 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
248 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
254 reg = reg_readl(priv, REG_SWITCH_CNTRL);
255 reg |= MDIO_MASTER_SEL;
256 reg_writel(priv, reg, REG_SWITCH_CNTRL);
258 /* Page << 8 | offset */
261 core_writel(priv, addr, reg);
263 /* Page << 8 | offset */
264 reg = 0x80 << 8 | regnum << 1;
268 ret = core_readl(priv, reg);
270 core_writel(priv, val, reg);
272 reg = reg_readl(priv, REG_SWITCH_CNTRL);
273 reg &= ~MDIO_MASTER_SEL;
274 reg_writel(priv, reg, REG_SWITCH_CNTRL);
279 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
281 struct bcm_sf2_priv *priv = bus->priv;
283 /* Intercept reads from Broadcom pseudo-PHY address, else, send
284 * them to our master MDIO bus controller
286 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
287 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
289 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
292 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
295 struct bcm_sf2_priv *priv = bus->priv;
297 /* Intercept writes to the Broadcom pseudo-PHY address, else,
298 * send them to our master MDIO bus controller
300 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
301 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
303 return mdiobus_write_nested(priv->master_mii_bus, addr,
307 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
309 struct dsa_switch *ds = dev_id;
310 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
312 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
314 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
319 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
321 struct dsa_switch *ds = dev_id;
322 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
324 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
326 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
328 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
329 priv->port_sts[7].link = true;
330 dsa_port_phylink_mac_change(ds, 7, true);
332 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
333 priv->port_sts[7].link = false;
334 dsa_port_phylink_mac_change(ds, 7, false);
340 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
342 unsigned int timeout = 1000;
345 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
346 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
347 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
350 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
351 if (!(reg & SOFTWARE_RESET))
354 usleep_range(1000, 2000);
355 } while (timeout-- > 0);
363 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
365 intrl2_0_mask_set(priv, 0xffffffff);
366 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
367 intrl2_1_mask_set(priv, 0xffffffff);
368 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
371 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
372 struct device_node *dn)
374 struct device_node *port;
376 unsigned int port_num;
378 priv->moca_port = -1;
380 for_each_available_child_of_node(dn, port) {
381 if (of_property_read_u32(port, "reg", &port_num))
384 /* Internal PHYs get assigned a specific 'phy-mode' property
385 * value: "internal" to help flag them before MDIO probing
386 * has completed, since they might be turned off at that
389 mode = of_get_phy_mode(port);
393 if (mode == PHY_INTERFACE_MODE_INTERNAL)
394 priv->int_phy_mask |= 1 << port_num;
396 if (mode == PHY_INTERFACE_MODE_MOCA)
397 priv->moca_port = port_num;
399 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
400 priv->brcm_tag_mask |= 1 << port_num;
404 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
406 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
407 struct device_node *dn;
411 /* Find our integrated MDIO bus node */
412 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
413 priv->master_mii_bus = of_mdio_find_bus(dn);
414 if (!priv->master_mii_bus)
415 return -EPROBE_DEFER;
417 get_device(&priv->master_mii_bus->dev);
418 priv->master_mii_dn = dn;
420 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
421 if (!priv->slave_mii_bus)
424 priv->slave_mii_bus->priv = priv;
425 priv->slave_mii_bus->name = "sf2 slave mii";
426 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
427 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
428 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
430 priv->slave_mii_bus->dev.of_node = dn;
432 /* Include the pseudo-PHY address to divert reads towards our
433 * workaround. This is only required for 7445D0, since 7445E0
434 * disconnects the internal switch pseudo-PHY such that we can use the
435 * regular SWITCH_MDIO master controller instead.
437 * Here we flag the pseudo PHY as needing special treatment and would
438 * otherwise make all other PHY read/writes go to the master MDIO bus
439 * controller that comes with this switch backed by the "mdio-unimac"
442 if (of_machine_is_compatible("brcm,bcm7445d0"))
443 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
445 priv->indir_phy_mask = 0;
447 ds->phys_mii_mask = priv->indir_phy_mask;
448 ds->slave_mii_bus = priv->slave_mii_bus;
449 priv->slave_mii_bus->parent = ds->dev->parent;
450 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
452 err = of_mdiobus_register(priv->slave_mii_bus, dn);
459 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
461 mdiobus_unregister(priv->slave_mii_bus);
462 of_node_put(priv->master_mii_dn);
465 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
467 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
469 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
470 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
471 * the REG_PHY_REVISION register layout is.
474 return priv->hw_params.gphy_rev;
477 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
478 unsigned long *supported,
479 struct phylink_link_state *state)
481 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
482 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
484 if (!phy_interface_mode_is_rgmii(state->interface) &&
485 state->interface != PHY_INTERFACE_MODE_MII &&
486 state->interface != PHY_INTERFACE_MODE_REVMII &&
487 state->interface != PHY_INTERFACE_MODE_GMII &&
488 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
489 state->interface != PHY_INTERFACE_MODE_MOCA) {
490 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
491 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
493 "Unsupported interface: %d for port %d\n",
494 state->interface, port);
498 /* Allow all the expected bits */
499 phylink_set(mask, Autoneg);
500 phylink_set_port_modes(mask);
501 phylink_set(mask, Pause);
502 phylink_set(mask, Asym_Pause);
504 /* With the exclusion of MII and Reverse MII, we support Gigabit,
505 * including Half duplex
507 if (state->interface != PHY_INTERFACE_MODE_MII &&
508 state->interface != PHY_INTERFACE_MODE_REVMII) {
509 phylink_set(mask, 1000baseT_Full);
510 phylink_set(mask, 1000baseT_Half);
513 phylink_set(mask, 10baseT_Half);
514 phylink_set(mask, 10baseT_Full);
515 phylink_set(mask, 100baseT_Half);
516 phylink_set(mask, 100baseT_Full);
518 bitmap_and(supported, supported, mask,
519 __ETHTOOL_LINK_MODE_MASK_NBITS);
520 bitmap_and(state->advertising, state->advertising, mask,
521 __ETHTOOL_LINK_MODE_MASK_NBITS);
524 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
526 const struct phylink_link_state *state)
528 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
529 u32 id_mode_dis = 0, port_mode;
532 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
535 if (priv->type == BCM7445_DEVICE_ID)
536 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
538 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
540 switch (state->interface) {
541 case PHY_INTERFACE_MODE_RGMII:
544 case PHY_INTERFACE_MODE_RGMII_TXID:
545 port_mode = EXT_GPHY;
547 case PHY_INTERFACE_MODE_MII:
548 port_mode = EXT_EPHY;
550 case PHY_INTERFACE_MODE_REVMII:
551 port_mode = EXT_REVMII;
554 /* all other PHYs: internal and MoCA */
558 /* Clear id_mode_dis bit, and the existing port mode, let
559 * RGMII_MODE_EN bet set by mac_link_{up,down}
561 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
563 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
564 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
570 if (state->pause & MLO_PAUSE_TXRX_MASK) {
571 if (state->pause & MLO_PAUSE_TX)
576 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
579 /* Force link settings detected from the PHY */
581 switch (state->speed) {
583 reg |= SPDSTS_1000 << SPEED_SHIFT;
586 reg |= SPDSTS_100 << SPEED_SHIFT;
592 if (state->duplex == DUPLEX_FULL)
595 core_writel(priv, reg, offset);
598 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
599 phy_interface_t interface, bool link)
601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
604 if (!phy_interface_mode_is_rgmii(interface) &&
605 interface != PHY_INTERFACE_MODE_MII &&
606 interface != PHY_INTERFACE_MODE_REVMII)
609 /* If the link is down, just disable the interface to conserve power */
610 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
612 reg |= RGMII_MODE_EN;
614 reg &= ~RGMII_MODE_EN;
615 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
618 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
620 phy_interface_t interface)
622 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
625 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
627 phy_interface_t interface,
628 struct phy_device *phydev)
630 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
631 struct ethtool_eee *p = &priv->dev->ports[port].eee;
633 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
635 if (mode == MLO_AN_PHY && phydev)
636 p->eee_enabled = b53_eee_init(ds, port, phydev);
639 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
640 struct phylink_link_state *status)
642 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
644 status->link = false;
646 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
647 * which means that we need to force the link at the port override
648 * level to get the data to flow. We do use what the interrupt handler
649 * did determine before.
651 * For the other ports, we just force the link status, since this is
652 * a fixed PHY device.
654 if (port == priv->moca_port) {
655 status->link = priv->port_sts[port].link;
656 /* For MoCA interfaces, also force a link down notification
657 * since some version of the user-space daemon (mocad) use
658 * cmd->autoneg to force the link, which messes up the PHY
659 * state machine and make it go in PHY_FORCING state instead.
662 netif_carrier_off(ds->ports[port].slave);
663 status->duplex = DUPLEX_FULL;
669 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
671 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
674 /* Enable ACB globally */
675 reg = acb_readl(priv, ACB_CONTROL);
676 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
677 acb_writel(priv, reg, ACB_CONTROL);
678 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
679 reg |= ACB_EN | ACB_ALGORITHM;
680 acb_writel(priv, reg, ACB_CONTROL);
683 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
685 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
688 bcm_sf2_intr_disable(priv);
690 /* Disable all ports physically present including the IMP
691 * port, the other ones have already been disabled during
694 for (port = 0; port < ds->num_ports; port++) {
695 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
696 bcm_sf2_port_disable(ds, port);
702 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
707 ret = bcm_sf2_sw_rst(priv);
709 pr_err("%s: failed to software reset switch\n", __func__);
713 ret = bcm_sf2_cfp_resume(ds);
717 if (priv->hw_params.num_gphy == 1)
718 bcm_sf2_gphy_enable_set(ds, true);
725 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
726 struct ethtool_wolinfo *wol)
728 struct net_device *p = ds->ports[port].cpu_dp->master;
729 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
730 struct ethtool_wolinfo pwol = { };
732 /* Get the parent device WoL settings */
733 if (p->ethtool_ops->get_wol)
734 p->ethtool_ops->get_wol(p, &pwol);
736 /* Advertise the parent device supported settings */
737 wol->supported = pwol.supported;
738 memset(&wol->sopass, 0, sizeof(wol->sopass));
740 if (pwol.wolopts & WAKE_MAGICSECURE)
741 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
743 if (priv->wol_ports_mask & (1 << port))
744 wol->wolopts = pwol.wolopts;
749 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
750 struct ethtool_wolinfo *wol)
752 struct net_device *p = ds->ports[port].cpu_dp->master;
753 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
754 s8 cpu_port = ds->ports[port].cpu_dp->index;
755 struct ethtool_wolinfo pwol = { };
757 if (p->ethtool_ops->get_wol)
758 p->ethtool_ops->get_wol(p, &pwol);
759 if (wol->wolopts & ~pwol.supported)
763 priv->wol_ports_mask |= (1 << port);
765 priv->wol_ports_mask &= ~(1 << port);
767 /* If we have at least one port enabled, make sure the CPU port
768 * is also enabled. If the CPU port is the last one enabled, we disable
769 * it since this configuration does not make sense.
771 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
772 priv->wol_ports_mask |= (1 << cpu_port);
774 priv->wol_ports_mask &= ~(1 << cpu_port);
776 return p->ethtool_ops->set_wol(p, wol);
779 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
781 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
784 /* Enable all valid ports and disable those unused */
785 for (port = 0; port < priv->hw_params.num_ports; port++) {
786 /* IMP port receives special treatment */
787 if (dsa_is_user_port(ds, port))
788 bcm_sf2_port_setup(ds, port, NULL);
789 else if (dsa_is_cpu_port(ds, port))
790 bcm_sf2_imp_setup(ds, port);
792 bcm_sf2_port_disable(ds, port);
795 b53_configure_vlan(ds);
796 bcm_sf2_enable_acb(ds);
801 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
802 * register basis so we need to translate that into an address that the
803 * bus-glue understands.
805 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
807 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
810 struct bcm_sf2_priv *priv = dev->priv;
812 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
817 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
820 struct bcm_sf2_priv *priv = dev->priv;
822 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
827 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
830 struct bcm_sf2_priv *priv = dev->priv;
832 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
837 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
840 struct bcm_sf2_priv *priv = dev->priv;
842 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
847 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
850 struct bcm_sf2_priv *priv = dev->priv;
852 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
857 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
860 struct bcm_sf2_priv *priv = dev->priv;
862 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
867 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
870 struct bcm_sf2_priv *priv = dev->priv;
872 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
877 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
880 struct bcm_sf2_priv *priv = dev->priv;
882 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
887 static const struct b53_io_ops bcm_sf2_io_ops = {
888 .read8 = bcm_sf2_core_read8,
889 .read16 = bcm_sf2_core_read16,
890 .read32 = bcm_sf2_core_read32,
891 .read48 = bcm_sf2_core_read64,
892 .read64 = bcm_sf2_core_read64,
893 .write8 = bcm_sf2_core_write8,
894 .write16 = bcm_sf2_core_write16,
895 .write32 = bcm_sf2_core_write32,
896 .write48 = bcm_sf2_core_write64,
897 .write64 = bcm_sf2_core_write64,
900 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
901 u32 stringset, uint8_t *data)
903 int cnt = b53_get_sset_count(ds, port, stringset);
905 b53_get_strings(ds, port, stringset, data);
906 bcm_sf2_cfp_get_strings(ds, port, stringset,
907 data + cnt * ETH_GSTRING_LEN);
910 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
913 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
915 b53_get_ethtool_stats(ds, port, data);
916 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
919 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
922 int cnt = b53_get_sset_count(ds, port, sset);
927 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
932 static const struct dsa_switch_ops bcm_sf2_ops = {
933 .get_tag_protocol = b53_get_tag_protocol,
934 .setup = bcm_sf2_sw_setup,
935 .get_strings = bcm_sf2_sw_get_strings,
936 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
937 .get_sset_count = bcm_sf2_sw_get_sset_count,
938 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
939 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
940 .phylink_validate = bcm_sf2_sw_validate,
941 .phylink_mac_config = bcm_sf2_sw_mac_config,
942 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
943 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
944 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
945 .suspend = bcm_sf2_sw_suspend,
946 .resume = bcm_sf2_sw_resume,
947 .get_wol = bcm_sf2_sw_get_wol,
948 .set_wol = bcm_sf2_sw_set_wol,
949 .port_enable = bcm_sf2_port_setup,
950 .port_disable = bcm_sf2_port_disable,
951 .get_mac_eee = b53_get_mac_eee,
952 .set_mac_eee = b53_set_mac_eee,
953 .port_bridge_join = b53_br_join,
954 .port_bridge_leave = b53_br_leave,
955 .port_stp_state_set = b53_br_set_stp_state,
956 .port_fast_age = b53_br_fast_age,
957 .port_vlan_filtering = b53_vlan_filtering,
958 .port_vlan_prepare = b53_vlan_prepare,
959 .port_vlan_add = b53_vlan_add,
960 .port_vlan_del = b53_vlan_del,
961 .port_fdb_dump = b53_fdb_dump,
962 .port_fdb_add = b53_fdb_add,
963 .port_fdb_del = b53_fdb_del,
964 .get_rxnfc = bcm_sf2_get_rxnfc,
965 .set_rxnfc = bcm_sf2_set_rxnfc,
966 .port_mirror_add = b53_mirror_add,
967 .port_mirror_del = b53_mirror_del,
970 struct bcm_sf2_of_data {
972 const u16 *reg_offsets;
973 unsigned int core_reg_align;
974 unsigned int num_cfp_rules;
977 /* Register offsets for the SWITCH_REG_* block */
978 static const u16 bcm_sf2_7445_reg_offsets[] = {
979 [REG_SWITCH_CNTRL] = 0x00,
980 [REG_SWITCH_STATUS] = 0x04,
981 [REG_DIR_DATA_WRITE] = 0x08,
982 [REG_DIR_DATA_READ] = 0x0C,
983 [REG_SWITCH_REVISION] = 0x18,
984 [REG_PHY_REVISION] = 0x1C,
985 [REG_SPHY_CNTRL] = 0x2C,
986 [REG_RGMII_0_CNTRL] = 0x34,
987 [REG_RGMII_1_CNTRL] = 0x40,
988 [REG_RGMII_2_CNTRL] = 0x4c,
989 [REG_LED_0_CNTRL] = 0x90,
990 [REG_LED_1_CNTRL] = 0x94,
991 [REG_LED_2_CNTRL] = 0x98,
994 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
995 .type = BCM7445_DEVICE_ID,
997 .reg_offsets = bcm_sf2_7445_reg_offsets,
998 .num_cfp_rules = 256,
1001 static const u16 bcm_sf2_7278_reg_offsets[] = {
1002 [REG_SWITCH_CNTRL] = 0x00,
1003 [REG_SWITCH_STATUS] = 0x04,
1004 [REG_DIR_DATA_WRITE] = 0x08,
1005 [REG_DIR_DATA_READ] = 0x0c,
1006 [REG_SWITCH_REVISION] = 0x10,
1007 [REG_PHY_REVISION] = 0x14,
1008 [REG_SPHY_CNTRL] = 0x24,
1009 [REG_RGMII_0_CNTRL] = 0xe0,
1010 [REG_RGMII_1_CNTRL] = 0xec,
1011 [REG_RGMII_2_CNTRL] = 0xf8,
1012 [REG_LED_0_CNTRL] = 0x40,
1013 [REG_LED_1_CNTRL] = 0x4c,
1014 [REG_LED_2_CNTRL] = 0x58,
1017 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1018 .type = BCM7278_DEVICE_ID,
1019 .core_reg_align = 1,
1020 .reg_offsets = bcm_sf2_7278_reg_offsets,
1021 .num_cfp_rules = 128,
1024 static const struct of_device_id bcm_sf2_of_match[] = {
1025 { .compatible = "brcm,bcm7445-switch-v4.0",
1026 .data = &bcm_sf2_7445_data
1028 { .compatible = "brcm,bcm7278-switch-v4.0",
1029 .data = &bcm_sf2_7278_data
1031 { .compatible = "brcm,bcm7278-switch-v4.8",
1032 .data = &bcm_sf2_7278_data
1036 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1038 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1040 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1041 struct device_node *dn = pdev->dev.of_node;
1042 const struct of_device_id *of_id = NULL;
1043 const struct bcm_sf2_of_data *data;
1044 struct b53_platform_data *pdata;
1045 struct dsa_switch_ops *ops;
1046 struct bcm_sf2_priv *priv;
1047 struct b53_device *dev;
1048 struct dsa_switch *ds;
1049 void __iomem **base;
1055 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1059 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1063 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1067 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1071 of_id = of_match_node(bcm_sf2_of_match, dn);
1072 if (!of_id || !of_id->data)
1077 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1078 priv->type = data->type;
1079 priv->reg_offsets = data->reg_offsets;
1080 priv->core_reg_align = data->core_reg_align;
1081 priv->num_cfp_rules = data->num_cfp_rules;
1083 /* Auto-detection using standard registers will not work, so
1084 * provide an indication of what kind of device we are for
1085 * b53_common to work with
1087 pdata->chip_id = priv->type;
1092 ds->ops = &bcm_sf2_ops;
1094 /* Advertise the 8 egress queues */
1095 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1097 dev_set_drvdata(&pdev->dev, priv);
1099 spin_lock_init(&priv->indir_lock);
1100 mutex_init(&priv->cfp.lock);
1101 INIT_LIST_HEAD(&priv->cfp.rules_list);
1103 /* CFP rule #0 cannot be used for specific classifications, flag it as
1106 set_bit(0, priv->cfp.used);
1107 set_bit(0, priv->cfp.unique);
1109 bcm_sf2_identify_ports(priv, dn->child);
1111 priv->irq0 = irq_of_parse_and_map(dn, 0);
1112 priv->irq1 = irq_of_parse_and_map(dn, 1);
1115 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1116 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1117 *base = devm_ioremap_resource(&pdev->dev, r);
1118 if (IS_ERR(*base)) {
1119 pr_err("unable to find register: %s\n", reg_names[i]);
1120 return PTR_ERR(*base);
1125 ret = bcm_sf2_sw_rst(priv);
1127 pr_err("unable to software reset switch: %d\n", ret);
1131 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1133 ret = bcm_sf2_mdio_register(ds);
1135 pr_err("failed to register MDIO bus\n");
1139 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1141 ret = bcm_sf2_cfp_rst(priv);
1143 pr_err("failed to reset CFP\n");
1147 /* Disable all interrupts and request them */
1148 bcm_sf2_intr_disable(priv);
1150 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1153 pr_err("failed to request switch_0 IRQ\n");
1157 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1160 pr_err("failed to request switch_1 IRQ\n");
1164 /* Reset the MIB counters */
1165 reg = core_readl(priv, CORE_GMNCFGCFG);
1167 core_writel(priv, reg, CORE_GMNCFGCFG);
1168 reg &= ~RST_MIB_CNT;
1169 core_writel(priv, reg, CORE_GMNCFGCFG);
1171 /* Get the maximum number of ports for this switch */
1172 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1173 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1174 priv->hw_params.num_ports = DSA_MAX_PORTS;
1176 /* Assume a single GPHY setup if we can't read that property */
1177 if (of_property_read_u32(dn, "brcm,num-gphy",
1178 &priv->hw_params.num_gphy))
1179 priv->hw_params.num_gphy = 1;
1181 rev = reg_readl(priv, REG_SWITCH_REVISION);
1182 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1183 SWITCH_TOP_REV_MASK;
1184 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1186 rev = reg_readl(priv, REG_PHY_REVISION);
1187 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1189 ret = b53_switch_register(dev);
1193 dev_info(&pdev->dev,
1194 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1195 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1196 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1197 priv->irq0, priv->irq1);
1202 bcm_sf2_mdio_unregister(priv);
1206 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1208 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1210 priv->wol_ports_mask = 0;
1211 dsa_unregister_switch(priv->dev->ds);
1212 bcm_sf2_cfp_exit(priv->dev->ds);
1213 /* Disable all ports and interrupts */
1214 bcm_sf2_sw_suspend(priv->dev->ds);
1215 bcm_sf2_mdio_unregister(priv);
1220 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1222 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1224 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1225 * successful MDIO bus scan to occur. If we did turn off the GPHY
1226 * before (e.g: port_disable), this will also power it back on.
1228 * Do not rely on kexec_in_progress, just power the PHY on.
1230 if (priv->hw_params.num_gphy == 1)
1231 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1234 #ifdef CONFIG_PM_SLEEP
1235 static int bcm_sf2_suspend(struct device *dev)
1237 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1239 return dsa_switch_suspend(priv->dev->ds);
1242 static int bcm_sf2_resume(struct device *dev)
1244 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1246 return dsa_switch_resume(priv->dev->ds);
1248 #endif /* CONFIG_PM_SLEEP */
1250 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1251 bcm_sf2_suspend, bcm_sf2_resume);
1254 static struct platform_driver bcm_sf2_driver = {
1255 .probe = bcm_sf2_sw_probe,
1256 .remove = bcm_sf2_sw_remove,
1257 .shutdown = bcm_sf2_sw_shutdown,
1260 .of_match_table = bcm_sf2_of_match,
1261 .pm = &bcm_sf2_pm_ops,
1264 module_platform_driver(bcm_sf2_driver);
1266 MODULE_AUTHOR("Broadcom Corporation");
1267 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1268 MODULE_LICENSE("GPL");
1269 MODULE_ALIAS("platform:brcm-sf2");