1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom Starfighter 2 DSA switch driver
5 * Copyright (C) 2014, Broadcom Corporation
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/clk.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_bridge.h>
26 #include <linux/brcmphy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/platform_data/b53.h>
31 #include "bcm_sf2_regs.h"
32 #include "b53/b53_priv.h"
33 #include "b53/b53_regs.h"
35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
38 case BCM4908_DEVICE_ID:
41 return REG_RGMII_11_CNTRL;
49 return REG_RGMII_0_CNTRL;
51 return REG_RGMII_1_CNTRL;
53 return REG_RGMII_2_CNTRL;
59 WARN_ONCE(1, "Unsupported port %d\n", port);
62 return REG_SWITCH_STATUS;
65 /* Return the number of active ports, not counting the IMP (CPU) port */
66 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
68 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
69 unsigned int port, count = 0;
71 for (port = 0; port < ds->num_ports; port++) {
72 if (dsa_is_cpu_port(ds, port))
74 if (priv->port_sts[port].enabled)
81 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
83 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
84 unsigned long new_rate;
85 unsigned int ports_active;
86 /* Frequenty in Mhz */
87 static const unsigned long rate_table[] = {
94 ports_active = bcm_sf2_num_active_ports(ds);
95 if (ports_active == 0 || !priv->clk_mdiv)
98 /* If we overflow our table, just use the recommended operational
101 if (ports_active > ARRAY_SIZE(rate_table))
104 new_rate = rate_table[ports_active - 1];
105 clk_set_rate(priv->clk_mdiv, new_rate);
108 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
110 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
114 /* Enable the port memories */
115 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
116 reg &= ~P_TXQ_PSM_VDD(port);
117 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
119 /* Enable forwarding */
120 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
122 /* Enable IMP port in dumb mode */
123 reg = core_readl(priv, CORE_SWITCH_CTRL);
124 reg |= MII_DUMB_FWDG_EN;
125 core_writel(priv, reg, CORE_SWITCH_CTRL);
127 /* Configure Traffic Class to QoS mapping, allow each priority to map
128 * to a different queue number
130 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
131 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
132 reg |= i << (PRT_TO_QID_SHIFT * i);
133 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
135 b53_brcm_hdr_setup(ds, port);
138 if (priv->type == BCM4908_DEVICE_ID ||
139 priv->type == BCM7445_DEVICE_ID)
140 offset = CORE_STS_OVERRIDE_IMP;
142 offset = CORE_STS_OVERRIDE_IMP2;
144 /* Force link status for IMP port */
145 reg = core_readl(priv, offset);
146 reg |= (MII_SW_OR | LINK_STS);
147 if (priv->type == BCM4908_DEVICE_ID)
148 reg |= GMII_SPEED_UP_2G;
150 reg &= ~GMII_SPEED_UP_2G;
151 core_writel(priv, reg, offset);
153 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
154 reg = core_readl(priv, CORE_IMP_CTL);
155 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
156 reg &= ~(RX_DIS | TX_DIS);
157 core_writel(priv, reg, CORE_IMP_CTL);
159 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
160 reg &= ~(RX_DIS | TX_DIS);
161 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
164 priv->port_sts[port].enabled = true;
167 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
169 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
172 reg = reg_readl(priv, REG_SPHY_CNTRL);
175 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
176 reg_writel(priv, reg, REG_SPHY_CNTRL);
178 reg = reg_readl(priv, REG_SPHY_CNTRL);
181 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
182 reg_writel(priv, reg, REG_SPHY_CNTRL);
186 reg_writel(priv, reg, REG_SPHY_CNTRL);
188 /* Use PHY-driven LED signaling */
190 reg = reg_readl(priv, REG_LED_CNTRL(0));
191 reg |= SPDLNK_SRC_SEL;
192 reg_writel(priv, reg, REG_LED_CNTRL(0));
196 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
206 /* Port 0 interrupts are located on the first bank */
207 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
210 off = P_IRQ_OFF(port);
214 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
217 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
227 /* Port 0 interrupts are located on the first bank */
228 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
229 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
232 off = P_IRQ_OFF(port);
236 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
237 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
240 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
241 struct phy_device *phy)
243 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
247 if (!dsa_is_user_port(ds, port))
250 priv->port_sts[port].enabled = true;
252 bcm_sf2_recalc_clock(ds);
254 /* Clear the memory power down */
255 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
256 reg &= ~P_TXQ_PSM_VDD(port);
257 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
259 /* Enable Broadcom tags for that port if requested */
260 if (priv->brcm_tag_mask & BIT(port))
261 b53_brcm_hdr_setup(ds, port);
263 /* Configure Traffic Class to QoS mapping, allow each priority to map
264 * to a different queue number
266 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
267 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
268 reg |= i << (PRT_TO_QID_SHIFT * i);
269 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
271 /* Re-enable the GPHY and re-apply workarounds */
272 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
273 bcm_sf2_gphy_enable_set(ds, true);
275 /* if phy_stop() has been called before, phy
276 * will be in halted state, and phy_start()
279 * the resume path does not configure back
280 * autoneg settings, and since we hard reset
281 * the phy manually here, we need to reset the
282 * state machine also.
284 phy->state = PHY_READY;
289 /* Enable MoCA port interrupts to get notified */
290 if (port == priv->moca_port)
291 bcm_sf2_port_intr_enable(priv, port);
293 /* Set per-queue pause threshold to 32 */
294 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
296 /* Set ACB threshold to 24 */
297 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
298 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
299 SF2_NUM_EGRESS_QUEUES + i));
300 reg &= ~XOFF_THRESHOLD_MASK;
302 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
303 SF2_NUM_EGRESS_QUEUES + i));
306 return b53_enable_port(ds, port, phy);
309 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
311 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
314 /* Disable learning while in WoL mode */
315 if (priv->wol_ports_mask & (1 << port)) {
316 reg = core_readl(priv, CORE_DIS_LEARN);
318 core_writel(priv, reg, CORE_DIS_LEARN);
322 if (port == priv->moca_port)
323 bcm_sf2_port_intr_disable(priv, port);
325 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
326 bcm_sf2_gphy_enable_set(ds, false);
328 b53_disable_port(ds, port);
330 /* Power down the port memory */
331 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
332 reg |= P_TXQ_PSM_VDD(port);
333 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
335 priv->port_sts[port].enabled = false;
337 bcm_sf2_recalc_clock(ds);
341 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
347 reg = reg_readl(priv, REG_SWITCH_CNTRL);
348 reg |= MDIO_MASTER_SEL;
349 reg_writel(priv, reg, REG_SWITCH_CNTRL);
351 /* Page << 8 | offset */
354 core_writel(priv, addr, reg);
356 /* Page << 8 | offset */
357 reg = 0x80 << 8 | regnum << 1;
361 ret = core_readl(priv, reg);
363 core_writel(priv, val, reg);
365 reg = reg_readl(priv, REG_SWITCH_CNTRL);
366 reg &= ~MDIO_MASTER_SEL;
367 reg_writel(priv, reg, REG_SWITCH_CNTRL);
372 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
374 struct bcm_sf2_priv *priv = bus->priv;
376 /* Intercept reads from Broadcom pseudo-PHY address, else, send
377 * them to our master MDIO bus controller
379 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
380 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
382 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
385 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
388 struct bcm_sf2_priv *priv = bus->priv;
390 /* Intercept writes to the Broadcom pseudo-PHY address, else,
391 * send them to our master MDIO bus controller
393 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
394 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
396 return mdiobus_write_nested(priv->master_mii_bus, addr,
400 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
402 struct dsa_switch *ds = dev_id;
403 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
405 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
407 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
412 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
414 struct dsa_switch *ds = dev_id;
415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
417 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
419 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
421 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
422 priv->port_sts[7].link = true;
423 dsa_port_phylink_mac_change(ds, 7, true);
425 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
426 priv->port_sts[7].link = false;
427 dsa_port_phylink_mac_change(ds, 7, false);
433 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
435 unsigned int timeout = 1000;
439 /* The watchdog reset does not work on 7278, we need to hit the
440 * "external" reset line through the reset controller.
442 if (priv->type == BCM7278_DEVICE_ID) {
443 ret = reset_control_assert(priv->rcdev);
447 return reset_control_deassert(priv->rcdev);
450 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
451 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
452 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
455 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
456 if (!(reg & SOFTWARE_RESET))
459 usleep_range(1000, 2000);
460 } while (timeout-- > 0);
468 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
470 struct device *dev = priv->dev->ds->dev;
476 mask = BIT(priv->num_crossbar_int_ports) - 1;
478 reg = reg_readl(priv, REG_CROSSBAR);
479 switch (priv->type) {
480 case BCM4908_DEVICE_ID:
481 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
482 reg &= ~(mask << shift);
484 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
485 else if (priv->int_phy_mask & BIT(7))
486 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
487 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
488 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
489 else if (WARN(1, "Invalid port mode\n"))
495 reg_writel(priv, reg, REG_CROSSBAR);
497 reg = reg_readl(priv, REG_CROSSBAR);
498 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
499 shift = i * priv->num_crossbar_int_ports;
501 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
502 (reg >> shift) & mask);
506 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
508 intrl2_0_mask_set(priv, 0xffffffff);
509 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
510 intrl2_1_mask_set(priv, 0xffffffff);
511 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
514 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
515 struct device_node *dn)
517 struct device *dev = priv->dev->ds->dev;
518 struct bcm_sf2_port_status *port_st;
519 struct device_node *port;
520 unsigned int port_num;
521 struct property *prop;
524 priv->moca_port = -1;
526 for_each_available_child_of_node(dn, port) {
527 if (of_property_read_u32(port, "reg", &port_num))
530 if (port_num >= DSA_MAX_PORTS) {
531 dev_err(dev, "Invalid port number %d\n", port_num);
535 port_st = &priv->port_sts[port_num];
537 /* Internal PHYs get assigned a specific 'phy-mode' property
538 * value: "internal" to help flag them before MDIO probing
539 * has completed, since they might be turned off at that
542 err = of_get_phy_mode(port, &port_st->mode);
546 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
547 priv->int_phy_mask |= 1 << port_num;
549 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
550 priv->moca_port = port_num;
552 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
553 priv->brcm_tag_mask |= 1 << port_num;
555 /* Ensure that port 5 is not picked up as a DSA CPU port
556 * flavour but a regular port instead. We should be using
557 * devlink to be able to set the port flavour.
559 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
560 prop = of_find_property(port, "ethernet", NULL);
562 of_remove_property(port, prop);
567 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
569 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
570 struct device_node *dn, *child;
571 struct phy_device *phydev;
572 struct property *prop;
576 /* Find our integrated MDIO bus node */
577 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
578 priv->master_mii_bus = of_mdio_find_bus(dn);
579 if (!priv->master_mii_bus) {
581 return -EPROBE_DEFER;
584 get_device(&priv->master_mii_bus->dev);
585 priv->master_mii_dn = dn;
587 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
588 if (!priv->slave_mii_bus) {
593 priv->slave_mii_bus->priv = priv;
594 priv->slave_mii_bus->name = "sf2 slave mii";
595 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
596 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
597 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
599 priv->slave_mii_bus->dev.of_node = dn;
601 /* Include the pseudo-PHY address to divert reads towards our
602 * workaround. This is only required for 7445D0, since 7445E0
603 * disconnects the internal switch pseudo-PHY such that we can use the
604 * regular SWITCH_MDIO master controller instead.
606 * Here we flag the pseudo PHY as needing special treatment and would
607 * otherwise make all other PHY read/writes go to the master MDIO bus
608 * controller that comes with this switch backed by the "mdio-unimac"
611 if (of_machine_is_compatible("brcm,bcm7445d0"))
612 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
614 priv->indir_phy_mask = 0;
616 ds->phys_mii_mask = priv->indir_phy_mask;
617 ds->slave_mii_bus = priv->slave_mii_bus;
618 priv->slave_mii_bus->parent = ds->dev->parent;
619 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
621 /* We need to make sure that of_phy_connect() will not work by
622 * removing the 'phandle' and 'linux,phandle' properties and
623 * unregister the existing PHY device that was already registered.
625 for_each_available_child_of_node(dn, child) {
626 if (of_property_read_u32(child, "reg", ®) ||
630 if (!(priv->indir_phy_mask & BIT(reg)))
633 prop = of_find_property(child, "phandle", NULL);
635 of_remove_property(child, prop);
637 prop = of_find_property(child, "linux,phandle", NULL);
639 of_remove_property(child, prop);
641 phydev = of_phy_find_device(child);
643 phy_device_remove(phydev);
646 err = mdiobus_register(priv->slave_mii_bus);
653 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
655 mdiobus_unregister(priv->slave_mii_bus);
656 of_node_put(priv->master_mii_dn);
659 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
661 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
663 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
664 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
665 * the REG_PHY_REVISION register layout is.
667 if (priv->int_phy_mask & BIT(port))
668 return priv->hw_params.gphy_rev;
673 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
674 unsigned long *supported,
675 struct phylink_link_state *state)
677 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
678 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
680 if (!phy_interface_mode_is_rgmii(state->interface) &&
681 state->interface != PHY_INTERFACE_MODE_MII &&
682 state->interface != PHY_INTERFACE_MODE_REVMII &&
683 state->interface != PHY_INTERFACE_MODE_GMII &&
684 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
685 state->interface != PHY_INTERFACE_MODE_MOCA) {
686 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
687 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
689 "Unsupported interface: %d for port %d\n",
690 state->interface, port);
694 /* Allow all the expected bits */
695 phylink_set(mask, Autoneg);
696 phylink_set_port_modes(mask);
697 phylink_set(mask, Pause);
698 phylink_set(mask, Asym_Pause);
700 /* With the exclusion of MII and Reverse MII, we support Gigabit,
701 * including Half duplex
703 if (state->interface != PHY_INTERFACE_MODE_MII &&
704 state->interface != PHY_INTERFACE_MODE_REVMII) {
705 phylink_set(mask, 1000baseT_Full);
706 phylink_set(mask, 1000baseT_Half);
709 phylink_set(mask, 10baseT_Half);
710 phylink_set(mask, 10baseT_Full);
711 phylink_set(mask, 100baseT_Half);
712 phylink_set(mask, 100baseT_Full);
714 bitmap_and(supported, supported, mask,
715 __ETHTOOL_LINK_MODE_MASK_NBITS);
716 bitmap_and(state->advertising, state->advertising, mask,
717 __ETHTOOL_LINK_MODE_MASK_NBITS);
720 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
722 const struct phylink_link_state *state)
724 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
725 u32 id_mode_dis = 0, port_mode;
729 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
732 switch (state->interface) {
733 case PHY_INTERFACE_MODE_RGMII:
736 case PHY_INTERFACE_MODE_RGMII_TXID:
737 port_mode = EXT_GPHY;
739 case PHY_INTERFACE_MODE_MII:
740 port_mode = EXT_EPHY;
742 case PHY_INTERFACE_MODE_REVMII:
743 port_mode = EXT_REVMII;
746 /* Nothing required for all other PHYs: internal and MoCA */
750 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
752 /* Clear id_mode_dis bit, and the existing port mode, let
753 * RGMII_MODE_EN bet set by mac_link_{up,down}
755 reg = reg_readl(priv, reg_rgmii_ctrl);
757 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
763 reg_writel(priv, reg, reg_rgmii_ctrl);
766 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
767 phy_interface_t interface, bool link)
769 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
773 if (!phy_interface_mode_is_rgmii(interface) &&
774 interface != PHY_INTERFACE_MODE_MII &&
775 interface != PHY_INTERFACE_MODE_REVMII)
778 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
780 /* If the link is down, just disable the interface to conserve power */
781 reg = reg_readl(priv, reg_rgmii_ctrl);
783 reg |= RGMII_MODE_EN;
785 reg &= ~RGMII_MODE_EN;
786 reg_writel(priv, reg, reg_rgmii_ctrl);
789 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
791 phy_interface_t interface)
793 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
796 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
797 if (priv->type == BCM4908_DEVICE_ID ||
798 priv->type == BCM7445_DEVICE_ID)
799 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
801 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
803 reg = core_readl(priv, offset);
805 core_writel(priv, reg, offset);
808 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
811 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
813 phy_interface_t interface,
814 struct phy_device *phydev,
815 int speed, int duplex,
816 bool tx_pause, bool rx_pause)
818 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
819 struct ethtool_eee *p = &priv->dev->ports[port].eee;
821 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
823 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
824 u32 reg_rgmii_ctrl = 0;
827 if (priv->type == BCM4908_DEVICE_ID ||
828 priv->type == BCM7445_DEVICE_ID)
829 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
831 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
833 if (interface == PHY_INTERFACE_MODE_RGMII ||
834 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
835 interface == PHY_INTERFACE_MODE_MII ||
836 interface == PHY_INTERFACE_MODE_REVMII) {
837 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
838 reg = reg_readl(priv, reg_rgmii_ctrl);
839 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
846 reg_writel(priv, reg, reg_rgmii_ctrl);
849 reg = SW_OVERRIDE | LINK_STS;
852 reg |= SPDSTS_1000 << SPEED_SHIFT;
855 reg |= SPDSTS_100 << SPEED_SHIFT;
859 if (duplex == DUPLEX_FULL)
862 core_writel(priv, reg, offset);
865 if (mode == MLO_AN_PHY && phydev)
866 p->eee_enabled = b53_eee_init(ds, port, phydev);
869 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
870 struct phylink_link_state *status)
872 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
874 status->link = false;
876 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
877 * which means that we need to force the link at the port override
878 * level to get the data to flow. We do use what the interrupt handler
879 * did determine before.
881 * For the other ports, we just force the link status, since this is
882 * a fixed PHY device.
884 if (port == priv->moca_port) {
885 status->link = priv->port_sts[port].link;
886 /* For MoCA interfaces, also force a link down notification
887 * since some version of the user-space daemon (mocad) use
888 * cmd->autoneg to force the link, which messes up the PHY
889 * state machine and make it go in PHY_FORCING state instead.
892 netif_carrier_off(dsa_to_port(ds, port)->slave);
893 status->duplex = DUPLEX_FULL;
899 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
901 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
904 /* Enable ACB globally */
905 reg = acb_readl(priv, ACB_CONTROL);
906 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
907 acb_writel(priv, reg, ACB_CONTROL);
908 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
909 reg |= ACB_EN | ACB_ALGORITHM;
910 acb_writel(priv, reg, ACB_CONTROL);
913 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
915 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
918 bcm_sf2_intr_disable(priv);
920 /* Disable all ports physically present including the IMP
921 * port, the other ones have already been disabled during
924 for (port = 0; port < ds->num_ports; port++) {
925 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
926 bcm_sf2_port_disable(ds, port);
929 if (!priv->wol_ports_mask)
930 clk_disable_unprepare(priv->clk);
935 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
937 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
940 if (!priv->wol_ports_mask)
941 clk_prepare_enable(priv->clk);
943 ret = bcm_sf2_sw_rst(priv);
945 pr_err("%s: failed to software reset switch\n", __func__);
949 bcm_sf2_crossbar_setup(priv);
951 ret = bcm_sf2_cfp_resume(ds);
955 if (priv->hw_params.num_gphy == 1)
956 bcm_sf2_gphy_enable_set(ds, true);
963 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
964 struct ethtool_wolinfo *wol)
966 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
967 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
968 struct ethtool_wolinfo pwol = { };
970 /* Get the parent device WoL settings */
971 if (p->ethtool_ops->get_wol)
972 p->ethtool_ops->get_wol(p, &pwol);
974 /* Advertise the parent device supported settings */
975 wol->supported = pwol.supported;
976 memset(&wol->sopass, 0, sizeof(wol->sopass));
978 if (pwol.wolopts & WAKE_MAGICSECURE)
979 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
981 if (priv->wol_ports_mask & (1 << port))
982 wol->wolopts = pwol.wolopts;
987 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
988 struct ethtool_wolinfo *wol)
990 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
991 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
992 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
993 struct ethtool_wolinfo pwol = { };
995 if (p->ethtool_ops->get_wol)
996 p->ethtool_ops->get_wol(p, &pwol);
997 if (wol->wolopts & ~pwol.supported)
1001 priv->wol_ports_mask |= (1 << port);
1003 priv->wol_ports_mask &= ~(1 << port);
1005 /* If we have at least one port enabled, make sure the CPU port
1006 * is also enabled. If the CPU port is the last one enabled, we disable
1007 * it since this configuration does not make sense.
1009 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1010 priv->wol_ports_mask |= (1 << cpu_port);
1012 priv->wol_ports_mask &= ~(1 << cpu_port);
1014 return p->ethtool_ops->set_wol(p, wol);
1017 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1019 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1022 /* Enable all valid ports and disable those unused */
1023 for (port = 0; port < priv->hw_params.num_ports; port++) {
1024 /* IMP port receives special treatment */
1025 if (dsa_is_user_port(ds, port))
1026 bcm_sf2_port_setup(ds, port, NULL);
1027 else if (dsa_is_cpu_port(ds, port))
1028 bcm_sf2_imp_setup(ds, port);
1030 bcm_sf2_port_disable(ds, port);
1033 b53_configure_vlan(ds);
1034 bcm_sf2_enable_acb(ds);
1036 return b53_setup_devlink_resources(ds);
1039 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1041 dsa_devlink_resources_unregister(ds);
1044 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
1045 * register basis so we need to translate that into an address that the
1046 * bus-glue understands.
1048 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1050 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1053 struct bcm_sf2_priv *priv = dev->priv;
1055 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1060 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1063 struct bcm_sf2_priv *priv = dev->priv;
1065 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1070 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1073 struct bcm_sf2_priv *priv = dev->priv;
1075 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1080 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1083 struct bcm_sf2_priv *priv = dev->priv;
1085 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1090 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1093 struct bcm_sf2_priv *priv = dev->priv;
1095 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1100 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1103 struct bcm_sf2_priv *priv = dev->priv;
1105 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1110 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1113 struct bcm_sf2_priv *priv = dev->priv;
1115 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1120 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1123 struct bcm_sf2_priv *priv = dev->priv;
1125 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1130 static const struct b53_io_ops bcm_sf2_io_ops = {
1131 .read8 = bcm_sf2_core_read8,
1132 .read16 = bcm_sf2_core_read16,
1133 .read32 = bcm_sf2_core_read32,
1134 .read48 = bcm_sf2_core_read64,
1135 .read64 = bcm_sf2_core_read64,
1136 .write8 = bcm_sf2_core_write8,
1137 .write16 = bcm_sf2_core_write16,
1138 .write32 = bcm_sf2_core_write32,
1139 .write48 = bcm_sf2_core_write64,
1140 .write64 = bcm_sf2_core_write64,
1143 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1144 u32 stringset, uint8_t *data)
1146 int cnt = b53_get_sset_count(ds, port, stringset);
1148 b53_get_strings(ds, port, stringset, data);
1149 bcm_sf2_cfp_get_strings(ds, port, stringset,
1150 data + cnt * ETH_GSTRING_LEN);
1153 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1156 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1158 b53_get_ethtool_stats(ds, port, data);
1159 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1162 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1165 int cnt = b53_get_sset_count(ds, port, sset);
1170 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1175 static const struct dsa_switch_ops bcm_sf2_ops = {
1176 .get_tag_protocol = b53_get_tag_protocol,
1177 .setup = bcm_sf2_sw_setup,
1178 .teardown = bcm_sf2_sw_teardown,
1179 .get_strings = bcm_sf2_sw_get_strings,
1180 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1181 .get_sset_count = bcm_sf2_sw_get_sset_count,
1182 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1183 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1184 .phylink_validate = bcm_sf2_sw_validate,
1185 .phylink_mac_config = bcm_sf2_sw_mac_config,
1186 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1187 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1188 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1189 .suspend = bcm_sf2_sw_suspend,
1190 .resume = bcm_sf2_sw_resume,
1191 .get_wol = bcm_sf2_sw_get_wol,
1192 .set_wol = bcm_sf2_sw_set_wol,
1193 .port_enable = bcm_sf2_port_setup,
1194 .port_disable = bcm_sf2_port_disable,
1195 .get_mac_eee = b53_get_mac_eee,
1196 .set_mac_eee = b53_set_mac_eee,
1197 .port_bridge_join = b53_br_join,
1198 .port_bridge_leave = b53_br_leave,
1199 .port_pre_bridge_flags = b53_br_flags_pre,
1200 .port_bridge_flags = b53_br_flags,
1201 .port_stp_state_set = b53_br_set_stp_state,
1202 .port_fast_age = b53_br_fast_age,
1203 .port_vlan_filtering = b53_vlan_filtering,
1204 .port_vlan_add = b53_vlan_add,
1205 .port_vlan_del = b53_vlan_del,
1206 .port_fdb_dump = b53_fdb_dump,
1207 .port_fdb_add = b53_fdb_add,
1208 .port_fdb_del = b53_fdb_del,
1209 .get_rxnfc = bcm_sf2_get_rxnfc,
1210 .set_rxnfc = bcm_sf2_set_rxnfc,
1211 .port_mirror_add = b53_mirror_add,
1212 .port_mirror_del = b53_mirror_del,
1213 .port_mdb_add = b53_mdb_add,
1214 .port_mdb_del = b53_mdb_del,
1217 struct bcm_sf2_of_data {
1219 const u16 *reg_offsets;
1220 unsigned int core_reg_align;
1221 unsigned int num_cfp_rules;
1222 unsigned int num_crossbar_int_ports;
1225 static const u16 bcm_sf2_4908_reg_offsets[] = {
1226 [REG_SWITCH_CNTRL] = 0x00,
1227 [REG_SWITCH_STATUS] = 0x04,
1228 [REG_DIR_DATA_WRITE] = 0x08,
1229 [REG_DIR_DATA_READ] = 0x0c,
1230 [REG_SWITCH_REVISION] = 0x10,
1231 [REG_PHY_REVISION] = 0x14,
1232 [REG_SPHY_CNTRL] = 0x24,
1233 [REG_CROSSBAR] = 0xc8,
1234 [REG_RGMII_11_CNTRL] = 0x014c,
1235 [REG_LED_0_CNTRL] = 0x40,
1236 [REG_LED_1_CNTRL] = 0x4c,
1237 [REG_LED_2_CNTRL] = 0x58,
1240 static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1241 .type = BCM4908_DEVICE_ID,
1242 .core_reg_align = 0,
1243 .reg_offsets = bcm_sf2_4908_reg_offsets,
1244 .num_cfp_rules = 256,
1245 .num_crossbar_int_ports = 2,
1248 /* Register offsets for the SWITCH_REG_* block */
1249 static const u16 bcm_sf2_7445_reg_offsets[] = {
1250 [REG_SWITCH_CNTRL] = 0x00,
1251 [REG_SWITCH_STATUS] = 0x04,
1252 [REG_DIR_DATA_WRITE] = 0x08,
1253 [REG_DIR_DATA_READ] = 0x0C,
1254 [REG_SWITCH_REVISION] = 0x18,
1255 [REG_PHY_REVISION] = 0x1C,
1256 [REG_SPHY_CNTRL] = 0x2C,
1257 [REG_RGMII_0_CNTRL] = 0x34,
1258 [REG_RGMII_1_CNTRL] = 0x40,
1259 [REG_RGMII_2_CNTRL] = 0x4c,
1260 [REG_LED_0_CNTRL] = 0x90,
1261 [REG_LED_1_CNTRL] = 0x94,
1262 [REG_LED_2_CNTRL] = 0x98,
1265 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1266 .type = BCM7445_DEVICE_ID,
1267 .core_reg_align = 0,
1268 .reg_offsets = bcm_sf2_7445_reg_offsets,
1269 .num_cfp_rules = 256,
1272 static const u16 bcm_sf2_7278_reg_offsets[] = {
1273 [REG_SWITCH_CNTRL] = 0x00,
1274 [REG_SWITCH_STATUS] = 0x04,
1275 [REG_DIR_DATA_WRITE] = 0x08,
1276 [REG_DIR_DATA_READ] = 0x0c,
1277 [REG_SWITCH_REVISION] = 0x10,
1278 [REG_PHY_REVISION] = 0x14,
1279 [REG_SPHY_CNTRL] = 0x24,
1280 [REG_RGMII_0_CNTRL] = 0xe0,
1281 [REG_RGMII_1_CNTRL] = 0xec,
1282 [REG_RGMII_2_CNTRL] = 0xf8,
1283 [REG_LED_0_CNTRL] = 0x40,
1284 [REG_LED_1_CNTRL] = 0x4c,
1285 [REG_LED_2_CNTRL] = 0x58,
1288 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1289 .type = BCM7278_DEVICE_ID,
1290 .core_reg_align = 1,
1291 .reg_offsets = bcm_sf2_7278_reg_offsets,
1292 .num_cfp_rules = 128,
1295 static const struct of_device_id bcm_sf2_of_match[] = {
1296 { .compatible = "brcm,bcm4908-switch",
1297 .data = &bcm_sf2_4908_data
1299 { .compatible = "brcm,bcm7445-switch-v4.0",
1300 .data = &bcm_sf2_7445_data
1302 { .compatible = "brcm,bcm7278-switch-v4.0",
1303 .data = &bcm_sf2_7278_data
1305 { .compatible = "brcm,bcm7278-switch-v4.8",
1306 .data = &bcm_sf2_7278_data
1310 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1312 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1314 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1315 struct device_node *dn = pdev->dev.of_node;
1316 const struct of_device_id *of_id = NULL;
1317 const struct bcm_sf2_of_data *data;
1318 struct b53_platform_data *pdata;
1319 struct dsa_switch_ops *ops;
1320 struct device_node *ports;
1321 struct bcm_sf2_priv *priv;
1322 struct b53_device *dev;
1323 struct dsa_switch *ds;
1324 void __iomem **base;
1329 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1333 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1337 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1341 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1345 of_id = of_match_node(bcm_sf2_of_match, dn);
1346 if (!of_id || !of_id->data)
1351 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1352 priv->type = data->type;
1353 priv->reg_offsets = data->reg_offsets;
1354 priv->core_reg_align = data->core_reg_align;
1355 priv->num_cfp_rules = data->num_cfp_rules;
1356 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1358 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1360 if (IS_ERR(priv->rcdev))
1361 return PTR_ERR(priv->rcdev);
1363 /* Auto-detection using standard registers will not work, so
1364 * provide an indication of what kind of device we are for
1365 * b53_common to work with
1367 pdata->chip_id = priv->type;
1372 ds->ops = &bcm_sf2_ops;
1374 /* Advertise the 8 egress queues */
1375 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1377 dev_set_drvdata(&pdev->dev, priv);
1379 spin_lock_init(&priv->indir_lock);
1380 mutex_init(&priv->cfp.lock);
1381 INIT_LIST_HEAD(&priv->cfp.rules_list);
1383 /* CFP rule #0 cannot be used for specific classifications, flag it as
1386 set_bit(0, priv->cfp.used);
1387 set_bit(0, priv->cfp.unique);
1389 /* Balance of_node_put() done by of_find_node_by_name() */
1391 ports = of_find_node_by_name(dn, "ports");
1393 bcm_sf2_identify_ports(priv, ports);
1397 priv->irq0 = irq_of_parse_and_map(dn, 0);
1398 priv->irq1 = irq_of_parse_and_map(dn, 1);
1401 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1402 *base = devm_platform_ioremap_resource(pdev, i);
1403 if (IS_ERR(*base)) {
1404 pr_err("unable to find register: %s\n", reg_names[i]);
1405 return PTR_ERR(*base);
1410 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1411 if (IS_ERR(priv->clk))
1412 return PTR_ERR(priv->clk);
1414 clk_prepare_enable(priv->clk);
1416 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1417 if (IS_ERR(priv->clk_mdiv)) {
1418 ret = PTR_ERR(priv->clk_mdiv);
1422 clk_prepare_enable(priv->clk_mdiv);
1424 ret = bcm_sf2_sw_rst(priv);
1426 pr_err("unable to software reset switch: %d\n", ret);
1430 bcm_sf2_crossbar_setup(priv);
1432 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1434 ret = bcm_sf2_mdio_register(ds);
1436 pr_err("failed to register MDIO bus\n");
1440 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1442 ret = bcm_sf2_cfp_rst(priv);
1444 pr_err("failed to reset CFP\n");
1448 /* Disable all interrupts and request them */
1449 bcm_sf2_intr_disable(priv);
1451 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1454 pr_err("failed to request switch_0 IRQ\n");
1458 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1461 pr_err("failed to request switch_1 IRQ\n");
1465 /* Reset the MIB counters */
1466 reg = core_readl(priv, CORE_GMNCFGCFG);
1468 core_writel(priv, reg, CORE_GMNCFGCFG);
1469 reg &= ~RST_MIB_CNT;
1470 core_writel(priv, reg, CORE_GMNCFGCFG);
1472 /* Get the maximum number of ports for this switch */
1473 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1474 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1475 priv->hw_params.num_ports = DSA_MAX_PORTS;
1477 /* Assume a single GPHY setup if we can't read that property */
1478 if (of_property_read_u32(dn, "brcm,num-gphy",
1479 &priv->hw_params.num_gphy))
1480 priv->hw_params.num_gphy = 1;
1482 rev = reg_readl(priv, REG_SWITCH_REVISION);
1483 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1484 SWITCH_TOP_REV_MASK;
1485 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1487 rev = reg_readl(priv, REG_PHY_REVISION);
1488 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1490 ret = b53_switch_register(dev);
1494 dev_info(&pdev->dev,
1495 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1496 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1497 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1498 priv->irq0, priv->irq1);
1503 bcm_sf2_mdio_unregister(priv);
1505 clk_disable_unprepare(priv->clk_mdiv);
1507 clk_disable_unprepare(priv->clk);
1511 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1513 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1518 priv->wol_ports_mask = 0;
1519 /* Disable interrupts */
1520 bcm_sf2_intr_disable(priv);
1521 dsa_unregister_switch(priv->dev->ds);
1522 bcm_sf2_cfp_exit(priv->dev->ds);
1523 bcm_sf2_mdio_unregister(priv);
1524 clk_disable_unprepare(priv->clk_mdiv);
1525 clk_disable_unprepare(priv->clk);
1526 if (priv->type == BCM7278_DEVICE_ID)
1527 reset_control_assert(priv->rcdev);
1529 platform_set_drvdata(pdev, NULL);
1534 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1536 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1541 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1542 * successful MDIO bus scan to occur. If we did turn off the GPHY
1543 * before (e.g: port_disable), this will also power it back on.
1545 * Do not rely on kexec_in_progress, just power the PHY on.
1547 if (priv->hw_params.num_gphy == 1)
1548 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1550 dsa_switch_shutdown(priv->dev->ds);
1552 platform_set_drvdata(pdev, NULL);
1555 #ifdef CONFIG_PM_SLEEP
1556 static int bcm_sf2_suspend(struct device *dev)
1558 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1560 return dsa_switch_suspend(priv->dev->ds);
1563 static int bcm_sf2_resume(struct device *dev)
1565 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1567 return dsa_switch_resume(priv->dev->ds);
1569 #endif /* CONFIG_PM_SLEEP */
1571 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1572 bcm_sf2_suspend, bcm_sf2_resume);
1575 static struct platform_driver bcm_sf2_driver = {
1576 .probe = bcm_sf2_sw_probe,
1577 .remove = bcm_sf2_sw_remove,
1578 .shutdown = bcm_sf2_sw_shutdown,
1581 .of_match_table = bcm_sf2_of_match,
1582 .pm = &bcm_sf2_pm_ops,
1585 module_platform_driver(bcm_sf2_driver);
1587 MODULE_AUTHOR("Broadcom Corporation");
1588 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1589 MODULE_LICENSE("GPL");
1590 MODULE_ALIAS("platform:brcm-sf2");