drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/if_bridge.h>
  32 #include <net/dsa.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         u8 mgmt;
 330
 331         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 332
 333         if (enable)
 334                 mgmt |= SM_SW_FWD_EN;
 335         else
 336                 mgmt &= ~SM_SW_FWD_EN;
 337
 338         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 339
 340         /* Include IMP port in dumb forwarding mode
 341          */
 342         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 343         mgmt |= B53_MII_DUMB_FWDG_EN;
 344         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 345
 346         /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
 347          * frames should be flooded or not.
 348          */
 349         b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
 350         mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN;
 351         b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
 352 }
 353
 354 static void b53_enable_vlan(struct b53_device *dev, bool enable,
 355                             bool enable_filtering)
 356 {
 357         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 358
 359         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 360         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 361         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 362
 363         if (is5325(dev) || is5365(dev)) {
 364                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 365                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 366         } else if (is63xx(dev)) {
 367                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 368                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 369         } else {
 370                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 371                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 372         }
 373
 374         mgmt &= ~SM_SW_FWD_MODE;
 375
 376         if (enable) {
 377                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 378                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 379                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 380                 if (enable_filtering) {
 381                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 382                         vc5 |= VC5_DROP_VTABLE_MISS;
 383                 } else {
 384                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 385                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 386                 }
 387
 388                 if (is5325(dev))
 389                         vc0 &= ~VC0_RESERVED_1;
 390
 391                 if (is5325(dev) || is5365(dev))
 392                         vc1 |= VC1_RX_MCST_TAG_EN;
 393
 394         } else {
 395                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 396                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 397                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 398                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 399
 400                 if (is5325(dev) || is5365(dev))
 401                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 402                 else
 403                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 404
 405                 if (is5325(dev) || is5365(dev))
 406                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 407         }
 408
 409         if (!is5325(dev) && !is5365(dev))
 410                 vc5 &= ~VC5_VID_FFF_EN;
 411
 412         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 413         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 414
 415         if (is5325(dev) || is5365(dev)) {
 416                 /* enable the high 8 bit vid check on 5325 */
 417                 if (is5325(dev) && enable)
 418                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 419                                    VC3_HIGH_8BIT_EN);
 420                 else
 421                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 422
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 425         } else if (is63xx(dev)) {
 426                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 427                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 428                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 429         } else {
 430                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 431                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 432                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 433         }
 434
 435         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 436
 437         dev->vlan_enabled = enable;
 438 }
 439
 440 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 441 {
 442         u32 port_mask = 0;
 443         u16 max_size = JMS_MIN_SIZE;
 444
 445         if (is5325(dev) || is5365(dev))
 446                 return -EINVAL;
 447
 448         if (enable) {
 449                 port_mask = dev->enabled_ports;
 450                 max_size = JMS_MAX_SIZE;
 451                 if (allow_10_100)
 452                         port_mask |= JPM_10_100_JUMBO_EN;
 453         }
 454
 455         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 456         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 457 }
 458
 459 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 460 {
 461         unsigned int i;
 462
 463         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 464                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 465
 466         for (i = 0; i < 10; i++) {
 467                 u8 fast_age_ctrl;
 468
 469                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 470                           &fast_age_ctrl);
 471
 472                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 473                         goto out;
 474
 475                 msleep(1);
 476         }
 477
 478         return -ETIMEDOUT;
 479 out:
 480         /* Only age dynamic entries (default behavior) */
 481         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 482         return 0;
 483 }
 484
 485 static int b53_fast_age_port(struct b53_device *dev, int port)
 486 {
 487         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 488
 489         return b53_flush_arl(dev, FAST_AGE_PORT);
 490 }
 491
 492 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 493 {
 494         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 495
 496         return b53_flush_arl(dev, FAST_AGE_VLAN);
 497 }
 498
 499 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 500 {
 501         struct b53_device *dev = ds->priv;
 502         unsigned int i;
 503         u16 pvlan;
 504
 505         /* Enable the IMP port to be in the same VLAN as the other ports
 506          * on a per-port basis such that we only have Port i and IMP in
 507          * the same VLAN.
 508          */
 509         b53_for_each_port(dev, i) {
 510                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 511                 pvlan |= BIT(cpu_port);
 512                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 513         }
 514 }
 515 EXPORT_SYMBOL(b53_imp_vlan_setup);
 516
 517 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 518 {
 519         struct b53_device *dev = ds->priv;
 520         unsigned int cpu_port;
 521         int ret = 0;
 522         u16 pvlan;
 523
 524         if (!dsa_is_user_port(ds, port))
 525                 return 0;
 526
 527         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
 528
 529         if (dev->ops->irq_enable)
 530                 ret = dev->ops->irq_enable(dev, port);
 531         if (ret)
 532                 return ret;
 533
 534         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 535         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 536
 537         /* Set this port, and only this one to be in the default VLAN,
 538          * if member of a bridge, restore its membership prior to
 539          * bringing down this port.
 540          */
 541         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 542         pvlan &= ~0x1ff;
 543         pvlan |= BIT(port);
 544         pvlan |= dev->ports[port].vlan_ctl_mask;
 545         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 546
 547         b53_imp_vlan_setup(ds, cpu_port);
 548
 549         /* If EEE was enabled, restore it */
 550         if (dev->ports[port].eee.eee_enabled)
 551                 b53_eee_enable_set(ds, port, true);
 552
 553         return 0;
 554 }
 555 EXPORT_SYMBOL(b53_enable_port);
 556
 557 void b53_disable_port(struct dsa_switch *ds, int port)
 558 {
 559         struct b53_device *dev = ds->priv;
 560         u8 reg;
 561
 562         /* Disable Tx/Rx for the port */
 563         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 564         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 565         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 566
 567         if (dev->ops->irq_disable)
 568                 dev->ops->irq_disable(dev, port);
 569 }
 570 EXPORT_SYMBOL(b53_disable_port);
 571
 572 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 573 {
 574         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 575                          DSA_TAG_PROTO_NONE);
 576         struct b53_device *dev = ds->priv;
 577         u8 hdr_ctl, val;
 578         u16 reg;
 579
 580         /* Resolve which bit controls the Broadcom tag */
 581         switch (port) {
 582         case 8:
 583                 val = BRCM_HDR_P8_EN;
 584                 break;
 585         case 7:
 586                 val = BRCM_HDR_P7_EN;
 587                 break;
 588         case 5:
 589                 val = BRCM_HDR_P5_EN;
 590                 break;
 591         default:
 592                 val = 0;
 593                 break;
 594         }
 595
 596         /* Enable Broadcom tags for IMP port */
 597         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 598         if (tag_en)
 599                 hdr_ctl |= val;
 600         else
 601                 hdr_ctl &= ~val;
 602         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 603
 604         /* Registers below are only accessible on newer devices */
 605         if (!is58xx(dev))
 606                 return;
 607
 608         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 609          * allow us to tag outgoing frames
 610          */
 611         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 612         if (tag_en)
 613                 reg &= ~BIT(port);
 614         else
 615                 reg |= BIT(port);
 616         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 617
 618         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 619          * allow delivering frames to the per-port net_devices
 620          */
 621         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 622         if (tag_en)
 623                 reg &= ~BIT(port);
 624         else
 625                 reg |= BIT(port);
 626         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 627 }
 628 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 629
 630 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 631 {
 632         u8 port_ctrl;
 633
 634         /* BCM5325 CPU port is at 8 */
 635         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 636                 port = B53_CPU_PORT;
 637
 638         port_ctrl = PORT_CTRL_RX_BCST_EN |
 639                     PORT_CTRL_RX_MCST_EN |
 640                     PORT_CTRL_RX_UCST_EN;
 641         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 642
 643         b53_brcm_hdr_setup(dev->ds, port);
 644 }
 645
 646 static void b53_enable_mib(struct b53_device *dev)
 647 {
 648         u8 gc;
 649
 650         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 651         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 652         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 653 }
 654
 655 static u16 b53_default_pvid(struct b53_device *dev)
 656 {
 657         if (is5325(dev) || is5365(dev))
 658                 return 1;
 659         else
 660                 return 0;
 661 }
 662
 663 int b53_configure_vlan(struct dsa_switch *ds)
 664 {
 665         struct b53_device *dev = ds->priv;
 666         struct b53_vlan vl = { 0 };
 667         int i, def_vid;
 668
 669         def_vid = b53_default_pvid(dev);
 670
 671         /* clear all vlan entries */
 672         if (is5325(dev) || is5365(dev)) {
 673                 for (i = def_vid; i < dev->num_vlans; i++)
 674                         b53_set_vlan_entry(dev, i, &vl);
 675         } else {
 676                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 677         }
 678
 679         b53_enable_vlan(dev, false, ds->vlan_filtering);
 680
 681         b53_for_each_port(dev, i)
 682                 b53_write16(dev, B53_VLAN_PAGE,
 683                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 684
 685         if (!is5325(dev) && !is5365(dev))
 686                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 687
 688         return 0;
 689 }
 690 EXPORT_SYMBOL(b53_configure_vlan);
 691
 692 static void b53_switch_reset_gpio(struct b53_device *dev)
 693 {
 694         int gpio = dev->reset_gpio;
 695
 696         if (gpio < 0)
 697                 return;
 698
 699         /* Reset sequence: RESET low(50ms)->high(20ms)
 700          */
 701         gpio_set_value(gpio, 0);
 702         mdelay(50);
 703
 704         gpio_set_value(gpio, 1);
 705         mdelay(20);
 706
 707         dev->current_page = 0xff;
 708 }
 709
 710 static int b53_switch_reset(struct b53_device *dev)
 711 {
 712         unsigned int timeout = 1000;
 713         u8 mgmt, reg;
 714
 715         b53_switch_reset_gpio(dev);
 716
 717         if (is539x(dev)) {
 718                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 719                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 720         }
 721
 722         /* This is specific to 58xx devices here, do not use is58xx() which
 723          * covers the larger Starfigther 2 family, including 7445/7278 which
 724          * still use this driver as a library and need to perform the reset
 725          * earlier.
 726          */
 727         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 728             dev->chip_id == BCM583XX_DEVICE_ID) {
 729                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 730                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 731                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 732
 733                 do {
 734                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 735                         if (!(reg & SW_RST))
 736                                 break;
 737
 738                         usleep_range(1000, 2000);
 739                 } while (timeout-- > 0);
 740
 741                 if (timeout == 0)
 742                         return -ETIMEDOUT;
 743         }
 744
 745         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 746
 747         if (!(mgmt & SM_SW_FWD_EN)) {
 748                 mgmt &= ~SM_SW_FWD_MODE;
 749                 mgmt |= SM_SW_FWD_EN;
 750
 751                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 752                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 753
 754                 if (!(mgmt & SM_SW_FWD_EN)) {
 755                         dev_err(dev->dev, "Failed to enable switch!\n");
 756                         return -EINVAL;
 757                 }
 758         }
 759
 760         b53_enable_mib(dev);
 761
 762         return b53_flush_arl(dev, FAST_AGE_STATIC);
 763 }
 764
 765 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 766 {
 767         struct b53_device *priv = ds->priv;
 768         u16 value = 0;
 769         int ret;
 770
 771         if (priv->ops->phy_read16)
 772                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 773         else
 774                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 775                                  reg * 2, &value);
 776
 777         return ret ? ret : value;
 778 }
 779
 780 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 781 {
 782         struct b53_device *priv = ds->priv;
 783
 784         if (priv->ops->phy_write16)
 785                 return priv->ops->phy_write16(priv, addr, reg, val);
 786
 787         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 788 }
 789
 790 static int b53_reset_switch(struct b53_device *priv)
 791 {
 792         /* reset vlans */
 793         priv->enable_jumbo = false;
 794
 795         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 796         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 797
 798         priv->serdes_lane = B53_INVALID_LANE;
 799
 800         return b53_switch_reset(priv);
 801 }
 802
 803 static int b53_apply_config(struct b53_device *priv)
 804 {
 805         /* disable switching */
 806         b53_set_forwarding(priv, 0);
 807
 808         b53_configure_vlan(priv->ds);
 809
 810         /* enable switching */
 811         b53_set_forwarding(priv, 1);
 812
 813         return 0;
 814 }
 815
 816 static void b53_reset_mib(struct b53_device *priv)
 817 {
 818         u8 gc;
 819
 820         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 821
 822         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 823         msleep(1);
 824         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 825         msleep(1);
 826 }
 827
 828 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 829 {
 830         if (is5365(dev))
 831                 return b53_mibs_65;
 832         else if (is63xx(dev))
 833                 return b53_mibs_63xx;
 834         else if (is58xx(dev))
 835                 return b53_mibs_58xx;
 836         else
 837                 return b53_mibs;
 838 }
 839
 840 static unsigned int b53_get_mib_size(struct b53_device *dev)
 841 {
 842         if (is5365(dev))
 843                 return B53_MIBS_65_SIZE;
 844         else if (is63xx(dev))
 845                 return B53_MIBS_63XX_SIZE;
 846         else if (is58xx(dev))
 847                 return B53_MIBS_58XX_SIZE;
 848         else
 849                 return B53_MIBS_SIZE;
 850 }
 851
 852 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 853 {
 854         /* These ports typically do not have built-in PHYs */
 855         switch (port) {
 856         case B53_CPU_PORT_25:
 857         case 7:
 858         case B53_CPU_PORT:
 859                 return NULL;
 860         }
 861
 862         return mdiobus_get_phy(ds->slave_mii_bus, port);
 863 }
 864
 865 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 866                      uint8_t *data)
 867 {
 868         struct b53_device *dev = ds->priv;
 869         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 870         unsigned int mib_size = b53_get_mib_size(dev);
 871         struct phy_device *phydev;
 872         unsigned int i;
 873
 874         if (stringset == ETH_SS_STATS) {
 875                 for (i = 0; i < mib_size; i++)
 876                         strlcpy(data + i * ETH_GSTRING_LEN,
 877                                 mibs[i].name, ETH_GSTRING_LEN);
 878         } else if (stringset == ETH_SS_PHY_STATS) {
 879                 phydev = b53_get_phy_device(ds, port);
 880                 if (!phydev)
 881                         return;
 882
 883                 phy_ethtool_get_strings(phydev, data);
 884         }
 885 }
 886 EXPORT_SYMBOL(b53_get_strings);
 887
 888 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 889 {
 890         struct b53_device *dev = ds->priv;
 891         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 892         unsigned int mib_size = b53_get_mib_size(dev);
 893         const struct b53_mib_desc *s;
 894         unsigned int i;
 895         u64 val = 0;
 896
 897         if (is5365(dev) && port == 5)
 898                 port = 8;
 899
 900         mutex_lock(&dev->stats_mutex);
 901
 902         for (i = 0; i < mib_size; i++) {
 903                 s = &mibs[i];
 904
 905                 if (s->size == 8) {
 906                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 907                 } else {
 908                         u32 val32;
 909
 910                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 911                                    &val32);
 912                         val = val32;
 913                 }
 914                 data[i] = (u64)val;
 915         }
 916
 917         mutex_unlock(&dev->stats_mutex);
 918 }
 919 EXPORT_SYMBOL(b53_get_ethtool_stats);
 920
 921 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 922 {
 923         struct phy_device *phydev;
 924
 925         phydev = b53_get_phy_device(ds, port);
 926         if (!phydev)
 927                 return;
 928
 929         phy_ethtool_get_stats(phydev, NULL, data);
 930 }
 931 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 932
 933 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 934 {
 935         struct b53_device *dev = ds->priv;
 936         struct phy_device *phydev;
 937
 938         if (sset == ETH_SS_STATS) {
 939                 return b53_get_mib_size(dev);
 940         } else if (sset == ETH_SS_PHY_STATS) {
 941                 phydev = b53_get_phy_device(ds, port);
 942                 if (!phydev)
 943                         return 0;
 944
 945                 return phy_ethtool_get_sset_count(phydev);
 946         }
 947
 948         return 0;
 949 }
 950 EXPORT_SYMBOL(b53_get_sset_count);
 951
 952 static int b53_setup(struct dsa_switch *ds)
 953 {
 954         struct b53_device *dev = ds->priv;
 955         unsigned int port;
 956         int ret;
 957
 958         ret = b53_reset_switch(dev);
 959         if (ret) {
 960                 dev_err(ds->dev, "failed to reset switch\n");
 961                 return ret;
 962         }
 963
 964         b53_reset_mib(dev);
 965
 966         ret = b53_apply_config(dev);
 967         if (ret)
 968                 dev_err(ds->dev, "failed to apply configuration\n");
 969
 970         /* Configure IMP/CPU port, disable all other ports. Enabled
 971          * ports will be configured with .port_enable
 972          */
 973         for (port = 0; port < dev->num_ports; port++) {
 974                 if (dsa_is_cpu_port(ds, port))
 975                         b53_enable_cpu_port(dev, port);
 976                 else
 977                         b53_disable_port(ds, port);
 978         }
 979
 980         /* Let DSA handle the case were multiple bridges span the same switch
 981          * device and different VLAN awareness settings are requested, which
 982          * would be breaking filtering semantics for any of the other bridge
 983          * devices. (not hardware supported)
 984          */
 985         ds->vlan_filtering_is_global = true;
 986
 987         return ret;
 988 }
 989
 990 static void b53_force_link(struct b53_device *dev, int port, int link)
 991 {
 992         u8 reg, val, off;
 993
 994         /* Override the port settings */
 995         if (port == dev->cpu_port) {
 996                 off = B53_PORT_OVERRIDE_CTRL;
 997                 val = PORT_OVERRIDE_EN;
 998         } else {
 999                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1000                 val = GMII_PO_EN;
1001         }
1002
1003         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1004         reg |= val;
1005         if (link)
1006                 reg |= PORT_OVERRIDE_LINK;
1007         else
1008                 reg &= ~PORT_OVERRIDE_LINK;
1009         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1010 }
1011
1012 static void b53_force_port_config(struct b53_device *dev, int port,
1013                                   int speed, int duplex, int pause)
1014 {
1015         u8 reg, val, off;
1016
1017         /* Override the port settings */
1018         if (port == dev->cpu_port) {
1019                 off = B53_PORT_OVERRIDE_CTRL;
1020                 val = PORT_OVERRIDE_EN;
1021         } else {
1022                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1023                 val = GMII_PO_EN;
1024         }
1025
1026         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1027         reg |= val;
1028         if (duplex == DUPLEX_FULL)
1029                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1030         else
1031                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1032
1033         switch (speed) {
1034         case 2000:
1035                 reg |= PORT_OVERRIDE_SPEED_2000M;
1036                 /* fallthrough */
1037         case SPEED_1000:
1038                 reg |= PORT_OVERRIDE_SPEED_1000M;
1039                 break;
1040         case SPEED_100:
1041                 reg |= PORT_OVERRIDE_SPEED_100M;
1042                 break;
1043         case SPEED_10:
1044                 reg |= PORT_OVERRIDE_SPEED_10M;
1045                 break;
1046         default:
1047                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1048                 return;
1049         }
1050
1051         if (pause & MLO_PAUSE_RX)
1052                 reg |= PORT_OVERRIDE_RX_FLOW;
1053         if (pause & MLO_PAUSE_TX)
1054                 reg |= PORT_OVERRIDE_TX_FLOW;
1055
1056         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1057 }
1058
1059 static void b53_adjust_link(struct dsa_switch *ds, int port,
1060                             struct phy_device *phydev)
1061 {
1062         struct b53_device *dev = ds->priv;
1063         struct ethtool_eee *p = &dev->ports[port].eee;
1064         u8 rgmii_ctrl = 0, reg = 0, off;
1065         int pause = 0;
1066
1067         if (!phy_is_pseudo_fixed_link(phydev))
1068                 return;
1069
1070         /* Enable flow control on BCM5301x's CPU port */
1071         if (is5301x(dev) && port == dev->cpu_port)
1072                 pause = MLO_PAUSE_TXRX_MASK;
1073
1074         if (phydev->pause) {
1075                 if (phydev->asym_pause)
1076                         pause |= MLO_PAUSE_TX;
1077                 pause |= MLO_PAUSE_RX;
1078         }
1079
1080         b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause);
1081         b53_force_link(dev, port, phydev->link);
1082
1083         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1084                 if (port == 8)
1085                         off = B53_RGMII_CTRL_IMP;
1086                 else
1087                         off = B53_RGMII_CTRL_P(port);
1088
1089                 /* Configure the port RGMII clock delay by DLL disabled and
1090                  * tx_clk aligned timing (restoring to reset defaults)
1091                  */
1092                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1093                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1094                                 RGMII_CTRL_TIMING_SEL);
1095
1096                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1097                  * sure that we enable the port TX clock internal delay to
1098                  * account for this internal delay that is inserted, otherwise
1099                  * the switch won't be able to receive correctly.
1100                  *
1101                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1102                  * any delay neither on transmission nor reception, so the
1103                  * BCM53125 must also be configured accordingly to account for
1104                  * the lack of delay and introduce
1105                  *
1106                  * The BCM53125 switch has its RX clock and TX clock control
1107                  * swapped, hence the reason why we modify the TX clock path in
1108                  * the "RGMII" case
1109                  */
1110                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1111                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1112                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1113                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1114                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1115                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1116
1117                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1118                          phy_modes(phydev->interface));
1119         }
1120
1121         /* configure MII port if necessary */
1122         if (is5325(dev)) {
1123                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1124                           &reg);
1125
1126                 /* reverse mii needs to be enabled */
1127                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1128                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1129                                    reg | PORT_OVERRIDE_RV_MII_25);
1130                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1131                                   &reg);
1132
1133                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1134                                 dev_err(ds->dev,
1135                                         "Failed to enable reverse MII mode\n");
1136                                 return;
1137                         }
1138                 }
1139         } else if (is5301x(dev)) {
1140                 if (port != dev->cpu_port) {
1141                         b53_force_port_config(dev, dev->cpu_port, 2000,
1142                                               DUPLEX_FULL, MLO_PAUSE_TXRX_MASK);
1143                         b53_force_link(dev, dev->cpu_port, 1);
1144                 }
1145         }
1146
1147         /* Re-negotiate EEE if it was enabled already */
1148         p->eee_enabled = b53_eee_init(ds, port, phydev);
1149 }
1150
1151 void b53_port_event(struct dsa_switch *ds, int port)
1152 {
1153         struct b53_device *dev = ds->priv;
1154         bool link;
1155         u16 sts;
1156
1157         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1158         link = !!(sts & BIT(port));
1159         dsa_port_phylink_mac_change(ds, port, link);
1160 }
1161 EXPORT_SYMBOL(b53_port_event);
1162
1163 void b53_phylink_validate(struct dsa_switch *ds, int port,
1164                           unsigned long *supported,
1165                           struct phylink_link_state *state)
1166 {
1167         struct b53_device *dev = ds->priv;
1168         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1169
1170         if (dev->ops->serdes_phylink_validate)
1171                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1172
1173         /* Allow all the expected bits */
1174         phylink_set(mask, Autoneg);
1175         phylink_set_port_modes(mask);
1176         phylink_set(mask, Pause);
1177         phylink_set(mask, Asym_Pause);
1178
1179         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1180          * support Gigabit, including Half duplex.
1181          */
1182         if (state->interface != PHY_INTERFACE_MODE_MII &&
1183             state->interface != PHY_INTERFACE_MODE_REVMII &&
1184             !phy_interface_mode_is_8023z(state->interface) &&
1185             !(is5325(dev) || is5365(dev))) {
1186                 phylink_set(mask, 1000baseT_Full);
1187                 phylink_set(mask, 1000baseT_Half);
1188         }
1189
1190         if (!phy_interface_mode_is_8023z(state->interface)) {
1191                 phylink_set(mask, 10baseT_Half);
1192                 phylink_set(mask, 10baseT_Full);
1193                 phylink_set(mask, 100baseT_Half);
1194                 phylink_set(mask, 100baseT_Full);
1195         }
1196
1197         bitmap_and(supported, supported, mask,
1198                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1199         bitmap_and(state->advertising, state->advertising, mask,
1200                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1201
1202         phylink_helper_basex_speed(state);
1203 }
1204 EXPORT_SYMBOL(b53_phylink_validate);
1205
1206 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1207                                struct phylink_link_state *state)
1208 {
1209         struct b53_device *dev = ds->priv;
1210         int ret = -EOPNOTSUPP;
1211
1212         if ((phy_interface_mode_is_8023z(state->interface) ||
1213              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1214              dev->ops->serdes_link_state)
1215                 ret = dev->ops->serdes_link_state(dev, port, state);
1216
1217         return ret;
1218 }
1219 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1220
1221 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1222                             unsigned int mode,
1223                             const struct phylink_link_state *state)
1224 {
1225         struct b53_device *dev = ds->priv;
1226
1227         if (mode == MLO_AN_PHY)
1228                 return;
1229
1230         if (mode == MLO_AN_FIXED) {
1231                 b53_force_port_config(dev, port, state->speed,
1232                                       state->duplex, state->pause);
1233                 return;
1234         }
1235
1236         if ((phy_interface_mode_is_8023z(state->interface) ||
1237              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1238              dev->ops->serdes_config)
1239                 dev->ops->serdes_config(dev, port, mode, state);
1240 }
1241 EXPORT_SYMBOL(b53_phylink_mac_config);
1242
1243 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1244 {
1245         struct b53_device *dev = ds->priv;
1246
1247         if (dev->ops->serdes_an_restart)
1248                 dev->ops->serdes_an_restart(dev, port);
1249 }
1250 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1251
1252 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1253                                unsigned int mode,
1254                                phy_interface_t interface)
1255 {
1256         struct b53_device *dev = ds->priv;
1257
1258         if (mode == MLO_AN_PHY)
1259                 return;
1260
1261         if (mode == MLO_AN_FIXED) {
1262                 b53_force_link(dev, port, false);
1263                 return;
1264         }
1265
1266         if (phy_interface_mode_is_8023z(interface) &&
1267             dev->ops->serdes_link_set)
1268                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1269 }
1270 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1271
1272 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1273                              unsigned int mode,
1274                              phy_interface_t interface,
1275                              struct phy_device *phydev)
1276 {
1277         struct b53_device *dev = ds->priv;
1278
1279         if (mode == MLO_AN_PHY)
1280                 return;
1281
1282         if (mode == MLO_AN_FIXED) {
1283                 b53_force_link(dev, port, true);
1284                 return;
1285         }
1286
1287         if (phy_interface_mode_is_8023z(interface) &&
1288             dev->ops->serdes_link_set)
1289                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1290 }
1291 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1292
1293 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1294 {
1295         struct b53_device *dev = ds->priv;
1296         u16 pvid, new_pvid;
1297
1298         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1299         new_pvid = pvid;
1300         if (!vlan_filtering) {
1301                 /* Filtering is currently enabled, use the default PVID since
1302                  * the bridge does not expect tagging anymore
1303                  */
1304                 dev->ports[port].pvid = pvid;
1305                 new_pvid = b53_default_pvid(dev);
1306         } else {
1307                 /* Filtering is currently disabled, restore the previous PVID */
1308                 new_pvid = dev->ports[port].pvid;
1309         }
1310
1311         if (pvid != new_pvid)
1312                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1313                             new_pvid);
1314
1315         b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1316
1317         return 0;
1318 }
1319 EXPORT_SYMBOL(b53_vlan_filtering);
1320
1321 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1322                      const struct switchdev_obj_port_vlan *vlan)
1323 {
1324         struct b53_device *dev = ds->priv;
1325
1326         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1327                 return -EOPNOTSUPP;
1328
1329         if (vlan->vid_end > dev->num_vlans)
1330                 return -ERANGE;
1331
1332         b53_enable_vlan(dev, true, ds->vlan_filtering);
1333
1334         return 0;
1335 }
1336 EXPORT_SYMBOL(b53_vlan_prepare);
1337
1338 void b53_vlan_add(struct dsa_switch *ds, int port,
1339                   const struct switchdev_obj_port_vlan *vlan)
1340 {
1341         struct b53_device *dev = ds->priv;
1342         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1343         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1344         struct b53_vlan *vl;
1345         u16 vid;
1346
1347         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1348                 vl = &dev->vlans[vid];
1349
1350                 b53_get_vlan_entry(dev, vid, vl);
1351
1352                 vl->members |= BIT(port);
1353                 if (untagged && !dsa_is_cpu_port(ds, port))
1354                         vl->untag |= BIT(port);
1355                 else
1356                         vl->untag &= ~BIT(port);
1357
1358                 b53_set_vlan_entry(dev, vid, vl);
1359                 b53_fast_age_vlan(dev, vid);
1360         }
1361
1362         if (pvid && !dsa_is_cpu_port(ds, port)) {
1363                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1364                             vlan->vid_end);
1365                 b53_fast_age_vlan(dev, vid);
1366         }
1367 }
1368 EXPORT_SYMBOL(b53_vlan_add);
1369
1370 int b53_vlan_del(struct dsa_switch *ds, int port,
1371                  const struct switchdev_obj_port_vlan *vlan)
1372 {
1373         struct b53_device *dev = ds->priv;
1374         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1375         struct b53_vlan *vl;
1376         u16 vid;
1377         u16 pvid;
1378
1379         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1380
1381         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1382                 vl = &dev->vlans[vid];
1383
1384                 b53_get_vlan_entry(dev, vid, vl);
1385
1386                 vl->members &= ~BIT(port);
1387
1388                 if (pvid == vid)
1389                         pvid = b53_default_pvid(dev);
1390
1391                 if (untagged && !dsa_is_cpu_port(ds, port))
1392                         vl->untag &= ~(BIT(port));
1393
1394                 b53_set_vlan_entry(dev, vid, vl);
1395                 b53_fast_age_vlan(dev, vid);
1396         }
1397
1398         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1399         b53_fast_age_vlan(dev, pvid);
1400
1401         return 0;
1402 }
1403 EXPORT_SYMBOL(b53_vlan_del);
1404
1405 /* Address Resolution Logic routines */
1406 static int b53_arl_op_wait(struct b53_device *dev)
1407 {
1408         unsigned int timeout = 10;
1409         u8 reg;
1410
1411         do {
1412                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1413                 if (!(reg & ARLTBL_START_DONE))
1414                         return 0;
1415
1416                 usleep_range(1000, 2000);
1417         } while (timeout--);
1418
1419         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1420
1421         return -ETIMEDOUT;
1422 }
1423
1424 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1425 {
1426         u8 reg;
1427
1428         if (op > ARLTBL_RW)
1429                 return -EINVAL;
1430
1431         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1432         reg |= ARLTBL_START_DONE;
1433         if (op)
1434                 reg |= ARLTBL_RW;
1435         else
1436                 reg &= ~ARLTBL_RW;
1437         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1438
1439         return b53_arl_op_wait(dev);
1440 }
1441
1442 static int b53_arl_read(struct b53_device *dev, u64 mac,
1443                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1444                         bool is_valid)
1445 {
1446         unsigned int i;
1447         int ret;
1448
1449         ret = b53_arl_op_wait(dev);
1450         if (ret)
1451                 return ret;
1452
1453         /* Read the bins */
1454         for (i = 0; i < dev->num_arl_entries; i++) {
1455                 u64 mac_vid;
1456                 u32 fwd_entry;
1457
1458                 b53_read64(dev, B53_ARLIO_PAGE,
1459                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1460                 b53_read32(dev, B53_ARLIO_PAGE,
1461                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1462                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1463
1464                 if (!(fwd_entry & ARLTBL_VALID))
1465                         continue;
1466                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1467                         continue;
1468                 *idx = i;
1469         }
1470
1471         return -ENOENT;
1472 }
1473
1474 static int b53_arl_op(struct b53_device *dev, int op, int port,
1475                       const unsigned char *addr, u16 vid, bool is_valid)
1476 {
1477         struct b53_arl_entry ent;
1478         u32 fwd_entry;
1479         u64 mac, mac_vid = 0;
1480         u8 idx = 0;
1481         int ret;
1482
1483         /* Convert the array into a 64-bit MAC */
1484         mac = ether_addr_to_u64(addr);
1485
1486         /* Perform a read for the given MAC and VID */
1487         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1488         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1489
1490         /* Issue a read operation for this MAC */
1491         ret = b53_arl_rw_op(dev, 1);
1492         if (ret)
1493                 return ret;
1494
1495         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1496         /* If this is a read, just finish now */
1497         if (op)
1498                 return ret;
1499
1500         /* We could not find a matching MAC, so reset to a new entry */
1501         if (ret) {
1502                 fwd_entry = 0;
1503                 idx = 1;
1504         }
1505
1506         memset(&ent, 0, sizeof(ent));
1507         ent.port = port;
1508         ent.is_valid = is_valid;
1509         ent.vid = vid;
1510         ent.is_static = true;
1511         memcpy(ent.mac, addr, ETH_ALEN);
1512         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1513
1514         b53_write64(dev, B53_ARLIO_PAGE,
1515                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1516         b53_write32(dev, B53_ARLIO_PAGE,
1517                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1518
1519         return b53_arl_rw_op(dev, 0);
1520 }
1521
1522 int b53_fdb_add(struct dsa_switch *ds, int port,
1523                 const unsigned char *addr, u16 vid)
1524 {
1525         struct b53_device *priv = ds->priv;
1526
1527         /* 5325 and 5365 require some more massaging, but could
1528          * be supported eventually
1529          */
1530         if (is5325(priv) || is5365(priv))
1531                 return -EOPNOTSUPP;
1532
1533         return b53_arl_op(priv, 0, port, addr, vid, true);
1534 }
1535 EXPORT_SYMBOL(b53_fdb_add);
1536
1537 int b53_fdb_del(struct dsa_switch *ds, int port,
1538                 const unsigned char *addr, u16 vid)
1539 {
1540         struct b53_device *priv = ds->priv;
1541
1542         return b53_arl_op(priv, 0, port, addr, vid, false);
1543 }
1544 EXPORT_SYMBOL(b53_fdb_del);
1545
1546 static int b53_arl_search_wait(struct b53_device *dev)
1547 {
1548         unsigned int timeout = 1000;
1549         u8 reg;
1550
1551         do {
1552                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1553                 if (!(reg & ARL_SRCH_STDN))
1554                         return 0;
1555
1556                 if (reg & ARL_SRCH_VLID)
1557                         return 0;
1558
1559                 usleep_range(1000, 2000);
1560         } while (timeout--);
1561
1562         return -ETIMEDOUT;
1563 }
1564
1565 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1566                               struct b53_arl_entry *ent)
1567 {
1568         u64 mac_vid;
1569         u32 fwd_entry;
1570
1571         b53_read64(dev, B53_ARLIO_PAGE,
1572                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1573         b53_read32(dev, B53_ARLIO_PAGE,
1574                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1575         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1576 }
1577
1578 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1579                         dsa_fdb_dump_cb_t *cb, void *data)
1580 {
1581         if (!ent->is_valid)
1582                 return 0;
1583
1584         if (port != ent->port)
1585                 return 0;
1586
1587         return cb(ent->mac, ent->vid, ent->is_static, data);
1588 }
1589
1590 int b53_fdb_dump(struct dsa_switch *ds, int port,
1591                  dsa_fdb_dump_cb_t *cb, void *data)
1592 {
1593         struct b53_device *priv = ds->priv;
1594         struct b53_arl_entry results[2];
1595         unsigned int count = 0;
1596         int ret;
1597         u8 reg;
1598
1599         /* Start search operation */
1600         reg = ARL_SRCH_STDN;
1601         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1602
1603         do {
1604                 ret = b53_arl_search_wait(priv);
1605                 if (ret)
1606                         return ret;
1607
1608                 b53_arl_search_rd(priv, 0, &results[0]);
1609                 ret = b53_fdb_copy(port, &results[0], cb, data);
1610                 if (ret)
1611                         return ret;
1612
1613                 if (priv->num_arl_entries > 2) {
1614                         b53_arl_search_rd(priv, 1, &results[1]);
1615                         ret = b53_fdb_copy(port, &results[1], cb, data);
1616                         if (ret)
1617                                 return ret;
1618
1619                         if (!results[0].is_valid && !results[1].is_valid)
1620                                 break;
1621                 }
1622
1623         } while (count++ < 1024);
1624
1625         return 0;
1626 }
1627 EXPORT_SYMBOL(b53_fdb_dump);
1628
1629 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1630 {
1631         struct b53_device *dev = ds->priv;
1632         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1633         u16 pvlan, reg;
1634         unsigned int i;
1635
1636         /* Make this port leave the all VLANs join since we will have proper
1637          * VLAN entries from now on
1638          */
1639         if (is58xx(dev)) {
1640                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1641                 reg &= ~BIT(port);
1642                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1643                         reg &= ~BIT(cpu_port);
1644                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1645         }
1646
1647         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1648
1649         b53_for_each_port(dev, i) {
1650                 if (dsa_to_port(ds, i)->bridge_dev != br)
1651                         continue;
1652
1653                 /* Add this local port to the remote port VLAN control
1654                  * membership and update the remote port bitmask
1655                  */
1656                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1657                 reg |= BIT(port);
1658                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1659                 dev->ports[i].vlan_ctl_mask = reg;
1660
1661                 pvlan |= BIT(i);
1662         }
1663
1664         /* Configure the local port VLAN control membership to include
1665          * remote ports and update the local port bitmask
1666          */
1667         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1668         dev->ports[port].vlan_ctl_mask = pvlan;
1669
1670         return 0;
1671 }
1672 EXPORT_SYMBOL(b53_br_join);
1673
1674 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1675 {
1676         struct b53_device *dev = ds->priv;
1677         struct b53_vlan *vl = &dev->vlans[0];
1678         s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1679         unsigned int i;
1680         u16 pvlan, reg, pvid;
1681
1682         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1683
1684         b53_for_each_port(dev, i) {
1685                 /* Don't touch the remaining ports */
1686                 if (dsa_to_port(ds, i)->bridge_dev != br)
1687                         continue;
1688
1689                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1690                 reg &= ~BIT(port);
1691                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1692                 dev->ports[port].vlan_ctl_mask = reg;
1693
1694                 /* Prevent self removal to preserve isolation */
1695                 if (port != i)
1696                         pvlan &= ~BIT(i);
1697         }
1698
1699         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1700         dev->ports[port].vlan_ctl_mask = pvlan;
1701
1702         pvid = b53_default_pvid(dev);
1703
1704         /* Make this port join all VLANs without VLAN entries */
1705         if (is58xx(dev)) {
1706                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1707                 reg |= BIT(port);
1708                 if (!(reg & BIT(cpu_port)))
1709                         reg |= BIT(cpu_port);
1710                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1711         } else {
1712                 b53_get_vlan_entry(dev, pvid, vl);
1713                 vl->members |= BIT(port) | BIT(cpu_port);
1714                 vl->untag |= BIT(port) | BIT(cpu_port);
1715                 b53_set_vlan_entry(dev, pvid, vl);
1716         }
1717 }
1718 EXPORT_SYMBOL(b53_br_leave);
1719
1720 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1721 {
1722         struct b53_device *dev = ds->priv;
1723         u8 hw_state;
1724         u8 reg;
1725
1726         switch (state) {
1727         case BR_STATE_DISABLED:
1728                 hw_state = PORT_CTRL_DIS_STATE;
1729                 break;
1730         case BR_STATE_LISTENING:
1731                 hw_state = PORT_CTRL_LISTEN_STATE;
1732                 break;
1733         case BR_STATE_LEARNING:
1734                 hw_state = PORT_CTRL_LEARN_STATE;
1735                 break;
1736         case BR_STATE_FORWARDING:
1737                 hw_state = PORT_CTRL_FWD_STATE;
1738                 break;
1739         case BR_STATE_BLOCKING:
1740                 hw_state = PORT_CTRL_BLOCK_STATE;
1741                 break;
1742         default:
1743                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1744                 return;
1745         }
1746
1747         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1748         reg &= ~PORT_CTRL_STP_STATE_MASK;
1749         reg |= hw_state;
1750         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1751 }
1752 EXPORT_SYMBOL(b53_br_set_stp_state);
1753
1754 void b53_br_fast_age(struct dsa_switch *ds, int port)
1755 {
1756         struct b53_device *dev = ds->priv;
1757
1758         if (b53_fast_age_port(dev, port))
1759                 dev_err(ds->dev, "fast ageing failed\n");
1760 }
1761 EXPORT_SYMBOL(b53_br_fast_age);
1762
1763 int b53_br_egress_floods(struct dsa_switch *ds, int port,
1764                          bool unicast, bool multicast)
1765 {
1766         struct b53_device *dev = ds->priv;
1767         u16 uc, mc;
1768
1769         b53_read16(dev, B53_CTRL_PAGE, B53_UC_FWD_EN, &uc);
1770         if (unicast)
1771                 uc |= BIT(port);
1772         else
1773                 uc &= ~BIT(port);
1774         b53_write16(dev, B53_CTRL_PAGE, B53_UC_FWD_EN, uc);
1775
1776         b53_read16(dev, B53_CTRL_PAGE, B53_MC_FWD_EN, &mc);
1777         if (multicast)
1778                 mc |= BIT(port);
1779         else
1780                 mc &= ~BIT(port);
1781         b53_write16(dev, B53_CTRL_PAGE, B53_MC_FWD_EN, mc);
1782
1783         return 0;
1784
1785 }
1786 EXPORT_SYMBOL(b53_br_egress_floods);
1787
1788 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1789 {
1790         /* Broadcom switches will accept enabling Broadcom tags on the
1791          * following ports: 5, 7 and 8, any other port is not supported
1792          */
1793         switch (port) {
1794         case B53_CPU_PORT_25:
1795         case 7:
1796         case B53_CPU_PORT:
1797                 return true;
1798         }
1799
1800         return false;
1801 }
1802
1803 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1804 {
1805         bool ret = b53_possible_cpu_port(ds, port);
1806
1807         if (!ret)
1808                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1809                          port);
1810         return ret;
1811 }
1812
1813 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1814 {
1815         struct b53_device *dev = ds->priv;
1816
1817         /* Older models (5325, 5365) support a different tag format that we do
1818          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1819          * mode to be turned on which means we need to specifically manage ARL
1820          * misses on multicast addresses (TBD).
1821          */
1822         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1823             !b53_can_enable_brcm_tags(ds, port))
1824                 return DSA_TAG_PROTO_NONE;
1825
1826         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1827          * which requires us to use the prepended Broadcom tag type
1828          */
1829         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1830                 return DSA_TAG_PROTO_BRCM_PREPEND;
1831
1832         return DSA_TAG_PROTO_BRCM;
1833 }
1834 EXPORT_SYMBOL(b53_get_tag_protocol);
1835
1836 int b53_mirror_add(struct dsa_switch *ds, int port,
1837                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1838 {
1839         struct b53_device *dev = ds->priv;
1840         u16 reg, loc;
1841
1842         if (ingress)
1843                 loc = B53_IG_MIR_CTL;
1844         else
1845                 loc = B53_EG_MIR_CTL;
1846
1847         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1848         reg |= BIT(port);
1849         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1850
1851         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1852         reg &= ~CAP_PORT_MASK;
1853         reg |= mirror->to_local_port;
1854         reg |= MIRROR_EN;
1855         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1856
1857         return 0;
1858 }
1859 EXPORT_SYMBOL(b53_mirror_add);
1860
1861 void b53_mirror_del(struct dsa_switch *ds, int port,
1862                     struct dsa_mall_mirror_tc_entry *mirror)
1863 {
1864         struct b53_device *dev = ds->priv;
1865         bool loc_disable = false, other_loc_disable = false;
1866         u16 reg, loc;
1867
1868         if (mirror->ingress)
1869                 loc = B53_IG_MIR_CTL;
1870         else
1871                 loc = B53_EG_MIR_CTL;
1872
1873         /* Update the desired ingress/egress register */
1874         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1875         reg &= ~BIT(port);
1876         if (!(reg & MIRROR_MASK))
1877                 loc_disable = true;
1878         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1879
1880         /* Now look at the other one to know if we can disable mirroring
1881          * entirely
1882          */
1883         if (mirror->ingress)
1884                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1885         else
1886                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1887         if (!(reg & MIRROR_MASK))
1888                 other_loc_disable = true;
1889
1890         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1891         /* Both no longer have ports, let's disable mirroring */
1892         if (loc_disable && other_loc_disable) {
1893                 reg &= ~MIRROR_EN;
1894                 reg &= ~mirror->to_local_port;
1895         }
1896         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1897 }
1898 EXPORT_SYMBOL(b53_mirror_del);
1899
1900 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1901 {
1902         struct b53_device *dev = ds->priv;
1903         u16 reg;
1904
1905         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1906         if (enable)
1907                 reg |= BIT(port);
1908         else
1909                 reg &= ~BIT(port);
1910         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1911 }
1912 EXPORT_SYMBOL(b53_eee_enable_set);
1913
1914
1915 /* Returns 0 if EEE was not enabled, or 1 otherwise
1916  */
1917 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1918 {
1919         int ret;
1920
1921         ret = phy_init_eee(phy, 0);
1922         if (ret)
1923                 return 0;
1924
1925         b53_eee_enable_set(ds, port, true);
1926
1927         return 1;
1928 }
1929 EXPORT_SYMBOL(b53_eee_init);
1930
1931 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1932 {
1933         struct b53_device *dev = ds->priv;
1934         struct ethtool_eee *p = &dev->ports[port].eee;
1935         u16 reg;
1936
1937         if (is5325(dev) || is5365(dev))
1938                 return -EOPNOTSUPP;
1939
1940         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1941         e->eee_enabled = p->eee_enabled;
1942         e->eee_active = !!(reg & BIT(port));
1943
1944         return 0;
1945 }
1946 EXPORT_SYMBOL(b53_get_mac_eee);
1947
1948 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1949 {
1950         struct b53_device *dev = ds->priv;
1951         struct ethtool_eee *p = &dev->ports[port].eee;
1952
1953         if (is5325(dev) || is5365(dev))
1954                 return -EOPNOTSUPP;
1955
1956         p->eee_enabled = e->eee_enabled;
1957         b53_eee_enable_set(ds, port, e->eee_enabled);
1958
1959         return 0;
1960 }
1961 EXPORT_SYMBOL(b53_set_mac_eee);
1962
1963 static const struct dsa_switch_ops b53_switch_ops = {
1964         .get_tag_protocol       = b53_get_tag_protocol,
1965         .setup                  = b53_setup,
1966         .get_strings            = b53_get_strings,
1967         .get_ethtool_stats      = b53_get_ethtool_stats,
1968         .get_sset_count         = b53_get_sset_count,
1969         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1970         .phy_read               = b53_phy_read16,
1971         .phy_write              = b53_phy_write16,
1972         .adjust_link            = b53_adjust_link,
1973         .phylink_validate       = b53_phylink_validate,
1974         .phylink_mac_link_state = b53_phylink_mac_link_state,
1975         .phylink_mac_config     = b53_phylink_mac_config,
1976         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
1977         .phylink_mac_link_down  = b53_phylink_mac_link_down,
1978         .phylink_mac_link_up    = b53_phylink_mac_link_up,
1979         .port_enable            = b53_enable_port,
1980         .port_disable           = b53_disable_port,
1981         .get_mac_eee            = b53_get_mac_eee,
1982         .set_mac_eee            = b53_set_mac_eee,
1983         .port_bridge_join       = b53_br_join,
1984         .port_bridge_leave      = b53_br_leave,
1985         .port_stp_state_set     = b53_br_set_stp_state,
1986         .port_fast_age          = b53_br_fast_age,
1987         .port_egress_floods     = b53_br_egress_floods,
1988         .port_vlan_filtering    = b53_vlan_filtering,
1989         .port_vlan_prepare      = b53_vlan_prepare,
1990         .port_vlan_add          = b53_vlan_add,
1991         .port_vlan_del          = b53_vlan_del,
1992         .port_fdb_dump          = b53_fdb_dump,
1993         .port_fdb_add           = b53_fdb_add,
1994         .port_fdb_del           = b53_fdb_del,
1995         .port_mirror_add        = b53_mirror_add,
1996         .port_mirror_del        = b53_mirror_del,
1997 };
1998
1999 struct b53_chip_data {
2000         u32 chip_id;
2001         const char *dev_name;
2002         u16 vlans;
2003         u16 enabled_ports;
2004         u8 cpu_port;
2005         u8 vta_regs[3];
2006         u8 arl_entries;
2007         u8 duplex_reg;
2008         u8 jumbo_pm_reg;
2009         u8 jumbo_size_reg;
2010 };
2011
2012 #define B53_VTA_REGS    \
2013         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2014 #define B53_VTA_REGS_9798 \
2015         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2016 #define B53_VTA_REGS_63XX \
2017         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2018
2019 static const struct b53_chip_data b53_switch_chips[] = {
2020         {
2021                 .chip_id = BCM5325_DEVICE_ID,
2022                 .dev_name = "BCM5325",
2023                 .vlans = 16,
2024                 .enabled_ports = 0x1f,
2025                 .arl_entries = 2,
2026                 .cpu_port = B53_CPU_PORT_25,
2027                 .duplex_reg = B53_DUPLEX_STAT_FE,
2028         },
2029         {
2030                 .chip_id = BCM5365_DEVICE_ID,
2031                 .dev_name = "BCM5365",
2032                 .vlans = 256,
2033                 .enabled_ports = 0x1f,
2034                 .arl_entries = 2,
2035                 .cpu_port = B53_CPU_PORT_25,
2036                 .duplex_reg = B53_DUPLEX_STAT_FE,
2037         },
2038         {
2039                 .chip_id = BCM5389_DEVICE_ID,
2040                 .dev_name = "BCM5389",
2041                 .vlans = 4096,
2042                 .enabled_ports = 0x1f,
2043                 .arl_entries = 4,
2044                 .cpu_port = B53_CPU_PORT,
2045                 .vta_regs = B53_VTA_REGS,
2046                 .duplex_reg = B53_DUPLEX_STAT_GE,
2047                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2048                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2049         },
2050         {
2051                 .chip_id = BCM5395_DEVICE_ID,
2052                 .dev_name = "BCM5395",
2053                 .vlans = 4096,
2054                 .enabled_ports = 0x1f,
2055                 .arl_entries = 4,
2056                 .cpu_port = B53_CPU_PORT,
2057                 .vta_regs = B53_VTA_REGS,
2058                 .duplex_reg = B53_DUPLEX_STAT_GE,
2059                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2060                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2061         },
2062         {
2063                 .chip_id = BCM5397_DEVICE_ID,
2064                 .dev_name = "BCM5397",
2065                 .vlans = 4096,
2066                 .enabled_ports = 0x1f,
2067                 .arl_entries = 4,
2068                 .cpu_port = B53_CPU_PORT,
2069                 .vta_regs = B53_VTA_REGS_9798,
2070                 .duplex_reg = B53_DUPLEX_STAT_GE,
2071                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2072                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2073         },
2074         {
2075                 .chip_id = BCM5398_DEVICE_ID,
2076                 .dev_name = "BCM5398",
2077                 .vlans = 4096,
2078                 .enabled_ports = 0x7f,
2079                 .arl_entries = 4,
2080                 .cpu_port = B53_CPU_PORT,
2081                 .vta_regs = B53_VTA_REGS_9798,
2082                 .duplex_reg = B53_DUPLEX_STAT_GE,
2083                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2084                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2085         },
2086         {
2087                 .chip_id = BCM53115_DEVICE_ID,
2088                 .dev_name = "BCM53115",
2089                 .vlans = 4096,
2090                 .enabled_ports = 0x1f,
2091                 .arl_entries = 4,
2092                 .vta_regs = B53_VTA_REGS,
2093                 .cpu_port = B53_CPU_PORT,
2094                 .duplex_reg = B53_DUPLEX_STAT_GE,
2095                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2096                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2097         },
2098         {
2099                 .chip_id = BCM53125_DEVICE_ID,
2100                 .dev_name = "BCM53125",
2101                 .vlans = 4096,
2102                 .enabled_ports = 0xff,
2103                 .arl_entries = 4,
2104                 .cpu_port = B53_CPU_PORT,
2105                 .vta_regs = B53_VTA_REGS,
2106                 .duplex_reg = B53_DUPLEX_STAT_GE,
2107                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2108                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2109         },
2110         {
2111                 .chip_id = BCM53128_DEVICE_ID,
2112                 .dev_name = "BCM53128",
2113                 .vlans = 4096,
2114                 .enabled_ports = 0x1ff,
2115                 .arl_entries = 4,
2116                 .cpu_port = B53_CPU_PORT,
2117                 .vta_regs = B53_VTA_REGS,
2118                 .duplex_reg = B53_DUPLEX_STAT_GE,
2119                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2120                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2121         },
2122         {
2123                 .chip_id = BCM63XX_DEVICE_ID,
2124                 .dev_name = "BCM63xx",
2125                 .vlans = 4096,
2126                 .enabled_ports = 0, /* pdata must provide them */
2127                 .arl_entries = 4,
2128                 .cpu_port = B53_CPU_PORT,
2129                 .vta_regs = B53_VTA_REGS_63XX,
2130                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2131                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2132                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2133         },
2134         {
2135                 .chip_id = BCM53010_DEVICE_ID,
2136                 .dev_name = "BCM53010",
2137                 .vlans = 4096,
2138                 .enabled_ports = 0x1f,
2139                 .arl_entries = 4,
2140                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2141                 .vta_regs = B53_VTA_REGS,
2142                 .duplex_reg = B53_DUPLEX_STAT_GE,
2143                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2144                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2145         },
2146         {
2147                 .chip_id = BCM53011_DEVICE_ID,
2148                 .dev_name = "BCM53011",
2149                 .vlans = 4096,
2150                 .enabled_ports = 0x1bf,
2151                 .arl_entries = 4,
2152                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2153                 .vta_regs = B53_VTA_REGS,
2154                 .duplex_reg = B53_DUPLEX_STAT_GE,
2155                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2156                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2157         },
2158         {
2159                 .chip_id = BCM53012_DEVICE_ID,
2160                 .dev_name = "BCM53012",
2161                 .vlans = 4096,
2162                 .enabled_ports = 0x1bf,
2163                 .arl_entries = 4,
2164                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2165                 .vta_regs = B53_VTA_REGS,
2166                 .duplex_reg = B53_DUPLEX_STAT_GE,
2167                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2168                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2169         },
2170         {
2171                 .chip_id = BCM53018_DEVICE_ID,
2172                 .dev_name = "BCM53018",
2173                 .vlans = 4096,
2174                 .enabled_ports = 0x1f,
2175                 .arl_entries = 4,
2176                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2177                 .vta_regs = B53_VTA_REGS,
2178                 .duplex_reg = B53_DUPLEX_STAT_GE,
2179                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2180                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2181         },
2182         {
2183                 .chip_id = BCM53019_DEVICE_ID,
2184                 .dev_name = "BCM53019",
2185                 .vlans = 4096,
2186                 .enabled_ports = 0x1f,
2187                 .arl_entries = 4,
2188                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2189                 .vta_regs = B53_VTA_REGS,
2190                 .duplex_reg = B53_DUPLEX_STAT_GE,
2191                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2192                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2193         },
2194         {
2195                 .chip_id = BCM58XX_DEVICE_ID,
2196                 .dev_name = "BCM585xx/586xx/88312",
2197                 .vlans  = 4096,
2198                 .enabled_ports = 0x1ff,
2199                 .arl_entries = 4,
2200                 .cpu_port = B53_CPU_PORT,
2201                 .vta_regs = B53_VTA_REGS,
2202                 .duplex_reg = B53_DUPLEX_STAT_GE,
2203                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2204                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2205         },
2206         {
2207                 .chip_id = BCM583XX_DEVICE_ID,
2208                 .dev_name = "BCM583xx/11360",
2209                 .vlans = 4096,
2210                 .enabled_ports = 0x103,
2211                 .arl_entries = 4,
2212                 .cpu_port = B53_CPU_PORT,
2213                 .vta_regs = B53_VTA_REGS,
2214                 .duplex_reg = B53_DUPLEX_STAT_GE,
2215                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2216                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2217         },
2218         {
2219                 .chip_id = BCM7445_DEVICE_ID,
2220                 .dev_name = "BCM7445",
2221                 .vlans  = 4096,
2222                 .enabled_ports = 0x1ff,
2223                 .arl_entries = 4,
2224                 .cpu_port = B53_CPU_PORT,
2225                 .vta_regs = B53_VTA_REGS,
2226                 .duplex_reg = B53_DUPLEX_STAT_GE,
2227                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2228                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2229         },
2230         {
2231                 .chip_id = BCM7278_DEVICE_ID,
2232                 .dev_name = "BCM7278",
2233                 .vlans = 4096,
2234                 .enabled_ports = 0x1ff,
2235                 .arl_entries= 4,
2236                 .cpu_port = B53_CPU_PORT,
2237                 .vta_regs = B53_VTA_REGS,
2238                 .duplex_reg = B53_DUPLEX_STAT_GE,
2239                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2240                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2241         },
2242 };
2243
2244 static int b53_switch_init(struct b53_device *dev)
2245 {
2246         unsigned int i;
2247         int ret;
2248
2249         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2250                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2251
2252                 if (chip->chip_id == dev->chip_id) {
2253                         if (!dev->enabled_ports)
2254                                 dev->enabled_ports = chip->enabled_ports;
2255                         dev->name = chip->dev_name;
2256                         dev->duplex_reg = chip->duplex_reg;
2257                         dev->vta_regs[0] = chip->vta_regs[0];
2258                         dev->vta_regs[1] = chip->vta_regs[1];
2259                         dev->vta_regs[2] = chip->vta_regs[2];
2260                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2261                         dev->cpu_port = chip->cpu_port;
2262                         dev->num_vlans = chip->vlans;
2263                         dev->num_arl_entries = chip->arl_entries;
2264                         break;
2265                 }
2266         }
2267
2268         /* check which BCM5325x version we have */
2269         if (is5325(dev)) {
2270                 u8 vc4;
2271
2272                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2273
2274                 /* check reserved bits */
2275                 switch (vc4 & 3) {
2276                 case 1:
2277                         /* BCM5325E */
2278                         break;
2279                 case 3:
2280                         /* BCM5325F - do not use port 4 */
2281                         dev->enabled_ports &= ~BIT(4);
2282                         break;
2283                 default:
2284 /* On the BCM47XX SoCs this is the supported internal switch.*/
2285 #ifndef CONFIG_BCM47XX
2286                         /* BCM5325M */
2287                         return -EINVAL;
2288 #else
2289                         break;
2290 #endif
2291                 }
2292         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2293                 u64 strap_value;
2294
2295                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2296                 /* use second IMP port if GMII is enabled */
2297                 if (strap_value & SV_GMII_CTRL_115)
2298                         dev->cpu_port = 5;
2299         }
2300
2301         /* cpu port is always last */
2302         dev->num_ports = dev->cpu_port + 1;
2303         dev->enabled_ports |= BIT(dev->cpu_port);
2304
2305         /* Include non standard CPU port built-in PHYs to be probed */
2306         if (is539x(dev) || is531x5(dev)) {
2307                 for (i = 0; i < dev->num_ports; i++) {
2308                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2309                             !b53_possible_cpu_port(dev->ds, i))
2310                                 dev->ds->phys_mii_mask |= BIT(i);
2311                 }
2312         }
2313
2314         dev->ports = devm_kcalloc(dev->dev,
2315                                   dev->num_ports, sizeof(struct b53_port),
2316                                   GFP_KERNEL);
2317         if (!dev->ports)
2318                 return -ENOMEM;
2319
2320         dev->vlans = devm_kcalloc(dev->dev,
2321                                   dev->num_vlans, sizeof(struct b53_vlan),
2322                                   GFP_KERNEL);
2323         if (!dev->vlans)
2324                 return -ENOMEM;
2325
2326         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2327         if (dev->reset_gpio >= 0) {
2328                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2329                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2330                 if (ret)
2331                         return ret;
2332         }
2333
2334         return 0;
2335 }
2336
2337 struct b53_device *b53_switch_alloc(struct device *base,
2338                                     const struct b53_io_ops *ops,
2339                                     void *priv)
2340 {
2341         struct dsa_switch *ds;
2342         struct b53_device *dev;
2343
2344         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2345         if (!ds)
2346                 return NULL;
2347
2348         ds->dev = base;
2349         ds->num_ports = DSA_MAX_PORTS;
2350
2351         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2352         if (!dev)
2353                 return NULL;
2354
2355         ds->priv = dev;
2356         dev->dev = base;
2357
2358         dev->ds = ds;
2359         dev->priv = priv;
2360         dev->ops = ops;
2361         ds->ops = &b53_switch_ops;
2362         mutex_init(&dev->reg_mutex);
2363         mutex_init(&dev->stats_mutex);
2364
2365         return dev;
2366 }
2367 EXPORT_SYMBOL(b53_switch_alloc);
2368
2369 int b53_switch_detect(struct b53_device *dev)
2370 {
2371         u32 id32;
2372         u16 tmp;
2373         u8 id8;
2374         int ret;
2375
2376         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2377         if (ret)
2378                 return ret;
2379
2380         switch (id8) {
2381         case 0:
2382                 /* BCM5325 and BCM5365 do not have this register so reads
2383                  * return 0. But the read operation did succeed, so assume this
2384                  * is one of them.
2385                  *
2386                  * Next check if we can write to the 5325's VTA register; for
2387                  * 5365 it is read only.
2388                  */
2389                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2390                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2391
2392                 if (tmp == 0xf)
2393                         dev->chip_id = BCM5325_DEVICE_ID;
2394                 else
2395                         dev->chip_id = BCM5365_DEVICE_ID;
2396                 break;
2397         case BCM5389_DEVICE_ID:
2398         case BCM5395_DEVICE_ID:
2399         case BCM5397_DEVICE_ID:
2400         case BCM5398_DEVICE_ID:
2401                 dev->chip_id = id8;
2402                 break;
2403         default:
2404                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2405                 if (ret)
2406                         return ret;
2407
2408                 switch (id32) {
2409                 case BCM53115_DEVICE_ID:
2410                 case BCM53125_DEVICE_ID:
2411                 case BCM53128_DEVICE_ID:
2412                 case BCM53010_DEVICE_ID:
2413                 case BCM53011_DEVICE_ID:
2414                 case BCM53012_DEVICE_ID:
2415                 case BCM53018_DEVICE_ID:
2416                 case BCM53019_DEVICE_ID:
2417                         dev->chip_id = id32;
2418                         break;
2419                 default:
2420                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2421                                id8, id32);
2422                         return -ENODEV;
2423                 }
2424         }
2425
2426         if (dev->chip_id == BCM5325_DEVICE_ID)
2427                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2428                                  &dev->core_rev);
2429         else
2430                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2431                                  &dev->core_rev);
2432 }
2433 EXPORT_SYMBOL(b53_switch_detect);
2434
2435 int b53_switch_register(struct b53_device *dev)
2436 {
2437         int ret;
2438
2439         if (dev->pdata) {
2440                 dev->chip_id = dev->pdata->chip_id;
2441                 dev->enabled_ports = dev->pdata->enabled_ports;
2442         }
2443
2444         if (!dev->chip_id && b53_switch_detect(dev))
2445                 return -EINVAL;
2446
2447         ret = b53_switch_init(dev);
2448         if (ret)
2449                 return ret;
2450
2451         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2452
2453         return dsa_register_switch(dev->ds);
2454 }
2455 EXPORT_SYMBOL(b53_switch_register);
2456
2457 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2458 MODULE_DESCRIPTION("B53 switch library");
2459 MODULE_LICENSE("Dual BSD/GPL");