1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
5 // Copyright (c) 2019, 2020 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
15 #include <linux/bitfield.h>
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
21 #include <linux/of_device.h>
22 #include <linux/pm_runtime.h>
24 #include <asm/unaligned.h>
26 #include "mcp251xfd.h"
28 #define DEVICE_NAME "mcp251xfd"
30 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
31 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
32 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
34 .model = MCP251XFD_MODEL_MCP2517FD,
37 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
38 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
39 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
40 .model = MCP251XFD_MODEL_MCP2518FD,
43 /* Autodetect model, start with CRC enabled. */
44 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
45 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
46 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
47 .model = MCP251XFD_MODEL_MCP251XFD,
50 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
62 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
74 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
77 case MCP251XFD_MODEL_MCP2517FD:
79 case MCP251XFD_MODEL_MCP2518FD:
81 case MCP251XFD_MODEL_MCP251XFD:
88 static inline const char *
89 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
91 return __mcp251xfd_get_model_str(priv->devtype_data.model);
94 static const char *mcp251xfd_get_mode_str(const u8 mode)
97 case MCP251XFD_REG_CON_MODE_MIXED:
98 return "Mixed (CAN FD/CAN 2.0)";
99 case MCP251XFD_REG_CON_MODE_SLEEP:
101 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
102 return "Internal Loopback";
103 case MCP251XFD_REG_CON_MODE_LISTENONLY:
104 return "Listen Only";
105 case MCP251XFD_REG_CON_MODE_CONFIG:
106 return "Configuration";
107 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
108 return "External Loopback";
109 case MCP251XFD_REG_CON_MODE_CAN2_0:
111 case MCP251XFD_REG_CON_MODE_RESTRICTED:
112 return "Restricted Operation";
118 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
123 return regulator_enable(priv->reg_vdd);
126 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
131 return regulator_disable(priv->reg_vdd);
135 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
137 if (!priv->reg_xceiver)
140 return regulator_enable(priv->reg_xceiver);
144 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
146 if (!priv->reg_xceiver)
149 return regulator_disable(priv->reg_xceiver);
152 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
156 err = clk_prepare_enable(priv->clk);
160 err = mcp251xfd_vdd_enable(priv);
162 clk_disable_unprepare(priv->clk);
164 /* Wait for oscillator stabilisation time after power up */
165 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
166 2 * MCP251XFD_OSC_STAB_SLEEP_US);
171 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
175 err = mcp251xfd_vdd_disable(priv);
179 clk_disable_unprepare(priv->clk);
185 mcp251xfd_cmd_prepare_write_reg(const struct mcp251xfd_priv *priv,
186 union mcp251xfd_write_reg_buf *write_reg_buf,
187 const u16 reg, const u32 mask, const u32 val)
189 u8 first_byte, last_byte, len;
193 first_byte = mcp251xfd_first_byte_set(mask);
194 last_byte = mcp251xfd_last_byte_set(mask);
195 len = last_byte - first_byte + 1;
197 data = mcp251xfd_spi_cmd_write(priv, write_reg_buf, reg + first_byte);
198 val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
199 memcpy(data, &val_le32, len);
201 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) {
204 mcp251xfd_spi_cmd_crc_set_len_in_reg(&write_reg_buf->crc.cmd,
207 len += sizeof(write_reg_buf->crc.cmd);
208 crc = mcp251xfd_crc16_compute(&write_reg_buf->crc, len);
209 put_unaligned_be16(crc, (void *)write_reg_buf + len);
212 len += sizeof(write_reg_buf->crc.crc);
214 len += sizeof(write_reg_buf->nocrc.cmd);
221 mcp251xfd_tef_tail_get_from_chip(const struct mcp251xfd_priv *priv,
227 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFUA, &tef_ua);
231 *tef_tail = tef_ua / sizeof(struct mcp251xfd_hw_tef_obj);
237 mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv,
243 err = regmap_read(priv->map_reg,
244 MCP251XFD_REG_FIFOSTA(MCP251XFD_TX_FIFO),
249 *tx_tail = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta);
255 mcp251xfd_rx_head_get_from_chip(const struct mcp251xfd_priv *priv,
256 const struct mcp251xfd_rx_ring *ring,
262 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
267 *rx_head = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta);
273 mcp251xfd_rx_tail_get_from_chip(const struct mcp251xfd_priv *priv,
274 const struct mcp251xfd_rx_ring *ring,
280 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOUA(ring->fifo_nr),
285 fifo_ua -= ring->base - MCP251XFD_RAM_START;
286 *rx_tail = fifo_ua / ring->obj_size;
292 mcp251xfd_tx_ring_init_tx_obj(const struct mcp251xfd_priv *priv,
293 const struct mcp251xfd_tx_ring *ring,
294 struct mcp251xfd_tx_obj *tx_obj,
295 const u8 rts_buf_len,
298 struct spi_transfer *xfer;
302 addr = mcp251xfd_get_tx_obj_addr(ring, n);
303 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX)
304 mcp251xfd_spi_cmd_write_crc_set_addr(&tx_obj->buf.crc.cmd,
307 mcp251xfd_spi_cmd_write_nocrc(&tx_obj->buf.nocrc.cmd,
310 xfer = &tx_obj->xfer[0];
311 xfer->tx_buf = &tx_obj->buf;
312 xfer->len = 0; /* actual len is assigned on the fly */
314 xfer->cs_change_delay.value = 0;
315 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
317 /* FIFO request to send */
318 xfer = &tx_obj->xfer[1];
319 xfer->tx_buf = &ring->rts_buf;
320 xfer->len = rts_buf_len;
323 spi_message_init_with_transfers(&tx_obj->msg, tx_obj->xfer,
324 ARRAY_SIZE(tx_obj->xfer));
327 static void mcp251xfd_ring_init(struct mcp251xfd_priv *priv)
329 struct mcp251xfd_tx_ring *tx_ring;
330 struct mcp251xfd_rx_ring *rx_ring, *prev_rx_ring = NULL;
331 struct mcp251xfd_tx_obj *tx_obj;
345 tx_ring->base = mcp251xfd_get_tef_obj_addr(tx_ring->obj_num);
347 /* FIFO request to send */
348 addr = MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO);
349 val = MCP251XFD_REG_FIFOCON_TXREQ | MCP251XFD_REG_FIFOCON_UINC;
350 len = mcp251xfd_cmd_prepare_write_reg(priv, &tx_ring->rts_buf,
353 mcp251xfd_for_each_tx_obj(tx_ring, tx_obj, i)
354 mcp251xfd_tx_ring_init_tx_obj(priv, tx_ring, tx_obj, len, i);
357 mcp251xfd_for_each_rx_ring(priv, rx_ring, i) {
361 rx_ring->fifo_nr = MCP251XFD_RX_FIFO(i);
365 mcp251xfd_get_tx_obj_addr(tx_ring,
368 rx_ring->base = prev_rx_ring->base +
369 prev_rx_ring->obj_size *
370 prev_rx_ring->obj_num;
372 prev_rx_ring = rx_ring;
376 static void mcp251xfd_ring_free(struct mcp251xfd_priv *priv)
380 for (i = ARRAY_SIZE(priv->rx) - 1; i >= 0; i--) {
386 static int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv)
388 struct mcp251xfd_tx_ring *tx_ring;
389 struct mcp251xfd_rx_ring *rx_ring;
390 int tef_obj_size, tx_obj_size, rx_obj_size;
394 tef_obj_size = sizeof(struct mcp251xfd_hw_tef_obj);
395 /* listen-only mode works like FD mode */
396 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD)) {
397 tx_obj_num = MCP251XFD_TX_OBJ_NUM_CANFD;
398 tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_canfd);
399 rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_canfd);
401 tx_obj_num = MCP251XFD_TX_OBJ_NUM_CAN;
402 tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_can);
403 rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_can);
407 tx_ring->obj_num = tx_obj_num;
408 tx_ring->obj_size = tx_obj_size;
410 ram_free = MCP251XFD_RAM_SIZE - tx_obj_num *
411 (tef_obj_size + tx_obj_size);
414 i < ARRAY_SIZE(priv->rx) && ram_free >= rx_obj_size;
418 rx_obj_num = ram_free / rx_obj_size;
419 rx_obj_num = min(1 << (fls(rx_obj_num) - 1), 32);
421 rx_ring = kzalloc(sizeof(*rx_ring) + rx_obj_size * rx_obj_num,
424 mcp251xfd_ring_free(priv);
427 rx_ring->obj_num = rx_obj_num;
428 rx_ring->obj_size = rx_obj_size;
429 priv->rx[i] = rx_ring;
431 ram_free -= rx_ring->obj_num * rx_ring->obj_size;
433 priv->rx_ring_num = i;
435 netdev_dbg(priv->ndev,
436 "FIFO setup: TEF: %d*%d bytes = %d bytes, TX: %d*%d bytes = %d bytes\n",
437 tx_obj_num, tef_obj_size, tef_obj_size * tx_obj_num,
438 tx_obj_num, tx_obj_size, tx_obj_size * tx_obj_num);
440 mcp251xfd_for_each_rx_ring(priv, rx_ring, i) {
441 netdev_dbg(priv->ndev,
442 "FIFO setup: RX-%d: %d*%d bytes = %d bytes\n",
443 i, rx_ring->obj_num, rx_ring->obj_size,
444 rx_ring->obj_size * rx_ring->obj_num);
447 netdev_dbg(priv->ndev,
448 "FIFO setup: free: %d bytes\n",
455 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
460 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
464 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
470 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
471 const u8 mode_req, bool nowait)
476 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
477 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
478 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
482 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
485 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
486 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
488 MCP251XFD_POLL_SLEEP_US,
489 MCP251XFD_POLL_TIMEOUT_US);
491 u8 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
493 netdev_err(priv->ndev,
494 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u).\n",
495 mcp251xfd_get_mode_str(mode_req), mode_req,
496 mcp251xfd_get_mode_str(mode), mode);
504 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
507 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
511 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
514 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
517 static inline bool mcp251xfd_osc_invalid(u32 reg)
519 return reg == 0x0 || reg == 0xffffffff;
522 static int mcp251xfd_chip_clock_enable(const struct mcp251xfd_priv *priv)
524 u32 osc, osc_reference, osc_mask;
527 /* Set Power On Defaults for "Clock Output Divisor" and remove
528 * "Oscillator Disable" bit.
530 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
531 MCP251XFD_REG_OSC_CLKODIV_10);
532 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
533 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
537 * If the controller is in Sleep Mode the following write only
538 * removes the "Oscillator Disable" bit and powers it up. All
539 * other bits are unaffected.
541 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
545 /* Wait for "Oscillator Ready" bit */
546 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
547 (osc & osc_mask) == osc_reference,
548 MCP251XFD_OSC_STAB_SLEEP_US,
549 MCP251XFD_OSC_STAB_TIMEOUT_US);
550 if (mcp251xfd_osc_invalid(osc)) {
551 netdev_err(priv->ndev,
552 "Failed to detect %s (osc=0x%08x).\n",
553 mcp251xfd_get_model_str(priv), osc);
555 } else if (err == -ETIMEDOUT) {
556 netdev_err(priv->ndev,
557 "Timeout waiting for Oscillator Ready (osc=0x%08x, osc_reference=0x%08x)\n",
567 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
569 const __be16 cmd = mcp251xfd_cmd_reset();
572 /* The Set Mode and SPI Reset command only seems to works if
573 * the controller is not in Sleep Mode.
575 err = mcp251xfd_chip_clock_enable(priv);
579 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
583 /* spi_write_then_read() works with non DMA-safe buffers */
584 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
587 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
589 u32 osc, osc_reference;
593 err = mcp251xfd_chip_get_mode(priv, &mode);
597 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
598 netdev_info(priv->ndev,
599 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
600 mcp251xfd_get_mode_str(mode), mode);
604 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
605 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
606 MCP251XFD_REG_OSC_CLKODIV_10);
608 /* check reset defaults of OSC reg */
609 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
613 if (osc != osc_reference) {
614 netdev_info(priv->ndev,
615 "Controller failed to reset. osc=0x%08x, reference value=0x%08x\n",
623 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
627 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
629 netdev_info(priv->ndev,
630 "Retrying to reset Controller.\n");
632 err = mcp251xfd_chip_softreset_do(priv);
633 if (err == -ETIMEDOUT)
638 err = mcp251xfd_chip_softreset_check(priv);
639 if (err == -ETIMEDOUT)
653 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
658 /* Activate Low Power Mode on Oscillator Disable. This only
659 * works on the MCP2518FD. The MCP2517FD will go into normal
660 * Sleep Mode instead.
662 osc = MCP251XFD_REG_OSC_LPMEN |
663 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
664 MCP251XFD_REG_OSC_CLKODIV_10);
665 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
669 /* Set Time Base Counter Prescaler to 1.
671 * This means an overflow of the 32 bit Time Base Counter
672 * register at 40 MHz every 107 seconds.
674 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
675 MCP251XFD_REG_TSCON_TBCEN);
678 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
680 const struct can_bittiming *bt = &priv->can.bittiming;
681 const struct can_bittiming *dbt = &priv->can.data_bittiming;
686 /* CAN Control Register
688 * - no transmit bandwidth sharing
690 * - disable transmit queue
691 * - store in transmit FIFO event
692 * - transition to restricted operation mode on system error
693 * - ESI is transmitted recessive when ESI of message is high or
694 * CAN controller error passive
695 * - restricted retransmission attempts,
696 * use TQXCON_TXAT and FIFOCON_TXAT
697 * - wake-up filter bits T11FILTER
698 * - use CAN bus line filter for wakeup
699 * - protocol exception is treated as a form error
700 * - Do not compare data bytes
702 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
703 MCP251XFD_REG_CON_MODE_CONFIG) |
704 MCP251XFD_REG_CON_STEF |
705 MCP251XFD_REG_CON_ESIGM |
706 MCP251XFD_REG_CON_RTXAT |
707 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
708 MCP251XFD_REG_CON_WFT_T11FILTER) |
709 MCP251XFD_REG_CON_WAKFIL |
710 MCP251XFD_REG_CON_PXEDIS;
712 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
713 val |= MCP251XFD_REG_CON_ISOCRCEN;
715 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
719 /* Nominal Bit Time */
720 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
721 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
722 bt->prop_seg + bt->phase_seg1 - 1) |
723 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
724 bt->phase_seg2 - 1) |
725 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
727 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
731 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
735 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
736 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
737 dbt->prop_seg + dbt->phase_seg1 - 1) |
738 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
739 dbt->phase_seg2 - 1) |
740 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
742 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
746 /* Transmitter Delay Compensation */
747 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
749 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
750 MCP251XFD_REG_TDC_TDCMOD_AUTO) |
751 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
753 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
756 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
765 * - PIN1: GPIO Input/RX Interrupt
767 * PIN1 must be Input, otherwise there is a glitch on the
768 * rx-INT line. It happens between setting the PIN as output
769 * (in the first byte of the SPI transfer) and configuring the
770 * PIN as interrupt (in the last byte of the SPI transfer).
772 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
773 MCP251XFD_REG_IOCON_TRIS0;
774 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
777 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
788 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
789 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
790 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
794 mcp251xfd_chip_rx_fifo_init_one(const struct mcp251xfd_priv *priv,
795 const struct mcp251xfd_rx_ring *ring)
799 /* Enable RXOVIE on _all_ RX FIFOs, not just the last one.
801 * FIFOs hit by a RX MAB overflow and RXOVIE enabled will
802 * generate a RXOVIF, use this to properly detect RX MAB
805 fifo_con = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK,
807 MCP251XFD_REG_FIFOCON_RXTSEN |
808 MCP251XFD_REG_FIFOCON_RXOVIE |
809 MCP251XFD_REG_FIFOCON_TFNRFNIE;
811 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD))
812 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
813 MCP251XFD_REG_FIFOCON_PLSIZE_64);
815 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
816 MCP251XFD_REG_FIFOCON_PLSIZE_8);
818 return regmap_write(priv->map_reg,
819 MCP251XFD_REG_FIFOCON(ring->fifo_nr), fifo_con);
823 mcp251xfd_chip_rx_filter_init_one(const struct mcp251xfd_priv *priv,
824 const struct mcp251xfd_rx_ring *ring)
828 fltcon = MCP251XFD_REG_FLTCON_FLTEN(ring->nr) |
829 MCP251XFD_REG_FLTCON_FBP(ring->nr, ring->fifo_nr);
831 return regmap_update_bits(priv->map_reg,
832 MCP251XFD_REG_FLTCON(ring->nr >> 2),
833 MCP251XFD_REG_FLTCON_FLT_MASK(ring->nr),
837 static int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv)
839 const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
840 const struct mcp251xfd_rx_ring *rx_ring;
845 val = FIELD_PREP(MCP251XFD_REG_TEFCON_FSIZE_MASK,
846 tx_ring->obj_num - 1) |
847 MCP251XFD_REG_TEFCON_TEFTSEN |
848 MCP251XFD_REG_TEFCON_TEFOVIE |
849 MCP251XFD_REG_TEFCON_TEFNEIE;
851 err = regmap_write(priv->map_reg, MCP251XFD_REG_TEFCON, val);
856 val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK,
857 tx_ring->obj_num - 1) |
858 MCP251XFD_REG_FIFOCON_TXEN |
859 MCP251XFD_REG_FIFOCON_TXATIE;
861 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD))
862 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
863 MCP251XFD_REG_FIFOCON_PLSIZE_64);
865 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK,
866 MCP251XFD_REG_FIFOCON_PLSIZE_8);
868 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
869 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK,
870 MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT);
872 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK,
873 MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED);
875 err = regmap_write(priv->map_reg,
876 MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO),
882 mcp251xfd_for_each_rx_ring(priv, rx_ring, n) {
883 err = mcp251xfd_chip_rx_fifo_init_one(priv, rx_ring);
887 err = mcp251xfd_chip_rx_filter_init_one(priv, rx_ring);
895 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
897 struct mcp251xfd_ecc *ecc = &priv->ecc;
904 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
905 val = MCP251XFD_REG_ECCCON_ECCEN;
907 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
908 MCP251XFD_REG_ECCCON_ECCEN, val);
912 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
916 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
923 static inline void mcp251xfd_ecc_tefif_successful(struct mcp251xfd_priv *priv)
925 struct mcp251xfd_ecc *ecc = &priv->ecc;
930 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
934 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
935 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
936 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
937 mode = MCP251XFD_REG_CON_MODE_MIXED;
939 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
945 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
950 mode = mcp251xfd_get_normal_mode(priv);
952 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
956 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
958 return __mcp251xfd_chip_set_normal_mode(priv, false);
962 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
964 return __mcp251xfd_chip_set_normal_mode(priv, true);
967 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
972 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
973 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
977 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
978 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
982 val = MCP251XFD_REG_INT_CERRIE |
983 MCP251XFD_REG_INT_SERRIE |
984 MCP251XFD_REG_INT_RXOVIE |
985 MCP251XFD_REG_INT_TXATIE |
986 MCP251XFD_REG_INT_SPICRCIE |
987 MCP251XFD_REG_INT_ECCIE |
988 MCP251XFD_REG_INT_TEFIE |
989 MCP251XFD_REG_INT_MODIE |
990 MCP251XFD_REG_INT_RXIE;
992 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
993 val |= MCP251XFD_REG_INT_IVMIE;
995 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
998 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
1003 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
1007 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
1008 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
1013 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
1016 static int mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
1017 const enum can_state state)
1019 priv->can.state = state;
1021 mcp251xfd_chip_interrupts_disable(priv);
1022 mcp251xfd_chip_rx_int_disable(priv);
1023 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
1026 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
1030 err = mcp251xfd_chip_softreset(priv);
1034 err = mcp251xfd_chip_clock_init(priv);
1038 err = mcp251xfd_set_bittiming(priv);
1042 err = mcp251xfd_chip_rx_int_enable(priv);
1046 err = mcp251xfd_chip_ecc_init(priv);
1050 mcp251xfd_ring_init(priv);
1052 err = mcp251xfd_chip_fifo_init(priv);
1056 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1058 err = mcp251xfd_chip_set_normal_mode(priv);
1065 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1070 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
1072 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1076 case CAN_MODE_START:
1077 err = mcp251xfd_chip_start(priv);
1081 err = mcp251xfd_chip_interrupts_enable(priv);
1083 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1087 netif_wake_queue(ndev);
1097 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
1098 struct can_berr_counter *bec)
1100 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
1104 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1108 if (trec & MCP251XFD_REG_TREC_TXBO)
1111 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
1112 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
1117 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
1118 struct can_berr_counter *bec)
1120 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
1122 /* Avoid waking up the controller if the interface is down */
1123 if (!(ndev->flags & IFF_UP))
1126 /* The controller is powered down during Bus Off, use saved
1129 if (priv->can.state == CAN_STATE_BUS_OFF) {
1134 return __mcp251xfd_get_berr_counter(ndev, bec);
1137 static int mcp251xfd_check_tef_tail(const struct mcp251xfd_priv *priv)
1139 u8 tef_tail_chip, tef_tail;
1142 if (!IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY))
1145 err = mcp251xfd_tef_tail_get_from_chip(priv, &tef_tail_chip);
1149 tef_tail = mcp251xfd_get_tef_tail(priv);
1150 if (tef_tail_chip != tef_tail) {
1151 netdev_err(priv->ndev,
1152 "TEF tail of chip (0x%02x) and ours (0x%08x) inconsistent.\n",
1153 tef_tail_chip, tef_tail);
1161 mcp251xfd_check_rx_tail(const struct mcp251xfd_priv *priv,
1162 const struct mcp251xfd_rx_ring *ring)
1164 u8 rx_tail_chip, rx_tail;
1167 if (!IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY))
1170 err = mcp251xfd_rx_tail_get_from_chip(priv, ring, &rx_tail_chip);
1174 rx_tail = mcp251xfd_get_rx_tail(ring);
1175 if (rx_tail_chip != rx_tail) {
1176 netdev_err(priv->ndev,
1177 "RX tail of chip (%d) and ours (%d) inconsistent.\n",
1178 rx_tail_chip, rx_tail);
1186 mcp251xfd_handle_tefif_recover(const struct mcp251xfd_priv *priv, const u32 seq)
1188 const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1192 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFSTA, &tef_sta);
1196 if (tef_sta & MCP251XFD_REG_TEFSTA_TEFOVIF) {
1197 netdev_err(priv->ndev,
1198 "Transmit Event FIFO buffer overflow.\n");
1202 netdev_info(priv->ndev,
1203 "Transmit Event FIFO buffer %s. (seq=0x%08x, tef_tail=0x%08x, tef_head=0x%08x, tx_head=0x%08x)\n",
1204 tef_sta & MCP251XFD_REG_TEFSTA_TEFFIF ?
1205 "full" : tef_sta & MCP251XFD_REG_TEFSTA_TEFNEIF ?
1206 "not empty" : "empty",
1207 seq, priv->tef.tail, priv->tef.head, tx_ring->head);
1209 /* The Sequence Number in the TEF doesn't match our tef_tail. */
1214 mcp251xfd_handle_tefif_one(struct mcp251xfd_priv *priv,
1215 const struct mcp251xfd_hw_tef_obj *hw_tef_obj)
1217 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1218 struct net_device_stats *stats = &priv->ndev->stats;
1219 u32 seq, seq_masked, tef_tail_masked;
1222 seq = FIELD_GET(MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK,
1225 /* Use the MCP2517FD mask on the MCP2518FD, too. We only
1226 * compare 7 bits, this should be enough to detect
1227 * net-yet-completed, i.e. old TEF objects.
1230 field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK);
1231 tef_tail_masked = priv->tef.tail &
1232 field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK);
1233 if (seq_masked != tef_tail_masked)
1234 return mcp251xfd_handle_tefif_recover(priv, seq);
1237 can_rx_offload_get_echo_skb(&priv->offload,
1238 mcp251xfd_get_tef_tail(priv),
1240 stats->tx_packets++;
1242 /* finally increment the TEF pointer */
1243 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_TEFCON,
1245 MCP251XFD_REG_TEFCON_UINC);
1252 return mcp251xfd_check_tef_tail(priv);
1255 static int mcp251xfd_tef_ring_update(struct mcp251xfd_priv *priv)
1257 const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1258 unsigned int new_head;
1262 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1266 /* chip_tx_tail, is the next TX-Object send by the HW.
1267 * The new TEF head must be >= the old head, ...
1269 new_head = round_down(priv->tef.head, tx_ring->obj_num) + chip_tx_tail;
1270 if (new_head <= priv->tef.head)
1271 new_head += tx_ring->obj_num;
1273 /* ... but it cannot exceed the TX head. */
1274 priv->tef.head = min(new_head, tx_ring->head);
1276 return mcp251xfd_check_tef_tail(priv);
1280 mcp251xfd_tef_obj_read(const struct mcp251xfd_priv *priv,
1281 struct mcp251xfd_hw_tef_obj *hw_tef_obj,
1282 const u8 offset, const u8 len)
1284 const struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1286 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
1287 (offset > tx_ring->obj_num ||
1288 len > tx_ring->obj_num ||
1289 offset + len > tx_ring->obj_num)) {
1290 netdev_err(priv->ndev,
1291 "Trying to read to many TEF objects (max=%d, offset=%d, len=%d).\n",
1292 tx_ring->obj_num, offset, len);
1296 return regmap_bulk_read(priv->map_rx,
1297 mcp251xfd_get_tef_obj_addr(offset),
1299 sizeof(*hw_tef_obj) / sizeof(u32) * len);
1302 static int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv)
1304 struct mcp251xfd_hw_tef_obj hw_tef_obj[MCP251XFD_TX_OBJ_NUM_MAX];
1305 u8 tef_tail, len, l;
1308 err = mcp251xfd_tef_ring_update(priv);
1312 tef_tail = mcp251xfd_get_tef_tail(priv);
1313 len = mcp251xfd_get_tef_len(priv);
1314 l = mcp251xfd_get_tef_linear_len(priv);
1315 err = mcp251xfd_tef_obj_read(priv, hw_tef_obj, tef_tail, l);
1320 err = mcp251xfd_tef_obj_read(priv, &hw_tef_obj[l], 0, len - l);
1325 for (i = 0; i < len; i++) {
1326 err = mcp251xfd_handle_tefif_one(priv, &hw_tef_obj[i]);
1327 /* -EAGAIN means the Sequence Number in the TEF
1328 * doesn't match our tef_tail. This can happen if we
1329 * read the TEF objects too early. Leave loop let the
1330 * interrupt handler call us again.
1333 goto out_netif_wake_queue;
1338 out_netif_wake_queue:
1339 mcp251xfd_ecc_tefif_successful(priv);
1341 if (mcp251xfd_get_tx_free(priv->tx)) {
1342 /* Make sure that anybody stopping the queue after
1343 * this sees the new tx_ring->tail.
1346 netif_wake_queue(priv->ndev);
1353 mcp251xfd_rx_ring_update(const struct mcp251xfd_priv *priv,
1354 struct mcp251xfd_rx_ring *ring)
1360 err = mcp251xfd_rx_head_get_from_chip(priv, ring, &chip_rx_head);
1364 /* chip_rx_head, is the next RX-Object filled by the HW.
1365 * The new RX head must be >= the old head.
1367 new_head = round_down(ring->head, ring->obj_num) + chip_rx_head;
1368 if (new_head <= ring->head)
1369 new_head += ring->obj_num;
1371 ring->head = new_head;
1373 return mcp251xfd_check_rx_tail(priv, ring);
1377 mcp251xfd_hw_rx_obj_to_skb(const struct mcp251xfd_priv *priv,
1378 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj,
1379 struct sk_buff *skb)
1381 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
1383 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_IDE) {
1386 eid = FIELD_GET(MCP251XFD_OBJ_ID_EID_MASK, hw_rx_obj->id);
1387 sid = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK, hw_rx_obj->id);
1389 cfd->can_id = CAN_EFF_FLAG |
1390 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_EID_MASK, eid) |
1391 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_SID_MASK, sid);
1393 cfd->can_id = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK,
1398 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF) {
1401 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_ESI)
1402 cfd->flags |= CANFD_ESI;
1404 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_BRS)
1405 cfd->flags |= CANFD_BRS;
1407 dlc = FIELD_GET(MCP251XFD_OBJ_FLAGS_DLC, hw_rx_obj->flags);
1408 cfd->len = can_dlc2len(get_canfd_dlc(dlc));
1410 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_RTR)
1411 cfd->can_id |= CAN_RTR_FLAG;
1413 cfd->len = get_can_dlc(FIELD_GET(MCP251XFD_OBJ_FLAGS_DLC,
1417 memcpy(cfd->data, hw_rx_obj->data, cfd->len);
1421 mcp251xfd_handle_rxif_one(struct mcp251xfd_priv *priv,
1422 struct mcp251xfd_rx_ring *ring,
1423 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj)
1425 struct net_device_stats *stats = &priv->ndev->stats;
1426 struct sk_buff *skb;
1427 struct canfd_frame *cfd;
1430 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF)
1431 skb = alloc_canfd_skb(priv->ndev, &cfd);
1433 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cfd);
1436 stats->rx_dropped++;
1440 mcp251xfd_hw_rx_obj_to_skb(priv, hw_rx_obj, skb);
1441 err = can_rx_offload_queue_sorted(&priv->offload, skb, hw_rx_obj->ts);
1443 stats->rx_fifo_errors++;
1447 /* finally increment the RX pointer */
1448 return regmap_update_bits(priv->map_reg,
1449 MCP251XFD_REG_FIFOCON(ring->fifo_nr),
1451 MCP251XFD_REG_FIFOCON_UINC);
1455 mcp251xfd_rx_obj_read(const struct mcp251xfd_priv *priv,
1456 const struct mcp251xfd_rx_ring *ring,
1457 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj,
1458 const u8 offset, const u8 len)
1462 err = regmap_bulk_read(priv->map_rx,
1463 mcp251xfd_get_rx_obj_addr(ring, offset),
1465 len * ring->obj_size / sizeof(u32));
1471 mcp251xfd_handle_rxif_ring(struct mcp251xfd_priv *priv,
1472 struct mcp251xfd_rx_ring *ring)
1474 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj = ring->obj;
1478 err = mcp251xfd_rx_ring_update(priv, ring);
1482 while ((len = mcp251xfd_get_rx_linear_len(ring))) {
1483 rx_tail = mcp251xfd_get_rx_tail(ring);
1485 err = mcp251xfd_rx_obj_read(priv, ring, hw_rx_obj,
1490 for (i = 0; i < len; i++) {
1491 err = mcp251xfd_handle_rxif_one(priv, ring,
1493 i * ring->obj_size);
1502 static int mcp251xfd_handle_rxif(struct mcp251xfd_priv *priv)
1504 struct mcp251xfd_rx_ring *ring;
1507 mcp251xfd_for_each_rx_ring(priv, ring, n) {
1508 err = mcp251xfd_handle_rxif_ring(priv, ring);
1516 static inline int mcp251xfd_get_timestamp(const struct mcp251xfd_priv *priv,
1519 return regmap_read(priv->map_reg, MCP251XFD_REG_TBC, timestamp);
1522 static struct sk_buff *
1523 mcp251xfd_alloc_can_err_skb(const struct mcp251xfd_priv *priv,
1524 struct can_frame **cf, u32 *timestamp)
1528 err = mcp251xfd_get_timestamp(priv, timestamp);
1532 return alloc_can_err_skb(priv->ndev, cf);
1535 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
1537 struct net_device_stats *stats = &priv->ndev->stats;
1538 struct mcp251xfd_rx_ring *ring;
1539 struct sk_buff *skb;
1540 struct can_frame *cf;
1541 u32 timestamp, rxovif;
1544 stats->rx_over_errors++;
1547 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
1551 mcp251xfd_for_each_rx_ring(priv, ring, i) {
1552 if (!(rxovif & BIT(ring->fifo_nr)))
1555 /* If SERRIF is active, there was a RX MAB overflow. */
1556 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
1557 netdev_info(priv->ndev,
1558 "RX-%d: MAB overflow detected.\n",
1561 netdev_info(priv->ndev,
1562 "RX-%d: FIFO overflow.\n", ring->nr);
1565 err = regmap_update_bits(priv->map_reg,
1566 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
1567 MCP251XFD_REG_FIFOSTA_RXOVIF,
1573 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
1577 cf->can_id |= CAN_ERR_CRTL;
1578 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
1580 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
1582 stats->rx_fifo_errors++;
1587 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
1589 netdev_info(priv->ndev, "%s\n", __func__);
1594 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
1596 struct net_device_stats *stats = &priv->ndev->stats;
1597 u32 bdiag1, timestamp;
1598 struct sk_buff *skb;
1599 struct can_frame *cf = NULL;
1602 err = mcp251xfd_get_timestamp(priv, ×tamp);
1606 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
1610 /* Write 0s to clear error bits, don't write 1s to non active
1611 * bits, as they will be set.
1613 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
1617 priv->can.can_stats.bus_error++;
1619 skb = alloc_can_err_skb(priv->ndev, &cf);
1621 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1623 /* Controller misconfiguration */
1624 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
1625 netdev_err(priv->ndev,
1626 "recv'd DLC is larger than PLSIZE of FIFO element.");
1629 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
1630 MCP251XFD_REG_BDIAG1_NCRCERR)) {
1631 netdev_dbg(priv->ndev, "CRC error\n");
1635 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1637 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
1638 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
1639 netdev_dbg(priv->ndev, "Stuff error\n");
1643 cf->data[2] |= CAN_ERR_PROT_STUFF;
1645 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1646 MCP251XFD_REG_BDIAG1_NFORMERR)) {
1647 netdev_dbg(priv->ndev, "Format error\n");
1651 cf->data[2] |= CAN_ERR_PROT_FORM;
1655 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1656 netdev_dbg(priv->ndev, "NACK error\n");
1660 cf->can_id |= CAN_ERR_ACK;
1661 cf->data[2] |= CAN_ERR_PROT_TX;
1664 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1665 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1666 netdev_dbg(priv->ndev, "Bit1 error\n");
1670 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1672 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1673 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1674 netdev_dbg(priv->ndev, "Bit0 error\n");
1678 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1684 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
1686 stats->rx_fifo_errors++;
1691 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1693 struct net_device_stats *stats = &priv->ndev->stats;
1694 struct sk_buff *skb;
1695 struct can_frame *cf = NULL;
1696 enum can_state new_state, rx_state, tx_state;
1697 u32 trec, timestamp;
1700 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1704 if (trec & MCP251XFD_REG_TREC_TXBO)
1705 tx_state = CAN_STATE_BUS_OFF;
1706 else if (trec & MCP251XFD_REG_TREC_TXBP)
1707 tx_state = CAN_STATE_ERROR_PASSIVE;
1708 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1709 tx_state = CAN_STATE_ERROR_WARNING;
1711 tx_state = CAN_STATE_ERROR_ACTIVE;
1713 if (trec & MCP251XFD_REG_TREC_RXBP)
1714 rx_state = CAN_STATE_ERROR_PASSIVE;
1715 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1716 rx_state = CAN_STATE_ERROR_WARNING;
1718 rx_state = CAN_STATE_ERROR_ACTIVE;
1720 new_state = max(tx_state, rx_state);
1721 if (new_state == priv->can.state)
1724 /* The skb allocation might fail, but can_change_state()
1725 * handles cf == NULL.
1727 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
1728 can_change_state(priv->ndev, cf, tx_state, rx_state);
1730 if (new_state == CAN_STATE_BUS_OFF) {
1731 /* As we're going to switch off the chip now, let's
1732 * save the error counters and return them to
1733 * userspace, if do_get_berr_counter() is called while
1734 * the chip is in Bus Off.
1736 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1740 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1741 can_bus_off(priv->ndev);
1747 if (new_state != CAN_STATE_BUS_OFF) {
1748 struct can_berr_counter bec;
1750 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1753 cf->data[6] = bec.txerr;
1754 cf->data[7] = bec.rxerr;
1757 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
1759 stats->rx_fifo_errors++;
1765 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1767 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1771 err = mcp251xfd_chip_get_mode(priv, &mode);
1775 if (mode == mode_reference) {
1776 netdev_dbg(priv->ndev,
1777 "Controller changed into %s Mode (%u).\n",
1778 mcp251xfd_get_mode_str(mode), mode);
1782 /* According to MCP2517FD errata DS80000792B 1., during a TX
1783 * MAB underflow, the controller will transition to Restricted
1784 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1786 * However this is not always the case. If SERR2LOM is
1787 * configured for Restricted Operation Mode (SERR2LOM not set)
1788 * the MCP2517FD will sometimes transition to Listen Only Mode
1789 * first. When polling this bit we see that it will transition
1790 * to Restricted Operation Mode shortly after.
1792 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1793 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1794 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1795 netdev_dbg(priv->ndev,
1796 "Controller changed into %s Mode (%u).\n",
1797 mcp251xfd_get_mode_str(mode), mode);
1799 netdev_err(priv->ndev,
1800 "Controller changed into %s Mode (%u).\n",
1801 mcp251xfd_get_mode_str(mode), mode);
1803 /* After the application requests Normal mode, the Controller
1804 * will automatically attempt to retransmit the message that
1805 * caused the TX MAB underflow.
1807 * However, if there is an ECC error in the TX-RAM, we first
1808 * have to reload the tx-object before requesting Normal
1809 * mode. This is done later in mcp251xfd_handle_eccif().
1811 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1812 *set_normal_mode = true;
1816 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1819 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1821 struct mcp251xfd_ecc *ecc = &priv->ecc;
1822 struct net_device_stats *stats = &priv->ndev->stats;
1823 bool handled = false;
1827 * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1828 * underflow is indicated by SERRIF and MODIF.
1830 * In addition to the effects mentioned in the Errata, there
1831 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1832 * will be seen as well.
1834 * Sometimes there is an ECC error in the TX-RAM, which leads
1835 * to a TX MAB underflow.
1837 * However, probably due to a race condition, there is no
1838 * associated MODIF pending.
1840 * Further, there are situations, where the SERRIF is caused
1841 * by an ECC error in the TX-RAM, but not even the ECCIF is
1842 * set. This only seems to happen _after_ the first occurrence
1843 * of a ECCIF (which is tracked in ecc->cnt).
1845 * Treat all as a known system errors..
1847 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1848 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1849 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1853 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1855 msg = "TX MAB underflow due to ECC error detected.";
1857 msg = "TX MAB underflow detected.";
1859 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1860 netdev_dbg(priv->ndev, "%s\n", msg);
1862 netdev_info(priv->ndev, "%s\n", msg);
1864 stats->tx_aborted_errors++;
1871 * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1872 * overflow is indicated by SERRIF.
1874 * In addition to the effects mentioned in the Errata, (most
1875 * of the times) a RXOVIF is raised, if the FIFO that is being
1876 * received into has the RXOVIE activated (and we have enabled
1877 * RXOVIE on all FIFOs).
1879 * Sometimes there is no RXOVIF just a RXIF is pending.
1881 * Treat all as a known system errors..
1883 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1884 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1885 stats->rx_dropped++;
1890 netdev_err(priv->ndev,
1891 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1892 priv->regs_status.intf);
1898 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1900 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1901 struct mcp251xfd_ecc *ecc = &priv->ecc;
1902 struct mcp251xfd_tx_obj *tx_obj;
1903 u8 chip_tx_tail, tx_tail, offset;
1907 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1909 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1913 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1914 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1916 /* Bail out if one of the following is met:
1917 * - tx_tail information is inconsistent
1918 * - for mcp2517fd: offset not 0
1919 * - for mcp2518fd: offset not 0 or 1
1921 if (chip_tx_tail != tx_tail ||
1922 !(offset == 0 || (offset == 1 && mcp251xfd_is_2518(priv)))) {
1923 netdev_err(priv->ndev,
1924 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1925 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1930 netdev_info(priv->ndev,
1931 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1932 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1933 "Single" : "Double",
1934 addr, nr, tx_ring->tail, tx_tail, offset);
1936 /* reload tx_obj into controller RAM ... */
1937 tx_obj = &tx_ring->obj[nr];
1938 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1942 /* ... and trigger retransmit */
1943 return mcp251xfd_chip_set_normal_mode(priv);
1947 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1949 struct mcp251xfd_ecc *ecc = &priv->ecc;
1957 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1961 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1962 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1966 /* Check if ECC error occurred in TX-RAM */
1967 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1968 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1971 else if (err == -ENOENT)
1976 /* Errata Reference:
1977 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1979 * ECC single error correction does not work in all cases:
1982 * Enable single error correction and double error detection
1983 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1984 * detection interrupt and do not rely on the error
1985 * correction. Instead, handle both interrupts as a
1986 * notification that the RAM word at ERRADDR was corrupted.
1988 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1989 msg = "Single ECC Error detected at address";
1990 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1991 msg = "Double ECC Error detected at address";
1998 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
2000 /* Re-occurring error? */
2001 if (ecc->ecc_stat == ecc_stat) {
2004 ecc->ecc_stat = ecc_stat;
2008 netdev_info(priv->ndev,
2009 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
2010 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
2012 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
2013 return mcp251xfd_handle_eccif_recover(priv, nr);
2016 if (set_normal_mode)
2017 return mcp251xfd_chip_set_normal_mode_nowait(priv);
2022 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
2027 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
2031 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
2032 MCP251XFD_REG_CRC_IF_MASK,
2037 if (crc & MCP251XFD_REG_CRC_FERRIF)
2038 netdev_notice(priv->ndev, "CRC write command format error.\n");
2039 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
2040 netdev_notice(priv->ndev,
2041 "CRC write error detected. CRC=0x%04lx.\n",
2042 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
2047 #define mcp251xfd_handle(priv, irq, ...) \
2049 struct mcp251xfd_priv *_priv = (priv); \
2052 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
2054 netdev_err(_priv->ndev, \
2055 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
2056 __stringify(irq), err); \
2060 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
2062 struct mcp251xfd_priv *priv = dev_id;
2063 irqreturn_t handled = IRQ_NONE;
2070 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
2074 err = mcp251xfd_handle(priv, rxif);
2078 handled = IRQ_HANDLED;
2082 u32 intf_pending, intf_pending_clearable;
2083 bool set_normal_mode = false;
2085 err = regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
2087 sizeof(priv->regs_status) /
2092 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
2093 priv->regs_status.intf) &
2094 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
2095 priv->regs_status.intf);
2097 if (!(intf_pending))
2100 /* Some interrupts must be ACKed in the
2101 * MCP251XFD_REG_INT register.
2102 * - First ACK then handle, to avoid lost-IRQ race
2103 * condition on fast re-occurring interrupts.
2104 * - Write "0" to clear active IRQs, "1" to all other,
2105 * to avoid r/m/w race condition on the
2106 * MCP251XFD_REG_INT register.
2108 intf_pending_clearable = intf_pending &
2109 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
2110 if (intf_pending_clearable) {
2111 err = regmap_update_bits(priv->map_reg,
2113 MCP251XFD_REG_INT_IF_MASK,
2114 ~intf_pending_clearable);
2119 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
2120 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
2125 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
2126 err = mcp251xfd_handle(priv, rxif);
2131 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
2132 err = mcp251xfd_handle(priv, tefif);
2137 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
2138 err = mcp251xfd_handle(priv, rxovif);
2143 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
2144 err = mcp251xfd_handle(priv, txatif);
2149 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
2150 err = mcp251xfd_handle(priv, ivmif);
2155 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
2156 err = mcp251xfd_handle(priv, serrif);
2161 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
2162 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
2167 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
2168 err = mcp251xfd_handle(priv, spicrcif);
2173 /* On the MCP2527FD and MCP2518FD, we don't get a
2174 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
2177 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
2178 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
2179 err = mcp251xfd_handle(priv, cerrif);
2183 /* In Bus Off we completely shut down the
2184 * controller. Every subsequent register read
2185 * will read bogus data, and if
2186 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
2187 * check will fail, too. So leave IRQ handler
2190 if (priv->can.state == CAN_STATE_BUS_OFF)
2194 handled = IRQ_HANDLED;
2198 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
2199 err, priv->regs_status.intf);
2200 mcp251xfd_chip_interrupts_disable(priv);
2205 static inline struct
2206 mcp251xfd_tx_obj *mcp251xfd_get_tx_obj_next(struct mcp251xfd_tx_ring *tx_ring)
2210 tx_head = mcp251xfd_get_tx_head(tx_ring);
2212 return &tx_ring->obj[tx_head];
2216 mcp251xfd_tx_obj_from_skb(const struct mcp251xfd_priv *priv,
2217 struct mcp251xfd_tx_obj *tx_obj,
2218 const struct sk_buff *skb,
2221 const struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
2222 struct mcp251xfd_hw_tx_obj_raw *hw_tx_obj;
2223 union mcp251xfd_tx_obj_load_buf *load_buf;
2228 if (cfd->can_id & CAN_EFF_FLAG) {
2231 sid = FIELD_GET(MCP251XFD_REG_FRAME_EFF_SID_MASK, cfd->can_id);
2232 eid = FIELD_GET(MCP251XFD_REG_FRAME_EFF_EID_MASK, cfd->can_id);
2234 id = FIELD_PREP(MCP251XFD_OBJ_ID_EID_MASK, eid) |
2235 FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, sid);
2237 flags = MCP251XFD_OBJ_FLAGS_IDE;
2239 id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, cfd->can_id);
2243 /* Use the MCP2518FD mask even on the MCP2517FD. It doesn't
2244 * harm, only the lower 7 bits will be transferred into the
2247 dlc = can_len2dlc(cfd->len);
2248 flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK, seq) |
2249 FIELD_PREP(MCP251XFD_OBJ_FLAGS_DLC, dlc);
2251 if (cfd->can_id & CAN_RTR_FLAG)
2252 flags |= MCP251XFD_OBJ_FLAGS_RTR;
2255 if (can_is_canfd_skb(skb)) {
2256 if (cfd->flags & CANFD_ESI)
2257 flags |= MCP251XFD_OBJ_FLAGS_ESI;
2259 flags |= MCP251XFD_OBJ_FLAGS_FDF;
2261 if (cfd->flags & CANFD_BRS)
2262 flags |= MCP251XFD_OBJ_FLAGS_BRS;
2265 load_buf = &tx_obj->buf;
2266 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX)
2267 hw_tx_obj = &load_buf->crc.hw_tx_obj;
2269 hw_tx_obj = &load_buf->nocrc.hw_tx_obj;
2271 put_unaligned_le32(id, &hw_tx_obj->id);
2272 put_unaligned_le32(flags, &hw_tx_obj->flags);
2274 /* Clear data at end of CAN frame */
2275 offset = round_down(cfd->len, sizeof(u32));
2276 len = round_up(can_dlc2len(dlc), sizeof(u32)) - offset;
2277 if (MCP251XFD_SANITIZE_CAN && len)
2278 memset(hw_tx_obj->data + offset, 0x0, len);
2279 memcpy(hw_tx_obj->data, cfd->data, cfd->len);
2281 /* Number of bytes to be written into the RAM of the controller */
2282 len = sizeof(hw_tx_obj->id) + sizeof(hw_tx_obj->flags);
2283 if (MCP251XFD_SANITIZE_CAN)
2284 len += round_up(can_dlc2len(dlc), sizeof(u32));
2286 len += round_up(cfd->len, sizeof(u32));
2288 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX) {
2291 mcp251xfd_spi_cmd_crc_set_len_in_ram(&load_buf->crc.cmd,
2294 len += sizeof(load_buf->crc.cmd);
2295 crc = mcp251xfd_crc16_compute(&load_buf->crc, len);
2296 put_unaligned_be16(crc, (void *)load_buf + len);
2299 len += sizeof(load_buf->crc.crc);
2301 len += sizeof(load_buf->nocrc.cmd);
2304 tx_obj->xfer[0].len = len;
2307 static int mcp251xfd_tx_obj_write(const struct mcp251xfd_priv *priv,
2308 struct mcp251xfd_tx_obj *tx_obj)
2310 return spi_async(priv->spi, &tx_obj->msg);
2313 static bool mcp251xfd_tx_busy(const struct mcp251xfd_priv *priv,
2314 struct mcp251xfd_tx_ring *tx_ring)
2316 if (mcp251xfd_get_tx_free(tx_ring) > 0)
2319 netif_stop_queue(priv->ndev);
2321 /* Memory barrier before checking tx_free (head and tail) */
2324 if (mcp251xfd_get_tx_free(tx_ring) == 0) {
2325 netdev_dbg(priv->ndev,
2326 "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n",
2327 tx_ring->head, tx_ring->tail,
2328 tx_ring->head - tx_ring->tail);
2333 netif_start_queue(priv->ndev);
2338 static netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb,
2339 struct net_device *ndev)
2341 struct mcp251xfd_priv *priv = netdev_priv(ndev);
2342 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
2343 struct mcp251xfd_tx_obj *tx_obj;
2347 if (can_dropped_invalid_skb(ndev, skb))
2348 return NETDEV_TX_OK;
2350 if (mcp251xfd_tx_busy(priv, tx_ring))
2351 return NETDEV_TX_BUSY;
2353 tx_obj = mcp251xfd_get_tx_obj_next(tx_ring);
2354 mcp251xfd_tx_obj_from_skb(priv, tx_obj, skb, tx_ring->head);
2356 /* Stop queue if we occupy the complete TX FIFO */
2357 tx_head = mcp251xfd_get_tx_head(tx_ring);
2359 if (tx_ring->head - tx_ring->tail >= tx_ring->obj_num)
2360 netif_stop_queue(ndev);
2362 can_put_echo_skb(skb, ndev, tx_head);
2364 err = mcp251xfd_tx_obj_write(priv, tx_obj);
2368 return NETDEV_TX_OK;
2371 netdev_err(priv->ndev, "ERROR in %s: %d\n", __func__, err);
2373 return NETDEV_TX_OK;
2376 static int mcp251xfd_open(struct net_device *ndev)
2378 struct mcp251xfd_priv *priv = netdev_priv(ndev);
2379 const struct spi_device *spi = priv->spi;
2382 err = pm_runtime_get_sync(ndev->dev.parent);
2384 pm_runtime_put_noidle(ndev->dev.parent);
2388 err = open_candev(ndev);
2390 goto out_pm_runtime_put;
2392 err = mcp251xfd_ring_alloc(priv);
2394 goto out_close_candev;
2396 err = mcp251xfd_transceiver_enable(priv);
2398 goto out_mcp251xfd_ring_free;
2400 err = mcp251xfd_chip_start(priv);
2402 goto out_transceiver_disable;
2404 can_rx_offload_enable(&priv->offload);
2406 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
2407 IRQF_ONESHOT, dev_name(&spi->dev),
2410 goto out_can_rx_offload_disable;
2412 err = mcp251xfd_chip_interrupts_enable(priv);
2416 netif_start_queue(ndev);
2421 free_irq(spi->irq, priv);
2422 out_can_rx_offload_disable:
2423 can_rx_offload_disable(&priv->offload);
2424 out_transceiver_disable:
2425 mcp251xfd_transceiver_disable(priv);
2426 out_mcp251xfd_ring_free:
2427 mcp251xfd_ring_free(priv);
2431 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
2432 pm_runtime_put(ndev->dev.parent);
2437 static int mcp251xfd_stop(struct net_device *ndev)
2439 struct mcp251xfd_priv *priv = netdev_priv(ndev);
2441 netif_stop_queue(ndev);
2442 mcp251xfd_chip_interrupts_disable(priv);
2443 free_irq(ndev->irq, priv);
2444 can_rx_offload_disable(&priv->offload);
2445 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
2446 mcp251xfd_transceiver_disable(priv);
2447 mcp251xfd_ring_free(priv);
2450 pm_runtime_put(ndev->dev.parent);
2455 static const struct net_device_ops mcp251xfd_netdev_ops = {
2456 .ndo_open = mcp251xfd_open,
2457 .ndo_stop = mcp251xfd_stop,
2458 .ndo_start_xmit = mcp251xfd_start_xmit,
2459 .ndo_change_mtu = can_change_mtu,
2463 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
2465 const struct spi_device *spi = priv->spi;
2466 const struct spi_controller *ctlr = spi->controller;
2468 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
2469 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
2472 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
2474 const struct net_device *ndev = priv->ndev;
2475 const struct mcp251xfd_devtype_data *devtype_data;
2479 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to
2480 * autodetect the model.
2482 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
2483 MCP251XFD_REG_OSC_LPMEN,
2484 MCP251XFD_REG_OSC_LPMEN);
2488 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
2492 if (osc & MCP251XFD_REG_OSC_LPMEN)
2493 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
2495 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
2497 if (!mcp251xfd_is_251X(priv) &&
2498 priv->devtype_data.model != devtype_data->model) {
2500 "Detected %s, but firmware specifies a %s. Fixing up.",
2501 __mcp251xfd_get_model_str(devtype_data->model),
2502 mcp251xfd_get_model_str(priv));
2504 priv->devtype_data = *devtype_data;
2506 /* We need to preserve the Half Duplex Quirk. */
2507 mcp251xfd_register_quirks(priv);
2509 /* Re-init regmap with quirks of detected model. */
2510 return mcp251xfd_regmap_init(priv);
2513 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
2515 int err, rx_pending;
2520 err = mcp251xfd_chip_rx_int_enable(priv);
2524 /* Check if RX_INT is properly working. The RX_INT should not
2525 * be active after a softreset.
2527 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
2529 err = mcp251xfd_chip_rx_int_disable(priv);
2536 netdev_info(priv->ndev,
2537 "RX_INT active after softreset, disabling RX_INT support.");
2538 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
2539 priv->rx_int = NULL;
2545 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv,
2546 u32 *dev_id, u32 *effective_speed_hz)
2548 struct mcp251xfd_map_buf_nocrc *buf_rx;
2549 struct mcp251xfd_map_buf_nocrc *buf_tx;
2550 struct spi_transfer xfer[2] = { };
2553 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
2557 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
2560 goto out_kfree_buf_rx;
2563 xfer[0].tx_buf = buf_tx;
2564 xfer[0].len = sizeof(buf_tx->cmd);
2565 xfer[1].rx_buf = buf_rx->data;
2566 xfer[1].len = sizeof(dev_id);
2568 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
2569 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
2571 goto out_kfree_buf_tx;
2573 *dev_id = be32_to_cpup((__be32 *)buf_rx->data);
2574 *effective_speed_hz = xfer->effective_speed_hz;
2584 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
2585 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
2588 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
2590 u32 dev_id, effective_speed_hz;
2593 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
2594 &effective_speed_hz);
2598 netdev_info(priv->ndev,
2599 "%s rev%lu.%lu (%cRX_INT %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD c:%u.%02uMHz m:%u.%02uMHz r:%u.%02uMHz e:%u.%02uMHz) successfully initialized.\n",
2600 mcp251xfd_get_model_str(priv),
2601 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
2602 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
2603 priv->rx_int ? '+' : '-',
2604 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
2605 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
2606 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
2607 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
2608 MCP251XFD_QUIRK_ACTIVE(ECC),
2609 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
2610 priv->can.clock.freq / 1000000,
2611 priv->can.clock.freq % 1000000 / 1000 / 10,
2612 priv->spi_max_speed_hz_orig / 1000000,
2613 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
2614 priv->spi->max_speed_hz / 1000000,
2615 priv->spi->max_speed_hz % 1000000 / 1000 / 10,
2616 effective_speed_hz / 1000000,
2617 effective_speed_hz % 1000000 / 1000 / 10);
2622 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
2624 struct net_device *ndev = priv->ndev;
2627 err = mcp251xfd_clks_and_vdd_enable(priv);
2631 pm_runtime_get_noresume(ndev->dev.parent);
2632 err = pm_runtime_set_active(ndev->dev.parent);
2634 goto out_runtime_put_noidle;
2635 pm_runtime_enable(ndev->dev.parent);
2637 mcp251xfd_register_quirks(priv);
2639 err = mcp251xfd_chip_softreset(priv);
2641 goto out_runtime_disable;
2643 goto out_chip_set_mode_sleep;
2645 err = mcp251xfd_register_chip_detect(priv);
2647 goto out_chip_set_mode_sleep;
2649 err = mcp251xfd_register_check_rx_int(priv);
2651 goto out_chip_set_mode_sleep;
2653 err = register_candev(ndev);
2655 goto out_chip_set_mode_sleep;
2657 err = mcp251xfd_register_done(priv);
2659 goto out_unregister_candev;
2661 /* Put controller into sleep mode and let pm_runtime_put()
2662 * disable the clocks and vdd. If CONFIG_PM is not enabled,
2663 * the clocks and vdd will stay powered.
2665 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
2667 goto out_unregister_candev;
2669 pm_runtime_put(ndev->dev.parent);
2673 out_unregister_candev:
2674 unregister_candev(ndev);
2675 out_chip_set_mode_sleep:
2676 mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
2677 out_runtime_disable:
2678 pm_runtime_disable(ndev->dev.parent);
2679 out_runtime_put_noidle:
2680 pm_runtime_put_noidle(ndev->dev.parent);
2681 mcp251xfd_clks_and_vdd_disable(priv);
2686 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
2688 struct net_device *ndev = priv->ndev;
2690 unregister_candev(ndev);
2692 pm_runtime_get_sync(ndev->dev.parent);
2693 pm_runtime_put_noidle(ndev->dev.parent);
2694 mcp251xfd_clks_and_vdd_disable(priv);
2695 pm_runtime_disable(ndev->dev.parent);
2698 static const struct of_device_id mcp251xfd_of_match[] = {
2700 .compatible = "microchip,mcp2517fd",
2701 .data = &mcp251xfd_devtype_data_mcp2517fd,
2703 .compatible = "microchip,mcp2518fd",
2704 .data = &mcp251xfd_devtype_data_mcp2518fd,
2706 .compatible = "microchip,mcp251xfd",
2707 .data = &mcp251xfd_devtype_data_mcp251xfd,
2712 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
2714 static const struct spi_device_id mcp251xfd_id_table[] = {
2716 .name = "mcp2517fd",
2717 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
2719 .name = "mcp2518fd",
2720 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
2722 .name = "mcp251xfd",
2723 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
2728 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
2730 static int mcp251xfd_probe(struct spi_device *spi)
2733 struct net_device *ndev;
2734 struct mcp251xfd_priv *priv;
2735 struct gpio_desc *rx_int;
2736 struct regulator *reg_vdd, *reg_xceiver;
2741 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2743 if (PTR_ERR(rx_int) == -EPROBE_DEFER)
2744 return -EPROBE_DEFER;
2745 else if (IS_ERR(rx_int))
2746 return PTR_ERR(rx_int);
2748 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2749 if (PTR_ERR(reg_vdd) == -EPROBE_DEFER)
2750 return -EPROBE_DEFER;
2751 else if (PTR_ERR(reg_vdd) == -ENODEV)
2753 else if (IS_ERR(reg_vdd))
2754 return PTR_ERR(reg_vdd);
2756 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2757 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2758 return -EPROBE_DEFER;
2759 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2761 else if (IS_ERR(reg_xceiver))
2762 return PTR_ERR(reg_xceiver);
2764 clk = devm_clk_get(&spi->dev, NULL);
2766 dev_err(&spi->dev, "No Oscillator (clock) defined.\n");
2767 return PTR_ERR(clk);
2769 freq = clk_get_rate(clk);
2772 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2773 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2775 "Oscillator frequency (%u Hz) is too low or high.\n",
2780 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) {
2782 "Oscillator frequency (%u Hz) is too low and PLL is not supported.\n",
2787 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2788 MCP251XFD_TX_OBJ_NUM_MAX);
2792 SET_NETDEV_DEV(ndev, &spi->dev);
2794 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2795 ndev->irq = spi->irq;
2796 ndev->flags |= IFF_ECHO;
2798 priv = netdev_priv(ndev);
2799 spi_set_drvdata(spi, priv);
2800 priv->can.clock.freq = freq;
2801 priv->can.do_set_mode = mcp251xfd_set_mode;
2802 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2803 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2804 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2805 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
2806 CAN_CTRLMODE_BERR_REPORTING | CAN_CTRLMODE_FD |
2807 CAN_CTRLMODE_FD_NON_ISO;
2810 priv->rx_int = rx_int;
2812 priv->reg_vdd = reg_vdd;
2813 priv->reg_xceiver = reg_xceiver;
2815 match = device_get_match_data(&spi->dev);
2817 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2819 priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2820 spi_get_device_id(spi)->driver_data;
2822 /* Errata Reference:
2823 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 4.
2825 * The SPI can write corrupted data to the RAM at fast SPI
2828 * Simultaneous activity on the CAN bus while writing data to
2829 * RAM via the SPI interface, with high SCK frequency, can
2830 * lead to corrupted data being written to RAM.
2833 * Ensure that FSCK is less than or equal to 0.85 *
2836 * Known good and bad combinations are:
2838 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk Status config
2840 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz good assigned-clocks = <&ccu CLK_SPIx>
2841 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 9375000 Hz 93.75% 600000000 Hz bad assigned-clocks = <&ccu CLK_SPIx>
2842 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz good assigned-clocks = <&ccu CLK_SPIx>
2843 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 18750000 Hz 93.75% 600000000 Hz bad assigned-clocks = <&ccu CLK_SPIx>
2844 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz good assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2845 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 9523809 Hz 95.34% 28571429 Hz bad assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2846 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz good default
2847 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz good default
2850 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2851 spi->max_speed_hz = min(spi->max_speed_hz, freq / 2 / 1000 * 850);
2852 spi->bits_per_word = 8;
2854 err = spi_setup(spi);
2856 goto out_free_candev;
2858 err = mcp251xfd_regmap_init(priv);
2860 goto out_free_candev;
2862 err = can_rx_offload_add_manual(ndev, &priv->offload,
2863 MCP251XFD_NAPI_WEIGHT);
2865 goto out_free_candev;
2867 err = mcp251xfd_register(priv);
2869 goto out_free_candev;
2874 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2881 static int mcp251xfd_remove(struct spi_device *spi)
2883 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2884 struct net_device *ndev = priv->ndev;
2886 can_rx_offload_del(&priv->offload);
2887 mcp251xfd_unregister(priv);
2888 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2894 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2896 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2898 return mcp251xfd_clks_and_vdd_disable(priv);
2901 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2903 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2905 return mcp251xfd_clks_and_vdd_enable(priv);
2908 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2909 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2910 mcp251xfd_runtime_resume, NULL)
2913 static struct spi_driver mcp251xfd_driver = {
2915 .name = DEVICE_NAME,
2916 .pm = &mcp251xfd_pm_ops,
2917 .of_match_table = mcp251xfd_of_match,
2919 .probe = mcp251xfd_probe,
2920 .remove = mcp251xfd_remove,
2921 .id_table = mcp251xfd_id_table,
2923 module_spi_driver(mcp251xfd_driver);
2925 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2926 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2927 MODULE_LICENSE("GPL v2");