1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * Your platform definition file should specify something like:
23 * static struct mcp251x_platform_data mcp251x_info = {
24 * .oscillator_frequency = 8000000,
27 * static struct spi_board_info spi_board_info[] = {
29 * .modalias = "mcp2510",
30 * // "mcp2515" or "mcp25625" depending on your controller
31 * .platform_data = &mcp251x_info,
33 * .max_speed_hz = 2*1000*1000,
38 * Please see mcp251x.h for a description of the fields in
39 * struct mcp251x_platform_data.
42 #include <linux/can/core.h>
43 #include <linux/can/dev.h>
44 #include <linux/can/led.h>
45 #include <linux/can/platform/mcp251x.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/freezer.h>
52 #include <linux/interrupt.h>
54 #include <linux/kernel.h>
55 #include <linux/module.h>
56 #include <linux/netdevice.h>
58 #include <linux/of_device.h>
59 #include <linux/platform_device.h>
60 #include <linux/slab.h>
61 #include <linux/spi/spi.h>
62 #include <linux/uaccess.h>
63 #include <linux/regulator/consumer.h>
65 /* SPI interface instruction set */
66 #define INSTRUCTION_WRITE 0x02
67 #define INSTRUCTION_READ 0x03
68 #define INSTRUCTION_BIT_MODIFY 0x05
69 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
70 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
71 #define INSTRUCTION_RESET 0xC0
75 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
78 /* MPC251x registers */
81 # define CANCTRL_REQOP_MASK 0xe0
82 # define CANCTRL_REQOP_CONF 0x80
83 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
84 # define CANCTRL_REQOP_LOOPBACK 0x40
85 # define CANCTRL_REQOP_SLEEP 0x20
86 # define CANCTRL_REQOP_NORMAL 0x00
87 # define CANCTRL_OSM 0x08
88 # define CANCTRL_ABAT 0x10
92 # define CNF1_SJW_SHIFT 6
94 # define CNF2_BTLMODE 0x80
95 # define CNF2_SAM 0x40
96 # define CNF2_PS1_SHIFT 3
98 # define CNF3_SOF 0x08
99 # define CNF3_WAKFIL 0x04
100 # define CNF3_PHSEG2_MASK 0x07
102 # define CANINTE_MERRE 0x80
103 # define CANINTE_WAKIE 0x40
104 # define CANINTE_ERRIE 0x20
105 # define CANINTE_TX2IE 0x10
106 # define CANINTE_TX1IE 0x08
107 # define CANINTE_TX0IE 0x04
108 # define CANINTE_RX1IE 0x02
109 # define CANINTE_RX0IE 0x01
111 # define CANINTF_MERRF 0x80
112 # define CANINTF_WAKIF 0x40
113 # define CANINTF_ERRIF 0x20
114 # define CANINTF_TX2IF 0x10
115 # define CANINTF_TX1IF 0x08
116 # define CANINTF_TX0IF 0x04
117 # define CANINTF_RX1IF 0x02
118 # define CANINTF_RX0IF 0x01
119 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
120 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
121 # define CANINTF_ERR (CANINTF_ERRIF)
123 # define EFLG_EWARN 0x01
124 # define EFLG_RXWAR 0x02
125 # define EFLG_TXWAR 0x04
126 # define EFLG_RXEP 0x08
127 # define EFLG_TXEP 0x10
128 # define EFLG_TXBO 0x20
129 # define EFLG_RX0OVR 0x40
130 # define EFLG_RX1OVR 0x80
131 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
132 # define TXBCTRL_ABTF 0x40
133 # define TXBCTRL_MLOA 0x20
134 # define TXBCTRL_TXERR 0x10
135 # define TXBCTRL_TXREQ 0x08
136 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
137 # define SIDH_SHIFT 3
138 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
139 # define SIDL_SID_MASK 7
140 # define SIDL_SID_SHIFT 5
141 # define SIDL_EXIDE_SHIFT 3
142 # define SIDL_EID_SHIFT 16
143 # define SIDL_EID_MASK 3
144 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
145 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
146 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
147 # define DLC_RTR_SHIFT 6
148 #define TXBCTRL_OFF 0
149 #define TXBSIDH_OFF 1
150 #define TXBSIDL_OFF 2
151 #define TXBEID8_OFF 3
152 #define TXBEID0_OFF 4
155 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
156 # define RXBCTRL_BUKT 0x04
157 # define RXBCTRL_RXM0 0x20
158 # define RXBCTRL_RXM1 0x40
159 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
160 # define RXBSIDH_SHIFT 3
161 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
162 # define RXBSIDL_IDE 0x08
163 # define RXBSIDL_SRR 0x10
164 # define RXBSIDL_EID 3
165 # define RXBSIDL_SHIFT 5
166 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
167 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
168 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
169 # define RXBDLC_LEN_MASK 0x0f
170 # define RXBDLC_RTR 0x40
171 #define RXBCTRL_OFF 0
172 #define RXBSIDH_OFF 1
173 #define RXBSIDL_OFF 2
174 #define RXBEID8_OFF 3
175 #define RXBEID0_OFF 4
178 #define RXFSID(n) ((n < 3) ? 0 : 4)
179 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
180 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
181 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
182 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
183 #define RXMSIDH(n) ((n) * 4 + 0x20)
184 #define RXMSIDL(n) ((n) * 4 + 0x21)
185 #define RXMEID8(n) ((n) * 4 + 0x22)
186 #define RXMEID0(n) ((n) * 4 + 0x23)
188 #define GET_BYTE(val, byte) \
189 (((val) >> ((byte) * 8)) & 0xff)
190 #define SET_BYTE(val, byte) \
191 (((val) & 0xff) << ((byte) * 8))
193 /* Buffer size required for the largest SPI transfer (i.e., reading a
196 #define CAN_FRAME_MAX_DATA_LEN 8
197 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
198 #define CAN_FRAME_MAX_BITS 128
200 #define TX_ECHO_SKB_MAX 1
202 #define MCP251X_OST_DELAY_MS (5)
204 #define DEVICE_NAME "mcp251x"
206 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
207 module_param(mcp251x_enable_dma, int, 0444);
208 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
210 static const struct can_bittiming_const mcp251x_bittiming_const = {
223 CAN_MCP251X_MCP2510 = 0x2510,
224 CAN_MCP251X_MCP2515 = 0x2515,
225 CAN_MCP251X_MCP25625 = 0x25625,
228 struct mcp251x_priv {
230 struct net_device *net;
231 struct spi_device *spi;
232 enum mcp251x_model model;
234 struct mutex mcp_lock; /* SPI device lock */
238 dma_addr_t spi_tx_dma;
239 dma_addr_t spi_rx_dma;
241 struct sk_buff *tx_skb;
244 struct workqueue_struct *wq;
245 struct work_struct tx_work;
246 struct work_struct restart_work;
250 #define AFTER_SUSPEND_UP 1
251 #define AFTER_SUSPEND_DOWN 2
252 #define AFTER_SUSPEND_POWER 4
253 #define AFTER_SUSPEND_RESTART 8
255 struct regulator *power;
256 struct regulator *transceiver;
260 #define MCP251X_IS(_model) \
261 static inline int mcp251x_is_##_model(struct spi_device *spi) \
263 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
264 return priv->model == CAN_MCP251X_MCP##_model; \
269 static void mcp251x_clean(struct net_device *net)
271 struct mcp251x_priv *priv = netdev_priv(net);
273 if (priv->tx_skb || priv->tx_len)
274 net->stats.tx_errors++;
276 dev_kfree_skb(priv->tx_skb);
278 can_free_echo_skb(priv->net, 0);
283 /* Note about handling of error return of mcp251x_spi_trans: accessing
284 * registers via SPI is not really different conceptually than using
285 * normal I/O assembler instructions, although it's much more
286 * complicated from a practical POV. So it's not advisable to always
287 * check the return value of this function. Imagine that every
288 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
289 * error();", it would be a great mess (well there are some situation
290 * when exception handling C++ like could be useful after all). So we
291 * just check that transfers are OK at the beginning of our
292 * conversation with the chip and to avoid doing really nasty things
293 * (like injecting bogus packets in the network stack).
295 static int mcp251x_spi_trans(struct spi_device *spi, int len)
297 struct mcp251x_priv *priv = spi_get_drvdata(spi);
298 struct spi_transfer t = {
299 .tx_buf = priv->spi_tx_buf,
300 .rx_buf = priv->spi_rx_buf,
304 struct spi_message m;
307 spi_message_init(&m);
309 if (mcp251x_enable_dma) {
310 t.tx_dma = priv->spi_tx_dma;
311 t.rx_dma = priv->spi_rx_dma;
315 spi_message_add_tail(&t, &m);
317 ret = spi_sync(spi, &m);
319 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
323 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
325 struct mcp251x_priv *priv = spi_get_drvdata(spi);
328 priv->spi_tx_buf[0] = INSTRUCTION_READ;
329 priv->spi_tx_buf[1] = reg;
331 mcp251x_spi_trans(spi, 3);
332 val = priv->spi_rx_buf[2];
337 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
338 uint8_t *v1, uint8_t *v2)
340 struct mcp251x_priv *priv = spi_get_drvdata(spi);
342 priv->spi_tx_buf[0] = INSTRUCTION_READ;
343 priv->spi_tx_buf[1] = reg;
345 mcp251x_spi_trans(spi, 4);
347 *v1 = priv->spi_rx_buf[2];
348 *v2 = priv->spi_rx_buf[3];
351 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
353 struct mcp251x_priv *priv = spi_get_drvdata(spi);
355 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
356 priv->spi_tx_buf[1] = reg;
357 priv->spi_tx_buf[2] = val;
359 mcp251x_spi_trans(spi, 3);
362 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
363 u8 mask, uint8_t val)
365 struct mcp251x_priv *priv = spi_get_drvdata(spi);
367 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
368 priv->spi_tx_buf[1] = reg;
369 priv->spi_tx_buf[2] = mask;
370 priv->spi_tx_buf[3] = val;
372 mcp251x_spi_trans(spi, 4);
375 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
376 int len, int tx_buf_idx)
378 struct mcp251x_priv *priv = spi_get_drvdata(spi);
380 if (mcp251x_is_2510(spi)) {
383 for (i = 1; i < TXBDAT_OFF + len; i++)
384 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
387 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
388 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
392 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
395 struct mcp251x_priv *priv = spi_get_drvdata(spi);
396 u32 sid, eid, exide, rtr;
397 u8 buf[SPI_TRANSFER_BUF_LEN];
399 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
401 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
403 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
404 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
405 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
407 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
408 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
409 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
410 (exide << SIDL_EXIDE_SHIFT) |
411 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
412 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
413 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
414 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
415 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
416 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
418 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
419 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
420 mcp251x_spi_trans(priv->spi, 1);
423 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
426 struct mcp251x_priv *priv = spi_get_drvdata(spi);
428 if (mcp251x_is_2510(spi)) {
431 for (i = 1; i < RXBDAT_OFF; i++)
432 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
434 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
435 for (; i < (RXBDAT_OFF + len); i++)
436 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
438 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
439 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
440 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
444 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
446 struct mcp251x_priv *priv = spi_get_drvdata(spi);
448 struct can_frame *frame;
449 u8 buf[SPI_TRANSFER_BUF_LEN];
451 skb = alloc_can_skb(priv->net, &frame);
453 dev_err(&spi->dev, "cannot allocate RX skb\n");
454 priv->net->stats.rx_dropped++;
458 mcp251x_hw_rx_frame(spi, buf, buf_idx);
459 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
460 /* Extended ID format */
461 frame->can_id = CAN_EFF_FLAG;
463 /* Extended ID part */
464 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
465 SET_BYTE(buf[RXBEID8_OFF], 1) |
466 SET_BYTE(buf[RXBEID0_OFF], 0) |
467 /* Standard ID part */
468 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
469 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
470 /* Remote transmission request */
471 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
472 frame->can_id |= CAN_RTR_FLAG;
474 /* Standard ID format */
476 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
477 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
478 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
479 frame->can_id |= CAN_RTR_FLAG;
482 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
483 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
485 priv->net->stats.rx_packets++;
486 priv->net->stats.rx_bytes += frame->can_dlc;
488 can_led_event(priv->net, CAN_LED_EVENT_RX);
493 static void mcp251x_hw_sleep(struct spi_device *spi)
495 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
498 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
499 struct net_device *net)
501 struct mcp251x_priv *priv = netdev_priv(net);
502 struct spi_device *spi = priv->spi;
504 if (priv->tx_skb || priv->tx_len) {
505 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
506 return NETDEV_TX_BUSY;
509 if (can_dropped_invalid_skb(net, skb))
512 netif_stop_queue(net);
514 queue_work(priv->wq, &priv->tx_work);
519 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
521 struct mcp251x_priv *priv = netdev_priv(net);
526 /* We have to delay work since SPI I/O may sleep */
527 priv->can.state = CAN_STATE_ERROR_ACTIVE;
528 priv->restart_tx = 1;
529 if (priv->can.restart_ms == 0)
530 priv->after_suspend = AFTER_SUSPEND_RESTART;
531 queue_work(priv->wq, &priv->restart_work);
540 static int mcp251x_set_normal_mode(struct spi_device *spi)
542 struct mcp251x_priv *priv = spi_get_drvdata(spi);
543 unsigned long timeout;
545 /* Enable interrupts */
546 mcp251x_write_reg(spi, CANINTE,
547 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
548 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
550 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
551 /* Put device into loopback mode */
552 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
553 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
554 /* Put device into listen-only mode */
555 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
557 /* Put device into normal mode */
558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
560 /* Wait for the device to enter normal mode */
561 timeout = jiffies + HZ;
562 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
564 if (time_after(jiffies, timeout)) {
565 dev_err(&spi->dev, "MCP251x didn't"
566 " enter in normal mode\n");
571 priv->can.state = CAN_STATE_ERROR_ACTIVE;
575 static int mcp251x_do_set_bittiming(struct net_device *net)
577 struct mcp251x_priv *priv = netdev_priv(net);
578 struct can_bittiming *bt = &priv->can.bittiming;
579 struct spi_device *spi = priv->spi;
581 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
583 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
584 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
586 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
588 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
589 (bt->phase_seg2 - 1));
590 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
591 mcp251x_read_reg(spi, CNF1),
592 mcp251x_read_reg(spi, CNF2),
593 mcp251x_read_reg(spi, CNF3));
598 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
600 mcp251x_do_set_bittiming(net);
602 mcp251x_write_reg(spi, RXBCTRL(0),
603 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
604 mcp251x_write_reg(spi, RXBCTRL(1),
605 RXBCTRL_RXM0 | RXBCTRL_RXM1);
609 static int mcp251x_hw_reset(struct spi_device *spi)
611 struct mcp251x_priv *priv = spi_get_drvdata(spi);
615 /* Wait for oscillator startup timer after power up */
616 mdelay(MCP251X_OST_DELAY_MS);
618 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
619 ret = mcp251x_spi_trans(spi, 1);
623 /* Wait for oscillator startup timer after reset */
624 mdelay(MCP251X_OST_DELAY_MS);
626 reg = mcp251x_read_reg(spi, CANSTAT);
627 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF)
633 static int mcp251x_hw_probe(struct spi_device *spi)
638 ret = mcp251x_hw_reset(spi);
642 ctrl = mcp251x_read_reg(spi, CANCTRL);
644 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
646 /* Check for power up default value */
647 if ((ctrl & 0x17) != 0x07)
653 static int mcp251x_power_enable(struct regulator *reg, int enable)
655 if (IS_ERR_OR_NULL(reg))
659 return regulator_enable(reg);
661 return regulator_disable(reg);
664 static int mcp251x_stop(struct net_device *net)
666 struct mcp251x_priv *priv = netdev_priv(net);
667 struct spi_device *spi = priv->spi;
671 priv->force_quit = 1;
672 free_irq(spi->irq, priv);
673 destroy_workqueue(priv->wq);
676 mutex_lock(&priv->mcp_lock);
678 /* Disable and clear pending interrupts */
679 mcp251x_write_reg(spi, CANINTE, 0x00);
680 mcp251x_write_reg(spi, CANINTF, 0x00);
682 mcp251x_write_reg(spi, TXBCTRL(0), 0);
685 mcp251x_hw_sleep(spi);
687 mcp251x_power_enable(priv->transceiver, 0);
689 priv->can.state = CAN_STATE_STOPPED;
691 mutex_unlock(&priv->mcp_lock);
693 can_led_event(net, CAN_LED_EVENT_STOP);
698 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
701 struct can_frame *frame;
703 skb = alloc_can_err_skb(net, &frame);
705 frame->can_id |= can_id;
706 frame->data[1] = data1;
709 netdev_err(net, "cannot allocate error skb\n");
713 static void mcp251x_tx_work_handler(struct work_struct *ws)
715 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
717 struct spi_device *spi = priv->spi;
718 struct net_device *net = priv->net;
719 struct can_frame *frame;
721 mutex_lock(&priv->mcp_lock);
723 if (priv->can.state == CAN_STATE_BUS_OFF) {
726 frame = (struct can_frame *)priv->tx_skb->data;
728 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
729 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
730 mcp251x_hw_tx(spi, frame, 0);
731 priv->tx_len = 1 + frame->can_dlc;
732 can_put_echo_skb(priv->tx_skb, net, 0);
736 mutex_unlock(&priv->mcp_lock);
739 static void mcp251x_restart_work_handler(struct work_struct *ws)
741 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
743 struct spi_device *spi = priv->spi;
744 struct net_device *net = priv->net;
746 mutex_lock(&priv->mcp_lock);
747 if (priv->after_suspend) {
748 mcp251x_hw_reset(spi);
749 mcp251x_setup(net, spi);
750 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
751 mcp251x_set_normal_mode(spi);
752 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
753 netif_device_attach(net);
755 mcp251x_set_normal_mode(spi);
756 netif_wake_queue(net);
758 mcp251x_hw_sleep(spi);
760 priv->after_suspend = 0;
761 priv->force_quit = 0;
764 if (priv->restart_tx) {
765 priv->restart_tx = 0;
766 mcp251x_write_reg(spi, TXBCTRL(0), 0);
768 netif_wake_queue(net);
769 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
771 mutex_unlock(&priv->mcp_lock);
774 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
776 struct mcp251x_priv *priv = dev_id;
777 struct spi_device *spi = priv->spi;
778 struct net_device *net = priv->net;
780 mutex_lock(&priv->mcp_lock);
781 while (!priv->force_quit) {
782 enum can_state new_state;
785 int can_id = 0, data1 = 0;
787 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
789 /* mask out flags we don't care about */
790 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
792 /* receive buffer 0 */
793 if (intf & CANINTF_RX0IF) {
794 mcp251x_hw_rx(spi, 0);
795 /* Free one buffer ASAP
796 * (The MCP2515/25625 does this automatically.)
798 if (mcp251x_is_2510(spi))
799 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
802 /* receive buffer 1 */
803 if (intf & CANINTF_RX1IF) {
804 mcp251x_hw_rx(spi, 1);
805 /* The MCP2515/25625 does this automatically. */
806 if (mcp251x_is_2510(spi))
807 clear_intf |= CANINTF_RX1IF;
810 /* any error or tx interrupt we need to clear? */
811 if (intf & (CANINTF_ERR | CANINTF_TX))
812 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
814 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
816 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
817 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
819 /* Update can state */
820 if (eflag & EFLG_TXBO) {
821 new_state = CAN_STATE_BUS_OFF;
822 can_id |= CAN_ERR_BUSOFF;
823 } else if (eflag & EFLG_TXEP) {
824 new_state = CAN_STATE_ERROR_PASSIVE;
825 can_id |= CAN_ERR_CRTL;
826 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
827 } else if (eflag & EFLG_RXEP) {
828 new_state = CAN_STATE_ERROR_PASSIVE;
829 can_id |= CAN_ERR_CRTL;
830 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
831 } else if (eflag & EFLG_TXWAR) {
832 new_state = CAN_STATE_ERROR_WARNING;
833 can_id |= CAN_ERR_CRTL;
834 data1 |= CAN_ERR_CRTL_TX_WARNING;
835 } else if (eflag & EFLG_RXWAR) {
836 new_state = CAN_STATE_ERROR_WARNING;
837 can_id |= CAN_ERR_CRTL;
838 data1 |= CAN_ERR_CRTL_RX_WARNING;
840 new_state = CAN_STATE_ERROR_ACTIVE;
843 /* Update can state statistics */
844 switch (priv->can.state) {
845 case CAN_STATE_ERROR_ACTIVE:
846 if (new_state >= CAN_STATE_ERROR_WARNING &&
847 new_state <= CAN_STATE_BUS_OFF)
848 priv->can.can_stats.error_warning++;
850 case CAN_STATE_ERROR_WARNING:
851 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
852 new_state <= CAN_STATE_BUS_OFF)
853 priv->can.can_stats.error_passive++;
858 priv->can.state = new_state;
860 if (intf & CANINTF_ERRIF) {
861 /* Handle overflow counters */
862 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
863 if (eflag & EFLG_RX0OVR) {
864 net->stats.rx_over_errors++;
865 net->stats.rx_errors++;
867 if (eflag & EFLG_RX1OVR) {
868 net->stats.rx_over_errors++;
869 net->stats.rx_errors++;
871 can_id |= CAN_ERR_CRTL;
872 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
874 mcp251x_error_skb(net, can_id, data1);
877 if (priv->can.state == CAN_STATE_BUS_OFF) {
878 if (priv->can.restart_ms == 0) {
879 priv->force_quit = 1;
880 priv->can.can_stats.bus_off++;
882 mcp251x_hw_sleep(spi);
890 if (intf & CANINTF_TX) {
891 net->stats.tx_packets++;
892 net->stats.tx_bytes += priv->tx_len - 1;
893 can_led_event(net, CAN_LED_EVENT_TX);
895 can_get_echo_skb(net, 0);
898 netif_wake_queue(net);
902 mutex_unlock(&priv->mcp_lock);
906 static int mcp251x_open(struct net_device *net)
908 struct mcp251x_priv *priv = netdev_priv(net);
909 struct spi_device *spi = priv->spi;
910 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
913 ret = open_candev(net);
915 dev_err(&spi->dev, "unable to set initial baudrate!\n");
919 mutex_lock(&priv->mcp_lock);
920 mcp251x_power_enable(priv->transceiver, 1);
922 priv->force_quit = 0;
926 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
927 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
929 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
933 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
939 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
940 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
942 ret = mcp251x_hw_reset(spi);
945 ret = mcp251x_setup(net, spi);
948 ret = mcp251x_set_normal_mode(spi);
952 can_led_event(net, CAN_LED_EVENT_OPEN);
954 netif_wake_queue(net);
955 mutex_unlock(&priv->mcp_lock);
960 destroy_workqueue(priv->wq);
962 free_irq(spi->irq, priv);
963 mcp251x_hw_sleep(spi);
965 mcp251x_power_enable(priv->transceiver, 0);
967 mutex_unlock(&priv->mcp_lock);
971 static const struct net_device_ops mcp251x_netdev_ops = {
972 .ndo_open = mcp251x_open,
973 .ndo_stop = mcp251x_stop,
974 .ndo_start_xmit = mcp251x_hard_start_xmit,
975 .ndo_change_mtu = can_change_mtu,
978 static const struct of_device_id mcp251x_of_match[] = {
980 .compatible = "microchip,mcp2510",
981 .data = (void *)CAN_MCP251X_MCP2510,
984 .compatible = "microchip,mcp2515",
985 .data = (void *)CAN_MCP251X_MCP2515,
988 .compatible = "microchip,mcp25625",
989 .data = (void *)CAN_MCP251X_MCP25625,
993 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
995 static const struct spi_device_id mcp251x_id_table[] = {
998 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1002 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1006 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1010 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1012 static int mcp251x_can_probe(struct spi_device *spi)
1014 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1016 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1017 struct net_device *net;
1018 struct mcp251x_priv *priv;
1022 clk = devm_clk_get(&spi->dev, NULL);
1025 freq = pdata->oscillator_frequency;
1027 return PTR_ERR(clk);
1029 freq = clk_get_rate(clk);
1033 if (freq < 1000000 || freq > 25000000)
1036 /* Allocate can/net device */
1037 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1042 ret = clk_prepare_enable(clk);
1047 net->netdev_ops = &mcp251x_netdev_ops;
1048 net->flags |= IFF_ECHO;
1050 priv = netdev_priv(net);
1051 priv->can.bittiming_const = &mcp251x_bittiming_const;
1052 priv->can.do_set_mode = mcp251x_do_set_mode;
1053 priv->can.clock.freq = freq / 2;
1054 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1055 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1057 priv->model = (enum mcp251x_model)of_id->data;
1059 priv->model = spi_get_device_id(spi)->driver_data;
1063 spi_set_drvdata(spi, priv);
1065 /* Configure the SPI bus */
1066 spi->bits_per_word = 8;
1067 if (mcp251x_is_2510(spi))
1068 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1070 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1071 ret = spi_setup(spi);
1075 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1076 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1077 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1078 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1079 ret = -EPROBE_DEFER;
1083 ret = mcp251x_power_enable(priv->power, 1);
1088 mutex_init(&priv->mcp_lock);
1090 /* If requested, allocate DMA buffers */
1091 if (mcp251x_enable_dma) {
1092 spi->dev.coherent_dma_mask = ~0;
1094 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1095 * that much and share it between Tx and Rx DMA buffers.
1097 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1102 if (priv->spi_tx_buf) {
1103 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1104 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1107 /* Fall back to non-DMA */
1108 mcp251x_enable_dma = 0;
1112 /* Allocate non-DMA buffers */
1113 if (!mcp251x_enable_dma) {
1114 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1116 if (!priv->spi_tx_buf) {
1120 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1122 if (!priv->spi_rx_buf) {
1128 SET_NETDEV_DEV(net, &spi->dev);
1130 /* Here is OK to not lock the MCP, no one knows about it yet */
1131 ret = mcp251x_hw_probe(spi);
1134 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model);
1138 mcp251x_hw_sleep(spi);
1140 ret = register_candev(net);
1144 devm_can_led_init(net);
1146 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1150 mcp251x_power_enable(priv->power, 0);
1154 clk_disable_unprepare(clk);
1159 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1163 static int mcp251x_can_remove(struct spi_device *spi)
1165 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1166 struct net_device *net = priv->net;
1168 unregister_candev(net);
1170 mcp251x_power_enable(priv->power, 0);
1172 if (!IS_ERR(priv->clk))
1173 clk_disable_unprepare(priv->clk);
1180 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1182 struct spi_device *spi = to_spi_device(dev);
1183 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1184 struct net_device *net = priv->net;
1186 priv->force_quit = 1;
1187 disable_irq(spi->irq);
1188 /* Note: at this point neither IST nor workqueues are running.
1189 * open/stop cannot be called anyway so locking is not needed
1191 if (netif_running(net)) {
1192 netif_device_detach(net);
1194 mcp251x_hw_sleep(spi);
1195 mcp251x_power_enable(priv->transceiver, 0);
1196 priv->after_suspend = AFTER_SUSPEND_UP;
1198 priv->after_suspend = AFTER_SUSPEND_DOWN;
1201 if (!IS_ERR_OR_NULL(priv->power)) {
1202 regulator_disable(priv->power);
1203 priv->after_suspend |= AFTER_SUSPEND_POWER;
1209 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1211 struct spi_device *spi = to_spi_device(dev);
1212 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1214 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1215 mcp251x_power_enable(priv->power, 1);
1217 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1218 mcp251x_power_enable(priv->transceiver, 1);
1219 queue_work(priv->wq, &priv->restart_work);
1221 priv->after_suspend = 0;
1224 priv->force_quit = 0;
1225 enable_irq(spi->irq);
1229 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1230 mcp251x_can_resume);
1232 static struct spi_driver mcp251x_can_driver = {
1234 .name = DEVICE_NAME,
1235 .of_match_table = mcp251x_of_match,
1236 .pm = &mcp251x_can_pm_ops,
1238 .id_table = mcp251x_id_table,
1239 .probe = mcp251x_can_probe,
1240 .remove = mcp251x_can_remove,
1242 module_spi_driver(mcp251x_can_driver);
1244 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1245 "Christian Pellegrin <chripell@evolware.org>");
1246 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1247 MODULE_LICENSE("GPL v2");