1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * Your platform definition file should specify something like:
23 * static struct mcp251x_platform_data mcp251x_info = {
24 * .oscillator_frequency = 8000000,
27 * static struct spi_board_info spi_board_info[] = {
29 * .modalias = "mcp2510",
30 * // "mcp2515" or "mcp25625" depending on your controller
31 * .platform_data = &mcp251x_info,
33 * .max_speed_hz = 2*1000*1000,
38 * Please see mcp251x.h for a description of the fields in
39 * struct mcp251x_platform_data.
42 #include <linux/can/core.h>
43 #include <linux/can/dev.h>
44 #include <linux/can/led.h>
45 #include <linux/can/platform/mcp251x.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/freezer.h>
52 #include <linux/interrupt.h>
54 #include <linux/kernel.h>
55 #include <linux/module.h>
56 #include <linux/netdevice.h>
58 #include <linux/of_device.h>
59 #include <linux/platform_device.h>
60 #include <linux/slab.h>
61 #include <linux/spi/spi.h>
62 #include <linux/uaccess.h>
63 #include <linux/regulator/consumer.h>
65 /* SPI interface instruction set */
66 #define INSTRUCTION_WRITE 0x02
67 #define INSTRUCTION_READ 0x03
68 #define INSTRUCTION_BIT_MODIFY 0x05
69 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
70 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
71 #define INSTRUCTION_RESET 0xC0
75 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
77 /* MPC251x registers */
80 # define CANCTRL_REQOP_MASK 0xe0
81 # define CANCTRL_REQOP_CONF 0x80
82 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
83 # define CANCTRL_REQOP_LOOPBACK 0x40
84 # define CANCTRL_REQOP_SLEEP 0x20
85 # define CANCTRL_REQOP_NORMAL 0x00
86 # define CANCTRL_OSM 0x08
87 # define CANCTRL_ABAT 0x10
91 # define CNF1_SJW_SHIFT 6
93 # define CNF2_BTLMODE 0x80
94 # define CNF2_SAM 0x40
95 # define CNF2_PS1_SHIFT 3
97 # define CNF3_SOF 0x08
98 # define CNF3_WAKFIL 0x04
99 # define CNF3_PHSEG2_MASK 0x07
101 # define CANINTE_MERRE 0x80
102 # define CANINTE_WAKIE 0x40
103 # define CANINTE_ERRIE 0x20
104 # define CANINTE_TX2IE 0x10
105 # define CANINTE_TX1IE 0x08
106 # define CANINTE_TX0IE 0x04
107 # define CANINTE_RX1IE 0x02
108 # define CANINTE_RX0IE 0x01
110 # define CANINTF_MERRF 0x80
111 # define CANINTF_WAKIF 0x40
112 # define CANINTF_ERRIF 0x20
113 # define CANINTF_TX2IF 0x10
114 # define CANINTF_TX1IF 0x08
115 # define CANINTF_TX0IF 0x04
116 # define CANINTF_RX1IF 0x02
117 # define CANINTF_RX0IF 0x01
118 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
119 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
120 # define CANINTF_ERR (CANINTF_ERRIF)
122 # define EFLG_EWARN 0x01
123 # define EFLG_RXWAR 0x02
124 # define EFLG_TXWAR 0x04
125 # define EFLG_RXEP 0x08
126 # define EFLG_TXEP 0x10
127 # define EFLG_TXBO 0x20
128 # define EFLG_RX0OVR 0x40
129 # define EFLG_RX1OVR 0x80
130 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
131 # define TXBCTRL_ABTF 0x40
132 # define TXBCTRL_MLOA 0x20
133 # define TXBCTRL_TXERR 0x10
134 # define TXBCTRL_TXREQ 0x08
135 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
136 # define SIDH_SHIFT 3
137 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
138 # define SIDL_SID_MASK 7
139 # define SIDL_SID_SHIFT 5
140 # define SIDL_EXIDE_SHIFT 3
141 # define SIDL_EID_SHIFT 16
142 # define SIDL_EID_MASK 3
143 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
144 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
145 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
146 # define DLC_RTR_SHIFT 6
147 #define TXBCTRL_OFF 0
148 #define TXBSIDH_OFF 1
149 #define TXBSIDL_OFF 2
150 #define TXBEID8_OFF 3
151 #define TXBEID0_OFF 4
154 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
155 # define RXBCTRL_BUKT 0x04
156 # define RXBCTRL_RXM0 0x20
157 # define RXBCTRL_RXM1 0x40
158 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
159 # define RXBSIDH_SHIFT 3
160 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
161 # define RXBSIDL_IDE 0x08
162 # define RXBSIDL_SRR 0x10
163 # define RXBSIDL_EID 3
164 # define RXBSIDL_SHIFT 5
165 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
166 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
167 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
168 # define RXBDLC_LEN_MASK 0x0f
169 # define RXBDLC_RTR 0x40
170 #define RXBCTRL_OFF 0
171 #define RXBSIDH_OFF 1
172 #define RXBSIDL_OFF 2
173 #define RXBEID8_OFF 3
174 #define RXBEID0_OFF 4
177 #define RXFSID(n) ((n < 3) ? 0 : 4)
178 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
179 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
180 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
181 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
182 #define RXMSIDH(n) ((n) * 4 + 0x20)
183 #define RXMSIDL(n) ((n) * 4 + 0x21)
184 #define RXMEID8(n) ((n) * 4 + 0x22)
185 #define RXMEID0(n) ((n) * 4 + 0x23)
187 #define GET_BYTE(val, byte) \
188 (((val) >> ((byte) * 8)) & 0xff)
189 #define SET_BYTE(val, byte) \
190 (((val) & 0xff) << ((byte) * 8))
192 /* Buffer size required for the largest SPI transfer (i.e., reading a
195 #define CAN_FRAME_MAX_DATA_LEN 8
196 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
197 #define CAN_FRAME_MAX_BITS 128
199 #define TX_ECHO_SKB_MAX 1
201 #define MCP251X_OST_DELAY_MS (5)
203 #define DEVICE_NAME "mcp251x"
205 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
206 module_param(mcp251x_enable_dma, int, 0444);
207 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
209 static const struct can_bittiming_const mcp251x_bittiming_const = {
222 CAN_MCP251X_MCP2510 = 0x2510,
223 CAN_MCP251X_MCP2515 = 0x2515,
224 CAN_MCP251X_MCP25625 = 0x25625,
227 struct mcp251x_priv {
229 struct net_device *net;
230 struct spi_device *spi;
231 enum mcp251x_model model;
233 struct mutex mcp_lock; /* SPI device lock */
237 dma_addr_t spi_tx_dma;
238 dma_addr_t spi_rx_dma;
240 struct sk_buff *tx_skb;
243 struct workqueue_struct *wq;
244 struct work_struct tx_work;
245 struct work_struct restart_work;
249 #define AFTER_SUSPEND_UP 1
250 #define AFTER_SUSPEND_DOWN 2
251 #define AFTER_SUSPEND_POWER 4
252 #define AFTER_SUSPEND_RESTART 8
254 struct regulator *power;
255 struct regulator *transceiver;
259 #define MCP251X_IS(_model) \
260 static inline int mcp251x_is_##_model(struct spi_device *spi) \
262 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
263 return priv->model == CAN_MCP251X_MCP##_model; \
268 static void mcp251x_clean(struct net_device *net)
270 struct mcp251x_priv *priv = netdev_priv(net);
272 if (priv->tx_skb || priv->tx_len)
273 net->stats.tx_errors++;
275 dev_kfree_skb(priv->tx_skb);
277 can_free_echo_skb(priv->net, 0);
282 /* Note about handling of error return of mcp251x_spi_trans: accessing
283 * registers via SPI is not really different conceptually than using
284 * normal I/O assembler instructions, although it's much more
285 * complicated from a practical POV. So it's not advisable to always
286 * check the return value of this function. Imagine that every
287 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
288 * error();", it would be a great mess (well there are some situation
289 * when exception handling C++ like could be useful after all). So we
290 * just check that transfers are OK at the beginning of our
291 * conversation with the chip and to avoid doing really nasty things
292 * (like injecting bogus packets in the network stack).
294 static int mcp251x_spi_trans(struct spi_device *spi, int len)
296 struct mcp251x_priv *priv = spi_get_drvdata(spi);
297 struct spi_transfer t = {
298 .tx_buf = priv->spi_tx_buf,
299 .rx_buf = priv->spi_rx_buf,
303 struct spi_message m;
306 spi_message_init(&m);
308 if (mcp251x_enable_dma) {
309 t.tx_dma = priv->spi_tx_dma;
310 t.rx_dma = priv->spi_rx_dma;
314 spi_message_add_tail(&t, &m);
316 ret = spi_sync(spi, &m);
318 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
322 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
324 struct mcp251x_priv *priv = spi_get_drvdata(spi);
327 priv->spi_tx_buf[0] = INSTRUCTION_READ;
328 priv->spi_tx_buf[1] = reg;
330 mcp251x_spi_trans(spi, 3);
331 val = priv->spi_rx_buf[2];
336 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
338 struct mcp251x_priv *priv = spi_get_drvdata(spi);
340 priv->spi_tx_buf[0] = INSTRUCTION_READ;
341 priv->spi_tx_buf[1] = reg;
343 mcp251x_spi_trans(spi, 4);
345 *v1 = priv->spi_rx_buf[2];
346 *v2 = priv->spi_rx_buf[3];
349 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
351 struct mcp251x_priv *priv = spi_get_drvdata(spi);
353 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
354 priv->spi_tx_buf[1] = reg;
355 priv->spi_tx_buf[2] = val;
357 mcp251x_spi_trans(spi, 3);
360 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
363 struct mcp251x_priv *priv = spi_get_drvdata(spi);
365 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
366 priv->spi_tx_buf[1] = reg;
367 priv->spi_tx_buf[2] = mask;
368 priv->spi_tx_buf[3] = val;
370 mcp251x_spi_trans(spi, 4);
373 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
374 int len, int tx_buf_idx)
376 struct mcp251x_priv *priv = spi_get_drvdata(spi);
378 if (mcp251x_is_2510(spi)) {
381 for (i = 1; i < TXBDAT_OFF + len; i++)
382 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
385 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
386 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
390 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
393 struct mcp251x_priv *priv = spi_get_drvdata(spi);
394 u32 sid, eid, exide, rtr;
395 u8 buf[SPI_TRANSFER_BUF_LEN];
397 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
399 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
401 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
402 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
403 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
405 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
406 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
407 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
408 (exide << SIDL_EXIDE_SHIFT) |
409 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
410 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
411 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
412 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
413 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
414 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
416 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
417 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
418 mcp251x_spi_trans(priv->spi, 1);
421 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
424 struct mcp251x_priv *priv = spi_get_drvdata(spi);
426 if (mcp251x_is_2510(spi)) {
429 for (i = 1; i < RXBDAT_OFF; i++)
430 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
432 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
433 for (; i < (RXBDAT_OFF + len); i++)
434 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
436 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
437 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
438 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
442 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
444 struct mcp251x_priv *priv = spi_get_drvdata(spi);
446 struct can_frame *frame;
447 u8 buf[SPI_TRANSFER_BUF_LEN];
449 skb = alloc_can_skb(priv->net, &frame);
451 dev_err(&spi->dev, "cannot allocate RX skb\n");
452 priv->net->stats.rx_dropped++;
456 mcp251x_hw_rx_frame(spi, buf, buf_idx);
457 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
458 /* Extended ID format */
459 frame->can_id = CAN_EFF_FLAG;
461 /* Extended ID part */
462 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
463 SET_BYTE(buf[RXBEID8_OFF], 1) |
464 SET_BYTE(buf[RXBEID0_OFF], 0) |
465 /* Standard ID part */
466 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
467 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
468 /* Remote transmission request */
469 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
470 frame->can_id |= CAN_RTR_FLAG;
472 /* Standard ID format */
474 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
475 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
476 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
477 frame->can_id |= CAN_RTR_FLAG;
480 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
481 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
483 priv->net->stats.rx_packets++;
484 priv->net->stats.rx_bytes += frame->can_dlc;
486 can_led_event(priv->net, CAN_LED_EVENT_RX);
491 static void mcp251x_hw_sleep(struct spi_device *spi)
493 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
496 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
497 struct net_device *net)
499 struct mcp251x_priv *priv = netdev_priv(net);
500 struct spi_device *spi = priv->spi;
502 if (priv->tx_skb || priv->tx_len) {
503 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
504 return NETDEV_TX_BUSY;
507 if (can_dropped_invalid_skb(net, skb))
510 netif_stop_queue(net);
512 queue_work(priv->wq, &priv->tx_work);
517 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
519 struct mcp251x_priv *priv = netdev_priv(net);
524 /* We have to delay work since SPI I/O may sleep */
525 priv->can.state = CAN_STATE_ERROR_ACTIVE;
526 priv->restart_tx = 1;
527 if (priv->can.restart_ms == 0)
528 priv->after_suspend = AFTER_SUSPEND_RESTART;
529 queue_work(priv->wq, &priv->restart_work);
538 static int mcp251x_set_normal_mode(struct spi_device *spi)
540 struct mcp251x_priv *priv = spi_get_drvdata(spi);
541 unsigned long timeout;
543 /* Enable interrupts */
544 mcp251x_write_reg(spi, CANINTE,
545 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
546 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
548 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
549 /* Put device into loopback mode */
550 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
551 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
552 /* Put device into listen-only mode */
553 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
555 /* Put device into normal mode */
556 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
558 /* Wait for the device to enter normal mode */
559 timeout = jiffies + HZ;
560 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
562 if (time_after(jiffies, timeout)) {
563 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
568 priv->can.state = CAN_STATE_ERROR_ACTIVE;
572 static int mcp251x_do_set_bittiming(struct net_device *net)
574 struct mcp251x_priv *priv = netdev_priv(net);
575 struct can_bittiming *bt = &priv->can.bittiming;
576 struct spi_device *spi = priv->spi;
578 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
580 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
581 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
583 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
585 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
586 (bt->phase_seg2 - 1));
587 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
588 mcp251x_read_reg(spi, CNF1),
589 mcp251x_read_reg(spi, CNF2),
590 mcp251x_read_reg(spi, CNF3));
595 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
597 mcp251x_do_set_bittiming(net);
599 mcp251x_write_reg(spi, RXBCTRL(0),
600 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
601 mcp251x_write_reg(spi, RXBCTRL(1),
602 RXBCTRL_RXM0 | RXBCTRL_RXM1);
606 static int mcp251x_hw_reset(struct spi_device *spi)
608 struct mcp251x_priv *priv = spi_get_drvdata(spi);
609 unsigned long timeout;
612 /* Wait for oscillator startup timer after power up */
613 mdelay(MCP251X_OST_DELAY_MS);
615 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
616 ret = mcp251x_spi_trans(spi, 1);
620 /* Wait for oscillator startup timer after reset */
621 mdelay(MCP251X_OST_DELAY_MS);
623 /* Wait for reset to finish */
624 timeout = jiffies + HZ;
625 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
626 CANCTRL_REQOP_CONF) {
627 usleep_range(MCP251X_OST_DELAY_MS * 1000,
628 MCP251X_OST_DELAY_MS * 1000 * 2);
630 if (time_after(jiffies, timeout)) {
632 "MCP251x didn't enter in conf mode after reset\n");
639 static int mcp251x_hw_probe(struct spi_device *spi)
644 ret = mcp251x_hw_reset(spi);
648 ctrl = mcp251x_read_reg(spi, CANCTRL);
650 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
652 /* Check for power up default value */
653 if ((ctrl & 0x17) != 0x07)
659 static int mcp251x_power_enable(struct regulator *reg, int enable)
661 if (IS_ERR_OR_NULL(reg))
665 return regulator_enable(reg);
667 return regulator_disable(reg);
670 static int mcp251x_stop(struct net_device *net)
672 struct mcp251x_priv *priv = netdev_priv(net);
673 struct spi_device *spi = priv->spi;
677 priv->force_quit = 1;
678 free_irq(spi->irq, priv);
679 destroy_workqueue(priv->wq);
682 mutex_lock(&priv->mcp_lock);
684 /* Disable and clear pending interrupts */
685 mcp251x_write_reg(spi, CANINTE, 0x00);
686 mcp251x_write_reg(spi, CANINTF, 0x00);
688 mcp251x_write_reg(spi, TXBCTRL(0), 0);
691 mcp251x_hw_sleep(spi);
693 mcp251x_power_enable(priv->transceiver, 0);
695 priv->can.state = CAN_STATE_STOPPED;
697 mutex_unlock(&priv->mcp_lock);
699 can_led_event(net, CAN_LED_EVENT_STOP);
704 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
707 struct can_frame *frame;
709 skb = alloc_can_err_skb(net, &frame);
711 frame->can_id |= can_id;
712 frame->data[1] = data1;
715 netdev_err(net, "cannot allocate error skb\n");
719 static void mcp251x_tx_work_handler(struct work_struct *ws)
721 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
723 struct spi_device *spi = priv->spi;
724 struct net_device *net = priv->net;
725 struct can_frame *frame;
727 mutex_lock(&priv->mcp_lock);
729 if (priv->can.state == CAN_STATE_BUS_OFF) {
732 frame = (struct can_frame *)priv->tx_skb->data;
734 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
735 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
736 mcp251x_hw_tx(spi, frame, 0);
737 priv->tx_len = 1 + frame->can_dlc;
738 can_put_echo_skb(priv->tx_skb, net, 0);
742 mutex_unlock(&priv->mcp_lock);
745 static void mcp251x_restart_work_handler(struct work_struct *ws)
747 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
749 struct spi_device *spi = priv->spi;
750 struct net_device *net = priv->net;
752 mutex_lock(&priv->mcp_lock);
753 if (priv->after_suspend) {
754 mcp251x_hw_reset(spi);
755 mcp251x_setup(net, spi);
756 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
757 mcp251x_set_normal_mode(spi);
758 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
759 netif_device_attach(net);
761 mcp251x_set_normal_mode(spi);
762 netif_wake_queue(net);
764 mcp251x_hw_sleep(spi);
766 priv->after_suspend = 0;
767 priv->force_quit = 0;
770 if (priv->restart_tx) {
771 priv->restart_tx = 0;
772 mcp251x_write_reg(spi, TXBCTRL(0), 0);
774 netif_wake_queue(net);
775 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
777 mutex_unlock(&priv->mcp_lock);
780 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
782 struct mcp251x_priv *priv = dev_id;
783 struct spi_device *spi = priv->spi;
784 struct net_device *net = priv->net;
786 mutex_lock(&priv->mcp_lock);
787 while (!priv->force_quit) {
788 enum can_state new_state;
791 int can_id = 0, data1 = 0;
793 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
795 /* mask out flags we don't care about */
796 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
798 /* receive buffer 0 */
799 if (intf & CANINTF_RX0IF) {
800 mcp251x_hw_rx(spi, 0);
801 /* Free one buffer ASAP
802 * (The MCP2515/25625 does this automatically.)
804 if (mcp251x_is_2510(spi))
805 mcp251x_write_bits(spi, CANINTF,
806 CANINTF_RX0IF, 0x00);
809 /* receive buffer 1 */
810 if (intf & CANINTF_RX1IF) {
811 mcp251x_hw_rx(spi, 1);
812 /* The MCP2515/25625 does this automatically. */
813 if (mcp251x_is_2510(spi))
814 clear_intf |= CANINTF_RX1IF;
817 /* any error or tx interrupt we need to clear? */
818 if (intf & (CANINTF_ERR | CANINTF_TX))
819 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
821 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
823 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
824 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
826 /* Update can state */
827 if (eflag & EFLG_TXBO) {
828 new_state = CAN_STATE_BUS_OFF;
829 can_id |= CAN_ERR_BUSOFF;
830 } else if (eflag & EFLG_TXEP) {
831 new_state = CAN_STATE_ERROR_PASSIVE;
832 can_id |= CAN_ERR_CRTL;
833 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
834 } else if (eflag & EFLG_RXEP) {
835 new_state = CAN_STATE_ERROR_PASSIVE;
836 can_id |= CAN_ERR_CRTL;
837 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
838 } else if (eflag & EFLG_TXWAR) {
839 new_state = CAN_STATE_ERROR_WARNING;
840 can_id |= CAN_ERR_CRTL;
841 data1 |= CAN_ERR_CRTL_TX_WARNING;
842 } else if (eflag & EFLG_RXWAR) {
843 new_state = CAN_STATE_ERROR_WARNING;
844 can_id |= CAN_ERR_CRTL;
845 data1 |= CAN_ERR_CRTL_RX_WARNING;
847 new_state = CAN_STATE_ERROR_ACTIVE;
850 /* Update can state statistics */
851 switch (priv->can.state) {
852 case CAN_STATE_ERROR_ACTIVE:
853 if (new_state >= CAN_STATE_ERROR_WARNING &&
854 new_state <= CAN_STATE_BUS_OFF)
855 priv->can.can_stats.error_warning++;
857 case CAN_STATE_ERROR_WARNING:
858 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
859 new_state <= CAN_STATE_BUS_OFF)
860 priv->can.can_stats.error_passive++;
865 priv->can.state = new_state;
867 if (intf & CANINTF_ERRIF) {
868 /* Handle overflow counters */
869 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
870 if (eflag & EFLG_RX0OVR) {
871 net->stats.rx_over_errors++;
872 net->stats.rx_errors++;
874 if (eflag & EFLG_RX1OVR) {
875 net->stats.rx_over_errors++;
876 net->stats.rx_errors++;
878 can_id |= CAN_ERR_CRTL;
879 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
881 mcp251x_error_skb(net, can_id, data1);
884 if (priv->can.state == CAN_STATE_BUS_OFF) {
885 if (priv->can.restart_ms == 0) {
886 priv->force_quit = 1;
887 priv->can.can_stats.bus_off++;
889 mcp251x_hw_sleep(spi);
897 if (intf & CANINTF_TX) {
898 net->stats.tx_packets++;
899 net->stats.tx_bytes += priv->tx_len - 1;
900 can_led_event(net, CAN_LED_EVENT_TX);
902 can_get_echo_skb(net, 0);
905 netif_wake_queue(net);
908 mutex_unlock(&priv->mcp_lock);
912 static int mcp251x_open(struct net_device *net)
914 struct mcp251x_priv *priv = netdev_priv(net);
915 struct spi_device *spi = priv->spi;
916 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
919 ret = open_candev(net);
921 dev_err(&spi->dev, "unable to set initial baudrate!\n");
925 mutex_lock(&priv->mcp_lock);
926 mcp251x_power_enable(priv->transceiver, 1);
928 priv->force_quit = 0;
932 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
933 flags | IRQF_ONESHOT, dev_name(&spi->dev),
936 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
940 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
946 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
947 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
949 ret = mcp251x_hw_reset(spi);
952 ret = mcp251x_setup(net, spi);
955 ret = mcp251x_set_normal_mode(spi);
959 can_led_event(net, CAN_LED_EVENT_OPEN);
961 netif_wake_queue(net);
962 mutex_unlock(&priv->mcp_lock);
967 destroy_workqueue(priv->wq);
969 free_irq(spi->irq, priv);
970 mcp251x_hw_sleep(spi);
972 mcp251x_power_enable(priv->transceiver, 0);
974 mutex_unlock(&priv->mcp_lock);
978 static const struct net_device_ops mcp251x_netdev_ops = {
979 .ndo_open = mcp251x_open,
980 .ndo_stop = mcp251x_stop,
981 .ndo_start_xmit = mcp251x_hard_start_xmit,
982 .ndo_change_mtu = can_change_mtu,
985 static const struct of_device_id mcp251x_of_match[] = {
987 .compatible = "microchip,mcp2510",
988 .data = (void *)CAN_MCP251X_MCP2510,
991 .compatible = "microchip,mcp2515",
992 .data = (void *)CAN_MCP251X_MCP2515,
995 .compatible = "microchip,mcp25625",
996 .data = (void *)CAN_MCP251X_MCP25625,
1000 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1002 static const struct spi_device_id mcp251x_id_table[] = {
1005 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1009 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1013 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1017 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1019 static int mcp251x_can_probe(struct spi_device *spi)
1021 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1023 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1024 struct net_device *net;
1025 struct mcp251x_priv *priv;
1029 clk = devm_clk_get(&spi->dev, NULL);
1032 freq = pdata->oscillator_frequency;
1034 return PTR_ERR(clk);
1036 freq = clk_get_rate(clk);
1040 if (freq < 1000000 || freq > 25000000)
1043 /* Allocate can/net device */
1044 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1049 ret = clk_prepare_enable(clk);
1054 net->netdev_ops = &mcp251x_netdev_ops;
1055 net->flags |= IFF_ECHO;
1057 priv = netdev_priv(net);
1058 priv->can.bittiming_const = &mcp251x_bittiming_const;
1059 priv->can.do_set_mode = mcp251x_do_set_mode;
1060 priv->can.clock.freq = freq / 2;
1061 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1062 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1064 priv->model = (enum mcp251x_model)of_id->data;
1066 priv->model = spi_get_device_id(spi)->driver_data;
1070 spi_set_drvdata(spi, priv);
1072 /* Configure the SPI bus */
1073 spi->bits_per_word = 8;
1074 if (mcp251x_is_2510(spi))
1075 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1077 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1078 ret = spi_setup(spi);
1082 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1083 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1084 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1085 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1086 ret = -EPROBE_DEFER;
1090 ret = mcp251x_power_enable(priv->power, 1);
1095 mutex_init(&priv->mcp_lock);
1097 /* If requested, allocate DMA buffers */
1098 if (mcp251x_enable_dma) {
1099 spi->dev.coherent_dma_mask = ~0;
1101 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1102 * that much and share it between Tx and Rx DMA buffers.
1104 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1109 if (priv->spi_tx_buf) {
1110 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1111 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1114 /* Fall back to non-DMA */
1115 mcp251x_enable_dma = 0;
1119 /* Allocate non-DMA buffers */
1120 if (!mcp251x_enable_dma) {
1121 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1123 if (!priv->spi_tx_buf) {
1127 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1129 if (!priv->spi_rx_buf) {
1135 SET_NETDEV_DEV(net, &spi->dev);
1137 /* Here is OK to not lock the MCP, no one knows about it yet */
1138 ret = mcp251x_hw_probe(spi);
1141 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1146 mcp251x_hw_sleep(spi);
1148 ret = register_candev(net);
1152 devm_can_led_init(net);
1154 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1158 mcp251x_power_enable(priv->power, 0);
1162 clk_disable_unprepare(clk);
1167 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1171 static int mcp251x_can_remove(struct spi_device *spi)
1173 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1174 struct net_device *net = priv->net;
1176 unregister_candev(net);
1178 mcp251x_power_enable(priv->power, 0);
1180 if (!IS_ERR(priv->clk))
1181 clk_disable_unprepare(priv->clk);
1188 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1190 struct spi_device *spi = to_spi_device(dev);
1191 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1192 struct net_device *net = priv->net;
1194 priv->force_quit = 1;
1195 disable_irq(spi->irq);
1196 /* Note: at this point neither IST nor workqueues are running.
1197 * open/stop cannot be called anyway so locking is not needed
1199 if (netif_running(net)) {
1200 netif_device_detach(net);
1202 mcp251x_hw_sleep(spi);
1203 mcp251x_power_enable(priv->transceiver, 0);
1204 priv->after_suspend = AFTER_SUSPEND_UP;
1206 priv->after_suspend = AFTER_SUSPEND_DOWN;
1209 if (!IS_ERR_OR_NULL(priv->power)) {
1210 regulator_disable(priv->power);
1211 priv->after_suspend |= AFTER_SUSPEND_POWER;
1217 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1219 struct spi_device *spi = to_spi_device(dev);
1220 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1222 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1223 mcp251x_power_enable(priv->power, 1);
1225 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1226 mcp251x_power_enable(priv->transceiver, 1);
1227 queue_work(priv->wq, &priv->restart_work);
1229 priv->after_suspend = 0;
1232 priv->force_quit = 0;
1233 enable_irq(spi->irq);
1237 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1238 mcp251x_can_resume);
1240 static struct spi_driver mcp251x_can_driver = {
1242 .name = DEVICE_NAME,
1243 .of_match_table = mcp251x_of_match,
1244 .pm = &mcp251x_can_pm_ops,
1246 .id_table = mcp251x_id_table,
1247 .probe = mcp251x_can_probe,
1248 .remove = mcp251x_can_remove,
1250 module_spi_driver(mcp251x_can_driver);
1252 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1253 "Christian Pellegrin <chripell@evolware.org>");
1254 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1255 MODULE_LICENSE("GPL v2");