drivers/net/can/spi/hi311x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
   3  *
   4  * Copyright(C) Timesys Corporation 2016
   5  *
   6  * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
   7  * Copyright 2009 Christian Pellegrin EVOL S.r.l.
   8  * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
   9  * Copyright 2006 Arcom Control Systems Ltd.
  10  *
  11  * Based on CAN bus driver for the CCAN controller written by
  12  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
  13  * - Simon Kallweit, intefo AG
  14  * Copyright 2007
  15  */
  16
  17 #include <linux/can/core.h>
  18 #include <linux/can/dev.h>
  19 #include <linux/can/led.h>
  20 #include <linux/clk.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/freezer.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/uaccess.h>
  37
  38 #define HI3110_MASTER_RESET 0x56
  39 #define HI3110_READ_CTRL0 0xD2
  40 #define HI3110_READ_CTRL1 0xD4
  41 #define HI3110_READ_STATF 0xE2
  42 #define HI3110_WRITE_CTRL0 0x14
  43 #define HI3110_WRITE_CTRL1 0x16
  44 #define HI3110_WRITE_INTE 0x1C
  45 #define HI3110_WRITE_BTR0 0x18
  46 #define HI3110_WRITE_BTR1 0x1A
  47 #define HI3110_READ_BTR0 0xD6
  48 #define HI3110_READ_BTR1 0xD8
  49 #define HI3110_READ_INTF 0xDE
  50 #define HI3110_READ_ERR 0xDC
  51 #define HI3110_READ_FIFO_WOTIME 0x48
  52 #define HI3110_WRITE_FIFO 0x12
  53 #define HI3110_READ_MESSTAT 0xDA
  54 #define HI3110_READ_REC 0xEA
  55 #define HI3110_READ_TEC 0xEC
  56
  57 #define HI3110_CTRL0_MODE_MASK (7 << 5)
  58 #define HI3110_CTRL0_NORMAL_MODE (0 << 5)
  59 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
  60 #define HI3110_CTRL0_MONITOR_MODE (2 << 5)
  61 #define HI3110_CTRL0_SLEEP_MODE (3 << 5)
  62 #define HI3110_CTRL0_INIT_MODE (4 << 5)
  63
  64 #define HI3110_CTRL1_TXEN BIT(7)
  65
  66 #define HI3110_INT_RXTMP BIT(7)
  67 #define HI3110_INT_RXFIFO BIT(6)
  68 #define HI3110_INT_TXCPLT BIT(5)
  69 #define HI3110_INT_BUSERR BIT(4)
  70 #define HI3110_INT_MCHG BIT(3)
  71 #define HI3110_INT_WAKEUP BIT(2)
  72 #define HI3110_INT_F1MESS BIT(1)
  73 #define HI3110_INT_F0MESS BIT(0)
  74
  75 #define HI3110_ERR_BUSOFF BIT(7)
  76 #define HI3110_ERR_TXERRP BIT(6)
  77 #define HI3110_ERR_RXERRP BIT(5)
  78 #define HI3110_ERR_BITERR BIT(4)
  79 #define HI3110_ERR_FRMERR BIT(3)
  80 #define HI3110_ERR_CRCERR BIT(2)
  81 #define HI3110_ERR_ACKERR BIT(1)
  82 #define HI3110_ERR_STUFERR BIT(0)
  83 #define HI3110_ERR_PROTOCOL_MASK (0x1F)
  84 #define HI3110_ERR_PASSIVE_MASK (0x60)
  85
  86 #define HI3110_STAT_RXFMTY BIT(1)
  87 #define HI3110_STAT_BUSOFF BIT(2)
  88 #define HI3110_STAT_ERRP BIT(3)
  89 #define HI3110_STAT_ERRW BIT(4)
  90 #define HI3110_STAT_TXMTY BIT(7)
  91
  92 #define HI3110_BTR0_SJW_SHIFT 6
  93 #define HI3110_BTR0_BRP_SHIFT 0
  94
  95 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
  96 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
  97 #define HI3110_BTR1_TSEG2_SHIFT 4
  98 #define HI3110_BTR1_TSEG1_SHIFT 0
  99
 100 #define HI3110_FIFO_WOTIME_TAG_OFF 0
 101 #define HI3110_FIFO_WOTIME_ID_OFF 1
 102 #define HI3110_FIFO_WOTIME_DLC_OFF 5
 103 #define HI3110_FIFO_WOTIME_DAT_OFF 6
 104
 105 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
 106 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
 107
 108 #define HI3110_FIFO_TAG_OFF 0
 109 #define HI3110_FIFO_ID_OFF 1
 110 #define HI3110_FIFO_STD_DLC_OFF 3
 111 #define HI3110_FIFO_STD_DATA_OFF 4
 112 #define HI3110_FIFO_EXT_DLC_OFF 5
 113 #define HI3110_FIFO_EXT_DATA_OFF 6
 114
 115 #define HI3110_CAN_MAX_DATA_LEN 8
 116 #define HI3110_RX_BUF_LEN 15
 117 #define HI3110_TX_STD_BUF_LEN 12
 118 #define HI3110_TX_EXT_BUF_LEN 14
 119 #define HI3110_CAN_FRAME_MAX_BITS 128
 120 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */
 121
 122 #define HI3110_TX_ECHO_SKB_MAX 1
 123
 124 #define HI3110_OST_DELAY_MS (10)
 125
 126 #define DEVICE_NAME "hi3110"
 127
 128 static const struct can_bittiming_const hi3110_bittiming_const = {
 129         .name = DEVICE_NAME,
 130         .tseg1_min = 2,
 131         .tseg1_max = 16,
 132         .tseg2_min = 2,
 133         .tseg2_max = 8,
 134         .sjw_max = 4,
 135         .brp_min = 1,
 136         .brp_max = 64,
 137         .brp_inc = 1,
 138 };
 139
 140 enum hi3110_model {
 141         CAN_HI3110_HI3110 = 0x3110,
 142 };
 143
 144 struct hi3110_priv {
 145         struct can_priv can;
 146         struct net_device *net;
 147         struct spi_device *spi;
 148         enum hi3110_model model;
 149
 150         struct mutex hi3110_lock; /* SPI device lock */
 151
 152         u8 *spi_tx_buf;
 153         u8 *spi_rx_buf;
 154
 155         struct sk_buff *tx_skb;
 156         int tx_len;
 157
 158         struct workqueue_struct *wq;
 159         struct work_struct tx_work;
 160         struct work_struct restart_work;
 161
 162         int force_quit;
 163         int after_suspend;
 164 #define HI3110_AFTER_SUSPEND_UP 1
 165 #define HI3110_AFTER_SUSPEND_DOWN 2
 166 #define HI3110_AFTER_SUSPEND_POWER 4
 167 #define HI3110_AFTER_SUSPEND_RESTART 8
 168         int restart_tx;
 169         struct regulator *power;
 170         struct regulator *transceiver;
 171         struct clk *clk;
 172 };
 173
 174 static void hi3110_clean(struct net_device *net)
 175 {
 176         struct hi3110_priv *priv = netdev_priv(net);
 177
 178         if (priv->tx_skb || priv->tx_len)
 179                 net->stats.tx_errors++;
 180         if (priv->tx_skb)
 181                 dev_kfree_skb(priv->tx_skb);
 182         if (priv->tx_len)
 183                 can_free_echo_skb(priv->net, 0);
 184         priv->tx_skb = NULL;
 185         priv->tx_len = 0;
 186 }
 187
 188 /* Note about handling of error return of hi3110_spi_trans: accessing
 189  * registers via SPI is not really different conceptually than using
 190  * normal I/O assembler instructions, although it's much more
 191  * complicated from a practical POV. So it's not advisable to always
 192  * check the return value of this function. Imagine that every
 193  * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
 194  * error();", it would be a great mess (well there are some situation
 195  * when exception handling C++ like could be useful after all). So we
 196  * just check that transfers are OK at the beginning of our
 197  * conversation with the chip and to avoid doing really nasty things
 198  * (like injecting bogus packets in the network stack).
 199  */
 200 static int hi3110_spi_trans(struct spi_device *spi, int len)
 201 {
 202         struct hi3110_priv *priv = spi_get_drvdata(spi);
 203         struct spi_transfer t = {
 204                 .tx_buf = priv->spi_tx_buf,
 205                 .rx_buf = priv->spi_rx_buf,
 206                 .len = len,
 207                 .cs_change = 0,
 208         };
 209         struct spi_message m;
 210         int ret;
 211
 212         spi_message_init(&m);
 213         spi_message_add_tail(&t, &m);
 214
 215         ret = spi_sync(spi, &m);
 216
 217         if (ret)
 218                 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
 219         return ret;
 220 }
 221
 222 static u8 hi3110_cmd(struct spi_device *spi, u8 command)
 223 {
 224         struct hi3110_priv *priv = spi_get_drvdata(spi);
 225
 226         priv->spi_tx_buf[0] = command;
 227         dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
 228
 229         return hi3110_spi_trans(spi, 1);
 230 }
 231
 232 static u8 hi3110_read(struct spi_device *spi, u8 command)
 233 {
 234         struct hi3110_priv *priv = spi_get_drvdata(spi);
 235         u8 val = 0;
 236
 237         priv->spi_tx_buf[0] = command;
 238         hi3110_spi_trans(spi, 2);
 239         val = priv->spi_rx_buf[1];
 240
 241         return val;
 242 }
 243
 244 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
 245 {
 246         struct hi3110_priv *priv = spi_get_drvdata(spi);
 247
 248         priv->spi_tx_buf[0] = reg;
 249         priv->spi_tx_buf[1] = val;
 250         hi3110_spi_trans(spi, 2);
 251 }
 252
 253 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
 254 {
 255         struct hi3110_priv *priv = spi_get_drvdata(spi);
 256
 257         priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
 258         memcpy(priv->spi_tx_buf + 1, buf, len);
 259         hi3110_spi_trans(spi, len + 1);
 260 }
 261
 262 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
 263 {
 264         u8 buf[HI3110_TX_EXT_BUF_LEN];
 265
 266         buf[HI3110_FIFO_TAG_OFF] = 0;
 267
 268         if (frame->can_id & CAN_EFF_FLAG) {
 269                 /* Extended frame */
 270                 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
 271                 buf[HI3110_FIFO_ID_OFF + 1] =
 272                         (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
 273                         HI3110_EFF_FLAGS |
 274                         (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
 275                 buf[HI3110_FIFO_ID_OFF + 2] =
 276                         (frame->can_id & CAN_EFF_MASK) >> 7;
 277                 buf[HI3110_FIFO_ID_OFF + 3] =
 278                         ((frame->can_id & CAN_EFF_MASK) << 1) |
 279                         ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
 280
 281                 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc;
 282
 283                 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
 284                        frame->data, frame->can_dlc);
 285
 286                 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
 287                                    (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
 288         } else {
 289                 /* Standard frame */
 290                 buf[HI3110_FIFO_ID_OFF] =   (frame->can_id & CAN_SFF_MASK) >> 3;
 291                 buf[HI3110_FIFO_ID_OFF + 1] =
 292                         ((frame->can_id & CAN_SFF_MASK) << 5) |
 293                         ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
 294
 295                 buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc;
 296
 297                 memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
 298                        frame->data, frame->can_dlc);
 299
 300                 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
 301                                    (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
 302         }
 303 }
 304
 305 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
 306 {
 307         struct hi3110_priv *priv = spi_get_drvdata(spi);
 308
 309         priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
 310         hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
 311         memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
 312 }
 313
 314 static void hi3110_hw_rx(struct spi_device *spi)
 315 {
 316         struct hi3110_priv *priv = spi_get_drvdata(spi);
 317         struct sk_buff *skb;
 318         struct can_frame *frame;
 319         u8 buf[HI3110_RX_BUF_LEN - 1];
 320
 321         skb = alloc_can_skb(priv->net, &frame);
 322         if (!skb) {
 323                 priv->net->stats.rx_dropped++;
 324                 return;
 325         }
 326
 327         hi3110_hw_rx_frame(spi, buf);
 328         if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
 329                 /* IDE is recessive (1), indicating extended 29-bit frame */
 330                 frame->can_id = CAN_EFF_FLAG;
 331                 frame->can_id |=
 332                         (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
 333                         (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
 334                         ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
 335                         (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
 336                         (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
 337         } else {
 338                 /* IDE is dominant (0), frame indicating standard 11-bit */
 339                 frame->can_id =
 340                         (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
 341                         ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
 342         }
 343
 344         /* Data length */
 345         frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
 346
 347         if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
 348                 frame->can_id |= CAN_RTR_FLAG;
 349         else
 350                 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
 351                        frame->can_dlc);
 352
 353         priv->net->stats.rx_packets++;
 354         priv->net->stats.rx_bytes += frame->can_dlc;
 355
 356         can_led_event(priv->net, CAN_LED_EVENT_RX);
 357
 358         netif_rx_ni(skb);
 359 }
 360
 361 static void hi3110_hw_sleep(struct spi_device *spi)
 362 {
 363         hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
 364 }
 365
 366 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
 367                                           struct net_device *net)
 368 {
 369         struct hi3110_priv *priv = netdev_priv(net);
 370         struct spi_device *spi = priv->spi;
 371
 372         if (priv->tx_skb || priv->tx_len) {
 373                 dev_err(&spi->dev, "hard_xmit called while tx busy\n");
 374                 return NETDEV_TX_BUSY;
 375         }
 376
 377         if (can_dropped_invalid_skb(net, skb))
 378                 return NETDEV_TX_OK;
 379
 380         netif_stop_queue(net);
 381         priv->tx_skb = skb;
 382         queue_work(priv->wq, &priv->tx_work);
 383
 384         return NETDEV_TX_OK;
 385 }
 386
 387 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
 388 {
 389         struct hi3110_priv *priv = netdev_priv(net);
 390
 391         switch (mode) {
 392         case CAN_MODE_START:
 393                 hi3110_clean(net);
 394                 /* We have to delay work since SPI I/O may sleep */
 395                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
 396                 priv->restart_tx = 1;
 397                 if (priv->can.restart_ms == 0)
 398                         priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
 399                 queue_work(priv->wq, &priv->restart_work);
 400                 break;
 401         default:
 402                 return -EOPNOTSUPP;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int hi3110_get_berr_counter(const struct net_device *net,
 409                                    struct can_berr_counter *bec)
 410 {
 411         struct hi3110_priv *priv = netdev_priv(net);
 412         struct spi_device *spi = priv->spi;
 413
 414         mutex_lock(&priv->hi3110_lock);
 415         bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
 416         bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
 417         mutex_unlock(&priv->hi3110_lock);
 418
 419         return 0;
 420 }
 421
 422 static int hi3110_set_normal_mode(struct spi_device *spi)
 423 {
 424         struct hi3110_priv *priv = spi_get_drvdata(spi);
 425         u8 reg = 0;
 426
 427         hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
 428                      HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
 429
 430         /* Enable TX */
 431         hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
 432
 433         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 434                 reg = HI3110_CTRL0_LOOPBACK_MODE;
 435         else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 436                 reg = HI3110_CTRL0_MONITOR_MODE;
 437         else
 438                 reg = HI3110_CTRL0_NORMAL_MODE;
 439
 440         hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
 441
 442         /* Wait for the device to enter the mode */
 443         mdelay(HI3110_OST_DELAY_MS);
 444         reg = hi3110_read(spi, HI3110_READ_CTRL0);
 445         if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
 446                 return -EBUSY;
 447
 448         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 449         return 0;
 450 }
 451
 452 static int hi3110_do_set_bittiming(struct net_device *net)
 453 {
 454         struct hi3110_priv *priv = netdev_priv(net);
 455         struct can_bittiming *bt = &priv->can.bittiming;
 456         struct spi_device *spi = priv->spi;
 457
 458         hi3110_write(spi, HI3110_WRITE_BTR0,
 459                      ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
 460                      ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
 461
 462         hi3110_write(spi, HI3110_WRITE_BTR1,
 463                      (priv->can.ctrlmode &
 464                       CAN_CTRLMODE_3_SAMPLES ?
 465                       HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
 466                      ((bt->phase_seg1 + bt->prop_seg - 1)
 467                       << HI3110_BTR1_TSEG1_SHIFT) |
 468                      ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
 469
 470         dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
 471                 hi3110_read(spi, HI3110_READ_BTR0),
 472                 hi3110_read(spi, HI3110_READ_BTR1));
 473
 474         return 0;
 475 }
 476
 477 static int hi3110_setup(struct net_device *net)
 478 {
 479         hi3110_do_set_bittiming(net);
 480         return 0;
 481 }
 482
 483 static int hi3110_hw_reset(struct spi_device *spi)
 484 {
 485         u8 reg;
 486         int ret;
 487
 488         /* Wait for oscillator startup timer after power up */
 489         mdelay(HI3110_OST_DELAY_MS);
 490
 491         ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
 492         if (ret)
 493                 return ret;
 494
 495         /* Wait for oscillator startup timer after reset */
 496         mdelay(HI3110_OST_DELAY_MS);
 497
 498         reg = hi3110_read(spi, HI3110_READ_CTRL0);
 499         if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
 500                 return -ENODEV;
 501
 502         /* As per the datasheet it appears the error flags are
 503          * not cleared on reset. Explicitly clear them by performing a read
 504          */
 505         hi3110_read(spi, HI3110_READ_ERR);
 506
 507         return 0;
 508 }
 509
 510 static int hi3110_hw_probe(struct spi_device *spi)
 511 {
 512         u8 statf;
 513
 514         hi3110_hw_reset(spi);
 515
 516         /* Confirm correct operation by checking against reset values
 517          * in datasheet
 518          */
 519         statf = hi3110_read(spi, HI3110_READ_STATF);
 520
 521         dev_dbg(&spi->dev, "statf: %02X\n", statf);
 522
 523         if (statf != 0x82)
 524                 return -ENODEV;
 525
 526         return 0;
 527 }
 528
 529 static int hi3110_power_enable(struct regulator *reg, int enable)
 530 {
 531         if (IS_ERR_OR_NULL(reg))
 532                 return 0;
 533
 534         if (enable)
 535                 return regulator_enable(reg);
 536         else
 537                 return regulator_disable(reg);
 538 }
 539
 540 static int hi3110_stop(struct net_device *net)
 541 {
 542         struct hi3110_priv *priv = netdev_priv(net);
 543         struct spi_device *spi = priv->spi;
 544
 545         close_candev(net);
 546
 547         priv->force_quit = 1;
 548         free_irq(spi->irq, priv);
 549         destroy_workqueue(priv->wq);
 550         priv->wq = NULL;
 551
 552         mutex_lock(&priv->hi3110_lock);
 553
 554         /* Disable transmit, interrupts and clear flags */
 555         hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
 556         hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
 557         hi3110_read(spi, HI3110_READ_INTF);
 558
 559         hi3110_clean(net);
 560
 561         hi3110_hw_sleep(spi);
 562
 563         hi3110_power_enable(priv->transceiver, 0);
 564
 565         priv->can.state = CAN_STATE_STOPPED;
 566
 567         mutex_unlock(&priv->hi3110_lock);
 568
 569         can_led_event(net, CAN_LED_EVENT_STOP);
 570
 571         return 0;
 572 }
 573
 574 static void hi3110_tx_work_handler(struct work_struct *ws)
 575 {
 576         struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
 577                                                 tx_work);
 578         struct spi_device *spi = priv->spi;
 579         struct net_device *net = priv->net;
 580         struct can_frame *frame;
 581
 582         mutex_lock(&priv->hi3110_lock);
 583         if (priv->tx_skb) {
 584                 if (priv->can.state == CAN_STATE_BUS_OFF) {
 585                         hi3110_clean(net);
 586                 } else {
 587                         frame = (struct can_frame *)priv->tx_skb->data;
 588                         hi3110_hw_tx(spi, frame);
 589                         priv->tx_len = 1 + frame->can_dlc;
 590                         can_put_echo_skb(priv->tx_skb, net, 0);
 591                         priv->tx_skb = NULL;
 592                 }
 593         }
 594         mutex_unlock(&priv->hi3110_lock);
 595 }
 596
 597 static void hi3110_restart_work_handler(struct work_struct *ws)
 598 {
 599         struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
 600                                                 restart_work);
 601         struct spi_device *spi = priv->spi;
 602         struct net_device *net = priv->net;
 603
 604         mutex_lock(&priv->hi3110_lock);
 605         if (priv->after_suspend) {
 606                 hi3110_hw_reset(spi);
 607                 hi3110_setup(net);
 608                 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
 609                         hi3110_set_normal_mode(spi);
 610                 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
 611                         netif_device_attach(net);
 612                         hi3110_clean(net);
 613                         hi3110_set_normal_mode(spi);
 614                         netif_wake_queue(net);
 615                 } else {
 616                         hi3110_hw_sleep(spi);
 617                 }
 618                 priv->after_suspend = 0;
 619                 priv->force_quit = 0;
 620         }
 621
 622         if (priv->restart_tx) {
 623                 priv->restart_tx = 0;
 624                 hi3110_hw_reset(spi);
 625                 hi3110_setup(net);
 626                 hi3110_clean(net);
 627                 hi3110_set_normal_mode(spi);
 628                 netif_wake_queue(net);
 629         }
 630         mutex_unlock(&priv->hi3110_lock);
 631 }
 632
 633 static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
 634 {
 635         struct hi3110_priv *priv = dev_id;
 636         struct spi_device *spi = priv->spi;
 637         struct net_device *net = priv->net;
 638
 639         mutex_lock(&priv->hi3110_lock);
 640
 641         while (!priv->force_quit) {
 642                 enum can_state new_state;
 643                 u8 intf, eflag, statf;
 644
 645                 while (!(HI3110_STAT_RXFMTY &
 646                          (statf = hi3110_read(spi, HI3110_READ_STATF)))) {
 647                         hi3110_hw_rx(spi);
 648                 }
 649
 650                 intf = hi3110_read(spi, HI3110_READ_INTF);
 651                 eflag = hi3110_read(spi, HI3110_READ_ERR);
 652                 /* Update can state */
 653                 if (eflag & HI3110_ERR_BUSOFF)
 654                         new_state = CAN_STATE_BUS_OFF;
 655                 else if (eflag & HI3110_ERR_PASSIVE_MASK)
 656                         new_state = CAN_STATE_ERROR_PASSIVE;
 657                 else if (statf & HI3110_STAT_ERRW)
 658                         new_state = CAN_STATE_ERROR_WARNING;
 659                 else
 660                         new_state = CAN_STATE_ERROR_ACTIVE;
 661
 662                 if (new_state != priv->can.state) {
 663                         struct can_frame *cf;
 664                         struct sk_buff *skb;
 665                         enum can_state rx_state, tx_state;
 666                         u8 rxerr, txerr;
 667
 668                         skb = alloc_can_err_skb(net, &cf);
 669                         if (!skb)
 670                                 break;
 671
 672                         txerr = hi3110_read(spi, HI3110_READ_TEC);
 673                         rxerr = hi3110_read(spi, HI3110_READ_REC);
 674                         cf->data[6] = txerr;
 675                         cf->data[7] = rxerr;
 676                         tx_state = txerr >= rxerr ? new_state : 0;
 677                         rx_state = txerr <= rxerr ? new_state : 0;
 678                         can_change_state(net, cf, tx_state, rx_state);
 679                         netif_rx_ni(skb);
 680
 681                         if (new_state == CAN_STATE_BUS_OFF) {
 682                                 can_bus_off(net);
 683                                 if (priv->can.restart_ms == 0) {
 684                                         priv->force_quit = 1;
 685                                         hi3110_hw_sleep(spi);
 686                                         break;
 687                                 }
 688                         }
 689                 }
 690
 691                 /* Update bus errors */
 692                 if ((intf & HI3110_INT_BUSERR) &&
 693                     (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 694                         struct can_frame *cf;
 695                         struct sk_buff *skb;
 696
 697                         /* Check for protocol errors */
 698                         if (eflag & HI3110_ERR_PROTOCOL_MASK) {
 699                                 skb = alloc_can_err_skb(net, &cf);
 700                                 if (!skb)
 701                                         break;
 702
 703                                 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 704                                 priv->can.can_stats.bus_error++;
 705                                 priv->net->stats.rx_errors++;
 706                                 if (eflag & HI3110_ERR_BITERR)
 707                                         cf->data[2] |= CAN_ERR_PROT_BIT;
 708                                 else if (eflag & HI3110_ERR_FRMERR)
 709                                         cf->data[2] |= CAN_ERR_PROT_FORM;
 710                                 else if (eflag & HI3110_ERR_STUFERR)
 711                                         cf->data[2] |= CAN_ERR_PROT_STUFF;
 712                                 else if (eflag & HI3110_ERR_CRCERR)
 713                                         cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 714                                 else if (eflag & HI3110_ERR_ACKERR)
 715                                         cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 716
 717                                 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
 718                                 cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
 719                                 netdev_dbg(priv->net, "Bus Error\n");
 720                                 netif_rx_ni(skb);
 721                         }
 722                 }
 723
 724                 if (priv->tx_len && statf & HI3110_STAT_TXMTY) {
 725                         net->stats.tx_packets++;
 726                         net->stats.tx_bytes += priv->tx_len - 1;
 727                         can_led_event(net, CAN_LED_EVENT_TX);
 728                         if (priv->tx_len) {
 729                                 can_get_echo_skb(net, 0);
 730                                 priv->tx_len = 0;
 731                         }
 732                         netif_wake_queue(net);
 733                 }
 734
 735                 if (intf == 0)
 736                         break;
 737         }
 738         mutex_unlock(&priv->hi3110_lock);
 739         return IRQ_HANDLED;
 740 }
 741
 742 static int hi3110_open(struct net_device *net)
 743 {
 744         struct hi3110_priv *priv = netdev_priv(net);
 745         struct spi_device *spi = priv->spi;
 746         unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH;
 747         int ret;
 748
 749         ret = open_candev(net);
 750         if (ret)
 751                 return ret;
 752
 753         mutex_lock(&priv->hi3110_lock);
 754         hi3110_power_enable(priv->transceiver, 1);
 755
 756         priv->force_quit = 0;
 757         priv->tx_skb = NULL;
 758         priv->tx_len = 0;
 759
 760         ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
 761                                    flags, DEVICE_NAME, priv);
 762         if (ret) {
 763                 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
 764                 goto out_close;
 765         }
 766
 767         priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
 768                                    0);
 769         if (!priv->wq) {
 770                 ret = -ENOMEM;
 771                 goto out_free_irq;
 772         }
 773         INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
 774         INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
 775
 776         ret = hi3110_hw_reset(spi);
 777         if (ret)
 778                 goto out_free_wq;
 779
 780         ret = hi3110_setup(net);
 781         if (ret)
 782                 goto out_free_wq;
 783
 784         ret = hi3110_set_normal_mode(spi);
 785         if (ret)
 786                 goto out_free_wq;
 787
 788         can_led_event(net, CAN_LED_EVENT_OPEN);
 789         netif_wake_queue(net);
 790         mutex_unlock(&priv->hi3110_lock);
 791
 792         return 0;
 793
 794  out_free_wq:
 795         destroy_workqueue(priv->wq);
 796  out_free_irq:
 797         free_irq(spi->irq, priv);
 798         hi3110_hw_sleep(spi);
 799  out_close:
 800         hi3110_power_enable(priv->transceiver, 0);
 801         close_candev(net);
 802         mutex_unlock(&priv->hi3110_lock);
 803         return ret;
 804 }
 805
 806 static const struct net_device_ops hi3110_netdev_ops = {
 807         .ndo_open = hi3110_open,
 808         .ndo_stop = hi3110_stop,
 809         .ndo_start_xmit = hi3110_hard_start_xmit,
 810 };
 811
 812 static const struct of_device_id hi3110_of_match[] = {
 813         {
 814                 .compatible     = "holt,hi3110",
 815                 .data           = (void *)CAN_HI3110_HI3110,
 816         },
 817         { }
 818 };
 819 MODULE_DEVICE_TABLE(of, hi3110_of_match);
 820
 821 static const struct spi_device_id hi3110_id_table[] = {
 822         {
 823                 .name           = "hi3110",
 824                 .driver_data    = (kernel_ulong_t)CAN_HI3110_HI3110,
 825         },
 826         { }
 827 };
 828 MODULE_DEVICE_TABLE(spi, hi3110_id_table);
 829
 830 static int hi3110_can_probe(struct spi_device *spi)
 831 {
 832         const struct of_device_id *of_id = of_match_device(hi3110_of_match,
 833                                                            &spi->dev);
 834         struct net_device *net;
 835         struct hi3110_priv *priv;
 836         struct clk *clk;
 837         int freq, ret;
 838
 839         clk = devm_clk_get(&spi->dev, NULL);
 840         if (IS_ERR(clk)) {
 841                 dev_err(&spi->dev, "no CAN clock source defined\n");
 842                 return PTR_ERR(clk);
 843         }
 844         freq = clk_get_rate(clk);
 845
 846         /* Sanity check */
 847         if (freq > 40000000)
 848                 return -ERANGE;
 849
 850         /* Allocate can/net device */
 851         net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
 852         if (!net)
 853                 return -ENOMEM;
 854
 855         if (!IS_ERR(clk)) {
 856                 ret = clk_prepare_enable(clk);
 857                 if (ret)
 858                         goto out_free;
 859         }
 860
 861         net->netdev_ops = &hi3110_netdev_ops;
 862         net->flags |= IFF_ECHO;
 863
 864         priv = netdev_priv(net);
 865         priv->can.bittiming_const = &hi3110_bittiming_const;
 866         priv->can.do_set_mode = hi3110_do_set_mode;
 867         priv->can.do_get_berr_counter = hi3110_get_berr_counter;
 868         priv->can.clock.freq = freq / 2;
 869         priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
 870                 CAN_CTRLMODE_LOOPBACK |
 871                 CAN_CTRLMODE_LISTENONLY |
 872                 CAN_CTRLMODE_BERR_REPORTING;
 873
 874         if (of_id)
 875                 priv->model = (enum hi3110_model)of_id->data;
 876         else
 877                 priv->model = spi_get_device_id(spi)->driver_data;
 878         priv->net = net;
 879         priv->clk = clk;
 880
 881         spi_set_drvdata(spi, priv);
 882
 883         /* Configure the SPI bus */
 884         spi->bits_per_word = 8;
 885         ret = spi_setup(spi);
 886         if (ret)
 887                 goto out_clk;
 888
 889         priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
 890         priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
 891         if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
 892             (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
 893                 ret = -EPROBE_DEFER;
 894                 goto out_clk;
 895         }
 896
 897         ret = hi3110_power_enable(priv->power, 1);
 898         if (ret)
 899                 goto out_clk;
 900
 901         priv->spi = spi;
 902         mutex_init(&priv->hi3110_lock);
 903
 904         priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
 905                                         GFP_KERNEL);
 906         if (!priv->spi_tx_buf) {
 907                 ret = -ENOMEM;
 908                 goto error_probe;
 909         }
 910         priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
 911                                         GFP_KERNEL);
 912
 913         if (!priv->spi_rx_buf) {
 914                 ret = -ENOMEM;
 915                 goto error_probe;
 916         }
 917
 918         SET_NETDEV_DEV(net, &spi->dev);
 919
 920         ret = hi3110_hw_probe(spi);
 921         if (ret) {
 922                 if (ret == -ENODEV)
 923                         dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
 924                                 priv->model);
 925                 goto error_probe;
 926         }
 927         hi3110_hw_sleep(spi);
 928
 929         ret = register_candev(net);
 930         if (ret)
 931                 goto error_probe;
 932
 933         devm_can_led_init(net);
 934         netdev_info(net, "%x successfully initialized.\n", priv->model);
 935
 936         return 0;
 937
 938  error_probe:
 939         hi3110_power_enable(priv->power, 0);
 940
 941  out_clk:
 942         if (!IS_ERR(clk))
 943                 clk_disable_unprepare(clk);
 944
 945  out_free:
 946         free_candev(net);
 947
 948         dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
 949         return ret;
 950 }
 951
 952 static int hi3110_can_remove(struct spi_device *spi)
 953 {
 954         struct hi3110_priv *priv = spi_get_drvdata(spi);
 955         struct net_device *net = priv->net;
 956
 957         unregister_candev(net);
 958
 959         hi3110_power_enable(priv->power, 0);
 960
 961         if (!IS_ERR(priv->clk))
 962                 clk_disable_unprepare(priv->clk);
 963
 964         free_candev(net);
 965
 966         return 0;
 967 }
 968
 969 static int __maybe_unused hi3110_can_suspend(struct device *dev)
 970 {
 971         struct spi_device *spi = to_spi_device(dev);
 972         struct hi3110_priv *priv = spi_get_drvdata(spi);
 973         struct net_device *net = priv->net;
 974
 975         priv->force_quit = 1;
 976         disable_irq(spi->irq);
 977
 978         /* Note: at this point neither IST nor workqueues are running.
 979          * open/stop cannot be called anyway so locking is not needed
 980          */
 981         if (netif_running(net)) {
 982                 netif_device_detach(net);
 983
 984                 hi3110_hw_sleep(spi);
 985                 hi3110_power_enable(priv->transceiver, 0);
 986                 priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
 987         } else {
 988                 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
 989         }
 990
 991         if (!IS_ERR_OR_NULL(priv->power)) {
 992                 regulator_disable(priv->power);
 993                 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
 994         }
 995
 996         return 0;
 997 }
 998
 999 static int __maybe_unused hi3110_can_resume(struct device *dev)
1000 {
1001         struct spi_device *spi = to_spi_device(dev);
1002         struct hi3110_priv *priv = spi_get_drvdata(spi);
1003
1004         if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
1005                 hi3110_power_enable(priv->power, 1);
1006
1007         if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
1008                 hi3110_power_enable(priv->transceiver, 1);
1009                 queue_work(priv->wq, &priv->restart_work);
1010         } else {
1011                 priv->after_suspend = 0;
1012         }
1013
1014         priv->force_quit = 0;
1015         enable_irq(spi->irq);
1016         return 0;
1017 }
1018
1019 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume);
1020
1021 static struct spi_driver hi3110_can_driver = {
1022         .driver = {
1023                 .name = DEVICE_NAME,
1024                 .of_match_table = hi3110_of_match,
1025                 .pm = &hi3110_can_pm_ops,
1026         },
1027         .id_table = hi3110_id_table,
1028         .probe = hi3110_can_probe,
1029         .remove = hi3110_can_remove,
1030 };
1031
1032 module_spi_driver(hi3110_can_driver);
1033
1034 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
1035 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
1036 MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
1037 MODULE_LICENSE("GPL v2");