drivers/net/can/m_can/tcan4x5x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // SPI to CAN driver for the Texas Instruments TCAN4x5x
   3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
   4
   5 #include <linux/regmap.h>
   6 #include <linux/spi/spi.h>
   7
   8 #include <linux/regulator/consumer.h>
   9 #include <linux/gpio/consumer.h>
  10
  11 #include "m_can.h"
  12
  13 #define DEVICE_NAME "tcan4x5x"
  14 #define TCAN4X5X_EXT_CLK_DEF 40000000
  15
  16 #define TCAN4X5X_DEV_ID0 0x00
  17 #define TCAN4X5X_DEV_ID1 0x04
  18 #define TCAN4X5X_REV 0x08
  19 #define TCAN4X5X_STATUS 0x0C
  20 #define TCAN4X5X_ERROR_STATUS 0x10
  21 #define TCAN4X5X_CONTROL 0x14
  22
  23 #define TCAN4X5X_CONFIG 0x800
  24 #define TCAN4X5X_TS_PRESCALE 0x804
  25 #define TCAN4X5X_TEST_REG 0x808
  26 #define TCAN4X5X_INT_FLAGS 0x820
  27 #define TCAN4X5X_MCAN_INT_REG 0x824
  28 #define TCAN4X5X_INT_EN 0x830
  29
  30 /* Interrupt bits */
  31 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
  32 #define TCAN4X5X_CANHCANL_INT_EN BIT(29)
  33 #define TCAN4X5X_CANHBAT_INT_EN BIT(28)
  34 #define TCAN4X5X_CANLGND_INT_EN BIT(27)
  35 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
  36 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
  37 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
  38 #define TCAN4X5X_UVSUP_INT_EN BIT(22)
  39 #define TCAN4X5X_UVIO_INT_EN BIT(21)
  40 #define TCAN4X5X_TSD_INT_EN BIT(19)
  41 #define TCAN4X5X_ECCERR_INT_EN BIT(16)
  42 #define TCAN4X5X_CANINT_INT_EN BIT(15)
  43 #define TCAN4X5X_LWU_INT_EN BIT(14)
  44 #define TCAN4X5X_CANSLNT_INT_EN BIT(10)
  45 #define TCAN4X5X_CANDOM_INT_EN BIT(8)
  46 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
  47 #define TCAN4X5X_BUS_FAULT BIT(4)
  48 #define TCAN4X5X_MCAN_INT BIT(1)
  49 #define TCAN4X5X_ENABLE_TCAN_INT \
  50         (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
  51          TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
  52
  53 /* MCAN Interrupt bits */
  54 #define TCAN4X5X_MCAN_IR_ARA BIT(29)
  55 #define TCAN4X5X_MCAN_IR_PED BIT(28)
  56 #define TCAN4X5X_MCAN_IR_PEA BIT(27)
  57 #define TCAN4X5X_MCAN_IR_WD BIT(26)
  58 #define TCAN4X5X_MCAN_IR_BO BIT(25)
  59 #define TCAN4X5X_MCAN_IR_EW BIT(24)
  60 #define TCAN4X5X_MCAN_IR_EP BIT(23)
  61 #define TCAN4X5X_MCAN_IR_ELO BIT(22)
  62 #define TCAN4X5X_MCAN_IR_BEU BIT(21)
  63 #define TCAN4X5X_MCAN_IR_BEC BIT(20)
  64 #define TCAN4X5X_MCAN_IR_DRX BIT(19)
  65 #define TCAN4X5X_MCAN_IR_TOO BIT(18)
  66 #define TCAN4X5X_MCAN_IR_MRAF BIT(17)
  67 #define TCAN4X5X_MCAN_IR_TSW BIT(16)
  68 #define TCAN4X5X_MCAN_IR_TEFL BIT(15)
  69 #define TCAN4X5X_MCAN_IR_TEFF BIT(14)
  70 #define TCAN4X5X_MCAN_IR_TEFW BIT(13)
  71 #define TCAN4X5X_MCAN_IR_TEFN BIT(12)
  72 #define TCAN4X5X_MCAN_IR_TFE BIT(11)
  73 #define TCAN4X5X_MCAN_IR_TCF BIT(10)
  74 #define TCAN4X5X_MCAN_IR_TC BIT(9)
  75 #define TCAN4X5X_MCAN_IR_HPM BIT(8)
  76 #define TCAN4X5X_MCAN_IR_RF1L BIT(7)
  77 #define TCAN4X5X_MCAN_IR_RF1F BIT(6)
  78 #define TCAN4X5X_MCAN_IR_RF1W BIT(5)
  79 #define TCAN4X5X_MCAN_IR_RF1N BIT(4)
  80 #define TCAN4X5X_MCAN_IR_RF0L BIT(3)
  81 #define TCAN4X5X_MCAN_IR_RF0F BIT(2)
  82 #define TCAN4X5X_MCAN_IR_RF0W BIT(1)
  83 #define TCAN4X5X_MCAN_IR_RF0N BIT(0)
  84 #define TCAN4X5X_ENABLE_MCAN_INT \
  85         (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
  86          TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
  87          TCAN4X5X_MCAN_IR_RF1F)
  88
  89 #define TCAN4X5X_MRAM_START 0x8000
  90 #define TCAN4X5X_MCAN_OFFSET 0x1000
  91 #define TCAN4X5X_MAX_REGISTER 0x8fff
  92
  93 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
  94 #define TCAN4X5X_SET_ALL_INT 0xffffffff
  95
  96 #define TCAN4X5X_WRITE_CMD (0x61 << 24)
  97 #define TCAN4X5X_READ_CMD (0x41 << 24)
  98
  99 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
 100 #define TCAN4X5X_MODE_SLEEP 0x00
 101 #define TCAN4X5X_MODE_STANDBY BIT(6)
 102 #define TCAN4X5X_MODE_NORMAL BIT(7)
 103
 104 #define TCAN4X5X_DISABLE_WAKE_MSK       (BIT(31) | BIT(30))
 105 #define TCAN4X5X_DISABLE_INH_MSK        BIT(9)
 106
 107 #define TCAN4X5X_SW_RESET BIT(2)
 108
 109 #define TCAN4X5X_MCAN_CONFIGURED BIT(5)
 110 #define TCAN4X5X_WATCHDOG_EN BIT(3)
 111 #define TCAN4X5X_WD_60_MS_TIMER 0
 112 #define TCAN4X5X_WD_600_MS_TIMER BIT(28)
 113 #define TCAN4X5X_WD_3_S_TIMER BIT(29)
 114 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
 115
 116 struct tcan4x5x_priv {
 117         struct m_can_classdev cdev;
 118
 119         struct regmap *regmap;
 120         struct spi_device *spi;
 121
 122         struct gpio_desc *reset_gpio;
 123         struct gpio_desc *device_wake_gpio;
 124         struct gpio_desc *device_state_gpio;
 125         struct regulator *power;
 126 };
 127
 128 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev)
 129 {
 130         return container_of(cdev, struct tcan4x5x_priv, cdev);
 131
 132 }
 133
 134 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
 135 {
 136         int wake_state = 0;
 137
 138         if (priv->device_state_gpio)
 139                 wake_state = gpiod_get_value(priv->device_state_gpio);
 140
 141         if (priv->device_wake_gpio && wake_state) {
 142                 gpiod_set_value(priv->device_wake_gpio, 0);
 143                 usleep_range(5, 50);
 144                 gpiod_set_value(priv->device_wake_gpio, 1);
 145         }
 146 }
 147
 148 static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
 149 {
 150         int ret = 0;
 151
 152         if (priv->reset_gpio) {
 153                 gpiod_set_value(priv->reset_gpio, 1);
 154
 155                 /* tpulse_width minimum 30us */
 156                 usleep_range(30, 100);
 157                 gpiod_set_value(priv->reset_gpio, 0);
 158         } else {
 159                 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
 160                                    TCAN4X5X_SW_RESET);
 161                 if (ret)
 162                         return ret;
 163         }
 164
 165         usleep_range(700, 1000);
 166
 167         return ret;
 168 }
 169
 170 static int regmap_spi_gather_write(void *context, const void *reg,
 171                                    size_t reg_len, const void *val,
 172                                    size_t val_len)
 173 {
 174         struct device *dev = context;
 175         struct spi_device *spi = to_spi_device(dev);
 176         struct spi_message m;
 177         u32 addr;
 178         struct spi_transfer t[2] = {
 179                 { .tx_buf = &addr, .len = reg_len, .cs_change = 0,},
 180                 { .tx_buf = val, .len = val_len, },
 181         };
 182
 183         addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2;
 184
 185         spi_message_init(&m);
 186         spi_message_add_tail(&t[0], &m);
 187         spi_message_add_tail(&t[1], &m);
 188
 189         return spi_sync(spi, &m);
 190 }
 191
 192 static int tcan4x5x_regmap_write(void *context, const void *data, size_t count)
 193 {
 194         u16 *reg = (u16 *)(data);
 195         const u32 *val = data + 4;
 196
 197         return regmap_spi_gather_write(context, reg, 4, val, count - 4);
 198 }
 199
 200 static int regmap_spi_async_write(void *context,
 201                                   const void *reg, size_t reg_len,
 202                                   const void *val, size_t val_len,
 203                                   struct regmap_async *a)
 204 {
 205         return -ENOTSUPP;
 206 }
 207
 208 static struct regmap_async *regmap_spi_async_alloc(void)
 209 {
 210         return NULL;
 211 }
 212
 213 static int tcan4x5x_regmap_read(void *context,
 214                                 const void *reg, size_t reg_size,
 215                                 void *val, size_t val_size)
 216 {
 217         struct device *dev = context;
 218         struct spi_device *spi = to_spi_device(dev);
 219
 220         u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2;
 221
 222         return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size);
 223 }
 224
 225 static struct regmap_bus tcan4x5x_bus = {
 226         .write = tcan4x5x_regmap_write,
 227         .gather_write = regmap_spi_gather_write,
 228         .async_write = regmap_spi_async_write,
 229         .async_alloc = regmap_spi_async_alloc,
 230         .read = tcan4x5x_regmap_read,
 231         .read_flag_mask = 0x00,
 232         .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
 233         .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
 234 };
 235
 236 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
 237 {
 238         struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
 239         u32 val;
 240
 241         regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val);
 242
 243         return val;
 244 }
 245
 246 static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
 247 {
 248         struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
 249         u32 val;
 250
 251         regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val);
 252
 253         return val;
 254 }
 255
 256 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
 257 {
 258         struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
 259
 260         return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val);
 261 }
 262
 263 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
 264                                int addr_offset, int val)
 265 {
 266         struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
 267
 268         return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val);
 269 }
 270
 271 static int tcan4x5x_power_enable(struct regulator *reg, int enable)
 272 {
 273         if (IS_ERR_OR_NULL(reg))
 274                 return 0;
 275
 276         if (enable)
 277                 return regulator_enable(reg);
 278         else
 279                 return regulator_disable(reg);
 280 }
 281
 282 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
 283                                    int reg, int val)
 284 {
 285         struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
 286
 287         return regmap_write(priv->regmap, reg, val);
 288 }
 289
 290 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
 291 {
 292         int ret;
 293
 294         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
 295                                       TCAN4X5X_CLEAR_ALL_INT);
 296         if (ret)
 297                 return ret;
 298
 299         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
 300                                       TCAN4X5X_ENABLE_MCAN_INT);
 301         if (ret)
 302                 return ret;
 303
 304         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
 305                                       TCAN4X5X_CLEAR_ALL_INT);
 306         if (ret)
 307                 return ret;
 308
 309         return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
 310                                        TCAN4X5X_CLEAR_ALL_INT);
 311 }
 312
 313 static int tcan4x5x_init(struct m_can_classdev *cdev)
 314 {
 315         struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
 316         int ret;
 317
 318         tcan4x5x_check_wake(tcan4x5x);
 319
 320         ret = tcan4x5x_clear_interrupts(cdev);
 321         if (ret)
 322                 return ret;
 323
 324         ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
 325                                       TCAN4X5X_ENABLE_TCAN_INT);
 326         if (ret)
 327                 return ret;
 328
 329         ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 330                                  TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
 331         if (ret)
 332                 return ret;
 333
 334         /* Zero out the MCAN buffers */
 335         m_can_init_ram(cdev);
 336
 337         return ret;
 338 }
 339
 340 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
 341 {
 342         struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
 343
 344         return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 345                                   TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
 346 }
 347
 348 static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
 349 {
 350         struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
 351
 352         return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
 353                                   TCAN4X5X_DISABLE_INH_MSK, 0x01);
 354 }
 355
 356 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev)
 357 {
 358         struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
 359         int ret;
 360
 361         tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
 362                                                     GPIOD_OUT_HIGH);
 363         if (IS_ERR(tcan4x5x->device_wake_gpio)) {
 364                 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER)
 365                         return -EPROBE_DEFER;
 366
 367                 tcan4x5x_disable_wake(cdev);
 368         }
 369
 370         tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
 371                                                        GPIOD_OUT_LOW);
 372         if (IS_ERR(tcan4x5x->reset_gpio))
 373                 tcan4x5x->reset_gpio = NULL;
 374
 375         ret = tcan4x5x_reset(tcan4x5x);
 376         if (ret)
 377                 return ret;
 378
 379         tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
 380                                                               "device-state",
 381                                                               GPIOD_IN);
 382         if (IS_ERR(tcan4x5x->device_state_gpio)) {
 383                 tcan4x5x->device_state_gpio = NULL;
 384                 tcan4x5x_disable_state(cdev);
 385         }
 386
 387         return 0;
 388 }
 389
 390 static const struct regmap_config tcan4x5x_regmap = {
 391         .reg_bits = 32,
 392         .val_bits = 32,
 393         .cache_type = REGCACHE_NONE,
 394         .max_register = TCAN4X5X_MAX_REGISTER,
 395 };
 396
 397 static struct m_can_ops tcan4x5x_ops = {
 398         .init = tcan4x5x_init,
 399         .read_reg = tcan4x5x_read_reg,
 400         .write_reg = tcan4x5x_write_reg,
 401         .write_fifo = tcan4x5x_write_fifo,
 402         .read_fifo = tcan4x5x_read_fifo,
 403         .clear_interrupts = tcan4x5x_clear_interrupts,
 404 };
 405
 406 static int tcan4x5x_can_probe(struct spi_device *spi)
 407 {
 408         struct tcan4x5x_priv *priv;
 409         struct m_can_classdev *mcan_class;
 410         int freq, ret;
 411
 412         mcan_class = m_can_class_allocate_dev(&spi->dev,
 413                                               sizeof(struct tcan4x5x_priv));
 414         if (!mcan_class)
 415                 return -ENOMEM;
 416
 417         priv = cdev_to_priv(mcan_class);
 418
 419         priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
 420         if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
 421                 ret = -EPROBE_DEFER;
 422                 goto out_m_can_class_free_dev;
 423         } else {
 424                 priv->power = NULL;
 425         }
 426
 427         m_can_class_get_clocks(mcan_class);
 428         if (IS_ERR(mcan_class->cclk)) {
 429                 dev_err(&spi->dev, "no CAN clock source defined\n");
 430                 freq = TCAN4X5X_EXT_CLK_DEF;
 431         } else {
 432                 freq = clk_get_rate(mcan_class->cclk);
 433         }
 434
 435         /* Sanity check */
 436         if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) {
 437                 ret = -ERANGE;
 438                 goto out_m_can_class_free_dev;
 439         }
 440
 441         priv->spi = spi;
 442
 443         mcan_class->pm_clock_support = 0;
 444         mcan_class->can.clock.freq = freq;
 445         mcan_class->dev = &spi->dev;
 446         mcan_class->ops = &tcan4x5x_ops;
 447         mcan_class->is_peripheral = true;
 448         mcan_class->net->irq = spi->irq;
 449
 450         spi_set_drvdata(spi, priv);
 451
 452         /* Configure the SPI bus */
 453         spi->bits_per_word = 32;
 454         ret = spi_setup(spi);
 455         if (ret)
 456                 goto out_m_can_class_free_dev;
 457
 458         priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
 459                                         &spi->dev, &tcan4x5x_regmap);
 460         if (IS_ERR(priv->regmap)) {
 461                 ret = PTR_ERR(priv->regmap);
 462                 goto out_m_can_class_free_dev;
 463         }
 464
 465         ret = tcan4x5x_power_enable(priv->power, 1);
 466         if (ret)
 467                 goto out_m_can_class_free_dev;
 468
 469         ret = tcan4x5x_get_gpios(mcan_class);
 470         if (ret)
 471                 goto out_power;
 472
 473         ret = tcan4x5x_init(mcan_class);
 474         if (ret)
 475                 goto out_power;
 476
 477         ret = m_can_class_register(mcan_class);
 478         if (ret)
 479                 goto out_power;
 480
 481         netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
 482         return 0;
 483
 484 out_power:
 485         tcan4x5x_power_enable(priv->power, 0);
 486  out_m_can_class_free_dev:
 487         m_can_class_free_dev(mcan_class->net);
 488         return ret;
 489 }
 490
 491 static int tcan4x5x_can_remove(struct spi_device *spi)
 492 {
 493         struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
 494
 495         m_can_class_unregister(&priv->cdev);
 496
 497         tcan4x5x_power_enable(priv->power, 0);
 498
 499         m_can_class_free_dev(priv->cdev.net);
 500
 501         return 0;
 502 }
 503
 504 static const struct of_device_id tcan4x5x_of_match[] = {
 505         { .compatible = "ti,tcan4x5x", },
 506         { }
 507 };
 508 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
 509
 510 static const struct spi_device_id tcan4x5x_id_table[] = {
 511         {
 512                 .name           = "tcan4x5x",
 513                 .driver_data    = 0,
 514         },
 515         { }
 516 };
 517 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
 518
 519 static struct spi_driver tcan4x5x_can_driver = {
 520         .driver = {
 521                 .name = DEVICE_NAME,
 522                 .of_match_table = tcan4x5x_of_match,
 523                 .pm = NULL,
 524         },
 525         .id_table = tcan4x5x_id_table,
 526         .probe = tcan4x5x_can_probe,
 527         .remove = tcan4x5x_can_remove,
 528 };
 529 module_spi_driver(tcan4x5x_can_driver);
 530
 531 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
 532 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
 533 MODULE_LICENSE("GPL v2");