1 // SPDX-License-Identifier: GPL-2.0
2 // SPI to CAN driver for the Texas Instruments TCAN4x5x
3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
7 #define TCAN4X5X_EXT_CLK_DEF 40000000
9 #define TCAN4X5X_DEV_ID0 0x00
10 #define TCAN4X5X_DEV_ID1 0x04
11 #define TCAN4X5X_REV 0x08
12 #define TCAN4X5X_STATUS 0x0C
13 #define TCAN4X5X_ERROR_STATUS 0x10
14 #define TCAN4X5X_CONTROL 0x14
16 #define TCAN4X5X_CONFIG 0x800
17 #define TCAN4X5X_TS_PRESCALE 0x804
18 #define TCAN4X5X_TEST_REG 0x808
19 #define TCAN4X5X_INT_FLAGS 0x820
20 #define TCAN4X5X_MCAN_INT_REG 0x824
21 #define TCAN4X5X_INT_EN 0x830
24 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
25 #define TCAN4X5X_CANHCANL_INT_EN BIT(29)
26 #define TCAN4X5X_CANHBAT_INT_EN BIT(28)
27 #define TCAN4X5X_CANLGND_INT_EN BIT(27)
28 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
29 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
30 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
31 #define TCAN4X5X_UVSUP_INT_EN BIT(22)
32 #define TCAN4X5X_UVIO_INT_EN BIT(21)
33 #define TCAN4X5X_TSD_INT_EN BIT(19)
34 #define TCAN4X5X_ECCERR_INT_EN BIT(16)
35 #define TCAN4X5X_CANINT_INT_EN BIT(15)
36 #define TCAN4X5X_LWU_INT_EN BIT(14)
37 #define TCAN4X5X_CANSLNT_INT_EN BIT(10)
38 #define TCAN4X5X_CANDOM_INT_EN BIT(8)
39 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
40 #define TCAN4X5X_BUS_FAULT BIT(4)
41 #define TCAN4X5X_MCAN_INT BIT(1)
42 #define TCAN4X5X_ENABLE_TCAN_INT \
43 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
44 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
46 /* MCAN Interrupt bits */
47 #define TCAN4X5X_MCAN_IR_ARA BIT(29)
48 #define TCAN4X5X_MCAN_IR_PED BIT(28)
49 #define TCAN4X5X_MCAN_IR_PEA BIT(27)
50 #define TCAN4X5X_MCAN_IR_WD BIT(26)
51 #define TCAN4X5X_MCAN_IR_BO BIT(25)
52 #define TCAN4X5X_MCAN_IR_EW BIT(24)
53 #define TCAN4X5X_MCAN_IR_EP BIT(23)
54 #define TCAN4X5X_MCAN_IR_ELO BIT(22)
55 #define TCAN4X5X_MCAN_IR_BEU BIT(21)
56 #define TCAN4X5X_MCAN_IR_BEC BIT(20)
57 #define TCAN4X5X_MCAN_IR_DRX BIT(19)
58 #define TCAN4X5X_MCAN_IR_TOO BIT(18)
59 #define TCAN4X5X_MCAN_IR_MRAF BIT(17)
60 #define TCAN4X5X_MCAN_IR_TSW BIT(16)
61 #define TCAN4X5X_MCAN_IR_TEFL BIT(15)
62 #define TCAN4X5X_MCAN_IR_TEFF BIT(14)
63 #define TCAN4X5X_MCAN_IR_TEFW BIT(13)
64 #define TCAN4X5X_MCAN_IR_TEFN BIT(12)
65 #define TCAN4X5X_MCAN_IR_TFE BIT(11)
66 #define TCAN4X5X_MCAN_IR_TCF BIT(10)
67 #define TCAN4X5X_MCAN_IR_TC BIT(9)
68 #define TCAN4X5X_MCAN_IR_HPM BIT(8)
69 #define TCAN4X5X_MCAN_IR_RF1L BIT(7)
70 #define TCAN4X5X_MCAN_IR_RF1F BIT(6)
71 #define TCAN4X5X_MCAN_IR_RF1W BIT(5)
72 #define TCAN4X5X_MCAN_IR_RF1N BIT(4)
73 #define TCAN4X5X_MCAN_IR_RF0L BIT(3)
74 #define TCAN4X5X_MCAN_IR_RF0F BIT(2)
75 #define TCAN4X5X_MCAN_IR_RF0W BIT(1)
76 #define TCAN4X5X_MCAN_IR_RF0N BIT(0)
77 #define TCAN4X5X_ENABLE_MCAN_INT \
78 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
79 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
80 TCAN4X5X_MCAN_IR_RF1F)
82 #define TCAN4X5X_MRAM_START 0x8000
83 #define TCAN4X5X_MCAN_OFFSET 0x1000
85 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
86 #define TCAN4X5X_SET_ALL_INT 0xffffffff
88 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
89 #define TCAN4X5X_MODE_SLEEP 0x00
90 #define TCAN4X5X_MODE_STANDBY BIT(6)
91 #define TCAN4X5X_MODE_NORMAL BIT(7)
93 #define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30))
94 #define TCAN4X5X_DISABLE_INH_MSK BIT(9)
96 #define TCAN4X5X_SW_RESET BIT(2)
98 #define TCAN4X5X_MCAN_CONFIGURED BIT(5)
99 #define TCAN4X5X_WATCHDOG_EN BIT(3)
100 #define TCAN4X5X_WD_60_MS_TIMER 0
101 #define TCAN4X5X_WD_600_MS_TIMER BIT(28)
102 #define TCAN4X5X_WD_3_S_TIMER BIT(29)
103 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
105 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev)
107 return container_of(cdev, struct tcan4x5x_priv, cdev);
111 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
115 if (priv->device_state_gpio)
116 wake_state = gpiod_get_value(priv->device_state_gpio);
118 if (priv->device_wake_gpio && wake_state) {
119 gpiod_set_value(priv->device_wake_gpio, 0);
121 gpiod_set_value(priv->device_wake_gpio, 1);
125 static int tcan4x5x_reset(struct tcan4x5x_priv *priv)
129 if (priv->reset_gpio) {
130 gpiod_set_value(priv->reset_gpio, 1);
132 /* tpulse_width minimum 30us */
133 usleep_range(30, 100);
134 gpiod_set_value(priv->reset_gpio, 0);
136 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG,
142 usleep_range(700, 1000);
147 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
149 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
152 regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val);
157 static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
159 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
162 regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val);
167 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
169 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
171 return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val);
174 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
175 int addr_offset, int val)
177 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
179 return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val);
182 static int tcan4x5x_power_enable(struct regulator *reg, int enable)
184 if (IS_ERR_OR_NULL(reg))
188 return regulator_enable(reg);
190 return regulator_disable(reg);
193 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
196 struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
198 return regmap_write(priv->regmap, reg, val);
201 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
205 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
206 TCAN4X5X_CLEAR_ALL_INT);
210 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
211 TCAN4X5X_ENABLE_MCAN_INT);
215 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
216 TCAN4X5X_CLEAR_ALL_INT);
220 return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
221 TCAN4X5X_CLEAR_ALL_INT);
224 static int tcan4x5x_init(struct m_can_classdev *cdev)
226 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
229 tcan4x5x_check_wake(tcan4x5x);
231 ret = tcan4x5x_clear_interrupts(cdev);
235 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
236 TCAN4X5X_ENABLE_TCAN_INT);
240 /* Zero out the MCAN buffers */
241 m_can_init_ram(cdev);
243 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
244 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
251 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
253 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
255 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
256 TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
259 static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
261 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
263 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
264 TCAN4X5X_DISABLE_INH_MSK, 0x01);
267 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev)
269 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
272 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
274 if (IS_ERR(tcan4x5x->device_wake_gpio)) {
275 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER)
276 return -EPROBE_DEFER;
278 tcan4x5x_disable_wake(cdev);
281 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
283 if (IS_ERR(tcan4x5x->reset_gpio))
284 tcan4x5x->reset_gpio = NULL;
286 ret = tcan4x5x_reset(tcan4x5x);
290 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
293 if (IS_ERR(tcan4x5x->device_state_gpio)) {
294 tcan4x5x->device_state_gpio = NULL;
295 tcan4x5x_disable_state(cdev);
301 static struct m_can_ops tcan4x5x_ops = {
302 .init = tcan4x5x_init,
303 .read_reg = tcan4x5x_read_reg,
304 .write_reg = tcan4x5x_write_reg,
305 .write_fifo = tcan4x5x_write_fifo,
306 .read_fifo = tcan4x5x_read_fifo,
307 .clear_interrupts = tcan4x5x_clear_interrupts,
310 static int tcan4x5x_can_probe(struct spi_device *spi)
312 struct tcan4x5x_priv *priv;
313 struct m_can_classdev *mcan_class;
316 mcan_class = m_can_class_allocate_dev(&spi->dev,
317 sizeof(struct tcan4x5x_priv));
321 priv = cdev_to_priv(mcan_class);
323 priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
324 if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
326 goto out_m_can_class_free_dev;
331 m_can_class_get_clocks(mcan_class);
332 if (IS_ERR(mcan_class->cclk)) {
333 dev_err(&spi->dev, "no CAN clock source defined\n");
334 freq = TCAN4X5X_EXT_CLK_DEF;
336 freq = clk_get_rate(mcan_class->cclk);
340 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) {
342 goto out_m_can_class_free_dev;
347 mcan_class->pm_clock_support = 0;
348 mcan_class->can.clock.freq = freq;
349 mcan_class->dev = &spi->dev;
350 mcan_class->ops = &tcan4x5x_ops;
351 mcan_class->is_peripheral = true;
352 mcan_class->net->irq = spi->irq;
354 spi_set_drvdata(spi, priv);
356 /* Configure the SPI bus */
357 spi->bits_per_word = 8;
358 ret = spi_setup(spi);
360 goto out_m_can_class_free_dev;
362 ret = tcan4x5x_regmap_init(priv);
364 goto out_m_can_class_free_dev;
366 ret = tcan4x5x_power_enable(priv->power, 1);
368 goto out_m_can_class_free_dev;
370 ret = tcan4x5x_get_gpios(mcan_class);
374 ret = tcan4x5x_init(mcan_class);
378 ret = m_can_class_register(mcan_class);
382 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
386 tcan4x5x_power_enable(priv->power, 0);
387 out_m_can_class_free_dev:
388 m_can_class_free_dev(mcan_class->net);
392 static int tcan4x5x_can_remove(struct spi_device *spi)
394 struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
396 m_can_class_unregister(&priv->cdev);
398 tcan4x5x_power_enable(priv->power, 0);
400 m_can_class_free_dev(priv->cdev.net);
405 static const struct of_device_id tcan4x5x_of_match[] = {
407 .compatible = "ti,tcan4x5x",
412 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
414 static const struct spi_device_id tcan4x5x_id_table[] = {
421 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
423 static struct spi_driver tcan4x5x_can_driver = {
425 .name = KBUILD_MODNAME,
426 .of_match_table = tcan4x5x_of_match,
429 .id_table = tcan4x5x_id_table,
430 .probe = tcan4x5x_can_probe,
431 .remove = tcan4x5x_can_remove,
433 module_spi_driver(tcan4x5x_can_driver);
435 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
436 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
437 MODULE_LICENSE("GPL v2");