drivers/net/can/grcan.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
   4  *
   5  * 2012 (c) Aeroflex Gaisler AB
   6  *
   7  * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
   8  * VHDL IP core library.
   9  *
  10  * Full documentation of the GRCAN core can be found here:
  11  * http://www.gaisler.com/products/grlib/grip.pdf
  12  *
  13  * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
  14  * open firmware properties.
  15  *
  16  * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
  17  * sysfs interface.
  18  *
  19  * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module
  20  * parameters.
  21  *
  22  * Contributors: Andreas Larsson <andreas@gaisler.com>
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/delay.h>
  30 #include <linux/io.h>
  31 #include <linux/can/dev.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_irq.h>
  35
  36 #include <linux/dma-mapping.h>
  37
  38 #define DRV_NAME        "grcan"
  39
  40 #define GRCAN_NAPI_WEIGHT       32
  41
  42 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
  43
  44 struct grcan_registers {
  45         u32 conf;       /* 0x00 */
  46         u32 stat;       /* 0x04 */
  47         u32 ctrl;       /* 0x08 */
  48         u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
  49         u32 smask;      /* 0x18 - CanMASK */
  50         u32 scode;      /* 0x1c - CanCODE */
  51         u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
  52         u32 pimsr;      /* 0x100 */
  53         u32 pimr;       /* 0x104 */
  54         u32 pisr;       /* 0x108 */
  55         u32 pir;        /* 0x10C */
  56         u32 imr;        /* 0x110 */
  57         u32 picr;       /* 0x114 */
  58         u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
  59         u32 txctrl;     /* 0x200 */
  60         u32 txaddr;     /* 0x204 */
  61         u32 txsize;     /* 0x208 */
  62         u32 txwr;       /* 0x20C */
  63         u32 txrd;       /* 0x210 */
  64         u32 txirq;      /* 0x214 */
  65         u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
  66         u32 rxctrl;     /* 0x300 */
  67         u32 rxaddr;     /* 0x304 */
  68         u32 rxsize;     /* 0x308 */
  69         u32 rxwr;       /* 0x30C */
  70         u32 rxrd;       /* 0x310 */
  71         u32 rxirq;      /* 0x314 */
  72         u32 rxmask;     /* 0x318 */
  73         u32 rxcode;     /* 0x31C */
  74 };
  75
  76 #define GRCAN_CONF_ABORT        0x00000001
  77 #define GRCAN_CONF_ENABLE0      0x00000002
  78 #define GRCAN_CONF_ENABLE1      0x00000004
  79 #define GRCAN_CONF_SELECT       0x00000008
  80 #define GRCAN_CONF_SILENT       0x00000010
  81 #define GRCAN_CONF_SAM          0x00000020 /* Available in some hardware */
  82 #define GRCAN_CONF_BPR          0x00000300 /* Note: not BRP */
  83 #define GRCAN_CONF_RSJ          0x00007000
  84 #define GRCAN_CONF_PS1          0x00f00000
  85 #define GRCAN_CONF_PS2          0x000f0000
  86 #define GRCAN_CONF_SCALER       0xff000000
  87 #define GRCAN_CONF_OPERATION                                            \
  88         (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1     \
  89          | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
  90 #define GRCAN_CONF_TIMING                                               \
  91         (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1               \
  92          | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
  93
  94 #define GRCAN_CONF_RSJ_MIN      1
  95 #define GRCAN_CONF_RSJ_MAX      4
  96 #define GRCAN_CONF_PS1_MIN      1
  97 #define GRCAN_CONF_PS1_MAX      15
  98 #define GRCAN_CONF_PS2_MIN      2
  99 #define GRCAN_CONF_PS2_MAX      8
 100 #define GRCAN_CONF_SCALER_MIN   0
 101 #define GRCAN_CONF_SCALER_MAX   255
 102 #define GRCAN_CONF_SCALER_INC   1
 103
 104 #define GRCAN_CONF_BPR_BIT      8
 105 #define GRCAN_CONF_RSJ_BIT      12
 106 #define GRCAN_CONF_PS1_BIT      20
 107 #define GRCAN_CONF_PS2_BIT      16
 108 #define GRCAN_CONF_SCALER_BIT   24
 109
 110 #define GRCAN_STAT_PASS         0x000001
 111 #define GRCAN_STAT_OFF          0x000002
 112 #define GRCAN_STAT_OR           0x000004
 113 #define GRCAN_STAT_AHBERR       0x000008
 114 #define GRCAN_STAT_ACTIVE       0x000010
 115 #define GRCAN_STAT_RXERRCNT     0x00ff00
 116 #define GRCAN_STAT_TXERRCNT     0xff0000
 117
 118 #define GRCAN_STAT_ERRCTR_RELATED       (GRCAN_STAT_PASS | GRCAN_STAT_OFF)
 119
 120 #define GRCAN_STAT_RXERRCNT_BIT 8
 121 #define GRCAN_STAT_TXERRCNT_BIT 16
 122
 123 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96
 124 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127
 125
 126 #define GRCAN_CTRL_RESET        0x2
 127 #define GRCAN_CTRL_ENABLE       0x1
 128
 129 #define GRCAN_TXCTRL_ENABLE     0x1
 130 #define GRCAN_TXCTRL_ONGOING    0x2
 131 #define GRCAN_TXCTRL_SINGLE     0x4
 132
 133 #define GRCAN_RXCTRL_ENABLE     0x1
 134 #define GRCAN_RXCTRL_ONGOING    0x2
 135
 136 /* Relative offset of IRQ sources to AMBA Plug&Play */
 137 #define GRCAN_IRQIX_IRQ         0
 138 #define GRCAN_IRQIX_TXSYNC      1
 139 #define GRCAN_IRQIX_RXSYNC      2
 140
 141 #define GRCAN_IRQ_PASS          0x00001
 142 #define GRCAN_IRQ_OFF           0x00002
 143 #define GRCAN_IRQ_OR            0x00004
 144 #define GRCAN_IRQ_RXAHBERR      0x00008
 145 #define GRCAN_IRQ_TXAHBERR      0x00010
 146 #define GRCAN_IRQ_RXIRQ         0x00020
 147 #define GRCAN_IRQ_TXIRQ         0x00040
 148 #define GRCAN_IRQ_RXFULL        0x00080
 149 #define GRCAN_IRQ_TXEMPTY       0x00100
 150 #define GRCAN_IRQ_RX            0x00200
 151 #define GRCAN_IRQ_TX            0x00400
 152 #define GRCAN_IRQ_RXSYNC        0x00800
 153 #define GRCAN_IRQ_TXSYNC        0x01000
 154 #define GRCAN_IRQ_RXERRCTR      0x02000
 155 #define GRCAN_IRQ_TXERRCTR      0x04000
 156 #define GRCAN_IRQ_RXMISS        0x08000
 157 #define GRCAN_IRQ_TXLOSS        0x10000
 158
 159 #define GRCAN_IRQ_NONE  0
 160 #define GRCAN_IRQ_ALL                                                   \
 161         (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR                  \
 162          | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR                      \
 163          | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ                            \
 164          | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY                         \
 165          | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC               \
 166          | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR                        \
 167          | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS                        \
 168          | GRCAN_IRQ_TXLOSS)
 169
 170 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
 171                                   | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
 172 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR       \
 173                           | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR     \
 174                           | GRCAN_IRQ_TXLOSS)
 175 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
 176
 177 #define GRCAN_MSG_SIZE          16
 178
 179 #define GRCAN_MSG_IDE           0x80000000
 180 #define GRCAN_MSG_RTR           0x40000000
 181 #define GRCAN_MSG_BID           0x1ffc0000
 182 #define GRCAN_MSG_EID           0x1fffffff
 183 #define GRCAN_MSG_IDE_BIT       31
 184 #define GRCAN_MSG_RTR_BIT       30
 185 #define GRCAN_MSG_BID_BIT       18
 186 #define GRCAN_MSG_EID_BIT       0
 187
 188 #define GRCAN_MSG_DLC           0xf0000000
 189 #define GRCAN_MSG_TXERRC        0x00ff0000
 190 #define GRCAN_MSG_RXERRC        0x0000ff00
 191 #define GRCAN_MSG_DLC_BIT       28
 192 #define GRCAN_MSG_TXERRC_BIT    16
 193 #define GRCAN_MSG_RXERRC_BIT    8
 194 #define GRCAN_MSG_AHBERR        0x00000008
 195 #define GRCAN_MSG_OR            0x00000004
 196 #define GRCAN_MSG_OFF           0x00000002
 197 #define GRCAN_MSG_PASS          0x00000001
 198
 199 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
 200 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
 201
 202 #define GRCAN_BUFFER_ALIGNMENT          1024
 203 #define GRCAN_DEFAULT_BUFFER_SIZE       1024
 204 #define GRCAN_VALID_TR_SIZE_MASK        0x001fffc0
 205
 206 #define GRCAN_INVALID_BUFFER_SIZE(s)                    \
 207         ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
 208
 209 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
 210 #error "Invalid default buffer size"
 211 #endif
 212
 213 struct grcan_dma_buffer {
 214         size_t size;
 215         void *buf;
 216         dma_addr_t handle;
 217 };
 218
 219 struct grcan_dma {
 220         size_t base_size;
 221         void *base_buf;
 222         dma_addr_t base_handle;
 223         struct grcan_dma_buffer tx;
 224         struct grcan_dma_buffer rx;
 225 };
 226
 227 /* GRCAN configuration parameters */
 228 struct grcan_device_config {
 229         unsigned short enable0;
 230         unsigned short enable1;
 231         unsigned short select;
 232         unsigned int txsize;
 233         unsigned int rxsize;
 234 };
 235
 236 #define GRCAN_DEFAULT_DEVICE_CONFIG {                           \
 237                 .enable0        = 0,                            \
 238                 .enable1        = 0,                            \
 239                 .select         = 0,                            \
 240                 .txsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 241                 .rxsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 242                 }
 243
 244 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION  0x4100
 245 #define GRLIB_VERSION_MASK              0xffff
 246
 247 /* GRCAN private data structure */
 248 struct grcan_priv {
 249         struct can_priv can;    /* must be the first member */
 250         struct net_device *dev;
 251         struct napi_struct napi;
 252
 253         struct grcan_registers __iomem *regs;   /* ioremap'ed registers */
 254         struct grcan_device_config config;
 255         struct grcan_dma dma;
 256
 257         struct sk_buff **echo_skb;      /* We allocate this on our own */
 258
 259         /* The echo skb pointer, pointing into echo_skb and indicating which
 260          * frames can be echoed back. See the "Notes on the tx cyclic buffer
 261          * handling"-comment for grcan_start_xmit for more details.
 262          */
 263         u32 eskbp;
 264
 265         /* Lock for controlling changes to the netif tx queue state, accesses to
 266          * the echo_skb pointer eskbp and for making sure that a running reset
 267          * and/or a close of the interface is done without interference from
 268          * other parts of the code.
 269          *
 270          * The echo_skb pointer, eskbp, should only be accessed under this lock
 271          * as it can be changed in several places and together with decisions on
 272          * whether to wake up the tx queue.
 273          *
 274          * The tx queue must never be woken up if there is a running reset or
 275          * close in progress.
 276          *
 277          * A running reset (see below on need_txbug_workaround) should never be
 278          * done if the interface is closing down and several running resets
 279          * should never be scheduled simultaneously.
 280          */
 281         spinlock_t lock;
 282
 283         /* Whether a workaround is needed due to a bug in older hardware. In
 284          * this case, the driver both tries to prevent the bug from being
 285          * triggered and recovers, if the bug nevertheless happens, by doing a
 286          * running reset. A running reset, resets the device and continues from
 287          * where it were without being noticeable from outside the driver (apart
 288          * from slight delays).
 289          */
 290         bool need_txbug_workaround;
 291
 292         /* To trigger initization of running reset and to trigger running reset
 293          * respectively in the case of a hanged device due to a txbug.
 294          */
 295         struct timer_list hang_timer;
 296         struct timer_list rr_timer;
 297
 298         /* To avoid waking up the netif queue and restarting timers
 299          * when a reset is scheduled or when closing of the device is
 300          * undergoing
 301          */
 302         bool resetting;
 303         bool closing;
 304 };
 305
 306 /* Wait time for a short wait for ongoing to clear */
 307 #define GRCAN_SHORTWAIT_USECS   10
 308
 309 /* Limit on the number of transmitted bits of an eff frame according to the CAN
 310  * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
 311  * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
 312  * bits end of frame
 313  */
 314 #define GRCAN_EFF_FRAME_MAX_BITS        (1+32+6+8*8+16+2+7)
 315
 316 #if defined(__BIG_ENDIAN)
 317 static inline u32 grcan_read_reg(u32 __iomem *reg)
 318 {
 319         return ioread32be(reg);
 320 }
 321
 322 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 323 {
 324         iowrite32be(val, reg);
 325 }
 326 #else
 327 static inline u32 grcan_read_reg(u32 __iomem *reg)
 328 {
 329         return ioread32(reg);
 330 }
 331
 332 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 333 {
 334         iowrite32(val, reg);
 335 }
 336 #endif
 337
 338 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
 339 {
 340         grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
 341 }
 342
 343 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
 344 {
 345         grcan_write_reg(reg, grcan_read_reg(reg) | mask);
 346 }
 347
 348 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
 349 {
 350         return grcan_read_reg(reg) & mask;
 351 }
 352
 353 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
 354 {
 355         u32 old = grcan_read_reg(reg);
 356
 357         grcan_write_reg(reg, (old & ~mask) | (value & mask));
 358 }
 359
 360 /* a and b should both be in [0,size] and a == b == size should not hold */
 361 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
 362 {
 363         u32 sum = a + b;
 364
 365         if (sum < size)
 366                 return sum;
 367         else
 368                 return sum - size;
 369 }
 370
 371 /* a and b should both be in [0,size) */
 372 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
 373 {
 374         return grcan_ring_add(a, size - b, size);
 375 }
 376
 377 /* Available slots for new transmissions */
 378 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
 379 {
 380         u32 slots = txsize / GRCAN_MSG_SIZE - 1;
 381         u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
 382
 383         return slots - used;
 384 }
 385
 386 /* Configuration parameters that can be set via module parameters */
 387 static struct grcan_device_config grcan_module_config =
 388         GRCAN_DEFAULT_DEVICE_CONFIG;
 389
 390 static const struct can_bittiming_const grcan_bittiming_const = {
 391         .name           = DRV_NAME,
 392         .tseg1_min      = GRCAN_CONF_PS1_MIN + 1,
 393         .tseg1_max      = GRCAN_CONF_PS1_MAX + 1,
 394         .tseg2_min      = GRCAN_CONF_PS2_MIN,
 395         .tseg2_max      = GRCAN_CONF_PS2_MAX,
 396         .sjw_max        = GRCAN_CONF_RSJ_MAX,
 397         .brp_min        = GRCAN_CONF_SCALER_MIN + 1,
 398         .brp_max        = GRCAN_CONF_SCALER_MAX + 1,
 399         .brp_inc        = GRCAN_CONF_SCALER_INC,
 400 };
 401
 402 static int grcan_set_bittiming(struct net_device *dev)
 403 {
 404         struct grcan_priv *priv = netdev_priv(dev);
 405         struct grcan_registers __iomem *regs = priv->regs;
 406         struct can_bittiming *bt = &priv->can.bittiming;
 407         u32 timing = 0;
 408         int bpr, rsj, ps1, ps2, scaler;
 409
 410         /* Should never happen - function will not be called when
 411          * device is up
 412          */
 413         if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
 414                 return -EBUSY;
 415
 416         bpr = 0; /* Note bpr and brp are different concepts */
 417         rsj = bt->sjw;
 418         ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
 419         ps2 = bt->phase_seg2;
 420         scaler = (bt->brp - 1);
 421         netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
 422                    bpr, rsj, ps1, ps2, scaler);
 423         if (!(ps1 > ps2)) {
 424                 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
 425                            ps1, ps2);
 426                 return -EINVAL;
 427         }
 428         if (!(ps2 >= rsj)) {
 429                 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
 430                            ps2, rsj);
 431                 return -EINVAL;
 432         }
 433
 434         timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
 435         timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
 436         timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
 437         timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
 438         timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
 439         netdev_info(dev, "setting timing=0x%x\n", timing);
 440         grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
 441
 442         return 0;
 443 }
 444
 445 static int grcan_get_berr_counter(const struct net_device *dev,
 446                                   struct can_berr_counter *bec)
 447 {
 448         struct grcan_priv *priv = netdev_priv(dev);
 449         struct grcan_registers __iomem *regs = priv->regs;
 450         u32 status = grcan_read_reg(&regs->stat);
 451
 452         bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
 453         bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
 454         return 0;
 455 }
 456
 457 static int grcan_poll(struct napi_struct *napi, int budget);
 458
 459 /* Reset device, but keep configuration information */
 460 static void grcan_reset(struct net_device *dev)
 461 {
 462         struct grcan_priv *priv = netdev_priv(dev);
 463         struct grcan_registers __iomem *regs = priv->regs;
 464         u32 config = grcan_read_reg(&regs->conf);
 465
 466         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
 467         grcan_write_reg(&regs->conf, config);
 468
 469         priv->eskbp = grcan_read_reg(&regs->txrd);
 470         priv->can.state = CAN_STATE_STOPPED;
 471
 472         /* Turn off hardware filtering - regs->rxcode set to 0 by reset */
 473         grcan_write_reg(&regs->rxmask, 0);
 474 }
 475
 476 /* stop device without changing any configurations */
 477 static void grcan_stop_hardware(struct net_device *dev)
 478 {
 479         struct grcan_priv *priv = netdev_priv(dev);
 480         struct grcan_registers __iomem *regs = priv->regs;
 481
 482         grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
 483         grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 484         grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 485         grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
 486 }
 487
 488 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
 489  * is true and free them otherwise.
 490  *
 491  * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
 492  * continue until priv->eskbp catches up to regs->txrd.
 493  *
 494  * priv->lock *must* be held when calling this function
 495  */
 496 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
 497 {
 498         struct grcan_priv *priv = netdev_priv(dev);
 499         struct grcan_registers __iomem *regs = priv->regs;
 500         struct grcan_dma *dma = &priv->dma;
 501         struct net_device_stats *stats = &dev->stats;
 502         int i, work_done;
 503
 504         /* Updates to priv->eskbp and wake-ups of the queue needs to
 505          * be atomic towards the reads of priv->eskbp and shut-downs
 506          * of the queue in grcan_start_xmit.
 507          */
 508         u32 txrd = grcan_read_reg(&regs->txrd);
 509
 510         for (work_done = 0; work_done < budget || budget < 0; work_done++) {
 511                 if (priv->eskbp == txrd)
 512                         break;
 513                 i = priv->eskbp / GRCAN_MSG_SIZE;
 514                 if (echo) {
 515                         /* Normal echo of messages */
 516                         stats->tx_packets++;
 517                         stats->tx_bytes += can_get_echo_skb(dev, i, NULL);
 518                 } else {
 519                         /* For cleanup of untransmitted messages */
 520                         can_free_echo_skb(dev, i, NULL);
 521                 }
 522
 523                 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
 524                                              dma->tx.size);
 525                 txrd = grcan_read_reg(&regs->txrd);
 526         }
 527         return work_done;
 528 }
 529
 530 static void grcan_lost_one_shot_frame(struct net_device *dev)
 531 {
 532         struct grcan_priv *priv = netdev_priv(dev);
 533         struct grcan_registers __iomem *regs = priv->regs;
 534         struct grcan_dma *dma = &priv->dma;
 535         u32 txrd;
 536         unsigned long flags;
 537
 538         spin_lock_irqsave(&priv->lock, flags);
 539
 540         catch_up_echo_skb(dev, -1, true);
 541
 542         if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
 543                 /* Should never happen */
 544                 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
 545         } else {
 546                 /* By the time an GRCAN_IRQ_TXLOSS is generated in
 547                  * one-shot mode there is no problem in writing
 548                  * to TXRD even in versions of the hardware in
 549                  * which GRCAN_TXCTRL_ONGOING is not cleared properly
 550                  * in one-shot mode.
 551                  */
 552
 553                 /* Skip message and discard echo-skb */
 554                 txrd = grcan_read_reg(&regs->txrd);
 555                 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
 556                 grcan_write_reg(&regs->txrd, txrd);
 557                 catch_up_echo_skb(dev, -1, false);
 558
 559                 if (!priv->resetting && !priv->closing &&
 560                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
 561                         netif_wake_queue(dev);
 562                         grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 563                 }
 564         }
 565
 566         spin_unlock_irqrestore(&priv->lock, flags);
 567 }
 568
 569 static void grcan_err(struct net_device *dev, u32 sources, u32 status)
 570 {
 571         struct grcan_priv *priv = netdev_priv(dev);
 572         struct grcan_registers __iomem *regs = priv->regs;
 573         struct grcan_dma *dma = &priv->dma;
 574         struct net_device_stats *stats = &dev->stats;
 575         struct can_frame cf;
 576
 577         /* Zero potential error_frame */
 578         memset(&cf, 0, sizeof(cf));
 579
 580         /* Message lost interrupt. This might be due to arbitration error, but
 581          * is also triggered when there is no one else on the can bus or when
 582          * there is a problem with the hardware interface or the bus itself. As
 583          * arbitration errors can not be singled out, no error frames are
 584          * generated reporting this event as an arbitration error.
 585          */
 586         if (sources & GRCAN_IRQ_TXLOSS) {
 587                 /* Take care of failed one-shot transmit */
 588                 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
 589                         grcan_lost_one_shot_frame(dev);
 590
 591                 /* Stop printing as soon as error passive or bus off is in
 592                  * effect to limit the amount of txloss debug printouts.
 593                  */
 594                 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
 595                         netdev_dbg(dev, "tx message lost\n");
 596                         stats->tx_errors++;
 597                 }
 598         }
 599
 600         /* Conditions dealing with the error counters. There is no interrupt for
 601          * error warning, but there are interrupts for increases of the error
 602          * counters.
 603          */
 604         if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
 605             (status & GRCAN_STAT_ERRCTR_RELATED)) {
 606                 enum can_state state = priv->can.state;
 607                 enum can_state oldstate = state;
 608                 u32 txerr = (status & GRCAN_STAT_TXERRCNT)
 609                         >> GRCAN_STAT_TXERRCNT_BIT;
 610                 u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
 611                         >> GRCAN_STAT_RXERRCNT_BIT;
 612
 613                 /* Figure out current state */
 614                 if (status & GRCAN_STAT_OFF) {
 615                         state = CAN_STATE_BUS_OFF;
 616                 } else if (status & GRCAN_STAT_PASS) {
 617                         state = CAN_STATE_ERROR_PASSIVE;
 618                 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
 619                            rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
 620                         state = CAN_STATE_ERROR_WARNING;
 621                 } else {
 622                         state = CAN_STATE_ERROR_ACTIVE;
 623                 }
 624
 625                 /* Handle and report state changes */
 626                 if (state != oldstate) {
 627                         switch (state) {
 628                         case CAN_STATE_BUS_OFF:
 629                                 netdev_dbg(dev, "bus-off\n");
 630                                 netif_carrier_off(dev);
 631                                 priv->can.can_stats.bus_off++;
 632
 633                                 /* Prevent the hardware from recovering from bus
 634                                  * off on its own if restart is disabled.
 635                                  */
 636                                 if (!priv->can.restart_ms)
 637                                         grcan_stop_hardware(dev);
 638
 639                                 cf.can_id |= CAN_ERR_BUSOFF;
 640                                 break;
 641
 642                         case CAN_STATE_ERROR_PASSIVE:
 643                                 netdev_dbg(dev, "Error passive condition\n");
 644                                 priv->can.can_stats.error_passive++;
 645
 646                                 cf.can_id |= CAN_ERR_CRTL;
 647                                 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 648                                         cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 649                                 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 650                                         cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 651                                 break;
 652
 653                         case CAN_STATE_ERROR_WARNING:
 654                                 netdev_dbg(dev, "Error warning condition\n");
 655                                 priv->can.can_stats.error_warning++;
 656
 657                                 cf.can_id |= CAN_ERR_CRTL;
 658                                 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 659                                         cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
 660                                 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 661                                         cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
 662                                 break;
 663
 664                         case CAN_STATE_ERROR_ACTIVE:
 665                                 netdev_dbg(dev, "Error active condition\n");
 666                                 cf.can_id |= CAN_ERR_CRTL;
 667                                 break;
 668
 669                         default:
 670                                 /* There are no others at this point */
 671                                 break;
 672                         }
 673                         cf.data[6] = txerr;
 674                         cf.data[7] = rxerr;
 675                         priv->can.state = state;
 676                 }
 677
 678                 /* Report automatic restarts */
 679                 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
 680                         unsigned long flags;
 681
 682                         cf.can_id |= CAN_ERR_RESTARTED;
 683                         netdev_dbg(dev, "restarted\n");
 684                         priv->can.can_stats.restarts++;
 685                         netif_carrier_on(dev);
 686
 687                         spin_lock_irqsave(&priv->lock, flags);
 688
 689                         if (!priv->resetting && !priv->closing) {
 690                                 u32 txwr = grcan_read_reg(&regs->txwr);
 691
 692                                 if (grcan_txspace(dma->tx.size, txwr,
 693                                                   priv->eskbp))
 694                                         netif_wake_queue(dev);
 695                         }
 696
 697                         spin_unlock_irqrestore(&priv->lock, flags);
 698                 }
 699         }
 700
 701         /* Data overrun interrupt */
 702         if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
 703                 netdev_dbg(dev, "got data overrun interrupt\n");
 704                 stats->rx_over_errors++;
 705                 stats->rx_errors++;
 706
 707                 cf.can_id |= CAN_ERR_CRTL;
 708                 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
 709         }
 710
 711         /* AHB bus error interrupts (not CAN bus errors) - shut down the
 712          * device.
 713          */
 714         if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
 715             (status & GRCAN_STAT_AHBERR)) {
 716                 char *txrx = "";
 717                 unsigned long flags;
 718
 719                 if (sources & GRCAN_IRQ_TXAHBERR) {
 720                         txrx = "on tx ";
 721                         stats->tx_errors++;
 722                 } else if (sources & GRCAN_IRQ_RXAHBERR) {
 723                         txrx = "on rx ";
 724                         stats->rx_errors++;
 725                 }
 726                 netdev_err(dev, "Fatal AHB bus error %s- halting device\n",
 727                            txrx);
 728
 729                 spin_lock_irqsave(&priv->lock, flags);
 730
 731                 /* Prevent anything to be enabled again and halt device */
 732                 priv->closing = true;
 733                 netif_stop_queue(dev);
 734                 grcan_stop_hardware(dev);
 735                 priv->can.state = CAN_STATE_STOPPED;
 736
 737                 spin_unlock_irqrestore(&priv->lock, flags);
 738         }
 739
 740         /* Pass on error frame if something to report,
 741          * i.e. id contains some information
 742          */
 743         if (cf.can_id) {
 744                 struct can_frame *skb_cf;
 745                 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
 746
 747                 if (skb == NULL) {
 748                         netdev_dbg(dev, "could not allocate error frame\n");
 749                         return;
 750                 }
 751                 skb_cf->can_id |= cf.can_id;
 752                 memcpy(skb_cf->data, cf.data, sizeof(cf.data));
 753
 754                 netif_rx(skb);
 755         }
 756 }
 757
 758 static irqreturn_t grcan_interrupt(int irq, void *dev_id)
 759 {
 760         struct net_device *dev = dev_id;
 761         struct grcan_priv *priv = netdev_priv(dev);
 762         struct grcan_registers __iomem *regs = priv->regs;
 763         u32 sources, status;
 764
 765         /* Find out the source */
 766         sources = grcan_read_reg(&regs->pimsr);
 767         if (!sources)
 768                 return IRQ_NONE;
 769         grcan_write_reg(&regs->picr, sources);
 770         status = grcan_read_reg(&regs->stat);
 771
 772         /* If we got TX progress, the device has not hanged,
 773          * so disable the hang timer
 774          */
 775         if (priv->need_txbug_workaround &&
 776             (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
 777                 del_timer(&priv->hang_timer);
 778         }
 779
 780         /* Frame(s) received or transmitted */
 781         if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
 782                 /* Disable tx/rx interrupts and schedule poll(). No need for
 783                  * locking as interference from a running reset at worst leads
 784                  * to an extra interrupt.
 785                  */
 786                 grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
 787                 napi_schedule(&priv->napi);
 788         }
 789
 790         /* (Potential) error conditions to take care of */
 791         if (sources & GRCAN_IRQ_ERRORS)
 792                 grcan_err(dev, sources, status);
 793
 794         return IRQ_HANDLED;
 795 }
 796
 797 /* Reset device and restart operations from where they were.
 798  *
 799  * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
 800  * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
 801  * for single shot)
 802  */
 803 static void grcan_running_reset(struct timer_list *t)
 804 {
 805         struct grcan_priv *priv = from_timer(priv, t, rr_timer);
 806         struct net_device *dev = priv->dev;
 807         struct grcan_registers __iomem *regs = priv->regs;
 808         unsigned long flags;
 809
 810         /* This temporarily messes with eskbp, so we need to lock
 811          * priv->lock
 812          */
 813         spin_lock_irqsave(&priv->lock, flags);
 814
 815         priv->resetting = false;
 816         del_timer(&priv->hang_timer);
 817         del_timer(&priv->rr_timer);
 818
 819         if (!priv->closing) {
 820                 /* Save and reset - config register preserved by grcan_reset */
 821                 u32 imr = grcan_read_reg(&regs->imr);
 822
 823                 u32 txaddr = grcan_read_reg(&regs->txaddr);
 824                 u32 txsize = grcan_read_reg(&regs->txsize);
 825                 u32 txwr = grcan_read_reg(&regs->txwr);
 826                 u32 txrd = grcan_read_reg(&regs->txrd);
 827                 u32 eskbp = priv->eskbp;
 828
 829                 u32 rxaddr = grcan_read_reg(&regs->rxaddr);
 830                 u32 rxsize = grcan_read_reg(&regs->rxsize);
 831                 u32 rxwr = grcan_read_reg(&regs->rxwr);
 832                 u32 rxrd = grcan_read_reg(&regs->rxrd);
 833
 834                 grcan_reset(dev);
 835
 836                 /* Restore */
 837                 grcan_write_reg(&regs->txaddr, txaddr);
 838                 grcan_write_reg(&regs->txsize, txsize);
 839                 grcan_write_reg(&regs->txwr, txwr);
 840                 grcan_write_reg(&regs->txrd, txrd);
 841                 priv->eskbp = eskbp;
 842
 843                 grcan_write_reg(&regs->rxaddr, rxaddr);
 844                 grcan_write_reg(&regs->rxsize, rxsize);
 845                 grcan_write_reg(&regs->rxwr, rxwr);
 846                 grcan_write_reg(&regs->rxrd, rxrd);
 847
 848                 /* Turn on device again */
 849                 grcan_write_reg(&regs->imr, imr);
 850                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
 851                 grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
 852                                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
 853                                    ? GRCAN_TXCTRL_SINGLE : 0));
 854                 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 855                 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
 856
 857                 /* Start queue if there is size and listen-onle mode is not
 858                  * enabled
 859                  */
 860                 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
 861                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
 862                         netif_wake_queue(dev);
 863         }
 864
 865         spin_unlock_irqrestore(&priv->lock, flags);
 866
 867         netdev_err(dev, "Device reset and restored\n");
 868 }
 869
 870 /* Waiting time in usecs corresponding to the transmission of three maximum
 871  * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
 872  * of time makes sure that the can controller have time to finish sending or
 873  * receiving a frame with a good margin.
 874  *
 875  * usecs/sec * number of frames * bits/frame / bits/sec
 876  */
 877 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
 878 {
 879         return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
 880 }
 881
 882 /* Set timer so that it will not fire until after a period in which the can
 883  * controller have a good margin to finish transmitting a frame unless it has
 884  * hanged
 885  */
 886 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
 887 {
 888         u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
 889
 890         mod_timer(timer, jiffies + wait_jiffies);
 891 }
 892
 893 /* Disable channels and schedule a running reset */
 894 static void grcan_initiate_running_reset(struct timer_list *t)
 895 {
 896         struct grcan_priv *priv = from_timer(priv, t, hang_timer);
 897         struct net_device *dev = priv->dev;
 898         struct grcan_registers __iomem *regs = priv->regs;
 899         unsigned long flags;
 900
 901         netdev_err(dev, "Device seems hanged - reset scheduled\n");
 902
 903         spin_lock_irqsave(&priv->lock, flags);
 904
 905         /* The main body of this function must never be executed again
 906          * until after an execution of grcan_running_reset
 907          */
 908         if (!priv->resetting && !priv->closing) {
 909                 priv->resetting = true;
 910                 netif_stop_queue(dev);
 911                 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 912                 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 913                 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
 914         }
 915
 916         spin_unlock_irqrestore(&priv->lock, flags);
 917 }
 918
 919 static void grcan_free_dma_buffers(struct net_device *dev)
 920 {
 921         struct grcan_priv *priv = netdev_priv(dev);
 922         struct grcan_dma *dma = &priv->dma;
 923
 924         dma_free_coherent(&dev->dev, dma->base_size, dma->base_buf,
 925                           dma->base_handle);
 926         memset(dma, 0, sizeof(*dma));
 927 }
 928
 929 static int grcan_allocate_dma_buffers(struct net_device *dev,
 930                                       size_t tsize, size_t rsize)
 931 {
 932         struct grcan_priv *priv = netdev_priv(dev);
 933         struct grcan_dma *dma = &priv->dma;
 934         struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
 935         struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
 936         size_t shift;
 937
 938         /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
 939          * i.e. first buffer
 940          */
 941         size_t maxs = max(tsize, rsize);
 942         size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
 943
 944         /* Put the small buffer after that */
 945         size_t ssize = min(tsize, rsize);
 946
 947         /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
 948         dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
 949         dma->base_buf = dma_alloc_coherent(&dev->dev,
 950                                            dma->base_size,
 951                                            &dma->base_handle,
 952                                            GFP_KERNEL);
 953
 954         if (!dma->base_buf)
 955                 return -ENOMEM;
 956
 957         dma->tx.size = tsize;
 958         dma->rx.size = rsize;
 959
 960         large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
 961         small->handle = large->handle + lsize;
 962         shift = large->handle - dma->base_handle;
 963
 964         large->buf = dma->base_buf + shift;
 965         small->buf = large->buf + lsize;
 966
 967         return 0;
 968 }
 969
 970 /* priv->lock *must* be held when calling this function */
 971 static int grcan_start(struct net_device *dev)
 972 {
 973         struct grcan_priv *priv = netdev_priv(dev);
 974         struct grcan_registers __iomem *regs = priv->regs;
 975         u32 confop, txctrl;
 976
 977         grcan_reset(dev);
 978
 979         grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
 980         grcan_write_reg(&regs->txsize, priv->dma.tx.size);
 981         /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
 982
 983         grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
 984         grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
 985         /* regs->rxwr and regs->rxrd already set to 0 by reset */
 986
 987         /* Enable interrupts */
 988         grcan_read_reg(&regs->pir);
 989         grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
 990
 991         /* Enable interfaces, channels and device */
 992         confop = GRCAN_CONF_ABORT
 993                 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
 994                 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
 995                 | (priv->config.select ? GRCAN_CONF_SELECT : 0)
 996                 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
 997                    GRCAN_CONF_SILENT : 0)
 998                 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
 999                    GRCAN_CONF_SAM : 0);
1000         grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1001         txctrl = GRCAN_TXCTRL_ENABLE
1002                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1003                    ? GRCAN_TXCTRL_SINGLE : 0);
1004         grcan_write_reg(&regs->txctrl, txctrl);
1005         grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1006         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1007
1008         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1009
1010         return 0;
1011 }
1012
1013 static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1014 {
1015         struct grcan_priv *priv = netdev_priv(dev);
1016         unsigned long flags;
1017         int err = 0;
1018
1019         if (mode == CAN_MODE_START) {
1020                 /* This might be called to restart the device to recover from
1021                  * bus off errors
1022                  */
1023                 spin_lock_irqsave(&priv->lock, flags);
1024                 if (priv->closing || priv->resetting) {
1025                         err = -EBUSY;
1026                 } else {
1027                         netdev_info(dev, "Restarting device\n");
1028                         grcan_start(dev);
1029                         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1030                                 netif_wake_queue(dev);
1031                 }
1032                 spin_unlock_irqrestore(&priv->lock, flags);
1033                 return err;
1034         }
1035         return -EOPNOTSUPP;
1036 }
1037
1038 static int grcan_open(struct net_device *dev)
1039 {
1040         struct grcan_priv *priv = netdev_priv(dev);
1041         struct grcan_dma *dma = &priv->dma;
1042         unsigned long flags;
1043         int err;
1044
1045         /* Allocate memory */
1046         err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1047                                          priv->config.rxsize);
1048         if (err) {
1049                 netdev_err(dev, "could not allocate DMA buffers\n");
1050                 return err;
1051         }
1052
1053         priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb),
1054                                  GFP_KERNEL);
1055         if (!priv->echo_skb) {
1056                 err = -ENOMEM;
1057                 goto exit_free_dma_buffers;
1058         }
1059         priv->can.echo_skb_max = dma->tx.size;
1060         priv->can.echo_skb = priv->echo_skb;
1061
1062         /* Get can device up */
1063         err = open_candev(dev);
1064         if (err)
1065                 goto exit_free_echo_skb;
1066
1067         err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1068                           dev->name, dev);
1069         if (err)
1070                 goto exit_close_candev;
1071
1072         spin_lock_irqsave(&priv->lock, flags);
1073
1074         napi_enable(&priv->napi);
1075         grcan_start(dev);
1076         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1077                 netif_start_queue(dev);
1078         priv->resetting = false;
1079         priv->closing = false;
1080
1081         spin_unlock_irqrestore(&priv->lock, flags);
1082
1083         return 0;
1084
1085 exit_close_candev:
1086         close_candev(dev);
1087 exit_free_echo_skb:
1088         kfree(priv->echo_skb);
1089 exit_free_dma_buffers:
1090         grcan_free_dma_buffers(dev);
1091         return err;
1092 }
1093
1094 static int grcan_close(struct net_device *dev)
1095 {
1096         struct grcan_priv *priv = netdev_priv(dev);
1097         unsigned long flags;
1098
1099         napi_disable(&priv->napi);
1100
1101         spin_lock_irqsave(&priv->lock, flags);
1102
1103         priv->closing = true;
1104         if (priv->need_txbug_workaround) {
1105                 del_timer_sync(&priv->hang_timer);
1106                 del_timer_sync(&priv->rr_timer);
1107         }
1108         netif_stop_queue(dev);
1109         grcan_stop_hardware(dev);
1110         priv->can.state = CAN_STATE_STOPPED;
1111
1112         spin_unlock_irqrestore(&priv->lock, flags);
1113
1114         free_irq(dev->irq, dev);
1115         close_candev(dev);
1116
1117         grcan_free_dma_buffers(dev);
1118         priv->can.echo_skb_max = 0;
1119         priv->can.echo_skb = NULL;
1120         kfree(priv->echo_skb);
1121
1122         return 0;
1123 }
1124
1125 static int grcan_transmit_catch_up(struct net_device *dev, int budget)
1126 {
1127         struct grcan_priv *priv = netdev_priv(dev);
1128         unsigned long flags;
1129         int work_done;
1130
1131         spin_lock_irqsave(&priv->lock, flags);
1132
1133         work_done = catch_up_echo_skb(dev, budget, true);
1134         if (work_done) {
1135                 if (!priv->resetting && !priv->closing &&
1136                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1137                         netif_wake_queue(dev);
1138
1139                 /* With napi we don't get TX interrupts for a while,
1140                  * so prevent a running reset while catching up
1141                  */
1142                 if (priv->need_txbug_workaround)
1143                         del_timer(&priv->hang_timer);
1144         }
1145
1146         spin_unlock_irqrestore(&priv->lock, flags);
1147
1148         return work_done;
1149 }
1150
1151 static int grcan_receive(struct net_device *dev, int budget)
1152 {
1153         struct grcan_priv *priv = netdev_priv(dev);
1154         struct grcan_registers __iomem *regs = priv->regs;
1155         struct grcan_dma *dma = &priv->dma;
1156         struct net_device_stats *stats = &dev->stats;
1157         struct can_frame *cf;
1158         struct sk_buff *skb;
1159         u32 wr, rd, startrd;
1160         u32 *slot;
1161         u32 i, rtr, eff, j, shift;
1162         int work_done = 0;
1163
1164         rd = grcan_read_reg(&regs->rxrd);
1165         startrd = rd;
1166         for (work_done = 0; work_done < budget; work_done++) {
1167                 /* Check for packet to receive */
1168                 wr = grcan_read_reg(&regs->rxwr);
1169                 if (rd == wr)
1170                         break;
1171
1172                 /* Take care of packet */
1173                 skb = alloc_can_skb(dev, &cf);
1174                 if (skb == NULL) {
1175                         netdev_err(dev,
1176                                    "dropping frame: skb allocation failed\n");
1177                         stats->rx_dropped++;
1178                         continue;
1179                 }
1180
1181                 slot = dma->rx.buf + rd;
1182                 eff = slot[0] & GRCAN_MSG_IDE;
1183                 rtr = slot[0] & GRCAN_MSG_RTR;
1184                 if (eff) {
1185                         cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1186                                       >> GRCAN_MSG_EID_BIT);
1187                         cf->can_id |= CAN_EFF_FLAG;
1188                 } else {
1189                         cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1190                                       >> GRCAN_MSG_BID_BIT);
1191                 }
1192                 cf->len = can_cc_dlc2len((slot[1] & GRCAN_MSG_DLC)
1193                                           >> GRCAN_MSG_DLC_BIT);
1194                 if (rtr) {
1195                         cf->can_id |= CAN_RTR_FLAG;
1196                 } else {
1197                         for (i = 0; i < cf->len; i++) {
1198                                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1199                                 shift = GRCAN_MSG_DATA_SHIFT(i);
1200                                 cf->data[i] = (u8)(slot[j] >> shift);
1201                         }
1202
1203                         stats->rx_bytes += cf->len;
1204                 }
1205                 stats->rx_packets++;
1206
1207                 netif_receive_skb(skb);
1208
1209                 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1210         }
1211
1212         /* Make sure everything is read before allowing hardware to
1213          * use the memory
1214          */
1215         mb();
1216
1217         /* Update read pointer - no need to check for ongoing */
1218         if (likely(rd != startrd))
1219                 grcan_write_reg(&regs->rxrd, rd);
1220
1221         return work_done;
1222 }
1223
1224 static int grcan_poll(struct napi_struct *napi, int budget)
1225 {
1226         struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1227         struct net_device *dev = priv->dev;
1228         struct grcan_registers __iomem *regs = priv->regs;
1229         unsigned long flags;
1230         int tx_work_done, rx_work_done;
1231         int rx_budget = budget / 2;
1232         int tx_budget = budget - rx_budget;
1233
1234         /* Half of the budget for receiving messages */
1235         rx_work_done = grcan_receive(dev, rx_budget);
1236
1237         /* Half of the budget for transmitting messages as that can trigger echo
1238          * frames being received
1239          */
1240         tx_work_done = grcan_transmit_catch_up(dev, tx_budget);
1241
1242         if (rx_work_done < rx_budget && tx_work_done < tx_budget) {
1243                 napi_complete(napi);
1244
1245                 /* Guarantee no interference with a running reset that otherwise
1246                  * could turn off interrupts.
1247                  */
1248                 spin_lock_irqsave(&priv->lock, flags);
1249
1250                 /* Enable tx and rx interrupts again. No need to check
1251                  * priv->closing as napi_disable in grcan_close is waiting for
1252                  * scheduled napi calls to finish.
1253                  */
1254                 grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1255
1256                 spin_unlock_irqrestore(&priv->lock, flags);
1257         }
1258
1259         return rx_work_done + tx_work_done;
1260 }
1261
1262 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
1263  * drop a frame in one-shot mode or indicate a busy device otherwise.
1264  *
1265  * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1266  * value that should be returned by grcan_start_xmit when aborting the xmit.
1267  */
1268 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1269                                   u32 txwr, u32 oneshotmode,
1270                                   netdev_tx_t *netdev_tx_status)
1271 {
1272         struct grcan_priv *priv = netdev_priv(dev);
1273         struct grcan_registers __iomem *regs = priv->regs;
1274         struct grcan_dma *dma = &priv->dma;
1275         int i;
1276         unsigned long flags;
1277
1278         /* Wait a while for ongoing to be cleared or read pointer to catch up to
1279          * write pointer. The latter is needed due to a bug in older versions of
1280          * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1281          * transmission fails.
1282          */
1283         for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1284                 udelay(1);
1285                 if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1286                     grcan_read_reg(&regs->txrd) == txwr) {
1287                         return 0;
1288                 }
1289         }
1290
1291         /* Clean up, in case the situation was not resolved */
1292         spin_lock_irqsave(&priv->lock, flags);
1293         if (!priv->resetting && !priv->closing) {
1294                 /* Queue might have been stopped earlier in grcan_start_xmit */
1295                 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1296                         netif_wake_queue(dev);
1297                 /* Set a timer to resolve a hanged tx controller */
1298                 if (!timer_pending(&priv->hang_timer))
1299                         grcan_reset_timer(&priv->hang_timer,
1300                                           priv->can.bittiming.bitrate);
1301         }
1302         spin_unlock_irqrestore(&priv->lock, flags);
1303
1304         if (oneshotmode) {
1305                 /* In one-shot mode we should never end up here because
1306                  * then the interrupt handler increases txrd on TXLOSS,
1307                  * but it is consistent with one-shot mode to drop the
1308                  * frame in this case.
1309                  */
1310                 kfree_skb(skb);
1311                 *netdev_tx_status = NETDEV_TX_OK;
1312         } else {
1313                 /* In normal mode the socket-can transmission queue get
1314                  * to keep the frame so that it can be retransmitted
1315                  * later
1316                  */
1317                 *netdev_tx_status = NETDEV_TX_BUSY;
1318         }
1319         return -EBUSY;
1320 }
1321
1322 /* Notes on the tx cyclic buffer handling:
1323  *
1324  * regs->txwr   - the next slot for the driver to put data to be sent
1325  * regs->txrd   - the next slot for the device to read data
1326  * priv->eskbp  - the next slot for the driver to call can_put_echo_skb for
1327  *
1328  * grcan_start_xmit can enter more messages as long as regs->txwr does
1329  * not reach priv->eskbp (within 1 message gap)
1330  *
1331  * The device sends messages until regs->txrd reaches regs->txwr
1332  *
1333  * The interrupt calls handler calls can_put_echo_skb until
1334  * priv->eskbp reaches regs->txrd
1335  */
1336 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1337                                     struct net_device *dev)
1338 {
1339         struct grcan_priv *priv = netdev_priv(dev);
1340         struct grcan_registers __iomem *regs = priv->regs;
1341         struct grcan_dma *dma = &priv->dma;
1342         struct can_frame *cf = (struct can_frame *)skb->data;
1343         u32 id, txwr, txrd, space, txctrl;
1344         int slotindex;
1345         u32 *slot;
1346         u32 i, rtr, eff, dlc, tmp, err;
1347         int j, shift;
1348         unsigned long flags;
1349         u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1350
1351         if (can_dropped_invalid_skb(dev, skb))
1352                 return NETDEV_TX_OK;
1353
1354         /* Trying to transmit in silent mode will generate error interrupts, but
1355          * this should never happen - the queue should not have been started.
1356          */
1357         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1358                 return NETDEV_TX_BUSY;
1359
1360         /* Reads of priv->eskbp and shut-downs of the queue needs to
1361          * be atomic towards the updates to priv->eskbp and wake-ups
1362          * of the queue in the interrupt handler.
1363          */
1364         spin_lock_irqsave(&priv->lock, flags);
1365
1366         txwr = grcan_read_reg(&regs->txwr);
1367         space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1368
1369         slotindex = txwr / GRCAN_MSG_SIZE;
1370         slot = dma->tx.buf + txwr;
1371
1372         if (unlikely(space == 1))
1373                 netif_stop_queue(dev);
1374
1375         spin_unlock_irqrestore(&priv->lock, flags);
1376         /* End of critical section*/
1377
1378         /* This should never happen. If circular buffer is full, the
1379          * netif_stop_queue should have been stopped already.
1380          */
1381         if (unlikely(!space)) {
1382                 netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1383                 return NETDEV_TX_BUSY;
1384         }
1385
1386         /* Convert and write CAN message to DMA buffer */
1387         eff = cf->can_id & CAN_EFF_FLAG;
1388         rtr = cf->can_id & CAN_RTR_FLAG;
1389         id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1390         dlc = cf->len;
1391         if (eff)
1392                 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1393         else
1394                 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1395         slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1396
1397         slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1398         slot[2] = 0;
1399         slot[3] = 0;
1400         for (i = 0; i < dlc; i++) {
1401                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1402                 shift = GRCAN_MSG_DATA_SHIFT(i);
1403                 slot[j] |= cf->data[i] << shift;
1404         }
1405
1406         /* Checking that channel has not been disabled. These cases
1407          * should never happen
1408          */
1409         txctrl = grcan_read_reg(&regs->txctrl);
1410         if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1411                 netdev_err(dev, "tx channel spuriously disabled\n");
1412
1413         if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1414                 netdev_err(dev, "one-shot mode spuriously disabled\n");
1415
1416         /* Bug workaround for old version of grcan where updating txwr
1417          * in the same clock cycle as the controller updates txrd to
1418          * the current txwr could hang the can controller
1419          */
1420         if (priv->need_txbug_workaround) {
1421                 txrd = grcan_read_reg(&regs->txrd);
1422                 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1423                         netdev_tx_t txstatus;
1424
1425                         err = grcan_txbug_workaround(dev, skb, txwr,
1426                                                      oneshotmode, &txstatus);
1427                         if (err)
1428                                 return txstatus;
1429                 }
1430         }
1431
1432         /* Prepare skb for echoing. This must be after the bug workaround above
1433          * as ownership of the skb is passed on by calling can_put_echo_skb.
1434          * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1435          * can_put_echo_skb would be an error unless other measures are
1436          * taken.
1437          */
1438         can_put_echo_skb(skb, dev, slotindex, 0);
1439
1440         /* Make sure everything is written before allowing hardware to
1441          * read from the memory
1442          */
1443         wmb();
1444
1445         /* Update write pointer to start transmission */
1446         grcan_write_reg(&regs->txwr,
1447                         grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1448
1449         return NETDEV_TX_OK;
1450 }
1451
1452 /* ========== Setting up sysfs interface and module parameters ========== */
1453
1454 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1455
1456 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)                \
1457         static void grcan_sanitize_##name(struct platform_device *pd)   \
1458         {                                                               \
1459                 struct grcan_device_config grcan_default_config         \
1460                         = GRCAN_DEFAULT_DEVICE_CONFIG;                  \
1461                 if (valcheckf(grcan_module_config.name)) {              \
1462                         dev_err(&pd->dev,                               \
1463                                 "Invalid module parameter value for "   \
1464                                 #name " - setting default\n");          \
1465                         grcan_module_config.name =                      \
1466                                 grcan_default_config.name;              \
1467                 }                                                       \
1468         }                                                               \
1469         module_param_named(name, grcan_module_config.name,              \
1470                            mtype, 0444);                                \
1471         MODULE_PARM_DESC(name, desc)
1472
1473 #define GRCAN_CONFIG_ATTR(name, desc)                                   \
1474         static ssize_t grcan_store_##name(struct device *sdev,          \
1475                                           struct device_attribute *att, \
1476                                           const char *buf,              \
1477                                           size_t count)                 \
1478         {                                                               \
1479                 struct net_device *dev = to_net_dev(sdev);              \
1480                 struct grcan_priv *priv = netdev_priv(dev);             \
1481                 u8 val;                                                 \
1482                 int ret;                                                \
1483                 if (dev->flags & IFF_UP)                                \
1484                         return -EBUSY;                                  \
1485                 ret = kstrtou8(buf, 0, &val);                           \
1486                 if (ret < 0 || val > 1)                                 \
1487                         return -EINVAL;                                 \
1488                 priv->config.name = val;                                \
1489                 return count;                                           \
1490         }                                                               \
1491         static ssize_t grcan_show_##name(struct device *sdev,           \
1492                                          struct device_attribute *att,  \
1493                                          char *buf)                     \
1494         {                                                               \
1495                 struct net_device *dev = to_net_dev(sdev);              \
1496                 struct grcan_priv *priv = netdev_priv(dev);             \
1497                 return sprintf(buf, "%d\n", priv->config.name);         \
1498         }                                                               \
1499         static DEVICE_ATTR(name, 0644,                                  \
1500                            grcan_show_##name,                           \
1501                            grcan_store_##name);                         \
1502         GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1503
1504 /* The following configuration options are made available both via module
1505  * parameters and writable sysfs files. See the chapter about GRCAN in the
1506  * documentation for the GRLIB VHDL library for further details.
1507  */
1508 GRCAN_CONFIG_ATTR(enable0,
1509                   "Configuration of physical interface 0. Determines\n" \
1510                   "the \"Enable 0\" bit of the configuration register.\n" \
1511                   "Format: 0 | 1\nDefault: 0\n");
1512
1513 GRCAN_CONFIG_ATTR(enable1,
1514                   "Configuration of physical interface 1. Determines\n" \
1515                   "the \"Enable 1\" bit of the configuration register.\n" \
1516                   "Format: 0 | 1\nDefault: 0\n");
1517
1518 GRCAN_CONFIG_ATTR(select,
1519                   "Select which physical interface to use.\n"   \
1520                   "Format: 0 | 1\nDefault: 0\n");
1521
1522 /* The tx and rx buffer size configuration options are only available via module
1523  * parameters.
1524  */
1525 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1526                    "Sets the size of the tx buffer.\n"                  \
1527                    "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1528                    "Default: 1024\n");
1529 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1530                    "Sets the size of the rx buffer.\n"                  \
1531                    "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1532                    "Default: 1024\n");
1533
1534 /* Function that makes sure that configuration done using
1535  * module parameters are set to valid values
1536  */
1537 static void grcan_sanitize_module_config(struct platform_device *ofdev)
1538 {
1539         grcan_sanitize_enable0(ofdev);
1540         grcan_sanitize_enable1(ofdev);
1541         grcan_sanitize_select(ofdev);
1542         grcan_sanitize_txsize(ofdev);
1543         grcan_sanitize_rxsize(ofdev);
1544 }
1545
1546 static const struct attribute *const sysfs_grcan_attrs[] = {
1547         /* Config attrs */
1548         &dev_attr_enable0.attr,
1549         &dev_attr_enable1.attr,
1550         &dev_attr_select.attr,
1551         NULL,
1552 };
1553
1554 static const struct attribute_group sysfs_grcan_group = {
1555         .name   = "grcan",
1556         .attrs  = (struct attribute **)sysfs_grcan_attrs,
1557 };
1558
1559 /* ========== Setting up the driver ========== */
1560
1561 static const struct net_device_ops grcan_netdev_ops = {
1562         .ndo_open       = grcan_open,
1563         .ndo_stop       = grcan_close,
1564         .ndo_start_xmit = grcan_start_xmit,
1565         .ndo_change_mtu = can_change_mtu,
1566 };
1567
1568 static int grcan_setup_netdev(struct platform_device *ofdev,
1569                               void __iomem *base,
1570                               int irq, u32 ambafreq, bool txbug)
1571 {
1572         struct net_device *dev;
1573         struct grcan_priv *priv;
1574         struct grcan_registers __iomem *regs;
1575         int err;
1576
1577         dev = alloc_candev(sizeof(struct grcan_priv), 0);
1578         if (!dev)
1579                 return -ENOMEM;
1580
1581         dev->irq = irq;
1582         dev->flags |= IFF_ECHO;
1583         dev->netdev_ops = &grcan_netdev_ops;
1584         dev->sysfs_groups[0] = &sysfs_grcan_group;
1585
1586         priv = netdev_priv(dev);
1587         memcpy(&priv->config, &grcan_module_config,
1588                sizeof(struct grcan_device_config));
1589         priv->dev = dev;
1590         priv->regs = base;
1591         priv->can.bittiming_const = &grcan_bittiming_const;
1592         priv->can.do_set_bittiming = grcan_set_bittiming;
1593         priv->can.do_set_mode = grcan_set_mode;
1594         priv->can.do_get_berr_counter = grcan_get_berr_counter;
1595         priv->can.clock.freq = ambafreq;
1596         priv->can.ctrlmode_supported =
1597                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1598         priv->need_txbug_workaround = txbug;
1599
1600         /* Discover if triple sampling is supported by hardware */
1601         regs = priv->regs;
1602         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1603         grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1604         if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1605                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1606                 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1607         }
1608
1609         spin_lock_init(&priv->lock);
1610
1611         if (priv->need_txbug_workaround) {
1612                 timer_setup(&priv->rr_timer, grcan_running_reset, 0);
1613                 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0);
1614         }
1615
1616         netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1617
1618         SET_NETDEV_DEV(dev, &ofdev->dev);
1619         dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1620                  priv->regs, dev->irq, priv->can.clock.freq);
1621
1622         err = register_candev(dev);
1623         if (err)
1624                 goto exit_free_candev;
1625
1626         platform_set_drvdata(ofdev, dev);
1627
1628         /* Reset device to allow bit-timing to be set. No need to call
1629          * grcan_reset at this stage. That is done in grcan_open.
1630          */
1631         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1632
1633         return 0;
1634 exit_free_candev:
1635         free_candev(dev);
1636         return err;
1637 }
1638
1639 static int grcan_probe(struct platform_device *ofdev)
1640 {
1641         struct device_node *np = ofdev->dev.of_node;
1642         u32 sysid, ambafreq;
1643         int irq, err;
1644         void __iomem *base;
1645         bool txbug = true;
1646
1647         /* Compare GRLIB version number with the first that does not
1648          * have the tx bug (see start_xmit)
1649          */
1650         err = of_property_read_u32(np, "systemid", &sysid);
1651         if (!err && ((sysid & GRLIB_VERSION_MASK)
1652                      >= GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1653                 txbug = false;
1654
1655         err = of_property_read_u32(np, "freq", &ambafreq);
1656         if (err) {
1657                 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1658                 goto exit_error;
1659         }
1660
1661         base = devm_platform_ioremap_resource(ofdev, 0);
1662         if (IS_ERR(base)) {
1663                 err = PTR_ERR(base);
1664                 goto exit_error;
1665         }
1666
1667         irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1668         if (!irq) {
1669                 dev_err(&ofdev->dev, "no irq found\n");
1670                 err = -ENODEV;
1671                 goto exit_error;
1672         }
1673
1674         grcan_sanitize_module_config(ofdev);
1675
1676         err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1677         if (err)
1678                 goto exit_dispose_irq;
1679
1680         return 0;
1681
1682 exit_dispose_irq:
1683         irq_dispose_mapping(irq);
1684 exit_error:
1685         dev_err(&ofdev->dev,
1686                 "%s socket CAN driver initialization failed with error %d\n",
1687                 DRV_NAME, err);
1688         return err;
1689 }
1690
1691 static int grcan_remove(struct platform_device *ofdev)
1692 {
1693         struct net_device *dev = platform_get_drvdata(ofdev);
1694         struct grcan_priv *priv = netdev_priv(dev);
1695
1696         unregister_candev(dev); /* Will in turn call grcan_close */
1697
1698         irq_dispose_mapping(dev->irq);
1699         netif_napi_del(&priv->napi);
1700         free_candev(dev);
1701
1702         return 0;
1703 }
1704
1705 static const struct of_device_id grcan_match[] = {
1706         {.name = "GAISLER_GRCAN"},
1707         {.name = "01_03d"},
1708         {.name = "GAISLER_GRHCAN"},
1709         {.name = "01_034"},
1710         {},
1711 };
1712
1713 MODULE_DEVICE_TABLE(of, grcan_match);
1714
1715 static struct platform_driver grcan_driver = {
1716         .driver = {
1717                 .name = DRV_NAME,
1718                 .of_match_table = grcan_match,
1719         },
1720         .probe = grcan_probe,
1721         .remove = grcan_remove,
1722 };
1723
1724 module_platform_driver(grcan_driver);
1725
1726 MODULE_AUTHOR("Aeroflex Gaisler AB.");
1727 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1728 MODULE_LICENSE("GPL");