drivers/net/can/grcan.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
   4  *
   5  * 2012 (c) Aeroflex Gaisler AB
   6  *
   7  * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
   8  * VHDL IP core library.
   9  *
  10  * Full documentation of the GRCAN core can be found here:
  11  * http://www.gaisler.com/products/grlib/grip.pdf
  12  *
  13  * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
  14  * open firmware properties.
  15  *
  16  * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
  17  * sysfs interface.
  18  *
  19  * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module
  20  * parameters.
  21  *
  22  * Contributors: Andreas Larsson <andreas@gaisler.com>
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/delay.h>
  30 #include <linux/io.h>
  31 #include <linux/can/dev.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_irq.h>
  35
  36 #include <linux/dma-mapping.h>
  37
  38 #define DRV_NAME        "grcan"
  39
  40 #define GRCAN_NAPI_WEIGHT       32
  41
  42 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
  43
  44 struct grcan_registers {
  45         u32 conf;       /* 0x00 */
  46         u32 stat;       /* 0x04 */
  47         u32 ctrl;       /* 0x08 */
  48         u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
  49         u32 smask;      /* 0x18 - CanMASK */
  50         u32 scode;      /* 0x1c - CanCODE */
  51         u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
  52         u32 pimsr;      /* 0x100 */
  53         u32 pimr;       /* 0x104 */
  54         u32 pisr;       /* 0x108 */
  55         u32 pir;        /* 0x10C */
  56         u32 imr;        /* 0x110 */
  57         u32 picr;       /* 0x114 */
  58         u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
  59         u32 txctrl;     /* 0x200 */
  60         u32 txaddr;     /* 0x204 */
  61         u32 txsize;     /* 0x208 */
  62         u32 txwr;       /* 0x20C */
  63         u32 txrd;       /* 0x210 */
  64         u32 txirq;      /* 0x214 */
  65         u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
  66         u32 rxctrl;     /* 0x300 */
  67         u32 rxaddr;     /* 0x304 */
  68         u32 rxsize;     /* 0x308 */
  69         u32 rxwr;       /* 0x30C */
  70         u32 rxrd;       /* 0x310 */
  71         u32 rxirq;      /* 0x314 */
  72         u32 rxmask;     /* 0x318 */
  73         u32 rxcode;     /* 0x31C */
  74 };
  75
  76 #define GRCAN_CONF_ABORT        0x00000001
  77 #define GRCAN_CONF_ENABLE0      0x00000002
  78 #define GRCAN_CONF_ENABLE1      0x00000004
  79 #define GRCAN_CONF_SELECT       0x00000008
  80 #define GRCAN_CONF_SILENT       0x00000010
  81 #define GRCAN_CONF_SAM          0x00000020 /* Available in some hardware */
  82 #define GRCAN_CONF_BPR          0x00000300 /* Note: not BRP */
  83 #define GRCAN_CONF_RSJ          0x00007000
  84 #define GRCAN_CONF_PS1          0x00f00000
  85 #define GRCAN_CONF_PS2          0x000f0000
  86 #define GRCAN_CONF_SCALER       0xff000000
  87 #define GRCAN_CONF_OPERATION                                            \
  88         (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1     \
  89          | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
  90 #define GRCAN_CONF_TIMING                                               \
  91         (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1               \
  92          | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
  93
  94 #define GRCAN_CONF_RSJ_MIN      1
  95 #define GRCAN_CONF_RSJ_MAX      4
  96 #define GRCAN_CONF_PS1_MIN      1
  97 #define GRCAN_CONF_PS1_MAX      15
  98 #define GRCAN_CONF_PS2_MIN      2
  99 #define GRCAN_CONF_PS2_MAX      8
 100 #define GRCAN_CONF_SCALER_MIN   0
 101 #define GRCAN_CONF_SCALER_MAX   255
 102 #define GRCAN_CONF_SCALER_INC   1
 103
 104 #define GRCAN_CONF_BPR_BIT      8
 105 #define GRCAN_CONF_RSJ_BIT      12
 106 #define GRCAN_CONF_PS1_BIT      20
 107 #define GRCAN_CONF_PS2_BIT      16
 108 #define GRCAN_CONF_SCALER_BIT   24
 109
 110 #define GRCAN_STAT_PASS         0x000001
 111 #define GRCAN_STAT_OFF          0x000002
 112 #define GRCAN_STAT_OR           0x000004
 113 #define GRCAN_STAT_AHBERR       0x000008
 114 #define GRCAN_STAT_ACTIVE       0x000010
 115 #define GRCAN_STAT_RXERRCNT     0x00ff00
 116 #define GRCAN_STAT_TXERRCNT     0xff0000
 117
 118 #define GRCAN_STAT_ERRCTR_RELATED       (GRCAN_STAT_PASS | GRCAN_STAT_OFF)
 119
 120 #define GRCAN_STAT_RXERRCNT_BIT 8
 121 #define GRCAN_STAT_TXERRCNT_BIT 16
 122
 123 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96
 124 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127
 125
 126 #define GRCAN_CTRL_RESET        0x2
 127 #define GRCAN_CTRL_ENABLE       0x1
 128
 129 #define GRCAN_TXCTRL_ENABLE     0x1
 130 #define GRCAN_TXCTRL_ONGOING    0x2
 131 #define GRCAN_TXCTRL_SINGLE     0x4
 132
 133 #define GRCAN_RXCTRL_ENABLE     0x1
 134 #define GRCAN_RXCTRL_ONGOING    0x2
 135
 136 /* Relative offset of IRQ sources to AMBA Plug&Play */
 137 #define GRCAN_IRQIX_IRQ         0
 138 #define GRCAN_IRQIX_TXSYNC      1
 139 #define GRCAN_IRQIX_RXSYNC      2
 140
 141 #define GRCAN_IRQ_PASS          0x00001
 142 #define GRCAN_IRQ_OFF           0x00002
 143 #define GRCAN_IRQ_OR            0x00004
 144 #define GRCAN_IRQ_RXAHBERR      0x00008
 145 #define GRCAN_IRQ_TXAHBERR      0x00010
 146 #define GRCAN_IRQ_RXIRQ         0x00020
 147 #define GRCAN_IRQ_TXIRQ         0x00040
 148 #define GRCAN_IRQ_RXFULL        0x00080
 149 #define GRCAN_IRQ_TXEMPTY       0x00100
 150 #define GRCAN_IRQ_RX            0x00200
 151 #define GRCAN_IRQ_TX            0x00400
 152 #define GRCAN_IRQ_RXSYNC        0x00800
 153 #define GRCAN_IRQ_TXSYNC        0x01000
 154 #define GRCAN_IRQ_RXERRCTR      0x02000
 155 #define GRCAN_IRQ_TXERRCTR      0x04000
 156 #define GRCAN_IRQ_RXMISS        0x08000
 157 #define GRCAN_IRQ_TXLOSS        0x10000
 158
 159 #define GRCAN_IRQ_NONE  0
 160 #define GRCAN_IRQ_ALL                                                   \
 161         (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR                  \
 162          | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR                      \
 163          | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ                            \
 164          | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY                         \
 165          | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC               \
 166          | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR                        \
 167          | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS                        \
 168          | GRCAN_IRQ_TXLOSS)
 169
 170 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
 171                                   | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
 172 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR       \
 173                           | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR     \
 174                           | GRCAN_IRQ_TXLOSS)
 175 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
 176
 177 #define GRCAN_MSG_SIZE          16
 178
 179 #define GRCAN_MSG_IDE           0x80000000
 180 #define GRCAN_MSG_RTR           0x40000000
 181 #define GRCAN_MSG_BID           0x1ffc0000
 182 #define GRCAN_MSG_EID           0x1fffffff
 183 #define GRCAN_MSG_IDE_BIT       31
 184 #define GRCAN_MSG_RTR_BIT       30
 185 #define GRCAN_MSG_BID_BIT       18
 186 #define GRCAN_MSG_EID_BIT       0
 187
 188 #define GRCAN_MSG_DLC           0xf0000000
 189 #define GRCAN_MSG_TXERRC        0x00ff0000
 190 #define GRCAN_MSG_RXERRC        0x0000ff00
 191 #define GRCAN_MSG_DLC_BIT       28
 192 #define GRCAN_MSG_TXERRC_BIT    16
 193 #define GRCAN_MSG_RXERRC_BIT    8
 194 #define GRCAN_MSG_AHBERR        0x00000008
 195 #define GRCAN_MSG_OR            0x00000004
 196 #define GRCAN_MSG_OFF           0x00000002
 197 #define GRCAN_MSG_PASS          0x00000001
 198
 199 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
 200 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
 201
 202 #define GRCAN_BUFFER_ALIGNMENT          1024
 203 #define GRCAN_DEFAULT_BUFFER_SIZE       1024
 204 #define GRCAN_VALID_TR_SIZE_MASK        0x001fffc0
 205
 206 #define GRCAN_INVALID_BUFFER_SIZE(s)                    \
 207         ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
 208
 209 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
 210 #error "Invalid default buffer size"
 211 #endif
 212
 213 struct grcan_dma_buffer {
 214         size_t size;
 215         void *buf;
 216         dma_addr_t handle;
 217 };
 218
 219 struct grcan_dma {
 220         size_t base_size;
 221         void *base_buf;
 222         dma_addr_t base_handle;
 223         struct grcan_dma_buffer tx;
 224         struct grcan_dma_buffer rx;
 225 };
 226
 227 /* GRCAN configuration parameters */
 228 struct grcan_device_config {
 229         unsigned short enable0;
 230         unsigned short enable1;
 231         unsigned short select;
 232         unsigned int txsize;
 233         unsigned int rxsize;
 234 };
 235
 236 #define GRCAN_DEFAULT_DEVICE_CONFIG {                           \
 237                 .enable0        = 0,                            \
 238                 .enable1        = 0,                            \
 239                 .select         = 0,                            \
 240                 .txsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 241                 .rxsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 242                 }
 243
 244 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION  0x4100
 245 #define GRLIB_VERSION_MASK              0xffff
 246
 247 /* GRCAN private data structure */
 248 struct grcan_priv {
 249         struct can_priv can;    /* must be the first member */
 250         struct net_device *dev;
 251         struct napi_struct napi;
 252
 253         struct grcan_registers __iomem *regs;   /* ioremap'ed registers */
 254         struct grcan_device_config config;
 255         struct grcan_dma dma;
 256
 257         struct sk_buff **echo_skb;      /* We allocate this on our own */
 258         u8 *txdlc;                      /* Length of queued frames */
 259
 260         /* The echo skb pointer, pointing into echo_skb and indicating which
 261          * frames can be echoed back. See the "Notes on the tx cyclic buffer
 262          * handling"-comment for grcan_start_xmit for more details.
 263          */
 264         u32 eskbp;
 265
 266         /* Lock for controlling changes to the netif tx queue state, accesses to
 267          * the echo_skb pointer eskbp and for making sure that a running reset
 268          * and/or a close of the interface is done without interference from
 269          * other parts of the code.
 270          *
 271          * The echo_skb pointer, eskbp, should only be accessed under this lock
 272          * as it can be changed in several places and together with decisions on
 273          * whether to wake up the tx queue.
 274          *
 275          * The tx queue must never be woken up if there is a running reset or
 276          * close in progress.
 277          *
 278          * A running reset (see below on need_txbug_workaround) should never be
 279          * done if the interface is closing down and several running resets
 280          * should never be scheduled simultaneously.
 281          */
 282         spinlock_t lock;
 283
 284         /* Whether a workaround is needed due to a bug in older hardware. In
 285          * this case, the driver both tries to prevent the bug from being
 286          * triggered and recovers, if the bug nevertheless happens, by doing a
 287          * running reset. A running reset, resets the device and continues from
 288          * where it were without being noticeable from outside the driver (apart
 289          * from slight delays).
 290          */
 291         bool need_txbug_workaround;
 292
 293         /* To trigger initization of running reset and to trigger running reset
 294          * respectively in the case of a hanged device due to a txbug.
 295          */
 296         struct timer_list hang_timer;
 297         struct timer_list rr_timer;
 298
 299         /* To avoid waking up the netif queue and restarting timers
 300          * when a reset is scheduled or when closing of the device is
 301          * undergoing
 302          */
 303         bool resetting;
 304         bool closing;
 305 };
 306
 307 /* Wait time for a short wait for ongoing to clear */
 308 #define GRCAN_SHORTWAIT_USECS   10
 309
 310 /* Limit on the number of transmitted bits of an eff frame according to the CAN
 311  * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
 312  * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
 313  * bits end of frame
 314  */
 315 #define GRCAN_EFF_FRAME_MAX_BITS        (1+32+6+8*8+16+2+7)
 316
 317 #if defined(__BIG_ENDIAN)
 318 static inline u32 grcan_read_reg(u32 __iomem *reg)
 319 {
 320         return ioread32be(reg);
 321 }
 322
 323 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 324 {
 325         iowrite32be(val, reg);
 326 }
 327 #else
 328 static inline u32 grcan_read_reg(u32 __iomem *reg)
 329 {
 330         return ioread32(reg);
 331 }
 332
 333 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 334 {
 335         iowrite32(val, reg);
 336 }
 337 #endif
 338
 339 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
 340 {
 341         grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
 342 }
 343
 344 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
 345 {
 346         grcan_write_reg(reg, grcan_read_reg(reg) | mask);
 347 }
 348
 349 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
 350 {
 351         return grcan_read_reg(reg) & mask;
 352 }
 353
 354 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
 355 {
 356         u32 old = grcan_read_reg(reg);
 357
 358         grcan_write_reg(reg, (old & ~mask) | (value & mask));
 359 }
 360
 361 /* a and b should both be in [0,size] and a == b == size should not hold */
 362 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
 363 {
 364         u32 sum = a + b;
 365
 366         if (sum < size)
 367                 return sum;
 368         else
 369                 return sum - size;
 370 }
 371
 372 /* a and b should both be in [0,size) */
 373 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
 374 {
 375         return grcan_ring_add(a, size - b, size);
 376 }
 377
 378 /* Available slots for new transmissions */
 379 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
 380 {
 381         u32 slots = txsize / GRCAN_MSG_SIZE - 1;
 382         u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
 383
 384         return slots - used;
 385 }
 386
 387 /* Configuration parameters that can be set via module parameters */
 388 static struct grcan_device_config grcan_module_config =
 389         GRCAN_DEFAULT_DEVICE_CONFIG;
 390
 391 static const struct can_bittiming_const grcan_bittiming_const = {
 392         .name           = DRV_NAME,
 393         .tseg1_min      = GRCAN_CONF_PS1_MIN + 1,
 394         .tseg1_max      = GRCAN_CONF_PS1_MAX + 1,
 395         .tseg2_min      = GRCAN_CONF_PS2_MIN,
 396         .tseg2_max      = GRCAN_CONF_PS2_MAX,
 397         .sjw_max        = GRCAN_CONF_RSJ_MAX,
 398         .brp_min        = GRCAN_CONF_SCALER_MIN + 1,
 399         .brp_max        = GRCAN_CONF_SCALER_MAX + 1,
 400         .brp_inc        = GRCAN_CONF_SCALER_INC,
 401 };
 402
 403 static int grcan_set_bittiming(struct net_device *dev)
 404 {
 405         struct grcan_priv *priv = netdev_priv(dev);
 406         struct grcan_registers __iomem *regs = priv->regs;
 407         struct can_bittiming *bt = &priv->can.bittiming;
 408         u32 timing = 0;
 409         int bpr, rsj, ps1, ps2, scaler;
 410
 411         /* Should never happen - function will not be called when
 412          * device is up
 413          */
 414         if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
 415                 return -EBUSY;
 416
 417         bpr = 0; /* Note bpr and brp are different concepts */
 418         rsj = bt->sjw;
 419         ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
 420         ps2 = bt->phase_seg2;
 421         scaler = (bt->brp - 1);
 422         netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
 423                    bpr, rsj, ps1, ps2, scaler);
 424         if (!(ps1 > ps2)) {
 425                 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
 426                            ps1, ps2);
 427                 return -EINVAL;
 428         }
 429         if (!(ps2 >= rsj)) {
 430                 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
 431                            ps2, rsj);
 432                 return -EINVAL;
 433         }
 434
 435         timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
 436         timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
 437         timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
 438         timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
 439         timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
 440         netdev_info(dev, "setting timing=0x%x\n", timing);
 441         grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
 442
 443         return 0;
 444 }
 445
 446 static int grcan_get_berr_counter(const struct net_device *dev,
 447                                   struct can_berr_counter *bec)
 448 {
 449         struct grcan_priv *priv = netdev_priv(dev);
 450         struct grcan_registers __iomem *regs = priv->regs;
 451         u32 status = grcan_read_reg(&regs->stat);
 452
 453         bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
 454         bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
 455         return 0;
 456 }
 457
 458 static int grcan_poll(struct napi_struct *napi, int budget);
 459
 460 /* Reset device, but keep configuration information */
 461 static void grcan_reset(struct net_device *dev)
 462 {
 463         struct grcan_priv *priv = netdev_priv(dev);
 464         struct grcan_registers __iomem *regs = priv->regs;
 465         u32 config = grcan_read_reg(&regs->conf);
 466
 467         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
 468         grcan_write_reg(&regs->conf, config);
 469
 470         priv->eskbp = grcan_read_reg(&regs->txrd);
 471         priv->can.state = CAN_STATE_STOPPED;
 472
 473         /* Turn off hardware filtering - regs->rxcode set to 0 by reset */
 474         grcan_write_reg(&regs->rxmask, 0);
 475 }
 476
 477 /* stop device without changing any configurations */
 478 static void grcan_stop_hardware(struct net_device *dev)
 479 {
 480         struct grcan_priv *priv = netdev_priv(dev);
 481         struct grcan_registers __iomem *regs = priv->regs;
 482
 483         grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
 484         grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 485         grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 486         grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
 487 }
 488
 489 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
 490  * is true and free them otherwise.
 491  *
 492  * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
 493  * continue until priv->eskbp catches up to regs->txrd.
 494  *
 495  * priv->lock *must* be held when calling this function
 496  */
 497 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
 498 {
 499         struct grcan_priv *priv = netdev_priv(dev);
 500         struct grcan_registers __iomem *regs = priv->regs;
 501         struct grcan_dma *dma = &priv->dma;
 502         struct net_device_stats *stats = &dev->stats;
 503         int i, work_done;
 504
 505         /* Updates to priv->eskbp and wake-ups of the queue needs to
 506          * be atomic towards the reads of priv->eskbp and shut-downs
 507          * of the queue in grcan_start_xmit.
 508          */
 509         u32 txrd = grcan_read_reg(&regs->txrd);
 510
 511         for (work_done = 0; work_done < budget || budget < 0; work_done++) {
 512                 if (priv->eskbp == txrd)
 513                         break;
 514                 i = priv->eskbp / GRCAN_MSG_SIZE;
 515                 if (echo) {
 516                         /* Normal echo of messages */
 517                         stats->tx_packets++;
 518                         stats->tx_bytes += priv->txdlc[i];
 519                         priv->txdlc[i] = 0;
 520                         can_get_echo_skb(dev, i);
 521                 } else {
 522                         /* For cleanup of untransmitted messages */
 523                         can_free_echo_skb(dev, i);
 524                 }
 525
 526                 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
 527                                              dma->tx.size);
 528                 txrd = grcan_read_reg(&regs->txrd);
 529         }
 530         return work_done;
 531 }
 532
 533 static void grcan_lost_one_shot_frame(struct net_device *dev)
 534 {
 535         struct grcan_priv *priv = netdev_priv(dev);
 536         struct grcan_registers __iomem *regs = priv->regs;
 537         struct grcan_dma *dma = &priv->dma;
 538         u32 txrd;
 539         unsigned long flags;
 540
 541         spin_lock_irqsave(&priv->lock, flags);
 542
 543         catch_up_echo_skb(dev, -1, true);
 544
 545         if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
 546                 /* Should never happen */
 547                 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
 548         } else {
 549                 /* By the time an GRCAN_IRQ_TXLOSS is generated in
 550                  * one-shot mode there is no problem in writing
 551                  * to TXRD even in versions of the hardware in
 552                  * which GRCAN_TXCTRL_ONGOING is not cleared properly
 553                  * in one-shot mode.
 554                  */
 555
 556                 /* Skip message and discard echo-skb */
 557                 txrd = grcan_read_reg(&regs->txrd);
 558                 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
 559                 grcan_write_reg(&regs->txrd, txrd);
 560                 catch_up_echo_skb(dev, -1, false);
 561
 562                 if (!priv->resetting && !priv->closing &&
 563                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
 564                         netif_wake_queue(dev);
 565                         grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 566                 }
 567         }
 568
 569         spin_unlock_irqrestore(&priv->lock, flags);
 570 }
 571
 572 static void grcan_err(struct net_device *dev, u32 sources, u32 status)
 573 {
 574         struct grcan_priv *priv = netdev_priv(dev);
 575         struct grcan_registers __iomem *regs = priv->regs;
 576         struct grcan_dma *dma = &priv->dma;
 577         struct net_device_stats *stats = &dev->stats;
 578         struct can_frame cf;
 579
 580         /* Zero potential error_frame */
 581         memset(&cf, 0, sizeof(cf));
 582
 583         /* Message lost interrupt. This might be due to arbitration error, but
 584          * is also triggered when there is no one else on the can bus or when
 585          * there is a problem with the hardware interface or the bus itself. As
 586          * arbitration errors can not be singled out, no error frames are
 587          * generated reporting this event as an arbitration error.
 588          */
 589         if (sources & GRCAN_IRQ_TXLOSS) {
 590                 /* Take care of failed one-shot transmit */
 591                 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
 592                         grcan_lost_one_shot_frame(dev);
 593
 594                 /* Stop printing as soon as error passive or bus off is in
 595                  * effect to limit the amount of txloss debug printouts.
 596                  */
 597                 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
 598                         netdev_dbg(dev, "tx message lost\n");
 599                         stats->tx_errors++;
 600                 }
 601         }
 602
 603         /* Conditions dealing with the error counters. There is no interrupt for
 604          * error warning, but there are interrupts for increases of the error
 605          * counters.
 606          */
 607         if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
 608             (status & GRCAN_STAT_ERRCTR_RELATED)) {
 609                 enum can_state state = priv->can.state;
 610                 enum can_state oldstate = state;
 611                 u32 txerr = (status & GRCAN_STAT_TXERRCNT)
 612                         >> GRCAN_STAT_TXERRCNT_BIT;
 613                 u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
 614                         >> GRCAN_STAT_RXERRCNT_BIT;
 615
 616                 /* Figure out current state */
 617                 if (status & GRCAN_STAT_OFF) {
 618                         state = CAN_STATE_BUS_OFF;
 619                 } else if (status & GRCAN_STAT_PASS) {
 620                         state = CAN_STATE_ERROR_PASSIVE;
 621                 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
 622                            rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
 623                         state = CAN_STATE_ERROR_WARNING;
 624                 } else {
 625                         state = CAN_STATE_ERROR_ACTIVE;
 626                 }
 627
 628                 /* Handle and report state changes */
 629                 if (state != oldstate) {
 630                         switch (state) {
 631                         case CAN_STATE_BUS_OFF:
 632                                 netdev_dbg(dev, "bus-off\n");
 633                                 netif_carrier_off(dev);
 634                                 priv->can.can_stats.bus_off++;
 635
 636                                 /* Prevent the hardware from recovering from bus
 637                                  * off on its own if restart is disabled.
 638                                  */
 639                                 if (!priv->can.restart_ms)
 640                                         grcan_stop_hardware(dev);
 641
 642                                 cf.can_id |= CAN_ERR_BUSOFF;
 643                                 break;
 644
 645                         case CAN_STATE_ERROR_PASSIVE:
 646                                 netdev_dbg(dev, "Error passive condition\n");
 647                                 priv->can.can_stats.error_passive++;
 648
 649                                 cf.can_id |= CAN_ERR_CRTL;
 650                                 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 651                                         cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 652                                 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 653                                         cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 654                                 break;
 655
 656                         case CAN_STATE_ERROR_WARNING:
 657                                 netdev_dbg(dev, "Error warning condition\n");
 658                                 priv->can.can_stats.error_warning++;
 659
 660                                 cf.can_id |= CAN_ERR_CRTL;
 661                                 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 662                                         cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
 663                                 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 664                                         cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
 665                                 break;
 666
 667                         case CAN_STATE_ERROR_ACTIVE:
 668                                 netdev_dbg(dev, "Error active condition\n");
 669                                 cf.can_id |= CAN_ERR_CRTL;
 670                                 break;
 671
 672                         default:
 673                                 /* There are no others at this point */
 674                                 break;
 675                         }
 676                         cf.data[6] = txerr;
 677                         cf.data[7] = rxerr;
 678                         priv->can.state = state;
 679                 }
 680
 681                 /* Report automatic restarts */
 682                 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
 683                         unsigned long flags;
 684
 685                         cf.can_id |= CAN_ERR_RESTARTED;
 686                         netdev_dbg(dev, "restarted\n");
 687                         priv->can.can_stats.restarts++;
 688                         netif_carrier_on(dev);
 689
 690                         spin_lock_irqsave(&priv->lock, flags);
 691
 692                         if (!priv->resetting && !priv->closing) {
 693                                 u32 txwr = grcan_read_reg(&regs->txwr);
 694
 695                                 if (grcan_txspace(dma->tx.size, txwr,
 696                                                   priv->eskbp))
 697                                         netif_wake_queue(dev);
 698                         }
 699
 700                         spin_unlock_irqrestore(&priv->lock, flags);
 701                 }
 702         }
 703
 704         /* Data overrun interrupt */
 705         if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
 706                 netdev_dbg(dev, "got data overrun interrupt\n");
 707                 stats->rx_over_errors++;
 708                 stats->rx_errors++;
 709
 710                 cf.can_id |= CAN_ERR_CRTL;
 711                 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
 712         }
 713
 714         /* AHB bus error interrupts (not CAN bus errors) - shut down the
 715          * device.
 716          */
 717         if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
 718             (status & GRCAN_STAT_AHBERR)) {
 719                 char *txrx = "";
 720                 unsigned long flags;
 721
 722                 if (sources & GRCAN_IRQ_TXAHBERR) {
 723                         txrx = "on tx ";
 724                         stats->tx_errors++;
 725                 } else if (sources & GRCAN_IRQ_RXAHBERR) {
 726                         txrx = "on rx ";
 727                         stats->rx_errors++;
 728                 }
 729                 netdev_err(dev, "Fatal AHB bus error %s- halting device\n",
 730                            txrx);
 731
 732                 spin_lock_irqsave(&priv->lock, flags);
 733
 734                 /* Prevent anything to be enabled again and halt device */
 735                 priv->closing = true;
 736                 netif_stop_queue(dev);
 737                 grcan_stop_hardware(dev);
 738                 priv->can.state = CAN_STATE_STOPPED;
 739
 740                 spin_unlock_irqrestore(&priv->lock, flags);
 741         }
 742
 743         /* Pass on error frame if something to report,
 744          * i.e. id contains some information
 745          */
 746         if (cf.can_id) {
 747                 struct can_frame *skb_cf;
 748                 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
 749
 750                 if (skb == NULL) {
 751                         netdev_dbg(dev, "could not allocate error frame\n");
 752                         return;
 753                 }
 754                 skb_cf->can_id |= cf.can_id;
 755                 memcpy(skb_cf->data, cf.data, sizeof(cf.data));
 756
 757                 netif_rx(skb);
 758         }
 759 }
 760
 761 static irqreturn_t grcan_interrupt(int irq, void *dev_id)
 762 {
 763         struct net_device *dev = dev_id;
 764         struct grcan_priv *priv = netdev_priv(dev);
 765         struct grcan_registers __iomem *regs = priv->regs;
 766         u32 sources, status;
 767
 768         /* Find out the source */
 769         sources = grcan_read_reg(&regs->pimsr);
 770         if (!sources)
 771                 return IRQ_NONE;
 772         grcan_write_reg(&regs->picr, sources);
 773         status = grcan_read_reg(&regs->stat);
 774
 775         /* If we got TX progress, the device has not hanged,
 776          * so disable the hang timer
 777          */
 778         if (priv->need_txbug_workaround &&
 779             (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
 780                 del_timer(&priv->hang_timer);
 781         }
 782
 783         /* Frame(s) received or transmitted */
 784         if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
 785                 /* Disable tx/rx interrupts and schedule poll(). No need for
 786                  * locking as interference from a running reset at worst leads
 787                  * to an extra interrupt.
 788                  */
 789                 grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
 790                 napi_schedule(&priv->napi);
 791         }
 792
 793         /* (Potential) error conditions to take care of */
 794         if (sources & GRCAN_IRQ_ERRORS)
 795                 grcan_err(dev, sources, status);
 796
 797         return IRQ_HANDLED;
 798 }
 799
 800 /* Reset device and restart operations from where they were.
 801  *
 802  * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
 803  * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
 804  * for single shot)
 805  */
 806 static void grcan_running_reset(struct timer_list *t)
 807 {
 808         struct grcan_priv *priv = from_timer(priv, t, rr_timer);
 809         struct net_device *dev = priv->dev;
 810         struct grcan_registers __iomem *regs = priv->regs;
 811         unsigned long flags;
 812
 813         /* This temporarily messes with eskbp, so we need to lock
 814          * priv->lock
 815          */
 816         spin_lock_irqsave(&priv->lock, flags);
 817
 818         priv->resetting = false;
 819         del_timer(&priv->hang_timer);
 820         del_timer(&priv->rr_timer);
 821
 822         if (!priv->closing) {
 823                 /* Save and reset - config register preserved by grcan_reset */
 824                 u32 imr = grcan_read_reg(&regs->imr);
 825
 826                 u32 txaddr = grcan_read_reg(&regs->txaddr);
 827                 u32 txsize = grcan_read_reg(&regs->txsize);
 828                 u32 txwr = grcan_read_reg(&regs->txwr);
 829                 u32 txrd = grcan_read_reg(&regs->txrd);
 830                 u32 eskbp = priv->eskbp;
 831
 832                 u32 rxaddr = grcan_read_reg(&regs->rxaddr);
 833                 u32 rxsize = grcan_read_reg(&regs->rxsize);
 834                 u32 rxwr = grcan_read_reg(&regs->rxwr);
 835                 u32 rxrd = grcan_read_reg(&regs->rxrd);
 836
 837                 grcan_reset(dev);
 838
 839                 /* Restore */
 840                 grcan_write_reg(&regs->txaddr, txaddr);
 841                 grcan_write_reg(&regs->txsize, txsize);
 842                 grcan_write_reg(&regs->txwr, txwr);
 843                 grcan_write_reg(&regs->txrd, txrd);
 844                 priv->eskbp = eskbp;
 845
 846                 grcan_write_reg(&regs->rxaddr, rxaddr);
 847                 grcan_write_reg(&regs->rxsize, rxsize);
 848                 grcan_write_reg(&regs->rxwr, rxwr);
 849                 grcan_write_reg(&regs->rxrd, rxrd);
 850
 851                 /* Turn on device again */
 852                 grcan_write_reg(&regs->imr, imr);
 853                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
 854                 grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
 855                                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
 856                                    ? GRCAN_TXCTRL_SINGLE : 0));
 857                 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 858                 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
 859
 860                 /* Start queue if there is size and listen-onle mode is not
 861                  * enabled
 862                  */
 863                 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
 864                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
 865                         netif_wake_queue(dev);
 866         }
 867
 868         spin_unlock_irqrestore(&priv->lock, flags);
 869
 870         netdev_err(dev, "Device reset and restored\n");
 871 }
 872
 873 /* Waiting time in usecs corresponding to the transmission of three maximum
 874  * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
 875  * of time makes sure that the can controller have time to finish sending or
 876  * receiving a frame with a good margin.
 877  *
 878  * usecs/sec * number of frames * bits/frame / bits/sec
 879  */
 880 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
 881 {
 882         return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
 883 }
 884
 885 /* Set timer so that it will not fire until after a period in which the can
 886  * controller have a good margin to finish transmitting a frame unless it has
 887  * hanged
 888  */
 889 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
 890 {
 891         u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
 892
 893         mod_timer(timer, jiffies + wait_jiffies);
 894 }
 895
 896 /* Disable channels and schedule a running reset */
 897 static void grcan_initiate_running_reset(struct timer_list *t)
 898 {
 899         struct grcan_priv *priv = from_timer(priv, t, hang_timer);
 900         struct net_device *dev = priv->dev;
 901         struct grcan_registers __iomem *regs = priv->regs;
 902         unsigned long flags;
 903
 904         netdev_err(dev, "Device seems hanged - reset scheduled\n");
 905
 906         spin_lock_irqsave(&priv->lock, flags);
 907
 908         /* The main body of this function must never be executed again
 909          * until after an execution of grcan_running_reset
 910          */
 911         if (!priv->resetting && !priv->closing) {
 912                 priv->resetting = true;
 913                 netif_stop_queue(dev);
 914                 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 915                 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 916                 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
 917         }
 918
 919         spin_unlock_irqrestore(&priv->lock, flags);
 920 }
 921
 922 static void grcan_free_dma_buffers(struct net_device *dev)
 923 {
 924         struct grcan_priv *priv = netdev_priv(dev);
 925         struct grcan_dma *dma = &priv->dma;
 926
 927         dma_free_coherent(&dev->dev, dma->base_size, dma->base_buf,
 928                           dma->base_handle);
 929         memset(dma, 0, sizeof(*dma));
 930 }
 931
 932 static int grcan_allocate_dma_buffers(struct net_device *dev,
 933                                       size_t tsize, size_t rsize)
 934 {
 935         struct grcan_priv *priv = netdev_priv(dev);
 936         struct grcan_dma *dma = &priv->dma;
 937         struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
 938         struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
 939         size_t shift;
 940
 941         /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
 942          * i.e. first buffer
 943          */
 944         size_t maxs = max(tsize, rsize);
 945         size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
 946
 947         /* Put the small buffer after that */
 948         size_t ssize = min(tsize, rsize);
 949
 950         /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
 951         dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
 952         dma->base_buf = dma_alloc_coherent(&dev->dev,
 953                                            dma->base_size,
 954                                            &dma->base_handle,
 955                                            GFP_KERNEL);
 956
 957         if (!dma->base_buf)
 958                 return -ENOMEM;
 959
 960         dma->tx.size = tsize;
 961         dma->rx.size = rsize;
 962
 963         large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
 964         small->handle = large->handle + lsize;
 965         shift = large->handle - dma->base_handle;
 966
 967         large->buf = dma->base_buf + shift;
 968         small->buf = large->buf + lsize;
 969
 970         return 0;
 971 }
 972
 973 /* priv->lock *must* be held when calling this function */
 974 static int grcan_start(struct net_device *dev)
 975 {
 976         struct grcan_priv *priv = netdev_priv(dev);
 977         struct grcan_registers __iomem *regs = priv->regs;
 978         u32 confop, txctrl;
 979
 980         grcan_reset(dev);
 981
 982         grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
 983         grcan_write_reg(&regs->txsize, priv->dma.tx.size);
 984         /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
 985
 986         grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
 987         grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
 988         /* regs->rxwr and regs->rxrd already set to 0 by reset */
 989
 990         /* Enable interrupts */
 991         grcan_read_reg(&regs->pir);
 992         grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
 993
 994         /* Enable interfaces, channels and device */
 995         confop = GRCAN_CONF_ABORT
 996                 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
 997                 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
 998                 | (priv->config.select ? GRCAN_CONF_SELECT : 0)
 999                 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1000                    GRCAN_CONF_SILENT : 0)
1001                 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1002                    GRCAN_CONF_SAM : 0);
1003         grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1004         txctrl = GRCAN_TXCTRL_ENABLE
1005                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1006                    ? GRCAN_TXCTRL_SINGLE : 0);
1007         grcan_write_reg(&regs->txctrl, txctrl);
1008         grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1009         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1010
1011         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1012
1013         return 0;
1014 }
1015
1016 static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1017 {
1018         struct grcan_priv *priv = netdev_priv(dev);
1019         unsigned long flags;
1020         int err = 0;
1021
1022         if (mode == CAN_MODE_START) {
1023                 /* This might be called to restart the device to recover from
1024                  * bus off errors
1025                  */
1026                 spin_lock_irqsave(&priv->lock, flags);
1027                 if (priv->closing || priv->resetting) {
1028                         err = -EBUSY;
1029                 } else {
1030                         netdev_info(dev, "Restarting device\n");
1031                         grcan_start(dev);
1032                         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1033                                 netif_wake_queue(dev);
1034                 }
1035                 spin_unlock_irqrestore(&priv->lock, flags);
1036                 return err;
1037         }
1038         return -EOPNOTSUPP;
1039 }
1040
1041 static int grcan_open(struct net_device *dev)
1042 {
1043         struct grcan_priv *priv = netdev_priv(dev);
1044         struct grcan_dma *dma = &priv->dma;
1045         unsigned long flags;
1046         int err;
1047
1048         /* Allocate memory */
1049         err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1050                                          priv->config.rxsize);
1051         if (err) {
1052                 netdev_err(dev, "could not allocate DMA buffers\n");
1053                 return err;
1054         }
1055
1056         priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb),
1057                                  GFP_KERNEL);
1058         if (!priv->echo_skb) {
1059                 err = -ENOMEM;
1060                 goto exit_free_dma_buffers;
1061         }
1062         priv->can.echo_skb_max = dma->tx.size;
1063         priv->can.echo_skb = priv->echo_skb;
1064
1065         priv->txdlc = kcalloc(dma->tx.size, sizeof(*priv->txdlc), GFP_KERNEL);
1066         if (!priv->txdlc) {
1067                 err = -ENOMEM;
1068                 goto exit_free_echo_skb;
1069         }
1070
1071         /* Get can device up */
1072         err = open_candev(dev);
1073         if (err)
1074                 goto exit_free_txdlc;
1075
1076         err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1077                           dev->name, dev);
1078         if (err)
1079                 goto exit_close_candev;
1080
1081         spin_lock_irqsave(&priv->lock, flags);
1082
1083         napi_enable(&priv->napi);
1084         grcan_start(dev);
1085         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1086                 netif_start_queue(dev);
1087         priv->resetting = false;
1088         priv->closing = false;
1089
1090         spin_unlock_irqrestore(&priv->lock, flags);
1091
1092         return 0;
1093
1094 exit_close_candev:
1095         close_candev(dev);
1096 exit_free_txdlc:
1097         kfree(priv->txdlc);
1098 exit_free_echo_skb:
1099         kfree(priv->echo_skb);
1100 exit_free_dma_buffers:
1101         grcan_free_dma_buffers(dev);
1102         return err;
1103 }
1104
1105 static int grcan_close(struct net_device *dev)
1106 {
1107         struct grcan_priv *priv = netdev_priv(dev);
1108         unsigned long flags;
1109
1110         napi_disable(&priv->napi);
1111
1112         spin_lock_irqsave(&priv->lock, flags);
1113
1114         priv->closing = true;
1115         if (priv->need_txbug_workaround) {
1116                 del_timer_sync(&priv->hang_timer);
1117                 del_timer_sync(&priv->rr_timer);
1118         }
1119         netif_stop_queue(dev);
1120         grcan_stop_hardware(dev);
1121         priv->can.state = CAN_STATE_STOPPED;
1122
1123         spin_unlock_irqrestore(&priv->lock, flags);
1124
1125         free_irq(dev->irq, dev);
1126         close_candev(dev);
1127
1128         grcan_free_dma_buffers(dev);
1129         priv->can.echo_skb_max = 0;
1130         priv->can.echo_skb = NULL;
1131         kfree(priv->echo_skb);
1132         kfree(priv->txdlc);
1133
1134         return 0;
1135 }
1136
1137 static int grcan_transmit_catch_up(struct net_device *dev, int budget)
1138 {
1139         struct grcan_priv *priv = netdev_priv(dev);
1140         unsigned long flags;
1141         int work_done;
1142
1143         spin_lock_irqsave(&priv->lock, flags);
1144
1145         work_done = catch_up_echo_skb(dev, budget, true);
1146         if (work_done) {
1147                 if (!priv->resetting && !priv->closing &&
1148                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1149                         netif_wake_queue(dev);
1150
1151                 /* With napi we don't get TX interrupts for a while,
1152                  * so prevent a running reset while catching up
1153                  */
1154                 if (priv->need_txbug_workaround)
1155                         del_timer(&priv->hang_timer);
1156         }
1157
1158         spin_unlock_irqrestore(&priv->lock, flags);
1159
1160         return work_done;
1161 }
1162
1163 static int grcan_receive(struct net_device *dev, int budget)
1164 {
1165         struct grcan_priv *priv = netdev_priv(dev);
1166         struct grcan_registers __iomem *regs = priv->regs;
1167         struct grcan_dma *dma = &priv->dma;
1168         struct net_device_stats *stats = &dev->stats;
1169         struct can_frame *cf;
1170         struct sk_buff *skb;
1171         u32 wr, rd, startrd;
1172         u32 *slot;
1173         u32 i, rtr, eff, j, shift;
1174         int work_done = 0;
1175
1176         rd = grcan_read_reg(&regs->rxrd);
1177         startrd = rd;
1178         for (work_done = 0; work_done < budget; work_done++) {
1179                 /* Check for packet to receive */
1180                 wr = grcan_read_reg(&regs->rxwr);
1181                 if (rd == wr)
1182                         break;
1183
1184                 /* Take care of packet */
1185                 skb = alloc_can_skb(dev, &cf);
1186                 if (skb == NULL) {
1187                         netdev_err(dev,
1188                                    "dropping frame: skb allocation failed\n");
1189                         stats->rx_dropped++;
1190                         continue;
1191                 }
1192
1193                 slot = dma->rx.buf + rd;
1194                 eff = slot[0] & GRCAN_MSG_IDE;
1195                 rtr = slot[0] & GRCAN_MSG_RTR;
1196                 if (eff) {
1197                         cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1198                                       >> GRCAN_MSG_EID_BIT);
1199                         cf->can_id |= CAN_EFF_FLAG;
1200                 } else {
1201                         cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1202                                       >> GRCAN_MSG_BID_BIT);
1203                 }
1204                 cf->can_dlc = get_can_dlc((slot[1] & GRCAN_MSG_DLC)
1205                                           >> GRCAN_MSG_DLC_BIT);
1206                 if (rtr) {
1207                         cf->can_id |= CAN_RTR_FLAG;
1208                 } else {
1209                         for (i = 0; i < cf->can_dlc; i++) {
1210                                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1211                                 shift = GRCAN_MSG_DATA_SHIFT(i);
1212                                 cf->data[i] = (u8)(slot[j] >> shift);
1213                         }
1214                 }
1215
1216                 /* Update statistics and read pointer */
1217                 stats->rx_packets++;
1218                 stats->rx_bytes += cf->can_dlc;
1219                 netif_receive_skb(skb);
1220
1221                 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1222         }
1223
1224         /* Make sure everything is read before allowing hardware to
1225          * use the memory
1226          */
1227         mb();
1228
1229         /* Update read pointer - no need to check for ongoing */
1230         if (likely(rd != startrd))
1231                 grcan_write_reg(&regs->rxrd, rd);
1232
1233         return work_done;
1234 }
1235
1236 static int grcan_poll(struct napi_struct *napi, int budget)
1237 {
1238         struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1239         struct net_device *dev = priv->dev;
1240         struct grcan_registers __iomem *regs = priv->regs;
1241         unsigned long flags;
1242         int tx_work_done, rx_work_done;
1243         int rx_budget = budget / 2;
1244         int tx_budget = budget - rx_budget;
1245
1246         /* Half of the budget for receiving messages */
1247         rx_work_done = grcan_receive(dev, rx_budget);
1248
1249         /* Half of the budget for transmitting messages as that can trigger echo
1250          * frames being received
1251          */
1252         tx_work_done = grcan_transmit_catch_up(dev, tx_budget);
1253
1254         if (rx_work_done < rx_budget && tx_work_done < tx_budget) {
1255                 napi_complete(napi);
1256
1257                 /* Guarantee no interference with a running reset that otherwise
1258                  * could turn off interrupts.
1259                  */
1260                 spin_lock_irqsave(&priv->lock, flags);
1261
1262                 /* Enable tx and rx interrupts again. No need to check
1263                  * priv->closing as napi_disable in grcan_close is waiting for
1264                  * scheduled napi calls to finish.
1265                  */
1266                 grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1267
1268                 spin_unlock_irqrestore(&priv->lock, flags);
1269         }
1270
1271         return rx_work_done + tx_work_done;
1272 }
1273
1274 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
1275  * drop a frame in one-shot mode or indicate a busy device otherwise.
1276  *
1277  * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1278  * value that should be returned by grcan_start_xmit when aborting the xmit.
1279  */
1280 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1281                                   u32 txwr, u32 oneshotmode,
1282                                   netdev_tx_t *netdev_tx_status)
1283 {
1284         struct grcan_priv *priv = netdev_priv(dev);
1285         struct grcan_registers __iomem *regs = priv->regs;
1286         struct grcan_dma *dma = &priv->dma;
1287         int i;
1288         unsigned long flags;
1289
1290         /* Wait a while for ongoing to be cleared or read pointer to catch up to
1291          * write pointer. The latter is needed due to a bug in older versions of
1292          * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1293          * transmission fails.
1294          */
1295         for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1296                 udelay(1);
1297                 if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1298                     grcan_read_reg(&regs->txrd) == txwr) {
1299                         return 0;
1300                 }
1301         }
1302
1303         /* Clean up, in case the situation was not resolved */
1304         spin_lock_irqsave(&priv->lock, flags);
1305         if (!priv->resetting && !priv->closing) {
1306                 /* Queue might have been stopped earlier in grcan_start_xmit */
1307                 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1308                         netif_wake_queue(dev);
1309                 /* Set a timer to resolve a hanged tx controller */
1310                 if (!timer_pending(&priv->hang_timer))
1311                         grcan_reset_timer(&priv->hang_timer,
1312                                           priv->can.bittiming.bitrate);
1313         }
1314         spin_unlock_irqrestore(&priv->lock, flags);
1315
1316         if (oneshotmode) {
1317                 /* In one-shot mode we should never end up here because
1318                  * then the interrupt handler increases txrd on TXLOSS,
1319                  * but it is consistent with one-shot mode to drop the
1320                  * frame in this case.
1321                  */
1322                 kfree_skb(skb);
1323                 *netdev_tx_status = NETDEV_TX_OK;
1324         } else {
1325                 /* In normal mode the socket-can transmission queue get
1326                  * to keep the frame so that it can be retransmitted
1327                  * later
1328                  */
1329                 *netdev_tx_status = NETDEV_TX_BUSY;
1330         }
1331         return -EBUSY;
1332 }
1333
1334 /* Notes on the tx cyclic buffer handling:
1335  *
1336  * regs->txwr   - the next slot for the driver to put data to be sent
1337  * regs->txrd   - the next slot for the device to read data
1338  * priv->eskbp  - the next slot for the driver to call can_put_echo_skb for
1339  *
1340  * grcan_start_xmit can enter more messages as long as regs->txwr does
1341  * not reach priv->eskbp (within 1 message gap)
1342  *
1343  * The device sends messages until regs->txrd reaches regs->txwr
1344  *
1345  * The interrupt calls handler calls can_put_echo_skb until
1346  * priv->eskbp reaches regs->txrd
1347  */
1348 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1349                                     struct net_device *dev)
1350 {
1351         struct grcan_priv *priv = netdev_priv(dev);
1352         struct grcan_registers __iomem *regs = priv->regs;
1353         struct grcan_dma *dma = &priv->dma;
1354         struct can_frame *cf = (struct can_frame *)skb->data;
1355         u32 id, txwr, txrd, space, txctrl;
1356         int slotindex;
1357         u32 *slot;
1358         u32 i, rtr, eff, dlc, tmp, err;
1359         int j, shift;
1360         unsigned long flags;
1361         u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1362
1363         if (can_dropped_invalid_skb(dev, skb))
1364                 return NETDEV_TX_OK;
1365
1366         /* Trying to transmit in silent mode will generate error interrupts, but
1367          * this should never happen - the queue should not have been started.
1368          */
1369         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1370                 return NETDEV_TX_BUSY;
1371
1372         /* Reads of priv->eskbp and shut-downs of the queue needs to
1373          * be atomic towards the updates to priv->eskbp and wake-ups
1374          * of the queue in the interrupt handler.
1375          */
1376         spin_lock_irqsave(&priv->lock, flags);
1377
1378         txwr = grcan_read_reg(&regs->txwr);
1379         space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1380
1381         slotindex = txwr / GRCAN_MSG_SIZE;
1382         slot = dma->tx.buf + txwr;
1383
1384         if (unlikely(space == 1))
1385                 netif_stop_queue(dev);
1386
1387         spin_unlock_irqrestore(&priv->lock, flags);
1388         /* End of critical section*/
1389
1390         /* This should never happen. If circular buffer is full, the
1391          * netif_stop_queue should have been stopped already.
1392          */
1393         if (unlikely(!space)) {
1394                 netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1395                 return NETDEV_TX_BUSY;
1396         }
1397
1398         /* Convert and write CAN message to DMA buffer */
1399         eff = cf->can_id & CAN_EFF_FLAG;
1400         rtr = cf->can_id & CAN_RTR_FLAG;
1401         id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1402         dlc = cf->can_dlc;
1403         if (eff)
1404                 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1405         else
1406                 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1407         slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1408
1409         slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1410         slot[2] = 0;
1411         slot[3] = 0;
1412         for (i = 0; i < dlc; i++) {
1413                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1414                 shift = GRCAN_MSG_DATA_SHIFT(i);
1415                 slot[j] |= cf->data[i] << shift;
1416         }
1417
1418         /* Checking that channel has not been disabled. These cases
1419          * should never happen
1420          */
1421         txctrl = grcan_read_reg(&regs->txctrl);
1422         if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1423                 netdev_err(dev, "tx channel spuriously disabled\n");
1424
1425         if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1426                 netdev_err(dev, "one-shot mode spuriously disabled\n");
1427
1428         /* Bug workaround for old version of grcan where updating txwr
1429          * in the same clock cycle as the controller updates txrd to
1430          * the current txwr could hang the can controller
1431          */
1432         if (priv->need_txbug_workaround) {
1433                 txrd = grcan_read_reg(&regs->txrd);
1434                 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1435                         netdev_tx_t txstatus;
1436
1437                         err = grcan_txbug_workaround(dev, skb, txwr,
1438                                                      oneshotmode, &txstatus);
1439                         if (err)
1440                                 return txstatus;
1441                 }
1442         }
1443
1444         /* Prepare skb for echoing. This must be after the bug workaround above
1445          * as ownership of the skb is passed on by calling can_put_echo_skb.
1446          * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1447          * can_put_echo_skb would be an error unless other measures are
1448          * taken.
1449          */
1450         priv->txdlc[slotindex] = cf->can_dlc; /* Store dlc for statistics */
1451         can_put_echo_skb(skb, dev, slotindex);
1452
1453         /* Make sure everything is written before allowing hardware to
1454          * read from the memory
1455          */
1456         wmb();
1457
1458         /* Update write pointer to start transmission */
1459         grcan_write_reg(&regs->txwr,
1460                         grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1461
1462         return NETDEV_TX_OK;
1463 }
1464
1465 /* ========== Setting up sysfs interface and module parameters ========== */
1466
1467 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1468
1469 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)                \
1470         static void grcan_sanitize_##name(struct platform_device *pd)   \
1471         {                                                               \
1472                 struct grcan_device_config grcan_default_config         \
1473                         = GRCAN_DEFAULT_DEVICE_CONFIG;                  \
1474                 if (valcheckf(grcan_module_config.name)) {              \
1475                         dev_err(&pd->dev,                               \
1476                                 "Invalid module parameter value for "   \
1477                                 #name " - setting default\n");          \
1478                         grcan_module_config.name =                      \
1479                                 grcan_default_config.name;              \
1480                 }                                                       \
1481         }                                                               \
1482         module_param_named(name, grcan_module_config.name,              \
1483                            mtype, 0444);                                \
1484         MODULE_PARM_DESC(name, desc)
1485
1486 #define GRCAN_CONFIG_ATTR(name, desc)                                   \
1487         static ssize_t grcan_store_##name(struct device *sdev,          \
1488                                           struct device_attribute *att, \
1489                                           const char *buf,              \
1490                                           size_t count)                 \
1491         {                                                               \
1492                 struct net_device *dev = to_net_dev(sdev);              \
1493                 struct grcan_priv *priv = netdev_priv(dev);             \
1494                 u8 val;                                                 \
1495                 int ret;                                                \
1496                 if (dev->flags & IFF_UP)                                \
1497                         return -EBUSY;                                  \
1498                 ret = kstrtou8(buf, 0, &val);                           \
1499                 if (ret < 0 || val > 1)                                 \
1500                         return -EINVAL;                                 \
1501                 priv->config.name = val;                                \
1502                 return count;                                           \
1503         }                                                               \
1504         static ssize_t grcan_show_##name(struct device *sdev,           \
1505                                          struct device_attribute *att,  \
1506                                          char *buf)                     \
1507         {                                                               \
1508                 struct net_device *dev = to_net_dev(sdev);              \
1509                 struct grcan_priv *priv = netdev_priv(dev);             \
1510                 return sprintf(buf, "%d\n", priv->config.name);         \
1511         }                                                               \
1512         static DEVICE_ATTR(name, 0644,                                  \
1513                            grcan_show_##name,                           \
1514                            grcan_store_##name);                         \
1515         GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1516
1517 /* The following configuration options are made available both via module
1518  * parameters and writable sysfs files. See the chapter about GRCAN in the
1519  * documentation for the GRLIB VHDL library for further details.
1520  */
1521 GRCAN_CONFIG_ATTR(enable0,
1522                   "Configuration of physical interface 0. Determines\n" \
1523                   "the \"Enable 0\" bit of the configuration register.\n" \
1524                   "Format: 0 | 1\nDefault: 0\n");
1525
1526 GRCAN_CONFIG_ATTR(enable1,
1527                   "Configuration of physical interface 1. Determines\n" \
1528                   "the \"Enable 1\" bit of the configuration register.\n" \
1529                   "Format: 0 | 1\nDefault: 0\n");
1530
1531 GRCAN_CONFIG_ATTR(select,
1532                   "Select which physical interface to use.\n"   \
1533                   "Format: 0 | 1\nDefault: 0\n");
1534
1535 /* The tx and rx buffer size configuration options are only available via module
1536  * parameters.
1537  */
1538 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1539                    "Sets the size of the tx buffer.\n"                  \
1540                    "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1541                    "Default: 1024\n");
1542 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1543                    "Sets the size of the rx buffer.\n"                  \
1544                    "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1545                    "Default: 1024\n");
1546
1547 /* Function that makes sure that configuration done using
1548  * module parameters are set to valid values
1549  */
1550 static void grcan_sanitize_module_config(struct platform_device *ofdev)
1551 {
1552         grcan_sanitize_enable0(ofdev);
1553         grcan_sanitize_enable1(ofdev);
1554         grcan_sanitize_select(ofdev);
1555         grcan_sanitize_txsize(ofdev);
1556         grcan_sanitize_rxsize(ofdev);
1557 }
1558
1559 static const struct attribute *const sysfs_grcan_attrs[] = {
1560         /* Config attrs */
1561         &dev_attr_enable0.attr,
1562         &dev_attr_enable1.attr,
1563         &dev_attr_select.attr,
1564         NULL,
1565 };
1566
1567 static const struct attribute_group sysfs_grcan_group = {
1568         .name   = "grcan",
1569         .attrs  = (struct attribute **)sysfs_grcan_attrs,
1570 };
1571
1572 /* ========== Setting up the driver ========== */
1573
1574 static const struct net_device_ops grcan_netdev_ops = {
1575         .ndo_open       = grcan_open,
1576         .ndo_stop       = grcan_close,
1577         .ndo_start_xmit = grcan_start_xmit,
1578         .ndo_change_mtu = can_change_mtu,
1579 };
1580
1581 static int grcan_setup_netdev(struct platform_device *ofdev,
1582                               void __iomem *base,
1583                               int irq, u32 ambafreq, bool txbug)
1584 {
1585         struct net_device *dev;
1586         struct grcan_priv *priv;
1587         struct grcan_registers __iomem *regs;
1588         int err;
1589
1590         dev = alloc_candev(sizeof(struct grcan_priv), 0);
1591         if (!dev)
1592                 return -ENOMEM;
1593
1594         dev->irq = irq;
1595         dev->flags |= IFF_ECHO;
1596         dev->netdev_ops = &grcan_netdev_ops;
1597         dev->sysfs_groups[0] = &sysfs_grcan_group;
1598
1599         priv = netdev_priv(dev);
1600         memcpy(&priv->config, &grcan_module_config,
1601                sizeof(struct grcan_device_config));
1602         priv->dev = dev;
1603         priv->regs = base;
1604         priv->can.bittiming_const = &grcan_bittiming_const;
1605         priv->can.do_set_bittiming = grcan_set_bittiming;
1606         priv->can.do_set_mode = grcan_set_mode;
1607         priv->can.do_get_berr_counter = grcan_get_berr_counter;
1608         priv->can.clock.freq = ambafreq;
1609         priv->can.ctrlmode_supported =
1610                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1611         priv->need_txbug_workaround = txbug;
1612
1613         /* Discover if triple sampling is supported by hardware */
1614         regs = priv->regs;
1615         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1616         grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1617         if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1618                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1619                 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1620         }
1621
1622         spin_lock_init(&priv->lock);
1623
1624         if (priv->need_txbug_workaround) {
1625                 timer_setup(&priv->rr_timer, grcan_running_reset, 0);
1626                 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0);
1627         }
1628
1629         netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1630
1631         SET_NETDEV_DEV(dev, &ofdev->dev);
1632         dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1633                  priv->regs, dev->irq, priv->can.clock.freq);
1634
1635         err = register_candev(dev);
1636         if (err)
1637                 goto exit_free_candev;
1638
1639         platform_set_drvdata(ofdev, dev);
1640
1641         /* Reset device to allow bit-timing to be set. No need to call
1642          * grcan_reset at this stage. That is done in grcan_open.
1643          */
1644         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1645
1646         return 0;
1647 exit_free_candev:
1648         free_candev(dev);
1649         return err;
1650 }
1651
1652 static int grcan_probe(struct platform_device *ofdev)
1653 {
1654         struct device_node *np = ofdev->dev.of_node;
1655         u32 sysid, ambafreq;
1656         int irq, err;
1657         void __iomem *base;
1658         bool txbug = true;
1659
1660         /* Compare GRLIB version number with the first that does not
1661          * have the tx bug (see start_xmit)
1662          */
1663         err = of_property_read_u32(np, "systemid", &sysid);
1664         if (!err && ((sysid & GRLIB_VERSION_MASK)
1665                      >= GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1666                 txbug = false;
1667
1668         err = of_property_read_u32(np, "freq", &ambafreq);
1669         if (err) {
1670                 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1671                 goto exit_error;
1672         }
1673
1674         base = devm_platform_ioremap_resource(ofdev, 0);
1675         if (IS_ERR(base)) {
1676                 err = PTR_ERR(base);
1677                 goto exit_error;
1678         }
1679
1680         irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1681         if (!irq) {
1682                 dev_err(&ofdev->dev, "no irq found\n");
1683                 err = -ENODEV;
1684                 goto exit_error;
1685         }
1686
1687         grcan_sanitize_module_config(ofdev);
1688
1689         err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1690         if (err)
1691                 goto exit_dispose_irq;
1692
1693         return 0;
1694
1695 exit_dispose_irq:
1696         irq_dispose_mapping(irq);
1697 exit_error:
1698         dev_err(&ofdev->dev,
1699                 "%s socket CAN driver initialization failed with error %d\n",
1700                 DRV_NAME, err);
1701         return err;
1702 }
1703
1704 static int grcan_remove(struct platform_device *ofdev)
1705 {
1706         struct net_device *dev = platform_get_drvdata(ofdev);
1707         struct grcan_priv *priv = netdev_priv(dev);
1708
1709         unregister_candev(dev); /* Will in turn call grcan_close */
1710
1711         irq_dispose_mapping(dev->irq);
1712         netif_napi_del(&priv->napi);
1713         free_candev(dev);
1714
1715         return 0;
1716 }
1717
1718 static const struct of_device_id grcan_match[] = {
1719         {.name = "GAISLER_GRCAN"},
1720         {.name = "01_03d"},
1721         {.name = "GAISLER_GRHCAN"},
1722         {.name = "01_034"},
1723         {},
1724 };
1725
1726 MODULE_DEVICE_TABLE(of, grcan_match);
1727
1728 static struct platform_driver grcan_driver = {
1729         .driver = {
1730                 .name = DRV_NAME,
1731                 .of_match_table = grcan_match,
1732         },
1733         .probe = grcan_probe,
1734         .remove = grcan_remove,
1735 };
1736
1737 module_platform_driver(grcan_driver);
1738
1739 MODULE_AUTHOR("Aeroflex Gaisler AB.");
1740 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1741 MODULE_LICENSE("GPL");