drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <dt-bindings/firmware/imx/rsrc.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/can.h>
  15 #include <linux/can/dev.h>
  16 #include <linux/can/error.h>
  17 #include <linux/can/led.h>
  18 #include <linux/can/rx-offload.h>
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/firmware/imx/sci.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pinctrl/consumer.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/regmap.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #define DRV_NAME                        "flexcan"
  36
  37 /* 8 for RX fifo and 2 error handling */
  38 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  39
  40 /* FLEXCAN module configuration register (CANMCR) bits */
  41 #define FLEXCAN_MCR_MDIS                BIT(31)
  42 #define FLEXCAN_MCR_FRZ                 BIT(30)
  43 #define FLEXCAN_MCR_FEN                 BIT(29)
  44 #define FLEXCAN_MCR_HALT                BIT(28)
  45 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  46 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  47 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  48 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  49 #define FLEXCAN_MCR_SUPV                BIT(23)
  50 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  51 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  52 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  53 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  54 #define FLEXCAN_MCR_DOZE                BIT(18)
  55 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  56 #define FLEXCAN_MCR_IRMQ                BIT(16)
  57 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  58 #define FLEXCAN_MCR_AEN                 BIT(12)
  59 #define FLEXCAN_MCR_FDEN                BIT(11)
  60 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  61 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  62 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  63 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  64 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  65 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  66
  67 /* FLEXCAN control register (CANCTRL) bits */
  68 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  69 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  70 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  71 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  72 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  73 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  74 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  75 #define FLEXCAN_CTRL_LPB                BIT(12)
  76 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  77 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  78 #define FLEXCAN_CTRL_SMP                BIT(7)
  79 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  80 #define FLEXCAN_CTRL_TSYN               BIT(5)
  81 #define FLEXCAN_CTRL_LBUF               BIT(4)
  82 #define FLEXCAN_CTRL_LOM                BIT(3)
  83 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  84 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  85 #define FLEXCAN_CTRL_ERR_STATE \
  86         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  87          FLEXCAN_CTRL_BOFF_MSK)
  88 #define FLEXCAN_CTRL_ERR_ALL \
  89         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  90
  91 /* FLEXCAN control register 2 (CTRL2) bits */
  92 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  93 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  94 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  95 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  96 #define FLEXCAN_CTRL2_MRP               BIT(18)
  97 #define FLEXCAN_CTRL2_RRS               BIT(17)
  98 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  99 #define FLEXCAN_CTRL2_ISOCANFDEN        BIT(12)
 100
 101 /* FLEXCAN memory error control register (MECR) bits */
 102 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
 103 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
 104 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
 105 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 106 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 107 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 108 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 109 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 110 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 111 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 112
 113 /* FLEXCAN error and status register (ESR) bits */
 114 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 115 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 116 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 117 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 118 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 119 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 120 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 121 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 122 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 123 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 124 #define FLEXCAN_ESR_IDLE                BIT(7)
 125 #define FLEXCAN_ESR_TXRX                BIT(6)
 126 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 127 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 128 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 129 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 130 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 131 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 132 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 133 #define FLEXCAN_ESR_ERR_BUS \
 134         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 135          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 136          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 137 #define FLEXCAN_ESR_ERR_STATE \
 138         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 139 #define FLEXCAN_ESR_ERR_ALL \
 140         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 141 #define FLEXCAN_ESR_ALL_INT \
 142         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 143          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 144
 145 /* FLEXCAN Bit Timing register (CBT) bits */
 146 #define FLEXCAN_CBT_BTF                 BIT(31)
 147 #define FLEXCAN_CBT_EPRESDIV_MASK       GENMASK(30, 21)
 148 #define FLEXCAN_CBT_ERJW_MASK           GENMASK(20, 16)
 149 #define FLEXCAN_CBT_EPROPSEG_MASK       GENMASK(15, 10)
 150 #define FLEXCAN_CBT_EPSEG1_MASK         GENMASK(9, 5)
 151 #define FLEXCAN_CBT_EPSEG2_MASK         GENMASK(4, 0)
 152
 153 /* FLEXCAN FD control register (FDCTRL) bits */
 154 #define FLEXCAN_FDCTRL_FDRATE           BIT(31)
 155 #define FLEXCAN_FDCTRL_MBDSR1           GENMASK(20, 19)
 156 #define FLEXCAN_FDCTRL_MBDSR0           GENMASK(17, 16)
 157 #define FLEXCAN_FDCTRL_MBDSR_8          0x0
 158 #define FLEXCAN_FDCTRL_MBDSR_12         0x1
 159 #define FLEXCAN_FDCTRL_MBDSR_32         0x2
 160 #define FLEXCAN_FDCTRL_MBDSR_64         0x3
 161 #define FLEXCAN_FDCTRL_TDCEN            BIT(15)
 162 #define FLEXCAN_FDCTRL_TDCFAIL          BIT(14)
 163 #define FLEXCAN_FDCTRL_TDCOFF           GENMASK(12, 8)
 164 #define FLEXCAN_FDCTRL_TDCVAL           GENMASK(5, 0)
 165
 166 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
 167 #define FLEXCAN_FDCBT_FPRESDIV_MASK     GENMASK(29, 20)
 168 #define FLEXCAN_FDCBT_FRJW_MASK         GENMASK(18, 16)
 169 #define FLEXCAN_FDCBT_FPROPSEG_MASK     GENMASK(14, 10)
 170 #define FLEXCAN_FDCBT_FPSEG1_MASK       GENMASK(7, 5)
 171 #define FLEXCAN_FDCBT_FPSEG2_MASK       GENMASK(2, 0)
 172
 173 /* FLEXCAN interrupt flag register (IFLAG) bits */
 174 /* Errata ERR005829 step7: Reserve first valid MB */
 175 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 176 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 177 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 178 #define FLEXCAN_IFLAG_MB(x)             BIT_ULL(x)
 179 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 180 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 181 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 182
 183 /* FLEXCAN message buffers */
 184 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 185 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 186 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 187 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 188 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 189 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 190 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 191
 192 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 193 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 194 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 195 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 196
 197 #define FLEXCAN_MB_CNT_EDL              BIT(31)
 198 #define FLEXCAN_MB_CNT_BRS              BIT(30)
 199 #define FLEXCAN_MB_CNT_ESI              BIT(29)
 200 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 201 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 202 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 203 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 204 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 205
 206 #define FLEXCAN_TIMEOUT_US              (250)
 207
 208 /* FLEXCAN hardware feature flags
 209  *
 210  * Below is some version info we got:
 211  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode
 212  *                                Filter? connected?  Passive detection  ption in MB Supported?
 213  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no
 214  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no
 215  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no
 216  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no
 217  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no
 218  *   MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes
 219  *   MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes
 220  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no
 221  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no
 222  * LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes
 223  *
 224  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 225  */
 226
 227 /* [TR]WRN_INT not connected */
 228 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
 229  /* Disable RX FIFO Global mask */
 230 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
 231 /* Enable EACEN and RRS bit in ctrl2 */
 232 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3)
 233 /* Disable non-correctable errors interrupt and freeze mode */
 234 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
 235 /* Use timestamp based offloading */
 236 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
 237 /* No interrupt for error passive */
 238 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
 239 /* default to BE register access */
 240 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
 241 /* Setup stop mode with GPR to support wakeup */
 242 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
 243 /* Support CAN-FD mode */
 244 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
 245 /* support memory detection and correction */
 246 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
 247 /* Setup stop mode with SCU firmware to support wakeup */
 248 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
 249
 250 /* Structure of the message buffer */
 251 struct flexcan_mb {
 252         u32 can_ctrl;
 253         u32 can_id;
 254         u32 data[];
 255 };
 256
 257 /* Structure of the hardware registers */
 258 struct flexcan_regs {
 259         u32 mcr;                /* 0x00 */
 260         u32 ctrl;               /* 0x04 - Not affected by Soft Reset */
 261         u32 timer;              /* 0x08 */
 262         u32 tcr;                /* 0x0c */
 263         u32 rxgmask;            /* 0x10 - Not affected by Soft Reset */
 264         u32 rx14mask;           /* 0x14 - Not affected by Soft Reset */
 265         u32 rx15mask;           /* 0x18 - Not affected by Soft Reset */
 266         u32 ecr;                /* 0x1c */
 267         u32 esr;                /* 0x20 */
 268         u32 imask2;             /* 0x24 */
 269         u32 imask1;             /* 0x28 */
 270         u32 iflag2;             /* 0x2c */
 271         u32 iflag1;             /* 0x30 */
 272         union {                 /* 0x34 */
 273                 u32 gfwr_mx28;  /* MX28, MX53 */
 274                 u32 ctrl2;      /* MX6, VF610 - Not affected by Soft Reset */
 275         };
 276         u32 esr2;               /* 0x38 */
 277         u32 imeur;              /* 0x3c */
 278         u32 lrfr;               /* 0x40 */
 279         u32 crcr;               /* 0x44 */
 280         u32 rxfgmask;           /* 0x48 */
 281         u32 rxfir;              /* 0x4c - Not affected by Soft Reset */
 282         u32 cbt;                /* 0x50 - Not affected by Soft Reset */
 283         u32 _reserved2;         /* 0x54 */
 284         u32 dbg1;               /* 0x58 */
 285         u32 dbg2;               /* 0x5c */
 286         u32 _reserved3[8];      /* 0x60 */
 287         u8 mb[2][512];          /* 0x80 - Not affected by Soft Reset */
 288         /* FIFO-mode:
 289          *                      MB
 290          * 0x080...0x08f        0       RX message buffer
 291          * 0x090...0x0df        1-5     reserved
 292          * 0x0e0...0x0ff        6-7     8 entry ID table
 293          *                              (mx25, mx28, mx35, mx53)
 294          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 295          *                              size conf'ed via ctrl2::RFFN
 296          *                              (mx6, vf610)
 297          */
 298         u32 _reserved4[256];    /* 0x480 */
 299         u32 rximr[64];          /* 0x880 - Not affected by Soft Reset */
 300         u32 _reserved5[24];     /* 0x980 */
 301         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 302         u32 _reserved6[39];     /* 0x9e4 */
 303         u32 _rxfir[6];          /* 0xa80 */
 304         u32 _reserved8[2];      /* 0xa98 */
 305         u32 _rxmgmask;          /* 0xaa0 */
 306         u32 _rxfgmask;          /* 0xaa4 */
 307         u32 _rx14mask;          /* 0xaa8 */
 308         u32 _rx15mask;          /* 0xaac */
 309         u32 tx_smb[4];          /* 0xab0 */
 310         u32 rx_smb0[4];         /* 0xac0 */
 311         u32 rx_smb1[4];         /* 0xad0 */
 312         u32 mecr;               /* 0xae0 */
 313         u32 erriar;             /* 0xae4 */
 314         u32 erridpr;            /* 0xae8 */
 315         u32 errippr;            /* 0xaec */
 316         u32 rerrar;             /* 0xaf0 */
 317         u32 rerrdr;             /* 0xaf4 */
 318         u32 rerrsynr;           /* 0xaf8 */
 319         u32 errsr;              /* 0xafc */
 320         u32 _reserved7[64];     /* 0xb00 */
 321         u32 fdctrl;             /* 0xc00 - Not affected by Soft Reset */
 322         u32 fdcbt;              /* 0xc04 - Not affected by Soft Reset */
 323         u32 fdcrc;              /* 0xc08 */
 324         u32 _reserved9[199];    /* 0xc0c */
 325         u32 tx_smb_fd[18];      /* 0xf28 */
 326         u32 rx_smb0_fd[18];     /* 0xf70 */
 327         u32 rx_smb1_fd[18];     /* 0xfb8 */
 328 };
 329
 330 static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
 331
 332 struct flexcan_devtype_data {
 333         u32 quirks;             /* quirks needed for different IP cores */
 334 };
 335
 336 struct flexcan_stop_mode {
 337         struct regmap *gpr;
 338         u8 req_gpr;
 339         u8 req_bit;
 340 };
 341
 342 struct flexcan_priv {
 343         struct can_priv can;
 344         struct can_rx_offload offload;
 345         struct device *dev;
 346
 347         struct flexcan_regs __iomem *regs;
 348         struct flexcan_mb __iomem *tx_mb;
 349         struct flexcan_mb __iomem *tx_mb_reserved;
 350         u8 tx_mb_idx;
 351         u8 mb_count;
 352         u8 mb_size;
 353         u8 clk_src;     /* clock source of CAN Protocol Engine */
 354         u8 scu_idx;
 355
 356         u64 rx_mask;
 357         u64 tx_mask;
 358         u32 reg_ctrl_default;
 359
 360         struct clk *clk_ipg;
 361         struct clk *clk_per;
 362         const struct flexcan_devtype_data *devtype_data;
 363         struct regulator *reg_xceiver;
 364         struct flexcan_stop_mode stm;
 365
 366         /* IPC handle when setup stop mode by System Controller firmware(scfw) */
 367         struct imx_sc_ipc *sc_ipc_handle;
 368
 369         /* Read and Write APIs */
 370         u32 (*read)(void __iomem *addr);
 371         void (*write)(u32 val, void __iomem *addr);
 372 };
 373
 374 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 375         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 376                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 377                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 378 };
 379
 380 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 381         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 382                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 383 };
 384
 385 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 386         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 387 };
 388
 389 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 390         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 391                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 392                 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR,
 393 };
 394
 395 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
 396         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 397                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 398                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW,
 399 };
 400
 401 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
 402         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 403                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 404                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
 405                 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
 406 };
 407
 408 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 409         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 410                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 411                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
 412 };
 413
 414 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 415         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 416                 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 417 };
 418
 419 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 420         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 421                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 422                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
 423                 FLEXCAN_QUIRK_SUPPORT_ECC,
 424 };
 425
 426 static const struct can_bittiming_const flexcan_bittiming_const = {
 427         .name = DRV_NAME,
 428         .tseg1_min = 4,
 429         .tseg1_max = 16,
 430         .tseg2_min = 2,
 431         .tseg2_max = 8,
 432         .sjw_max = 4,
 433         .brp_min = 1,
 434         .brp_max = 256,
 435         .brp_inc = 1,
 436 };
 437
 438 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
 439         .name = DRV_NAME,
 440         .tseg1_min = 2,
 441         .tseg1_max = 96,
 442         .tseg2_min = 2,
 443         .tseg2_max = 32,
 444         .sjw_max = 16,
 445         .brp_min = 1,
 446         .brp_max = 1024,
 447         .brp_inc = 1,
 448 };
 449
 450 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
 451         .name = DRV_NAME,
 452         .tseg1_min = 2,
 453         .tseg1_max = 39,
 454         .tseg2_min = 2,
 455         .tseg2_max = 8,
 456         .sjw_max = 4,
 457         .brp_min = 1,
 458         .brp_max = 1024,
 459         .brp_inc = 1,
 460 };
 461
 462 /* FlexCAN module is essentially modelled as a little-endian IP in most
 463  * SoCs, i.e the registers as well as the message buffer areas are
 464  * implemented in a little-endian fashion.
 465  *
 466  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 467  * module in a big-endian fashion (i.e the registers as well as the
 468  * message buffer areas are implemented in a big-endian way).
 469  *
 470  * In addition, the FlexCAN module can be found on SoCs having ARM or
 471  * PPC cores. So, we need to abstract off the register read/write
 472  * functions, ensuring that these cater to all the combinations of module
 473  * endianness and underlying CPU endianness.
 474  */
 475 static inline u32 flexcan_read_be(void __iomem *addr)
 476 {
 477         return ioread32be(addr);
 478 }
 479
 480 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 481 {
 482         iowrite32be(val, addr);
 483 }
 484
 485 static inline u32 flexcan_read_le(void __iomem *addr)
 486 {
 487         return ioread32(addr);
 488 }
 489
 490 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 491 {
 492         iowrite32(val, addr);
 493 }
 494
 495 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 496                                                  u8 mb_index)
 497 {
 498         u8 bank_size;
 499         bool bank;
 500
 501         if (WARN_ON(mb_index >= priv->mb_count))
 502                 return NULL;
 503
 504         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 505
 506         bank = mb_index >= bank_size;
 507         if (bank)
 508                 mb_index -= bank_size;
 509
 510         return (struct flexcan_mb __iomem *)
 511                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 512 }
 513
 514 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 515 {
 516         struct flexcan_regs __iomem *regs = priv->regs;
 517         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 518
 519         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 520                 udelay(10);
 521
 522         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 523                 return -ETIMEDOUT;
 524
 525         return 0;
 526 }
 527
 528 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 529 {
 530         struct flexcan_regs __iomem *regs = priv->regs;
 531         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 532
 533         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 534                 udelay(10);
 535
 536         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 537                 return -ETIMEDOUT;
 538
 539         return 0;
 540 }
 541
 542 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 543 {
 544         struct flexcan_regs __iomem *regs = priv->regs;
 545         u32 reg_mcr;
 546
 547         reg_mcr = priv->read(&regs->mcr);
 548
 549         if (enable)
 550                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 551         else
 552                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 553
 554         priv->write(reg_mcr, &regs->mcr);
 555 }
 556
 557 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
 558 {
 559         u8 idx = priv->scu_idx;
 560         u32 rsrc_id, val;
 561
 562         rsrc_id = IMX_SC_R_CAN(idx);
 563
 564         if (enabled)
 565                 val = 1;
 566         else
 567                 val = 0;
 568
 569         /* stop mode request via scu firmware */
 570         return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
 571                                        IMX_SC_C_IPG_STOP, val);
 572 }
 573
 574 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 575 {
 576         struct flexcan_regs __iomem *regs = priv->regs;
 577         u32 reg_mcr;
 578         int ret;
 579
 580         reg_mcr = priv->read(&regs->mcr);
 581         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 582         priv->write(reg_mcr, &regs->mcr);
 583
 584         /* enable stop request */
 585         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 586                 ret = flexcan_stop_mode_enable_scfw(priv, true);
 587                 if (ret < 0)
 588                         return ret;
 589         } else {
 590                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 591                                    1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 592         }
 593
 594         return flexcan_low_power_enter_ack(priv);
 595 }
 596
 597 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 598 {
 599         struct flexcan_regs __iomem *regs = priv->regs;
 600         u32 reg_mcr;
 601         int ret;
 602
 603         /* remove stop request */
 604         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
 605                 ret = flexcan_stop_mode_enable_scfw(priv, false);
 606                 if (ret < 0)
 607                         return ret;
 608         } else {
 609                 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 610                                    1 << priv->stm.req_bit, 0);
 611         }
 612
 613         reg_mcr = priv->read(&regs->mcr);
 614         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 615         priv->write(reg_mcr, &regs->mcr);
 616
 617         return flexcan_low_power_exit_ack(priv);
 618 }
 619
 620 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 621 {
 622         struct flexcan_regs __iomem *regs = priv->regs;
 623         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 624
 625         priv->write(reg_ctrl, &regs->ctrl);
 626 }
 627
 628 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 629 {
 630         struct flexcan_regs __iomem *regs = priv->regs;
 631         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 632
 633         priv->write(reg_ctrl, &regs->ctrl);
 634 }
 635
 636 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 637 {
 638         int err;
 639
 640         err = clk_prepare_enable(priv->clk_ipg);
 641         if (err)
 642                 return err;
 643
 644         err = clk_prepare_enable(priv->clk_per);
 645         if (err)
 646                 clk_disable_unprepare(priv->clk_ipg);
 647
 648         return err;
 649 }
 650
 651 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 652 {
 653         clk_disable_unprepare(priv->clk_per);
 654         clk_disable_unprepare(priv->clk_ipg);
 655 }
 656
 657 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 658 {
 659         if (!priv->reg_xceiver)
 660                 return 0;
 661
 662         return regulator_enable(priv->reg_xceiver);
 663 }
 664
 665 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 666 {
 667         if (!priv->reg_xceiver)
 668                 return 0;
 669
 670         return regulator_disable(priv->reg_xceiver);
 671 }
 672
 673 static int flexcan_chip_enable(struct flexcan_priv *priv)
 674 {
 675         struct flexcan_regs __iomem *regs = priv->regs;
 676         u32 reg;
 677
 678         reg = priv->read(&regs->mcr);
 679         reg &= ~FLEXCAN_MCR_MDIS;
 680         priv->write(reg, &regs->mcr);
 681
 682         return flexcan_low_power_exit_ack(priv);
 683 }
 684
 685 static int flexcan_chip_disable(struct flexcan_priv *priv)
 686 {
 687         struct flexcan_regs __iomem *regs = priv->regs;
 688         u32 reg;
 689
 690         reg = priv->read(&regs->mcr);
 691         reg |= FLEXCAN_MCR_MDIS;
 692         priv->write(reg, &regs->mcr);
 693
 694         return flexcan_low_power_enter_ack(priv);
 695 }
 696
 697 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 698 {
 699         struct flexcan_regs __iomem *regs = priv->regs;
 700         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 701         u32 reg;
 702
 703         reg = priv->read(&regs->mcr);
 704         reg |= FLEXCAN_MCR_HALT;
 705         priv->write(reg, &regs->mcr);
 706
 707         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 708                 udelay(100);
 709
 710         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 711                 return -ETIMEDOUT;
 712
 713         return 0;
 714 }
 715
 716 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 717 {
 718         struct flexcan_regs __iomem *regs = priv->regs;
 719         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 720         u32 reg;
 721
 722         reg = priv->read(&regs->mcr);
 723         reg &= ~FLEXCAN_MCR_HALT;
 724         priv->write(reg, &regs->mcr);
 725
 726         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 727                 udelay(10);
 728
 729         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 730                 return -ETIMEDOUT;
 731
 732         return 0;
 733 }
 734
 735 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 736 {
 737         struct flexcan_regs __iomem *regs = priv->regs;
 738         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 739
 740         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 741         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 742                 udelay(10);
 743
 744         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 745                 return -ETIMEDOUT;
 746
 747         return 0;
 748 }
 749
 750 static int __flexcan_get_berr_counter(const struct net_device *dev,
 751                                       struct can_berr_counter *bec)
 752 {
 753         const struct flexcan_priv *priv = netdev_priv(dev);
 754         struct flexcan_regs __iomem *regs = priv->regs;
 755         u32 reg = priv->read(&regs->ecr);
 756
 757         bec->txerr = (reg >> 0) & 0xff;
 758         bec->rxerr = (reg >> 8) & 0xff;
 759
 760         return 0;
 761 }
 762
 763 static int flexcan_get_berr_counter(const struct net_device *dev,
 764                                     struct can_berr_counter *bec)
 765 {
 766         const struct flexcan_priv *priv = netdev_priv(dev);
 767         int err;
 768
 769         err = pm_runtime_get_sync(priv->dev);
 770         if (err < 0) {
 771                 pm_runtime_put_noidle(priv->dev);
 772                 return err;
 773         }
 774
 775         err = __flexcan_get_berr_counter(dev, bec);
 776
 777         pm_runtime_put(priv->dev);
 778
 779         return err;
 780 }
 781
 782 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 783 {
 784         const struct flexcan_priv *priv = netdev_priv(dev);
 785         struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
 786         u32 can_id;
 787         u32 data;
 788         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
 789         int i;
 790
 791         if (can_dropped_invalid_skb(dev, skb))
 792                 return NETDEV_TX_OK;
 793
 794         netif_stop_queue(dev);
 795
 796         if (cfd->can_id & CAN_EFF_FLAG) {
 797                 can_id = cfd->can_id & CAN_EFF_MASK;
 798                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 799         } else {
 800                 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
 801         }
 802
 803         if (cfd->can_id & CAN_RTR_FLAG)
 804                 ctrl |= FLEXCAN_MB_CNT_RTR;
 805
 806         if (can_is_canfd_skb(skb)) {
 807                 ctrl |= FLEXCAN_MB_CNT_EDL;
 808
 809                 if (cfd->flags & CANFD_BRS)
 810                         ctrl |= FLEXCAN_MB_CNT_BRS;
 811         }
 812
 813         for (i = 0; i < cfd->len; i += sizeof(u32)) {
 814                 data = be32_to_cpup((__be32 *)&cfd->data[i]);
 815                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 816         }
 817
 818         can_put_echo_skb(skb, dev, 0, 0);
 819
 820         priv->write(can_id, &priv->tx_mb->can_id);
 821         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 822
 823         /* Errata ERR005829 step8:
 824          * Write twice INACTIVE(0x8) code to first MB.
 825          */
 826         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 827                     &priv->tx_mb_reserved->can_ctrl);
 828         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 829                     &priv->tx_mb_reserved->can_ctrl);
 830
 831         return NETDEV_TX_OK;
 832 }
 833
 834 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 835 {
 836         struct flexcan_priv *priv = netdev_priv(dev);
 837         struct flexcan_regs __iomem *regs = priv->regs;
 838         struct sk_buff *skb;
 839         struct can_frame *cf;
 840         bool rx_errors = false, tx_errors = false;
 841         u32 timestamp;
 842         int err;
 843
 844         timestamp = priv->read(&regs->timer) << 16;
 845
 846         skb = alloc_can_err_skb(dev, &cf);
 847         if (unlikely(!skb))
 848                 return;
 849
 850         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 851
 852         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 853                 netdev_dbg(dev, "BIT1_ERR irq\n");
 854                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 855                 tx_errors = true;
 856         }
 857         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 858                 netdev_dbg(dev, "BIT0_ERR irq\n");
 859                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 860                 tx_errors = true;
 861         }
 862         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 863                 netdev_dbg(dev, "ACK_ERR irq\n");
 864                 cf->can_id |= CAN_ERR_ACK;
 865                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 866                 tx_errors = true;
 867         }
 868         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 869                 netdev_dbg(dev, "CRC_ERR irq\n");
 870                 cf->data[2] |= CAN_ERR_PROT_BIT;
 871                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 872                 rx_errors = true;
 873         }
 874         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 875                 netdev_dbg(dev, "FRM_ERR irq\n");
 876                 cf->data[2] |= CAN_ERR_PROT_FORM;
 877                 rx_errors = true;
 878         }
 879         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 880                 netdev_dbg(dev, "STF_ERR irq\n");
 881                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 882                 rx_errors = true;
 883         }
 884
 885         priv->can.can_stats.bus_error++;
 886         if (rx_errors)
 887                 dev->stats.rx_errors++;
 888         if (tx_errors)
 889                 dev->stats.tx_errors++;
 890
 891         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 892         if (err)
 893                 dev->stats.rx_fifo_errors++;
 894 }
 895
 896 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 897 {
 898         struct flexcan_priv *priv = netdev_priv(dev);
 899         struct flexcan_regs __iomem *regs = priv->regs;
 900         struct sk_buff *skb;
 901         struct can_frame *cf;
 902         enum can_state new_state, rx_state, tx_state;
 903         int flt;
 904         struct can_berr_counter bec;
 905         u32 timestamp;
 906         int err;
 907
 908         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 909         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 910                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 911                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 912                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 913                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 914                 new_state = max(tx_state, rx_state);
 915         } else {
 916                 __flexcan_get_berr_counter(dev, &bec);
 917                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 918                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 919                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 920                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 921         }
 922
 923         /* state hasn't changed */
 924         if (likely(new_state == priv->can.state))
 925                 return;
 926
 927         timestamp = priv->read(&regs->timer) << 16;
 928
 929         skb = alloc_can_err_skb(dev, &cf);
 930         if (unlikely(!skb))
 931                 return;
 932
 933         can_change_state(dev, cf, tx_state, rx_state);
 934
 935         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 936                 can_bus_off(dev);
 937
 938         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 939         if (err)
 940                 dev->stats.rx_fifo_errors++;
 941 }
 942
 943 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 944 {
 945         u64 reg = 0;
 946
 947         if (upper_32_bits(mask))
 948                 reg = (u64)priv->read(addr - 4) << 32;
 949         if (lower_32_bits(mask))
 950                 reg |= priv->read(addr);
 951
 952         return reg & mask;
 953 }
 954
 955 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
 956 {
 957         if (upper_32_bits(val))
 958                 priv->write(upper_32_bits(val), addr - 4);
 959         if (lower_32_bits(val))
 960                 priv->write(lower_32_bits(val), addr);
 961 }
 962
 963 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 964 {
 965         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
 966 }
 967
 968 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
 969 {
 970         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
 971 }
 972
 973 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 974 {
 975         return container_of(offload, struct flexcan_priv, offload);
 976 }
 977
 978 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
 979                                             unsigned int n, u32 *timestamp,
 980                                             bool drop)
 981 {
 982         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 983         struct flexcan_regs __iomem *regs = priv->regs;
 984         struct flexcan_mb __iomem *mb;
 985         struct sk_buff *skb;
 986         struct canfd_frame *cfd;
 987         u32 reg_ctrl, reg_id, reg_iflag1;
 988         int i;
 989
 990         if (unlikely(drop)) {
 991                 skb = ERR_PTR(-ENOBUFS);
 992                 goto mark_as_read;
 993         }
 994
 995         mb = flexcan_get_mb(priv, n);
 996
 997         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 998                 u32 code;
 999
1000                 do {
1001                         reg_ctrl = priv->read(&mb->can_ctrl);
1002                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
1003
1004                 /* is this MB empty? */
1005                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
1006                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
1007                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
1008                         return NULL;
1009
1010                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
1011                         /* This MB was overrun, we lost data */
1012                         offload->dev->stats.rx_over_errors++;
1013                         offload->dev->stats.rx_errors++;
1014                 }
1015         } else {
1016                 reg_iflag1 = priv->read(&regs->iflag1);
1017                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
1018                         return NULL;
1019
1020                 reg_ctrl = priv->read(&mb->can_ctrl);
1021         }
1022
1023         if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1024                 skb = alloc_canfd_skb(offload->dev, &cfd);
1025         else
1026                 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1027         if (unlikely(!skb)) {
1028                 skb = ERR_PTR(-ENOMEM);
1029                 goto mark_as_read;
1030         }
1031
1032         /* increase timstamp to full 32 bit */
1033         *timestamp = reg_ctrl << 16;
1034
1035         reg_id = priv->read(&mb->can_id);
1036         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1037                 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1038         else
1039                 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1040
1041         if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1042                 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1043
1044                 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1045                         cfd->flags |= CANFD_BRS;
1046         } else {
1047                 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1048
1049                 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1050                         cfd->can_id |= CAN_RTR_FLAG;
1051         }
1052
1053         if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1054                 cfd->flags |= CANFD_ESI;
1055
1056         for (i = 0; i < cfd->len; i += sizeof(u32)) {
1057                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1058                 *(__be32 *)(cfd->data + i) = data;
1059         }
1060
1061  mark_as_read:
1062         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1063                 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1064         else
1065                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1066
1067         /* Read the Free Running Timer. It is optional but recommended
1068          * to unlock Mailbox as soon as possible and make it available
1069          * for reception.
1070          */
1071         priv->read(&regs->timer);
1072
1073         return skb;
1074 }
1075
1076 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1077 {
1078         struct net_device *dev = dev_id;
1079         struct net_device_stats *stats = &dev->stats;
1080         struct flexcan_priv *priv = netdev_priv(dev);
1081         struct flexcan_regs __iomem *regs = priv->regs;
1082         irqreturn_t handled = IRQ_NONE;
1083         u64 reg_iflag_tx;
1084         u32 reg_esr;
1085         enum can_state last_state = priv->can.state;
1086
1087         /* reception interrupt */
1088         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1089                 u64 reg_iflag_rx;
1090                 int ret;
1091
1092                 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1093                         handled = IRQ_HANDLED;
1094                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1095                                                                    reg_iflag_rx);
1096                         if (!ret)
1097                                 break;
1098                 }
1099         } else {
1100                 u32 reg_iflag1;
1101
1102                 reg_iflag1 = priv->read(&regs->iflag1);
1103                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1104                         handled = IRQ_HANDLED;
1105                         can_rx_offload_irq_offload_fifo(&priv->offload);
1106                 }
1107
1108                 /* FIFO overflow interrupt */
1109                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1110                         handled = IRQ_HANDLED;
1111                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1112                                     &regs->iflag1);
1113                         dev->stats.rx_over_errors++;
1114                         dev->stats.rx_errors++;
1115                 }
1116         }
1117
1118         reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1119
1120         /* transmission complete interrupt */
1121         if (reg_iflag_tx & priv->tx_mask) {
1122                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1123
1124                 handled = IRQ_HANDLED;
1125                 stats->tx_bytes +=
1126                         can_rx_offload_get_echo_skb(&priv->offload, 0,
1127                                                     reg_ctrl << 16, NULL);
1128                 stats->tx_packets++;
1129                 can_led_event(dev, CAN_LED_EVENT_TX);
1130
1131                 /* after sending a RTR frame MB is in RX mode */
1132                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1133                             &priv->tx_mb->can_ctrl);
1134                 flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1135                 netif_wake_queue(dev);
1136         }
1137
1138         reg_esr = priv->read(&regs->esr);
1139
1140         /* ACK all bus error, state change and wake IRQ sources */
1141         if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1142                 handled = IRQ_HANDLED;
1143                 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1144         }
1145
1146         /* state change interrupt or broken error state quirk fix is enabled */
1147         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1148             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1149                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1150                 flexcan_irq_state(dev, reg_esr);
1151
1152         /* bus error IRQ - handle if bus error reporting is activated */
1153         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1154             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1155                 flexcan_irq_bus_err(dev, reg_esr);
1156
1157         /* availability of error interrupt among state transitions in case
1158          * bus error reporting is de-activated and
1159          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1160          *  +--------------------------------------------------------------+
1161          *  | +----------------------------------------------+ [stopped /  |
1162          *  | |                                              |  sleeping] -+
1163          *  +-+-> active <-> warning <-> passive -> bus off -+
1164          *        ___________^^^^^^^^^^^^_______________________________
1165          *        disabled(1)  enabled             disabled
1166          *
1167          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1168          */
1169         if ((last_state != priv->can.state) &&
1170             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1171             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1172                 switch (priv->can.state) {
1173                 case CAN_STATE_ERROR_ACTIVE:
1174                         if (priv->devtype_data->quirks &
1175                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1176                                 flexcan_error_irq_enable(priv);
1177                         else
1178                                 flexcan_error_irq_disable(priv);
1179                         break;
1180
1181                 case CAN_STATE_ERROR_WARNING:
1182                         flexcan_error_irq_enable(priv);
1183                         break;
1184
1185                 case CAN_STATE_ERROR_PASSIVE:
1186                 case CAN_STATE_BUS_OFF:
1187                         flexcan_error_irq_disable(priv);
1188                         break;
1189
1190                 default:
1191                         break;
1192                 }
1193         }
1194
1195         return handled;
1196 }
1197
1198 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1199 {
1200         const struct flexcan_priv *priv = netdev_priv(dev);
1201         const struct can_bittiming *bt = &priv->can.bittiming;
1202         struct flexcan_regs __iomem *regs = priv->regs;
1203         u32 reg;
1204
1205         reg = priv->read(&regs->ctrl);
1206         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1207                  FLEXCAN_CTRL_RJW(0x3) |
1208                  FLEXCAN_CTRL_PSEG1(0x7) |
1209                  FLEXCAN_CTRL_PSEG2(0x7) |
1210                  FLEXCAN_CTRL_PROPSEG(0x7));
1211
1212         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1213                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1214                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1215                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1216                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1217
1218         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1219         priv->write(reg, &regs->ctrl);
1220
1221         /* print chip status */
1222         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1223                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1224 }
1225
1226 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1227 {
1228         struct flexcan_priv *priv = netdev_priv(dev);
1229         struct can_bittiming *bt = &priv->can.bittiming;
1230         struct can_bittiming *dbt = &priv->can.data_bittiming;
1231         struct flexcan_regs __iomem *regs = priv->regs;
1232         u32 reg_cbt, reg_fdctrl;
1233
1234         /* CBT */
1235         /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1236          * long. The can_calc_bittiming() tries to divide the tseg1
1237          * equally between phase_seg1 and prop_seg, which may not fit
1238          * in CBT register. Therefore, if phase_seg1 is more than
1239          * possible value, increase prop_seg and decrease phase_seg1.
1240          */
1241         if (bt->phase_seg1 > 0x20) {
1242                 bt->prop_seg += (bt->phase_seg1 - 0x20);
1243                 bt->phase_seg1 = 0x20;
1244         }
1245
1246         reg_cbt = FLEXCAN_CBT_BTF |
1247                 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1248                 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1249                 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1250                 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1251                 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1252
1253         netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1254         priv->write(reg_cbt, &regs->cbt);
1255
1256         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1257                 u32 reg_fdcbt, reg_ctrl2;
1258
1259                 if (bt->brp != dbt->brp)
1260                         netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1261                                     dbt->brp, bt->brp);
1262
1263                 /* FDCBT */
1264                 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1265                  * 5 bit long. The can_calc_bittiming tries to divide
1266                  * the tseg1 equally between phase_seg1 and prop_seg,
1267                  * which may not fit in FDCBT register. Therefore, if
1268                  * phase_seg1 is more than possible value, increase
1269                  * prop_seg and decrease phase_seg1
1270                  */
1271                 if (dbt->phase_seg1 > 0x8) {
1272                         dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1273                         dbt->phase_seg1 = 0x8;
1274                 }
1275
1276                 reg_fdcbt = priv->read(&regs->fdcbt);
1277                 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1278                                FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1279                                FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1280                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1281                                FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1282
1283                 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1284                         FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1285                         FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1286                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1287                         FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1288
1289                 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1290                 priv->write(reg_fdcbt, &regs->fdcbt);
1291
1292                 /* CTRL2 */
1293                 reg_ctrl2 = priv->read(&regs->ctrl2);
1294                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1295                 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1296                         reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1297
1298                 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1299                 priv->write(reg_ctrl2, &regs->ctrl2);
1300         }
1301
1302         /* FDCTRL */
1303         reg_fdctrl = priv->read(&regs->fdctrl);
1304         reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1305                         FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1306
1307         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1308                 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1309
1310                 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1311                         /* TDC must be disabled for Loop Back mode */
1312                         reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1313                 } else {
1314                         reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1315                                 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1316                                            ((dbt->phase_seg1 - 1) +
1317                                             dbt->prop_seg + 2) *
1318                                            ((dbt->brp - 1 ) + 1));
1319                 }
1320         }
1321
1322         netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1323         priv->write(reg_fdctrl, &regs->fdctrl);
1324
1325         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1326                    __func__,
1327                    priv->read(&regs->mcr), priv->read(&regs->ctrl),
1328                    priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1329                    priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1330 }
1331
1332 static void flexcan_set_bittiming(struct net_device *dev)
1333 {
1334         const struct flexcan_priv *priv = netdev_priv(dev);
1335         struct flexcan_regs __iomem *regs = priv->regs;
1336         u32 reg;
1337
1338         reg = priv->read(&regs->ctrl);
1339         reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1340                  FLEXCAN_CTRL_LOM);
1341
1342         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1343                 reg |= FLEXCAN_CTRL_LPB;
1344         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1345                 reg |= FLEXCAN_CTRL_LOM;
1346         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1347                 reg |= FLEXCAN_CTRL_SMP;
1348
1349         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1350         priv->write(reg, &regs->ctrl);
1351
1352         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1353                 return flexcan_set_bittiming_cbt(dev);
1354         else
1355                 return flexcan_set_bittiming_ctrl(dev);
1356 }
1357
1358 static void flexcan_ram_init(struct net_device *dev)
1359 {
1360         struct flexcan_priv *priv = netdev_priv(dev);
1361         struct flexcan_regs __iomem *regs = priv->regs;
1362         u32 reg_ctrl2;
1363
1364         /* 11.8.3.13 Detection and correction of memory errors:
1365          * CTRL2[WRMFRZ] grants write access to all memory positions
1366          * that require initialization, ranging from 0x080 to 0xADF
1367          * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1368          * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1369          * need to be initialized as well. MCR[RFEN] must not be set
1370          * during memory initialization.
1371          */
1372         reg_ctrl2 = priv->read(&regs->ctrl2);
1373         reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1374         priv->write(reg_ctrl2, &regs->ctrl2);
1375
1376         memset_io(&regs->mb[0][0], 0,
1377                   offsetof(struct flexcan_regs, rx_smb1[3]) -
1378                   offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1379
1380         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1381                 memset_io(&regs->tx_smb_fd[0], 0,
1382                           offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1383                           offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1384
1385         reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1386         priv->write(reg_ctrl2, &regs->ctrl2);
1387 }
1388
1389 static int flexcan_rx_offload_setup(struct net_device *dev)
1390 {
1391         struct flexcan_priv *priv = netdev_priv(dev);
1392         int err;
1393
1394         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1395                 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1396         else
1397                 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1398         priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1399                          (sizeof(priv->regs->mb[1]) / priv->mb_size);
1400
1401         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1402                 priv->tx_mb_reserved =
1403                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1404         else
1405                 priv->tx_mb_reserved =
1406                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1407         priv->tx_mb_idx = priv->mb_count - 1;
1408         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1409         priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1410
1411         priv->offload.mailbox_read = flexcan_mailbox_read;
1412
1413         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1414                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1415                 priv->offload.mb_last = priv->mb_count - 2;
1416
1417                 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1418                                             priv->offload.mb_first);
1419                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1420         } else {
1421                 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1422                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1423                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1424                                               FLEXCAN_NAPI_WEIGHT);
1425         }
1426
1427         return err;
1428 }
1429
1430 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1431 {
1432         const struct flexcan_priv *priv = netdev_priv(dev);
1433         struct flexcan_regs __iomem *regs = priv->regs;
1434         u64 reg_imask;
1435
1436         disable_irq(dev->irq);
1437         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1438         reg_imask = priv->rx_mask | priv->tx_mask;
1439         priv->write(upper_32_bits(reg_imask), &regs->imask2);
1440         priv->write(lower_32_bits(reg_imask), &regs->imask1);
1441         enable_irq(dev->irq);
1442 }
1443
1444 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1445 {
1446         const struct flexcan_priv *priv = netdev_priv(dev);
1447         struct flexcan_regs __iomem *regs = priv->regs;
1448
1449         priv->write(0, &regs->imask2);
1450         priv->write(0, &regs->imask1);
1451         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1452                     &regs->ctrl);
1453 }
1454
1455 /* flexcan_chip_start
1456  *
1457  * this functions is entered with clocks enabled
1458  *
1459  */
1460 static int flexcan_chip_start(struct net_device *dev)
1461 {
1462         struct flexcan_priv *priv = netdev_priv(dev);
1463         struct flexcan_regs __iomem *regs = priv->regs;
1464         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1465         int err, i;
1466         struct flexcan_mb __iomem *mb;
1467
1468         /* enable module */
1469         err = flexcan_chip_enable(priv);
1470         if (err)
1471                 return err;
1472
1473         /* soft reset */
1474         err = flexcan_chip_softreset(priv);
1475         if (err)
1476                 goto out_chip_disable;
1477
1478         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1479                 flexcan_ram_init(dev);
1480
1481         flexcan_set_bittiming(dev);
1482
1483         /* MCR
1484          *
1485          * enable freeze
1486          * halt now
1487          * only supervisor access
1488          * enable warning int
1489          * enable individual RX masking
1490          * choose format C
1491          * set max mailbox number
1492          */
1493         reg_mcr = priv->read(&regs->mcr);
1494         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1495         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1496                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1497                 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1498
1499         /* MCR
1500          *
1501          * FIFO:
1502          * - disable for timestamp mode
1503          * - enable for FIFO mode
1504          */
1505         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1506                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1507         else
1508                 reg_mcr |= FLEXCAN_MCR_FEN;
1509
1510         /* MCR
1511          *
1512          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1513          *       asserted because this will impede the self reception
1514          *       of a transmitted message. This is not documented in
1515          *       earlier versions of flexcan block guide.
1516          *
1517          * Self Reception:
1518          * - enable Self Reception for loopback mode
1519          *   (by clearing "Self Reception Disable" bit)
1520          * - disable for normal operation
1521          */
1522         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1523                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1524         else
1525                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1526
1527         /* MCR - CAN-FD */
1528         if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1529                 reg_mcr |= FLEXCAN_MCR_FDEN;
1530         else
1531                 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1532
1533         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1534         priv->write(reg_mcr, &regs->mcr);
1535
1536         /* CTRL
1537          *
1538          * disable timer sync feature
1539          *
1540          * disable auto busoff recovery
1541          * transmit lowest buffer first
1542          *
1543          * enable tx and rx warning interrupt
1544          * enable bus off interrupt
1545          * (== FLEXCAN_CTRL_ERR_STATE)
1546          */
1547         reg_ctrl = priv->read(&regs->ctrl);
1548         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1549         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1550                 FLEXCAN_CTRL_ERR_STATE;
1551
1552         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1553          * on most Flexcan cores, too. Otherwise we don't get
1554          * any error warning or passive interrupts.
1555          */
1556         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1557             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1558                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1559         else
1560                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1561
1562         /* save for later use */
1563         priv->reg_ctrl_default = reg_ctrl;
1564         /* leave interrupts disabled for now */
1565         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1566         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1567         priv->write(reg_ctrl, &regs->ctrl);
1568
1569         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1570                 reg_ctrl2 = priv->read(&regs->ctrl2);
1571                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1572                 priv->write(reg_ctrl2, &regs->ctrl2);
1573         }
1574
1575         if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1576                 u32 reg_fdctrl;
1577
1578                 reg_fdctrl = priv->read(&regs->fdctrl);
1579                 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1580                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1581
1582                 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1583                         reg_fdctrl |=
1584                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1585                                            FLEXCAN_FDCTRL_MBDSR_64) |
1586                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1587                                            FLEXCAN_FDCTRL_MBDSR_64);
1588                 } else {
1589                         reg_fdctrl |=
1590                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1591                                            FLEXCAN_FDCTRL_MBDSR_8) |
1592                                 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1593                                            FLEXCAN_FDCTRL_MBDSR_8);
1594                 }
1595
1596                 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1597                            __func__, reg_fdctrl);
1598                 priv->write(reg_fdctrl, &regs->fdctrl);
1599         }
1600
1601         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1602                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1603                         mb = flexcan_get_mb(priv, i);
1604                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1605                                     &mb->can_ctrl);
1606                 }
1607         } else {
1608                 /* clear and invalidate unused mailboxes first */
1609                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1610                         mb = flexcan_get_mb(priv, i);
1611                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1612                                     &mb->can_ctrl);
1613                 }
1614         }
1615
1616         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1617         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1618                     &priv->tx_mb_reserved->can_ctrl);
1619
1620         /* mark TX mailbox as INACTIVE */
1621         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1622                     &priv->tx_mb->can_ctrl);
1623
1624         /* acceptance mask/acceptance code (accept everything) */
1625         priv->write(0x0, &regs->rxgmask);
1626         priv->write(0x0, &regs->rx14mask);
1627         priv->write(0x0, &regs->rx15mask);
1628
1629         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1630                 priv->write(0x0, &regs->rxfgmask);
1631
1632         /* clear acceptance filters */
1633         for (i = 0; i < priv->mb_count; i++)
1634                 priv->write(0, &regs->rximr[i]);
1635
1636         /* On Vybrid, disable non-correctable errors interrupt and
1637          * freeze mode. It still can correct the correctable errors
1638          * when HW supports ECC.
1639          *
1640          * This also works around errata e5295 which generates false
1641          * positive memory errors and put the device in freeze mode.
1642          */
1643         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1644                 /* Follow the protocol as described in "Detection
1645                  * and Correction of Memory Errors" to write to
1646                  * MECR register (step 1 - 5)
1647                  *
1648                  * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1649                  * 2. set CTRL2[ECRWRE]
1650                  */
1651                 reg_ctrl2 = priv->read(&regs->ctrl2);
1652                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1653                 priv->write(reg_ctrl2, &regs->ctrl2);
1654
1655                 /* 3. clear MECR[ECRWRDIS] */
1656                 reg_mecr = priv->read(&regs->mecr);
1657                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1658                 priv->write(reg_mecr, &regs->mecr);
1659
1660                 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1661                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1662                               FLEXCAN_MECR_FANCEI_MSK);
1663                 priv->write(reg_mecr, &regs->mecr);
1664
1665                 /* 5. after configuration done, lock MECR by either
1666                  * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1667                  */
1668                 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1669                 priv->write(reg_mecr, &regs->mecr);
1670
1671                 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1672                 priv->write(reg_ctrl2, &regs->ctrl2);
1673         }
1674
1675         /* synchronize with the can bus */
1676         err = flexcan_chip_unfreeze(priv);
1677         if (err)
1678                 goto out_chip_disable;
1679
1680         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1681
1682         /* print chip status */
1683         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1684                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1685
1686         return 0;
1687
1688  out_chip_disable:
1689         flexcan_chip_disable(priv);
1690         return err;
1691 }
1692
1693 /* __flexcan_chip_stop
1694  *
1695  * this function is entered with clocks enabled
1696  */
1697 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1698 {
1699         struct flexcan_priv *priv = netdev_priv(dev);
1700         int err;
1701
1702         /* freeze + disable module */
1703         err = flexcan_chip_freeze(priv);
1704         if (err && !disable_on_error)
1705                 return err;
1706         err = flexcan_chip_disable(priv);
1707         if (err && !disable_on_error)
1708                 goto out_chip_unfreeze;
1709
1710         priv->can.state = CAN_STATE_STOPPED;
1711
1712         return 0;
1713
1714  out_chip_unfreeze:
1715         flexcan_chip_unfreeze(priv);
1716
1717         return err;
1718 }
1719
1720 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1721 {
1722         return __flexcan_chip_stop(dev, true);
1723 }
1724
1725 static inline int flexcan_chip_stop(struct net_device *dev)
1726 {
1727         return __flexcan_chip_stop(dev, false);
1728 }
1729
1730 static int flexcan_open(struct net_device *dev)
1731 {
1732         struct flexcan_priv *priv = netdev_priv(dev);
1733         int err;
1734
1735         if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1736             (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1737                 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1738                 return -EINVAL;
1739         }
1740
1741         err = pm_runtime_get_sync(priv->dev);
1742         if (err < 0) {
1743                 pm_runtime_put_noidle(priv->dev);
1744                 return err;
1745         }
1746
1747         err = open_candev(dev);
1748         if (err)
1749                 goto out_runtime_put;
1750
1751         err = flexcan_transceiver_enable(priv);
1752         if (err)
1753                 goto out_close;
1754
1755         err = flexcan_rx_offload_setup(dev);
1756         if (err)
1757                 goto out_transceiver_disable;
1758
1759         err = flexcan_chip_start(dev);
1760         if (err)
1761                 goto out_can_rx_offload_del;
1762
1763         can_rx_offload_enable(&priv->offload);
1764
1765         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1766         if (err)
1767                 goto out_can_rx_offload_disable;
1768
1769         flexcan_chip_interrupts_enable(dev);
1770
1771         can_led_event(dev, CAN_LED_EVENT_OPEN);
1772
1773         netif_start_queue(dev);
1774
1775         return 0;
1776
1777  out_can_rx_offload_disable:
1778         can_rx_offload_disable(&priv->offload);
1779         flexcan_chip_stop(dev);
1780  out_can_rx_offload_del:
1781         can_rx_offload_del(&priv->offload);
1782  out_transceiver_disable:
1783         flexcan_transceiver_disable(priv);
1784  out_close:
1785         close_candev(dev);
1786  out_runtime_put:
1787         pm_runtime_put(priv->dev);
1788
1789         return err;
1790 }
1791
1792 static int flexcan_close(struct net_device *dev)
1793 {
1794         struct flexcan_priv *priv = netdev_priv(dev);
1795
1796         netif_stop_queue(dev);
1797         flexcan_chip_interrupts_disable(dev);
1798         free_irq(dev->irq, dev);
1799         can_rx_offload_disable(&priv->offload);
1800         flexcan_chip_stop_disable_on_error(dev);
1801
1802         can_rx_offload_del(&priv->offload);
1803         flexcan_transceiver_disable(priv);
1804         close_candev(dev);
1805
1806         pm_runtime_put(priv->dev);
1807
1808         can_led_event(dev, CAN_LED_EVENT_STOP);
1809
1810         return 0;
1811 }
1812
1813 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1814 {
1815         int err;
1816
1817         switch (mode) {
1818         case CAN_MODE_START:
1819                 err = flexcan_chip_start(dev);
1820                 if (err)
1821                         return err;
1822
1823                 flexcan_chip_interrupts_enable(dev);
1824
1825                 netif_wake_queue(dev);
1826                 break;
1827
1828         default:
1829                 return -EOPNOTSUPP;
1830         }
1831
1832         return 0;
1833 }
1834
1835 static const struct net_device_ops flexcan_netdev_ops = {
1836         .ndo_open       = flexcan_open,
1837         .ndo_stop       = flexcan_close,
1838         .ndo_start_xmit = flexcan_start_xmit,
1839         .ndo_change_mtu = can_change_mtu,
1840 };
1841
1842 static int register_flexcandev(struct net_device *dev)
1843 {
1844         struct flexcan_priv *priv = netdev_priv(dev);
1845         struct flexcan_regs __iomem *regs = priv->regs;
1846         u32 reg, err;
1847
1848         err = flexcan_clks_enable(priv);
1849         if (err)
1850                 return err;
1851
1852         /* select "bus clock", chip must be disabled */
1853         err = flexcan_chip_disable(priv);
1854         if (err)
1855                 goto out_clks_disable;
1856
1857         reg = priv->read(&regs->ctrl);
1858         if (priv->clk_src)
1859                 reg |= FLEXCAN_CTRL_CLK_SRC;
1860         else
1861                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1862         priv->write(reg, &regs->ctrl);
1863
1864         err = flexcan_chip_enable(priv);
1865         if (err)
1866                 goto out_chip_disable;
1867
1868         /* set freeze, halt and activate FIFO, restrict register access */
1869         reg = priv->read(&regs->mcr);
1870         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1871                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1872         priv->write(reg, &regs->mcr);
1873
1874         /* Currently we only support newer versions of this core
1875          * featuring a RX hardware FIFO (although this driver doesn't
1876          * make use of it on some cores). Older cores, found on some
1877          * Coldfire derivates are not tested.
1878          */
1879         reg = priv->read(&regs->mcr);
1880         if (!(reg & FLEXCAN_MCR_FEN)) {
1881                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1882                 err = -ENODEV;
1883                 goto out_chip_disable;
1884         }
1885
1886         err = register_candev(dev);
1887         if (err)
1888                 goto out_chip_disable;
1889
1890         /* Disable core and let pm_runtime_put() disable the clocks.
1891          * If CONFIG_PM is not enabled, the clocks will stay powered.
1892          */
1893         flexcan_chip_disable(priv);
1894         pm_runtime_put(priv->dev);
1895
1896         return 0;
1897
1898  out_chip_disable:
1899         flexcan_chip_disable(priv);
1900  out_clks_disable:
1901         flexcan_clks_disable(priv);
1902         return err;
1903 }
1904
1905 static void unregister_flexcandev(struct net_device *dev)
1906 {
1907         unregister_candev(dev);
1908 }
1909
1910 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1911 {
1912         struct net_device *dev = platform_get_drvdata(pdev);
1913         struct device_node *np = pdev->dev.of_node;
1914         struct device_node *gpr_np;
1915         struct flexcan_priv *priv;
1916         phandle phandle;
1917         u32 out_val[3];
1918         int ret;
1919
1920         if (!np)
1921                 return -EINVAL;
1922
1923         /* stop mode property format is:
1924          * <&gpr req_gpr req_bit>.
1925          */
1926         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1927                                          ARRAY_SIZE(out_val));
1928         if (ret) {
1929                 dev_dbg(&pdev->dev, "no stop-mode property\n");
1930                 return ret;
1931         }
1932         phandle = *out_val;
1933
1934         gpr_np = of_find_node_by_phandle(phandle);
1935         if (!gpr_np) {
1936                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1937                 return -ENODEV;
1938         }
1939
1940         priv = netdev_priv(dev);
1941         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1942         if (IS_ERR(priv->stm.gpr)) {
1943                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1944                 ret = PTR_ERR(priv->stm.gpr);
1945                 goto out_put_node;
1946         }
1947
1948         priv->stm.req_gpr = out_val[1];
1949         priv->stm.req_bit = out_val[2];
1950
1951         dev_dbg(&pdev->dev,
1952                 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1953                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1954
1955         return 0;
1956
1957 out_put_node:
1958         of_node_put(gpr_np);
1959         return ret;
1960 }
1961
1962 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1963 {
1964         struct net_device *dev = platform_get_drvdata(pdev);
1965         struct flexcan_priv *priv;
1966         u8 scu_idx;
1967         int ret;
1968
1969         ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1970         if (ret < 0) {
1971                 dev_dbg(&pdev->dev, "failed to get scu index\n");
1972                 return ret;
1973         }
1974
1975         priv = netdev_priv(dev);
1976         priv->scu_idx = scu_idx;
1977
1978         /* this function could be deferred probe, return -EPROBE_DEFER */
1979         return imx_scu_get_handle(&priv->sc_ipc_handle);
1980 }
1981
1982 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1983  *
1984  * Return: = 0 setup stop mode successfully or doesn't support this feature
1985  *         < 0 fail to setup stop mode (could be deferred probe)
1986  */
1987 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1988 {
1989         struct net_device *dev = platform_get_drvdata(pdev);
1990         struct flexcan_priv *priv;
1991         int ret;
1992
1993         priv = netdev_priv(dev);
1994
1995         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1996                 ret = flexcan_setup_stop_mode_scfw(pdev);
1997         else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1998                 ret = flexcan_setup_stop_mode_gpr(pdev);
1999         else
2000                 /* return 0 directly if doesn't support stop mode feature */
2001                 return 0;
2002
2003         if (ret)
2004                 return ret;
2005
2006         device_set_wakeup_capable(&pdev->dev, true);
2007
2008         if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2009                 device_set_wakeup_enable(&pdev->dev, true);
2010
2011         return 0;
2012 }
2013
2014 static const struct of_device_id flexcan_of_match[] = {
2015         { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2016         { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2017         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2018         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2019         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2020         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2021         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2022         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2023         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2024         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2025         { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2026         { /* sentinel */ },
2027 };
2028 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2029
2030 static int flexcan_probe(struct platform_device *pdev)
2031 {
2032         const struct flexcan_devtype_data *devtype_data;
2033         struct net_device *dev;
2034         struct flexcan_priv *priv;
2035         struct regulator *reg_xceiver;
2036         struct clk *clk_ipg = NULL, *clk_per = NULL;
2037         struct flexcan_regs __iomem *regs;
2038         int err, irq;
2039         u8 clk_src = 1;
2040         u32 clock_freq = 0;
2041
2042         reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2043         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2044                 return -EPROBE_DEFER;
2045         else if (PTR_ERR(reg_xceiver) == -ENODEV)
2046                 reg_xceiver = NULL;
2047         else if (IS_ERR(reg_xceiver))
2048                 return PTR_ERR(reg_xceiver);
2049
2050         if (pdev->dev.of_node) {
2051                 of_property_read_u32(pdev->dev.of_node,
2052                                      "clock-frequency", &clock_freq);
2053                 of_property_read_u8(pdev->dev.of_node,
2054                                     "fsl,clk-source", &clk_src);
2055         }
2056
2057         if (!clock_freq) {
2058                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2059                 if (IS_ERR(clk_ipg)) {
2060                         dev_err(&pdev->dev, "no ipg clock defined\n");
2061                         return PTR_ERR(clk_ipg);
2062                 }
2063
2064                 clk_per = devm_clk_get(&pdev->dev, "per");
2065                 if (IS_ERR(clk_per)) {
2066                         dev_err(&pdev->dev, "no per clock defined\n");
2067                         return PTR_ERR(clk_per);
2068                 }
2069                 clock_freq = clk_get_rate(clk_per);
2070         }
2071
2072         irq = platform_get_irq(pdev, 0);
2073         if (irq <= 0)
2074                 return -ENODEV;
2075
2076         regs = devm_platform_ioremap_resource(pdev, 0);
2077         if (IS_ERR(regs))
2078                 return PTR_ERR(regs);
2079
2080         devtype_data = of_device_get_match_data(&pdev->dev);
2081
2082         if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2083             !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
2084                 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
2085                 return -EINVAL;
2086         }
2087
2088         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2089         if (!dev)
2090                 return -ENOMEM;
2091
2092         platform_set_drvdata(pdev, dev);
2093         SET_NETDEV_DEV(dev, &pdev->dev);
2094
2095         dev->netdev_ops = &flexcan_netdev_ops;
2096         dev->irq = irq;
2097         dev->flags |= IFF_ECHO;
2098
2099         priv = netdev_priv(dev);
2100
2101         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2102             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2103                 priv->read = flexcan_read_be;
2104                 priv->write = flexcan_write_be;
2105         } else {
2106                 priv->read = flexcan_read_le;
2107                 priv->write = flexcan_write_le;
2108         }
2109
2110         priv->dev = &pdev->dev;
2111         priv->can.clock.freq = clock_freq;
2112         priv->can.do_set_mode = flexcan_set_mode;
2113         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2114         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2115                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2116                 CAN_CTRLMODE_BERR_REPORTING;
2117         priv->regs = regs;
2118         priv->clk_ipg = clk_ipg;
2119         priv->clk_per = clk_per;
2120         priv->clk_src = clk_src;
2121         priv->devtype_data = devtype_data;
2122         priv->reg_xceiver = reg_xceiver;
2123
2124         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2125                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2126                         CAN_CTRLMODE_FD_NON_ISO;
2127                 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2128                 priv->can.data_bittiming_const =
2129                         &flexcan_fd_data_bittiming_const;
2130         } else {
2131                 priv->can.bittiming_const = &flexcan_bittiming_const;
2132         }
2133
2134         pm_runtime_get_noresume(&pdev->dev);
2135         pm_runtime_set_active(&pdev->dev);
2136         pm_runtime_enable(&pdev->dev);
2137
2138         err = register_flexcandev(dev);
2139         if (err) {
2140                 dev_err(&pdev->dev, "registering netdev failed\n");
2141                 goto failed_register;
2142         }
2143
2144         err = flexcan_setup_stop_mode(pdev);
2145         if (err < 0) {
2146                 if (err != -EPROBE_DEFER)
2147                         dev_err(&pdev->dev, "setup stop mode failed\n");
2148                 goto failed_setup_stop_mode;
2149         }
2150
2151         of_can_transceiver(dev);
2152         devm_can_led_init(dev);
2153
2154         return 0;
2155
2156  failed_setup_stop_mode:
2157         unregister_flexcandev(dev);
2158  failed_register:
2159         pm_runtime_put_noidle(&pdev->dev);
2160         pm_runtime_disable(&pdev->dev);
2161         free_candev(dev);
2162         return err;
2163 }
2164
2165 static int flexcan_remove(struct platform_device *pdev)
2166 {
2167         struct net_device *dev = platform_get_drvdata(pdev);
2168
2169         device_set_wakeup_enable(&pdev->dev, false);
2170         device_set_wakeup_capable(&pdev->dev, false);
2171         unregister_flexcandev(dev);
2172         pm_runtime_disable(&pdev->dev);
2173         free_candev(dev);
2174
2175         return 0;
2176 }
2177
2178 static int __maybe_unused flexcan_suspend(struct device *device)
2179 {
2180         struct net_device *dev = dev_get_drvdata(device);
2181         struct flexcan_priv *priv = netdev_priv(dev);
2182         int err;
2183
2184         if (netif_running(dev)) {
2185                 /* if wakeup is enabled, enter stop mode
2186                  * else enter disabled mode.
2187                  */
2188                 if (device_may_wakeup(device)) {
2189                         enable_irq_wake(dev->irq);
2190                         err = flexcan_enter_stop_mode(priv);
2191                         if (err)
2192                                 return err;
2193                 } else {
2194                         err = flexcan_chip_stop(dev);
2195                         if (err)
2196                                 return err;
2197
2198                         flexcan_chip_interrupts_disable(dev);
2199
2200                         err = pinctrl_pm_select_sleep_state(device);
2201                         if (err)
2202                                 return err;
2203                 }
2204                 netif_stop_queue(dev);
2205                 netif_device_detach(dev);
2206         }
2207         priv->can.state = CAN_STATE_SLEEPING;
2208
2209         return 0;
2210 }
2211
2212 static int __maybe_unused flexcan_resume(struct device *device)
2213 {
2214         struct net_device *dev = dev_get_drvdata(device);
2215         struct flexcan_priv *priv = netdev_priv(dev);
2216         int err;
2217
2218         priv->can.state = CAN_STATE_ERROR_ACTIVE;
2219         if (netif_running(dev)) {
2220                 netif_device_attach(dev);
2221                 netif_start_queue(dev);
2222                 if (device_may_wakeup(device)) {
2223                         disable_irq_wake(dev->irq);
2224                         err = flexcan_exit_stop_mode(priv);
2225                         if (err)
2226                                 return err;
2227                 } else {
2228                         err = pinctrl_pm_select_default_state(device);
2229                         if (err)
2230                                 return err;
2231
2232                         err = flexcan_chip_start(dev);
2233                         if (err)
2234                                 return err;
2235
2236                         flexcan_chip_interrupts_enable(dev);
2237                 }
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2244 {
2245         struct net_device *dev = dev_get_drvdata(device);
2246         struct flexcan_priv *priv = netdev_priv(dev);
2247
2248         flexcan_clks_disable(priv);
2249
2250         return 0;
2251 }
2252
2253 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2254 {
2255         struct net_device *dev = dev_get_drvdata(device);
2256         struct flexcan_priv *priv = netdev_priv(dev);
2257
2258         return flexcan_clks_enable(priv);
2259 }
2260
2261 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2262 {
2263         struct net_device *dev = dev_get_drvdata(device);
2264         struct flexcan_priv *priv = netdev_priv(dev);
2265
2266         if (netif_running(dev)) {
2267                 int err;
2268
2269                 if (device_may_wakeup(device))
2270                         flexcan_enable_wakeup_irq(priv, true);
2271
2272                 err = pm_runtime_force_suspend(device);
2273                 if (err)
2274                         return err;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2281 {
2282         struct net_device *dev = dev_get_drvdata(device);
2283         struct flexcan_priv *priv = netdev_priv(dev);
2284
2285         if (netif_running(dev)) {
2286                 int err;
2287
2288                 err = pm_runtime_force_resume(device);
2289                 if (err)
2290                         return err;
2291
2292                 if (device_may_wakeup(device))
2293                         flexcan_enable_wakeup_irq(priv, false);
2294         }
2295
2296         return 0;
2297 }
2298
2299 static const struct dev_pm_ops flexcan_pm_ops = {
2300         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2301         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2302         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2303 };
2304
2305 static struct platform_driver flexcan_driver = {
2306         .driver = {
2307                 .name = DRV_NAME,
2308                 .pm = &flexcan_pm_ops,
2309                 .of_match_table = flexcan_of_match,
2310         },
2311         .probe = flexcan_probe,
2312         .remove = flexcan_remove,
2313 };
2314
2315 module_platform_driver(flexcan_driver);
2316
2317 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2318               "Marc Kleine-Budde <kernel@pengutronix.de>");
2319 MODULE_LICENSE("GPL v2");
2320 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");