drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/can.h>
  14 #include <linux/can/dev.h>
  15 #include <linux/can/error.h>
  16 #include <linux/can/led.h>
  17 #include <linux/can/rx-offload.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regulator/consumer.h>
  27
  28 #define DRV_NAME                        "flexcan"
  29
  30 /* 8 for RX fifo and 2 error handling */
  31 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  32
  33 /* FLEXCAN module configuration register (CANMCR) bits */
  34 #define FLEXCAN_MCR_MDIS                BIT(31)
  35 #define FLEXCAN_MCR_FRZ                 BIT(30)
  36 #define FLEXCAN_MCR_FEN                 BIT(29)
  37 #define FLEXCAN_MCR_HALT                BIT(28)
  38 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  39 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  40 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  41 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  42 #define FLEXCAN_MCR_SUPV                BIT(23)
  43 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  44 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  45 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  46 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  47 #define FLEXCAN_MCR_DOZE                BIT(18)
  48 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  49 #define FLEXCAN_MCR_IRMQ                BIT(16)
  50 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  51 #define FLEXCAN_MCR_AEN                 BIT(12)
  52 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  53 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  54 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  55 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  56 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  57 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  58
  59 /* FLEXCAN control register (CANCTRL) bits */
  60 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  61 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  62 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  63 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  64 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  65 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  66 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  67 #define FLEXCAN_CTRL_LPB                BIT(12)
  68 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  69 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  70 #define FLEXCAN_CTRL_SMP                BIT(7)
  71 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  72 #define FLEXCAN_CTRL_TSYN               BIT(5)
  73 #define FLEXCAN_CTRL_LBUF               BIT(4)
  74 #define FLEXCAN_CTRL_LOM                BIT(3)
  75 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  76 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  77 #define FLEXCAN_CTRL_ERR_STATE \
  78         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  79          FLEXCAN_CTRL_BOFF_MSK)
  80 #define FLEXCAN_CTRL_ERR_ALL \
  81         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  82
  83 /* FLEXCAN control register 2 (CTRL2) bits */
  84 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  85 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  86 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  87 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  88 #define FLEXCAN_CTRL2_MRP               BIT(18)
  89 #define FLEXCAN_CTRL2_RRS               BIT(17)
  90 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  91
  92 /* FLEXCAN memory error control register (MECR) bits */
  93 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  94 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  95 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  96 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
  97 #define FLEXCAN_MECR_HAERRIE            BIT(15)
  98 #define FLEXCAN_MECR_FAERRIE            BIT(14)
  99 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 100 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 101 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 102 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 103
 104 /* FLEXCAN error and status register (ESR) bits */
 105 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 106 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 107 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 108 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 109 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 110 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 111 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 112 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 113 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 114 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 115 #define FLEXCAN_ESR_IDLE                BIT(7)
 116 #define FLEXCAN_ESR_TXRX                BIT(6)
 117 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 118 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 119 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 120 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 121 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 122 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 123 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 124 #define FLEXCAN_ESR_ERR_BUS \
 125         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 126          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 127          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 128 #define FLEXCAN_ESR_ERR_STATE \
 129         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 130 #define FLEXCAN_ESR_ERR_ALL \
 131         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 132 #define FLEXCAN_ESR_ALL_INT \
 133         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 134          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 135
 136 /* FLEXCAN interrupt flag register (IFLAG) bits */
 137 /* Errata ERR005829 step7: Reserve first valid MB */
 138 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
 139 #define FLEXCAN_TX_MB_OFF_FIFO          9
 140 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 141 #define FLEXCAN_TX_MB_OFF_TIMESTAMP             1
 142 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
 143 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST        63
 144 #define FLEXCAN_IFLAG_MB(x)             BIT(x)
 145 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 146 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 147 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 148
 149 /* FLEXCAN message buffers */
 150 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 151 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 152 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 153 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 154 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 155 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 156 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 157
 158 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 159 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 160 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 161 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 162
 163 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 164 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 165 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 166 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 167 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 168
 169 #define FLEXCAN_TIMEOUT_US              (50)
 170
 171 /* FLEXCAN hardware feature flags
 172  *
 173  * Below is some version info we got:
 174  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 175  *                                Filter? connected?  Passive detection  ception in MB
 176  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 177  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 178  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 179  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 180  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 181  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 182  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 183  *
 184  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 185  */
 186 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 187 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 188 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 189 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 190 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 191 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 192 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 193
 194 /* Structure of the message buffer */
 195 struct flexcan_mb {
 196         u32 can_ctrl;
 197         u32 can_id;
 198         u32 data[2];
 199 };
 200
 201 /* Structure of the hardware registers */
 202 struct flexcan_regs {
 203         u32 mcr;                /* 0x00 */
 204         u32 ctrl;               /* 0x04 */
 205         u32 timer;              /* 0x08 */
 206         u32 _reserved1;         /* 0x0c */
 207         u32 rxgmask;            /* 0x10 */
 208         u32 rx14mask;           /* 0x14 */
 209         u32 rx15mask;           /* 0x18 */
 210         u32 ecr;                /* 0x1c */
 211         u32 esr;                /* 0x20 */
 212         u32 imask2;             /* 0x24 */
 213         u32 imask1;             /* 0x28 */
 214         u32 iflag2;             /* 0x2c */
 215         u32 iflag1;             /* 0x30 */
 216         union {                 /* 0x34 */
 217                 u32 gfwr_mx28;  /* MX28, MX53 */
 218                 u32 ctrl2;      /* MX6, VF610 */
 219         };
 220         u32 esr2;               /* 0x38 */
 221         u32 imeur;              /* 0x3c */
 222         u32 lrfr;               /* 0x40 */
 223         u32 crcr;               /* 0x44 */
 224         u32 rxfgmask;           /* 0x48 */
 225         u32 rxfir;              /* 0x4c */
 226         u32 _reserved3[12];     /* 0x50 */
 227         struct flexcan_mb mb[64];       /* 0x80 */
 228         /* FIFO-mode:
 229          *                      MB
 230          * 0x080...0x08f        0       RX message buffer
 231          * 0x090...0x0df        1-5     reserverd
 232          * 0x0e0...0x0ff        6-7     8 entry ID table
 233          *                              (mx25, mx28, mx35, mx53)
 234          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 235          *                              size conf'ed via ctrl2::RFFN
 236          *                              (mx6, vf610)
 237          */
 238         u32 _reserved4[256];    /* 0x480 */
 239         u32 rximr[64];          /* 0x880 */
 240         u32 _reserved5[24];     /* 0x980 */
 241         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 242         u32 _reserved6[63];     /* 0x9e4 */
 243         u32 mecr;               /* 0xae0 */
 244         u32 erriar;             /* 0xae4 */
 245         u32 erridpr;            /* 0xae8 */
 246         u32 errippr;            /* 0xaec */
 247         u32 rerrar;             /* 0xaf0 */
 248         u32 rerrdr;             /* 0xaf4 */
 249         u32 rerrsynr;           /* 0xaf8 */
 250         u32 errsr;              /* 0xafc */
 251 };
 252
 253 struct flexcan_devtype_data {
 254         u32 quirks;             /* quirks needed for different IP cores */
 255 };
 256
 257 struct flexcan_priv {
 258         struct can_priv can;
 259         struct can_rx_offload offload;
 260
 261         struct flexcan_regs __iomem *regs;
 262         struct flexcan_mb __iomem *tx_mb;
 263         struct flexcan_mb __iomem *tx_mb_reserved;
 264         u8 tx_mb_idx;
 265         u32 reg_ctrl_default;
 266         u32 reg_imask1_default;
 267         u32 reg_imask2_default;
 268
 269         struct clk *clk_ipg;
 270         struct clk *clk_per;
 271         const struct flexcan_devtype_data *devtype_data;
 272         struct regulator *reg_xceiver;
 273
 274         /* Read and Write APIs */
 275         u32 (*read)(void __iomem *addr);
 276         void (*write)(u32 val, void __iomem *addr);
 277 };
 278
 279 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 280         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 281                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 282                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 283 };
 284
 285 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 286         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 287                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 288 };
 289
 290 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 291         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 292 };
 293
 294 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 295         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 296                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 297 };
 298
 299 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 300         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 301                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 302                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 303 };
 304
 305 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 306         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 307                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 308                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 309 };
 310
 311 static const struct can_bittiming_const flexcan_bittiming_const = {
 312         .name = DRV_NAME,
 313         .tseg1_min = 4,
 314         .tseg1_max = 16,
 315         .tseg2_min = 2,
 316         .tseg2_max = 8,
 317         .sjw_max = 4,
 318         .brp_min = 1,
 319         .brp_max = 256,
 320         .brp_inc = 1,
 321 };
 322
 323 /* FlexCAN module is essentially modelled as a little-endian IP in most
 324  * SoCs, i.e the registers as well as the message buffer areas are
 325  * implemented in a little-endian fashion.
 326  *
 327  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 328  * module in a big-endian fashion (i.e the registers as well as the
 329  * message buffer areas are implemented in a big-endian way).
 330  *
 331  * In addition, the FlexCAN module can be found on SoCs having ARM or
 332  * PPC cores. So, we need to abstract off the register read/write
 333  * functions, ensuring that these cater to all the combinations of module
 334  * endianness and underlying CPU endianness.
 335  */
 336 static inline u32 flexcan_read_be(void __iomem *addr)
 337 {
 338         return ioread32be(addr);
 339 }
 340
 341 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 342 {
 343         iowrite32be(val, addr);
 344 }
 345
 346 static inline u32 flexcan_read_le(void __iomem *addr)
 347 {
 348         return ioread32(addr);
 349 }
 350
 351 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 352 {
 353         iowrite32(val, addr);
 354 }
 355
 356 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 357 {
 358         struct flexcan_regs __iomem *regs = priv->regs;
 359         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 360
 361         priv->write(reg_ctrl, &regs->ctrl);
 362 }
 363
 364 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 365 {
 366         struct flexcan_regs __iomem *regs = priv->regs;
 367         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 368
 369         priv->write(reg_ctrl, &regs->ctrl);
 370 }
 371
 372 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 373 {
 374         if (!priv->reg_xceiver)
 375                 return 0;
 376
 377         return regulator_enable(priv->reg_xceiver);
 378 }
 379
 380 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 381 {
 382         if (!priv->reg_xceiver)
 383                 return 0;
 384
 385         return regulator_disable(priv->reg_xceiver);
 386 }
 387
 388 static int flexcan_chip_enable(struct flexcan_priv *priv)
 389 {
 390         struct flexcan_regs __iomem *regs = priv->regs;
 391         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 392         u32 reg;
 393
 394         reg = priv->read(&regs->mcr);
 395         reg &= ~FLEXCAN_MCR_MDIS;
 396         priv->write(reg, &regs->mcr);
 397
 398         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 399                 udelay(10);
 400
 401         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 402                 return -ETIMEDOUT;
 403
 404         return 0;
 405 }
 406
 407 static int flexcan_chip_disable(struct flexcan_priv *priv)
 408 {
 409         struct flexcan_regs __iomem *regs = priv->regs;
 410         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 411         u32 reg;
 412
 413         reg = priv->read(&regs->mcr);
 414         reg |= FLEXCAN_MCR_MDIS;
 415         priv->write(reg, &regs->mcr);
 416
 417         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 418                 udelay(10);
 419
 420         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 421                 return -ETIMEDOUT;
 422
 423         return 0;
 424 }
 425
 426 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 427 {
 428         struct flexcan_regs __iomem *regs = priv->regs;
 429         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 430         u32 reg;
 431
 432         reg = priv->read(&regs->mcr);
 433         reg |= FLEXCAN_MCR_HALT;
 434         priv->write(reg, &regs->mcr);
 435
 436         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 437                 udelay(100);
 438
 439         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 440                 return -ETIMEDOUT;
 441
 442         return 0;
 443 }
 444
 445 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 446 {
 447         struct flexcan_regs __iomem *regs = priv->regs;
 448         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 449         u32 reg;
 450
 451         reg = priv->read(&regs->mcr);
 452         reg &= ~FLEXCAN_MCR_HALT;
 453         priv->write(reg, &regs->mcr);
 454
 455         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 456                 udelay(10);
 457
 458         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 459                 return -ETIMEDOUT;
 460
 461         return 0;
 462 }
 463
 464 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 465 {
 466         struct flexcan_regs __iomem *regs = priv->regs;
 467         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 468
 469         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 470         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 471                 udelay(10);
 472
 473         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 474                 return -ETIMEDOUT;
 475
 476         return 0;
 477 }
 478
 479 static int __flexcan_get_berr_counter(const struct net_device *dev,
 480                                       struct can_berr_counter *bec)
 481 {
 482         const struct flexcan_priv *priv = netdev_priv(dev);
 483         struct flexcan_regs __iomem *regs = priv->regs;
 484         u32 reg = priv->read(&regs->ecr);
 485
 486         bec->txerr = (reg >> 0) & 0xff;
 487         bec->rxerr = (reg >> 8) & 0xff;
 488
 489         return 0;
 490 }
 491
 492 static int flexcan_get_berr_counter(const struct net_device *dev,
 493                                     struct can_berr_counter *bec)
 494 {
 495         const struct flexcan_priv *priv = netdev_priv(dev);
 496         int err;
 497
 498         err = clk_prepare_enable(priv->clk_ipg);
 499         if (err)
 500                 return err;
 501
 502         err = clk_prepare_enable(priv->clk_per);
 503         if (err)
 504                 goto out_disable_ipg;
 505
 506         err = __flexcan_get_berr_counter(dev, bec);
 507
 508         clk_disable_unprepare(priv->clk_per);
 509  out_disable_ipg:
 510         clk_disable_unprepare(priv->clk_ipg);
 511
 512         return err;
 513 }
 514
 515 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 516 {
 517         const struct flexcan_priv *priv = netdev_priv(dev);
 518         struct can_frame *cf = (struct can_frame *)skb->data;
 519         u32 can_id;
 520         u32 data;
 521         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 522
 523         if (can_dropped_invalid_skb(dev, skb))
 524                 return NETDEV_TX_OK;
 525
 526         netif_stop_queue(dev);
 527
 528         if (cf->can_id & CAN_EFF_FLAG) {
 529                 can_id = cf->can_id & CAN_EFF_MASK;
 530                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 531         } else {
 532                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 533         }
 534
 535         if (cf->can_id & CAN_RTR_FLAG)
 536                 ctrl |= FLEXCAN_MB_CNT_RTR;
 537
 538         if (cf->can_dlc > 0) {
 539                 data = be32_to_cpup((__be32 *)&cf->data[0]);
 540                 priv->write(data, &priv->tx_mb->data[0]);
 541         }
 542         if (cf->can_dlc > 4) {
 543                 data = be32_to_cpup((__be32 *)&cf->data[4]);
 544                 priv->write(data, &priv->tx_mb->data[1]);
 545         }
 546
 547         can_put_echo_skb(skb, dev, 0);
 548
 549         priv->write(can_id, &priv->tx_mb->can_id);
 550         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 551
 552         /* Errata ERR005829 step8:
 553          * Write twice INACTIVE(0x8) code to first MB.
 554          */
 555         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 556                       &priv->tx_mb_reserved->can_ctrl);
 557         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 558                       &priv->tx_mb_reserved->can_ctrl);
 559
 560         return NETDEV_TX_OK;
 561 }
 562
 563 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 564 {
 565         struct flexcan_priv *priv = netdev_priv(dev);
 566         struct sk_buff *skb;
 567         struct can_frame *cf;
 568         bool rx_errors = false, tx_errors = false;
 569
 570         skb = alloc_can_err_skb(dev, &cf);
 571         if (unlikely(!skb))
 572                 return;
 573
 574         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 575
 576         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 577                 netdev_dbg(dev, "BIT1_ERR irq\n");
 578                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 579                 tx_errors = true;
 580         }
 581         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 582                 netdev_dbg(dev, "BIT0_ERR irq\n");
 583                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 584                 tx_errors = true;
 585         }
 586         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 587                 netdev_dbg(dev, "ACK_ERR irq\n");
 588                 cf->can_id |= CAN_ERR_ACK;
 589                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 590                 tx_errors = true;
 591         }
 592         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 593                 netdev_dbg(dev, "CRC_ERR irq\n");
 594                 cf->data[2] |= CAN_ERR_PROT_BIT;
 595                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 596                 rx_errors = true;
 597         }
 598         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 599                 netdev_dbg(dev, "FRM_ERR irq\n");
 600                 cf->data[2] |= CAN_ERR_PROT_FORM;
 601                 rx_errors = true;
 602         }
 603         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 604                 netdev_dbg(dev, "STF_ERR irq\n");
 605                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 606                 rx_errors = true;
 607         }
 608
 609         priv->can.can_stats.bus_error++;
 610         if (rx_errors)
 611                 dev->stats.rx_errors++;
 612         if (tx_errors)
 613                 dev->stats.tx_errors++;
 614
 615         can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
 616 }
 617
 618 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 619 {
 620         struct flexcan_priv *priv = netdev_priv(dev);
 621         struct sk_buff *skb;
 622         struct can_frame *cf;
 623         enum can_state new_state, rx_state, tx_state;
 624         int flt;
 625         struct can_berr_counter bec;
 626
 627         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 628         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 629                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 630                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 631                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 632                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 633                 new_state = max(tx_state, rx_state);
 634         } else {
 635                 __flexcan_get_berr_counter(dev, &bec);
 636                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 637                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 638                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 639                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 640         }
 641
 642         /* state hasn't changed */
 643         if (likely(new_state == priv->can.state))
 644                 return;
 645
 646         skb = alloc_can_err_skb(dev, &cf);
 647         if (unlikely(!skb))
 648                 return;
 649
 650         can_change_state(dev, cf, tx_state, rx_state);
 651
 652         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 653                 can_bus_off(dev);
 654
 655         can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
 656 }
 657
 658 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 659 {
 660         return container_of(offload, struct flexcan_priv, offload);
 661 }
 662
 663 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 664                                          struct can_frame *cf,
 665                                          u32 *timestamp, unsigned int n)
 666 {
 667         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 668         struct flexcan_regs __iomem *regs = priv->regs;
 669         struct flexcan_mb __iomem *mb = &regs->mb[n];
 670         u32 reg_ctrl, reg_id, reg_iflag1;
 671
 672         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 673                 u32 code;
 674
 675                 do {
 676                         reg_ctrl = priv->read(&mb->can_ctrl);
 677                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 678
 679                 /* is this MB empty? */
 680                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 681                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 682                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 683                         return 0;
 684
 685                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 686                         /* This MB was overrun, we lost data */
 687                         offload->dev->stats.rx_over_errors++;
 688                         offload->dev->stats.rx_errors++;
 689                 }
 690         } else {
 691                 reg_iflag1 = priv->read(&regs->iflag1);
 692                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 693                         return 0;
 694
 695                 reg_ctrl = priv->read(&mb->can_ctrl);
 696         }
 697
 698         /* increase timstamp to full 32 bit */
 699         *timestamp = reg_ctrl << 16;
 700
 701         reg_id = priv->read(&mb->can_id);
 702         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 703                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 704         else
 705                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 706
 707         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 708                 cf->can_id |= CAN_RTR_FLAG;
 709         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 710
 711         *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
 712         *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 713
 714         /* mark as read */
 715         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 716                 /* Clear IRQ */
 717                 if (n < 32)
 718                         priv->write(BIT(n), &regs->iflag1);
 719                 else
 720                         priv->write(BIT(n - 32), &regs->iflag2);
 721         } else {
 722                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 723                 priv->read(&regs->timer);
 724         }
 725
 726         return 1;
 727 }
 728
 729
 730 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 731 {
 732         struct flexcan_regs __iomem *regs = priv->regs;
 733         u32 iflag1, iflag2;
 734
 735         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default;
 736         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default &
 737                 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 738
 739         return (u64)iflag2 << 32 | iflag1;
 740 }
 741
 742 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 743 {
 744         struct net_device *dev = dev_id;
 745         struct net_device_stats *stats = &dev->stats;
 746         struct flexcan_priv *priv = netdev_priv(dev);
 747         struct flexcan_regs __iomem *regs = priv->regs;
 748         irqreturn_t handled = IRQ_NONE;
 749         u32 reg_iflag1, reg_esr;
 750         enum can_state last_state = priv->can.state;
 751
 752         reg_iflag1 = priv->read(&regs->iflag1);
 753
 754         /* reception interrupt */
 755         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 756                 u64 reg_iflag;
 757                 int ret;
 758
 759                 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 760                         handled = IRQ_HANDLED;
 761                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 762                                                                    reg_iflag);
 763                         if (!ret)
 764                                 break;
 765                 }
 766         } else {
 767                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 768                         handled = IRQ_HANDLED;
 769                         can_rx_offload_irq_offload_fifo(&priv->offload);
 770                 }
 771
 772                 /* FIFO overflow interrupt */
 773                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 774                         handled = IRQ_HANDLED;
 775                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 776                                     &regs->iflag1);
 777                         dev->stats.rx_over_errors++;
 778                         dev->stats.rx_errors++;
 779                 }
 780         }
 781
 782         /* transmission complete interrupt */
 783         if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
 784                 handled = IRQ_HANDLED;
 785                 stats->tx_bytes += can_get_echo_skb(dev, 0);
 786                 stats->tx_packets++;
 787                 can_led_event(dev, CAN_LED_EVENT_TX);
 788
 789                 /* after sending a RTR frame MB is in RX mode */
 790                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 791                             &priv->tx_mb->can_ctrl);
 792                 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
 793                 netif_wake_queue(dev);
 794         }
 795
 796         reg_esr = priv->read(&regs->esr);
 797
 798         /* ACK all bus error and state change IRQ sources */
 799         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 800                 handled = IRQ_HANDLED;
 801                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 802         }
 803
 804         /* state change interrupt or broken error state quirk fix is enabled */
 805         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 806             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 807                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 808                 flexcan_irq_state(dev, reg_esr);
 809
 810         /* bus error IRQ - handle if bus error reporting is activated */
 811         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 812             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 813                 flexcan_irq_bus_err(dev, reg_esr);
 814
 815         /* availability of error interrupt among state transitions in case
 816          * bus error reporting is de-activated and
 817          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 818          *  +--------------------------------------------------------------+
 819          *  | +----------------------------------------------+ [stopped /  |
 820          *  | |                                              |  sleeping] -+
 821          *  +-+-> active <-> warning <-> passive -> bus off -+
 822          *        ___________^^^^^^^^^^^^_______________________________
 823          *        disabled(1)  enabled             disabled
 824          *
 825          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 826          */
 827         if ((last_state != priv->can.state) &&
 828             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 829             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 830                 switch (priv->can.state) {
 831                 case CAN_STATE_ERROR_ACTIVE:
 832                         if (priv->devtype_data->quirks &
 833                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 834                                 flexcan_error_irq_enable(priv);
 835                         else
 836                                 flexcan_error_irq_disable(priv);
 837                         break;
 838
 839                 case CAN_STATE_ERROR_WARNING:
 840                         flexcan_error_irq_enable(priv);
 841                         break;
 842
 843                 case CAN_STATE_ERROR_PASSIVE:
 844                 case CAN_STATE_BUS_OFF:
 845                         flexcan_error_irq_disable(priv);
 846                         break;
 847
 848                 default:
 849                         break;
 850                 }
 851         }
 852
 853         return handled;
 854 }
 855
 856 static void flexcan_set_bittiming(struct net_device *dev)
 857 {
 858         const struct flexcan_priv *priv = netdev_priv(dev);
 859         const struct can_bittiming *bt = &priv->can.bittiming;
 860         struct flexcan_regs __iomem *regs = priv->regs;
 861         u32 reg;
 862
 863         reg = priv->read(&regs->ctrl);
 864         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 865                  FLEXCAN_CTRL_RJW(0x3) |
 866                  FLEXCAN_CTRL_PSEG1(0x7) |
 867                  FLEXCAN_CTRL_PSEG2(0x7) |
 868                  FLEXCAN_CTRL_PROPSEG(0x7) |
 869                  FLEXCAN_CTRL_LPB |
 870                  FLEXCAN_CTRL_SMP |
 871                  FLEXCAN_CTRL_LOM);
 872
 873         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 874                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 875                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 876                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 877                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 878
 879         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 880                 reg |= FLEXCAN_CTRL_LPB;
 881         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 882                 reg |= FLEXCAN_CTRL_LOM;
 883         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 884                 reg |= FLEXCAN_CTRL_SMP;
 885
 886         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
 887         priv->write(reg, &regs->ctrl);
 888
 889         /* print chip status */
 890         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 891                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
 892 }
 893
 894 /* flexcan_chip_start
 895  *
 896  * this functions is entered with clocks enabled
 897  *
 898  */
 899 static int flexcan_chip_start(struct net_device *dev)
 900 {
 901         struct flexcan_priv *priv = netdev_priv(dev);
 902         struct flexcan_regs __iomem *regs = priv->regs;
 903         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
 904         int err, i;
 905
 906         /* enable module */
 907         err = flexcan_chip_enable(priv);
 908         if (err)
 909                 return err;
 910
 911         /* soft reset */
 912         err = flexcan_chip_softreset(priv);
 913         if (err)
 914                 goto out_chip_disable;
 915
 916         flexcan_set_bittiming(dev);
 917
 918         /* MCR
 919          *
 920          * enable freeze
 921          * enable fifo
 922          * halt now
 923          * only supervisor access
 924          * enable warning int
 925          * disable local echo
 926          * enable individual RX masking
 927          * choose format C
 928          * set max mailbox number
 929          */
 930         reg_mcr = priv->read(&regs->mcr);
 931         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 932         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
 933                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
 934                 FLEXCAN_MCR_IDAM_C;
 935
 936         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 937                 reg_mcr &= ~FLEXCAN_MCR_FEN;
 938                 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
 939         } else {
 940                 reg_mcr |= FLEXCAN_MCR_FEN |
 941                         FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
 942         }
 943         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 944         priv->write(reg_mcr, &regs->mcr);
 945
 946         /* CTRL
 947          *
 948          * disable timer sync feature
 949          *
 950          * disable auto busoff recovery
 951          * transmit lowest buffer first
 952          *
 953          * enable tx and rx warning interrupt
 954          * enable bus off interrupt
 955          * (== FLEXCAN_CTRL_ERR_STATE)
 956          */
 957         reg_ctrl = priv->read(&regs->ctrl);
 958         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 959         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 960                 FLEXCAN_CTRL_ERR_STATE;
 961
 962         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
 963          * on most Flexcan cores, too. Otherwise we don't get
 964          * any error warning or passive interrupts.
 965          */
 966         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
 967             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
 968                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
 969         else
 970                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
 971
 972         /* save for later use */
 973         priv->reg_ctrl_default = reg_ctrl;
 974         /* leave interrupts disabled for now */
 975         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
 976         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 977         priv->write(reg_ctrl, &regs->ctrl);
 978
 979         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
 980                 reg_ctrl2 = priv->read(&regs->ctrl2);
 981                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
 982                 priv->write(reg_ctrl2, &regs->ctrl2);
 983         }
 984
 985         /* clear and invalidate all mailboxes first */
 986         for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
 987                 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
 988                             &regs->mb[i].can_ctrl);
 989         }
 990
 991         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 992                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
 993                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
 994                                     &regs->mb[i].can_ctrl);
 995         }
 996
 997         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
 998         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 999                     &priv->tx_mb_reserved->can_ctrl);
1000
1001         /* mark TX mailbox as INACTIVE */
1002         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1003                     &priv->tx_mb->can_ctrl);
1004
1005         /* acceptance mask/acceptance code (accept everything) */
1006         priv->write(0x0, &regs->rxgmask);
1007         priv->write(0x0, &regs->rx14mask);
1008         priv->write(0x0, &regs->rx15mask);
1009
1010         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1011                 priv->write(0x0, &regs->rxfgmask);
1012
1013         /* clear acceptance filters */
1014         for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1015                 priv->write(0, &regs->rximr[i]);
1016
1017         /* On Vybrid, disable memory error detection interrupts
1018          * and freeze mode.
1019          * This also works around errata e5295 which generates
1020          * false positive memory errors and put the device in
1021          * freeze mode.
1022          */
1023         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1024                 /* Follow the protocol as described in "Detection
1025                  * and Correction of Memory Errors" to write to
1026                  * MECR register
1027                  */
1028                 reg_ctrl2 = priv->read(&regs->ctrl2);
1029                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1030                 priv->write(reg_ctrl2, &regs->ctrl2);
1031
1032                 reg_mecr = priv->read(&regs->mecr);
1033                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1034                 priv->write(reg_mecr, &regs->mecr);
1035                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1036                               FLEXCAN_MECR_FANCEI_MSK);
1037                 priv->write(reg_mecr, &regs->mecr);
1038         }
1039
1040         err = flexcan_transceiver_enable(priv);
1041         if (err)
1042                 goto out_chip_disable;
1043
1044         /* synchronize with the can bus */
1045         err = flexcan_chip_unfreeze(priv);
1046         if (err)
1047                 goto out_transceiver_disable;
1048
1049         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1050
1051         /* enable interrupts atomically */
1052         disable_irq(dev->irq);
1053         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1054         priv->write(priv->reg_imask1_default, &regs->imask1);
1055         priv->write(priv->reg_imask2_default, &regs->imask2);
1056         enable_irq(dev->irq);
1057
1058         /* print chip status */
1059         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1060                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1061
1062         return 0;
1063
1064  out_transceiver_disable:
1065         flexcan_transceiver_disable(priv);
1066  out_chip_disable:
1067         flexcan_chip_disable(priv);
1068         return err;
1069 }
1070
1071 /* flexcan_chip_stop
1072  *
1073  * this functions is entered with clocks enabled
1074  */
1075 static void flexcan_chip_stop(struct net_device *dev)
1076 {
1077         struct flexcan_priv *priv = netdev_priv(dev);
1078         struct flexcan_regs __iomem *regs = priv->regs;
1079
1080         /* freeze + disable module */
1081         flexcan_chip_freeze(priv);
1082         flexcan_chip_disable(priv);
1083
1084         /* Disable all interrupts */
1085         priv->write(0, &regs->imask2);
1086         priv->write(0, &regs->imask1);
1087         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1088                     &regs->ctrl);
1089
1090         flexcan_transceiver_disable(priv);
1091         priv->can.state = CAN_STATE_STOPPED;
1092 }
1093
1094 static int flexcan_open(struct net_device *dev)
1095 {
1096         struct flexcan_priv *priv = netdev_priv(dev);
1097         int err;
1098
1099         err = clk_prepare_enable(priv->clk_ipg);
1100         if (err)
1101                 return err;
1102
1103         err = clk_prepare_enable(priv->clk_per);
1104         if (err)
1105                 goto out_disable_ipg;
1106
1107         err = open_candev(dev);
1108         if (err)
1109                 goto out_disable_per;
1110
1111         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1112         if (err)
1113                 goto out_close;
1114
1115         /* start chip and queuing */
1116         err = flexcan_chip_start(dev);
1117         if (err)
1118                 goto out_free_irq;
1119
1120         can_led_event(dev, CAN_LED_EVENT_OPEN);
1121
1122         can_rx_offload_enable(&priv->offload);
1123         netif_start_queue(dev);
1124
1125         return 0;
1126
1127  out_free_irq:
1128         free_irq(dev->irq, dev);
1129  out_close:
1130         close_candev(dev);
1131  out_disable_per:
1132         clk_disable_unprepare(priv->clk_per);
1133  out_disable_ipg:
1134         clk_disable_unprepare(priv->clk_ipg);
1135
1136         return err;
1137 }
1138
1139 static int flexcan_close(struct net_device *dev)
1140 {
1141         struct flexcan_priv *priv = netdev_priv(dev);
1142
1143         netif_stop_queue(dev);
1144         can_rx_offload_disable(&priv->offload);
1145         flexcan_chip_stop(dev);
1146
1147         free_irq(dev->irq, dev);
1148         clk_disable_unprepare(priv->clk_per);
1149         clk_disable_unprepare(priv->clk_ipg);
1150
1151         close_candev(dev);
1152
1153         can_led_event(dev, CAN_LED_EVENT_STOP);
1154
1155         return 0;
1156 }
1157
1158 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1159 {
1160         int err;
1161
1162         switch (mode) {
1163         case CAN_MODE_START:
1164                 err = flexcan_chip_start(dev);
1165                 if (err)
1166                         return err;
1167
1168                 netif_wake_queue(dev);
1169                 break;
1170
1171         default:
1172                 return -EOPNOTSUPP;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static const struct net_device_ops flexcan_netdev_ops = {
1179         .ndo_open       = flexcan_open,
1180         .ndo_stop       = flexcan_close,
1181         .ndo_start_xmit = flexcan_start_xmit,
1182         .ndo_change_mtu = can_change_mtu,
1183 };
1184
1185 static int register_flexcandev(struct net_device *dev)
1186 {
1187         struct flexcan_priv *priv = netdev_priv(dev);
1188         struct flexcan_regs __iomem *regs = priv->regs;
1189         u32 reg, err;
1190
1191         err = clk_prepare_enable(priv->clk_ipg);
1192         if (err)
1193                 return err;
1194
1195         err = clk_prepare_enable(priv->clk_per);
1196         if (err)
1197                 goto out_disable_ipg;
1198
1199         /* select "bus clock", chip must be disabled */
1200         err = flexcan_chip_disable(priv);
1201         if (err)
1202                 goto out_disable_per;
1203         reg = priv->read(&regs->ctrl);
1204         reg |= FLEXCAN_CTRL_CLK_SRC;
1205         priv->write(reg, &regs->ctrl);
1206
1207         err = flexcan_chip_enable(priv);
1208         if (err)
1209                 goto out_chip_disable;
1210
1211         /* set freeze, halt and activate FIFO, restrict register access */
1212         reg = priv->read(&regs->mcr);
1213         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1214                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1215         priv->write(reg, &regs->mcr);
1216
1217         /* Currently we only support newer versions of this core
1218          * featuring a RX hardware FIFO (although this driver doesn't
1219          * make use of it on some cores). Older cores, found on some
1220          * Coldfire derivates are not tested.
1221          */
1222         reg = priv->read(&regs->mcr);
1223         if (!(reg & FLEXCAN_MCR_FEN)) {
1224                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1225                 err = -ENODEV;
1226                 goto out_chip_disable;
1227         }
1228
1229         err = register_candev(dev);
1230
1231         /* disable core and turn off clocks */
1232  out_chip_disable:
1233         flexcan_chip_disable(priv);
1234  out_disable_per:
1235         clk_disable_unprepare(priv->clk_per);
1236  out_disable_ipg:
1237         clk_disable_unprepare(priv->clk_ipg);
1238
1239         return err;
1240 }
1241
1242 static void unregister_flexcandev(struct net_device *dev)
1243 {
1244         unregister_candev(dev);
1245 }
1246
1247 static const struct of_device_id flexcan_of_match[] = {
1248         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1249         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1250         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1251         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1252         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1253         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1254         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1255         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1256         { /* sentinel */ },
1257 };
1258 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1259
1260 static const struct platform_device_id flexcan_id_table[] = {
1261         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1262         { /* sentinel */ },
1263 };
1264 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1265
1266 static int flexcan_probe(struct platform_device *pdev)
1267 {
1268         const struct of_device_id *of_id;
1269         const struct flexcan_devtype_data *devtype_data;
1270         struct net_device *dev;
1271         struct flexcan_priv *priv;
1272         struct regulator *reg_xceiver;
1273         struct resource *mem;
1274         struct clk *clk_ipg = NULL, *clk_per = NULL;
1275         struct flexcan_regs __iomem *regs;
1276         int err, irq;
1277         u32 clock_freq = 0;
1278
1279         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1280         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1281                 return -EPROBE_DEFER;
1282         else if (IS_ERR(reg_xceiver))
1283                 reg_xceiver = NULL;
1284
1285         if (pdev->dev.of_node)
1286                 of_property_read_u32(pdev->dev.of_node,
1287                                      "clock-frequency", &clock_freq);
1288
1289         if (!clock_freq) {
1290                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1291                 if (IS_ERR(clk_ipg)) {
1292                         dev_err(&pdev->dev, "no ipg clock defined\n");
1293                         return PTR_ERR(clk_ipg);
1294                 }
1295
1296                 clk_per = devm_clk_get(&pdev->dev, "per");
1297                 if (IS_ERR(clk_per)) {
1298                         dev_err(&pdev->dev, "no per clock defined\n");
1299                         return PTR_ERR(clk_per);
1300                 }
1301                 clock_freq = clk_get_rate(clk_per);
1302         }
1303
1304         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305         irq = platform_get_irq(pdev, 0);
1306         if (irq <= 0)
1307                 return -ENODEV;
1308
1309         regs = devm_ioremap_resource(&pdev->dev, mem);
1310         if (IS_ERR(regs))
1311                 return PTR_ERR(regs);
1312
1313         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1314         if (of_id) {
1315                 devtype_data = of_id->data;
1316         } else if (platform_get_device_id(pdev)->driver_data) {
1317                 devtype_data = (struct flexcan_devtype_data *)
1318                         platform_get_device_id(pdev)->driver_data;
1319         } else {
1320                 return -ENODEV;
1321         }
1322
1323         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1324         if (!dev)
1325                 return -ENOMEM;
1326
1327         platform_set_drvdata(pdev, dev);
1328         SET_NETDEV_DEV(dev, &pdev->dev);
1329
1330         dev->netdev_ops = &flexcan_netdev_ops;
1331         dev->irq = irq;
1332         dev->flags |= IFF_ECHO;
1333
1334         priv = netdev_priv(dev);
1335
1336         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1337             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1338                 priv->read = flexcan_read_be;
1339                 priv->write = flexcan_write_be;
1340         } else {
1341                 priv->read = flexcan_read_le;
1342                 priv->write = flexcan_write_le;
1343         }
1344
1345         priv->can.clock.freq = clock_freq;
1346         priv->can.bittiming_const = &flexcan_bittiming_const;
1347         priv->can.do_set_mode = flexcan_set_mode;
1348         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1349         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1350                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1351                 CAN_CTRLMODE_BERR_REPORTING;
1352         priv->regs = regs;
1353         priv->clk_ipg = clk_ipg;
1354         priv->clk_per = clk_per;
1355         priv->devtype_data = devtype_data;
1356         priv->reg_xceiver = reg_xceiver;
1357
1358         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1359                 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1360                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1361         } else {
1362                 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1363                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1364         }
1365         priv->tx_mb = &regs->mb[priv->tx_mb_idx];
1366
1367         priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1368         priv->reg_imask2_default = 0;
1369
1370         priv->offload.mailbox_read = flexcan_mailbox_read;
1371
1372         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1373                 u64 imask;
1374
1375                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1376                 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1377
1378                 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1379                 priv->reg_imask1_default |= imask;
1380                 priv->reg_imask2_default |= imask >> 32;
1381
1382                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1383         } else {
1384                 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1385                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1386                 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1387         }
1388         if (err)
1389                 goto failed_offload;
1390
1391         err = register_flexcandev(dev);
1392         if (err) {
1393                 dev_err(&pdev->dev, "registering netdev failed\n");
1394                 goto failed_register;
1395         }
1396
1397         devm_can_led_init(dev);
1398
1399         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1400                  priv->regs, dev->irq);
1401
1402         return 0;
1403
1404  failed_offload:
1405  failed_register:
1406         free_candev(dev);
1407         return err;
1408 }
1409
1410 static int flexcan_remove(struct platform_device *pdev)
1411 {
1412         struct net_device *dev = platform_get_drvdata(pdev);
1413         struct flexcan_priv *priv = netdev_priv(dev);
1414
1415         unregister_flexcandev(dev);
1416         can_rx_offload_del(&priv->offload);
1417         free_candev(dev);
1418
1419         return 0;
1420 }
1421
1422 static int __maybe_unused flexcan_suspend(struct device *device)
1423 {
1424         struct net_device *dev = dev_get_drvdata(device);
1425         struct flexcan_priv *priv = netdev_priv(dev);
1426         int err;
1427
1428         if (netif_running(dev)) {
1429                 err = flexcan_chip_disable(priv);
1430                 if (err)
1431                         return err;
1432                 netif_stop_queue(dev);
1433                 netif_device_detach(dev);
1434         }
1435         priv->can.state = CAN_STATE_SLEEPING;
1436
1437         return 0;
1438 }
1439
1440 static int __maybe_unused flexcan_resume(struct device *device)
1441 {
1442         struct net_device *dev = dev_get_drvdata(device);
1443         struct flexcan_priv *priv = netdev_priv(dev);
1444         int err;
1445
1446         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1447         if (netif_running(dev)) {
1448                 netif_device_attach(dev);
1449                 netif_start_queue(dev);
1450                 err = flexcan_chip_enable(priv);
1451                 if (err)
1452                         return err;
1453         }
1454         return 0;
1455 }
1456
1457 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1458
1459 static struct platform_driver flexcan_driver = {
1460         .driver = {
1461                 .name = DRV_NAME,
1462                 .pm = &flexcan_pm_ops,
1463                 .of_match_table = flexcan_of_match,
1464         },
1465         .probe = flexcan_probe,
1466         .remove = flexcan_remove,
1467         .id_table = flexcan_id_table,
1468 };
1469
1470 module_platform_driver(flexcan_driver);
1471
1472 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1473               "Marc Kleine-Budde <kernel@pengutronix.de>");
1474 MODULE_LICENSE("GPL v2");
1475 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");