1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 #include <dt-bindings/firmware/imx/rsrc.h>
13 #include <linux/bitfield.h>
14 #include <linux/can.h>
15 #include <linux/can/dev.h>
16 #include <linux/can/error.h>
17 #include <linux/can/led.h>
18 #include <linux/can/rx-offload.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/firmware/imx/sci.h>
22 #include <linux/interrupt.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
28 #include <linux/of_device.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/regulator/consumer.h>
35 #define DRV_NAME "flexcan"
37 /* 8 for RX fifo and 2 error handling */
38 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
40 /* FLEXCAN module configuration register (CANMCR) bits */
41 #define FLEXCAN_MCR_MDIS BIT(31)
42 #define FLEXCAN_MCR_FRZ BIT(30)
43 #define FLEXCAN_MCR_FEN BIT(29)
44 #define FLEXCAN_MCR_HALT BIT(28)
45 #define FLEXCAN_MCR_NOT_RDY BIT(27)
46 #define FLEXCAN_MCR_WAK_MSK BIT(26)
47 #define FLEXCAN_MCR_SOFTRST BIT(25)
48 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
49 #define FLEXCAN_MCR_SUPV BIT(23)
50 #define FLEXCAN_MCR_SLF_WAK BIT(22)
51 #define FLEXCAN_MCR_WRN_EN BIT(21)
52 #define FLEXCAN_MCR_LPM_ACK BIT(20)
53 #define FLEXCAN_MCR_WAK_SRC BIT(19)
54 #define FLEXCAN_MCR_DOZE BIT(18)
55 #define FLEXCAN_MCR_SRX_DIS BIT(17)
56 #define FLEXCAN_MCR_IRMQ BIT(16)
57 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
58 #define FLEXCAN_MCR_AEN BIT(12)
59 #define FLEXCAN_MCR_FDEN BIT(11)
60 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
61 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
62 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
63 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
64 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
65 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
67 /* FLEXCAN control register (CANCTRL) bits */
68 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
69 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
70 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
71 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
72 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
73 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
74 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
75 #define FLEXCAN_CTRL_LPB BIT(12)
76 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
77 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
78 #define FLEXCAN_CTRL_SMP BIT(7)
79 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
80 #define FLEXCAN_CTRL_TSYN BIT(5)
81 #define FLEXCAN_CTRL_LBUF BIT(4)
82 #define FLEXCAN_CTRL_LOM BIT(3)
83 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
84 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
85 #define FLEXCAN_CTRL_ERR_STATE \
86 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
87 FLEXCAN_CTRL_BOFF_MSK)
88 #define FLEXCAN_CTRL_ERR_ALL \
89 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
91 /* FLEXCAN control register 2 (CTRL2) bits */
92 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
93 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
94 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
95 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
96 #define FLEXCAN_CTRL2_MRP BIT(18)
97 #define FLEXCAN_CTRL2_RRS BIT(17)
98 #define FLEXCAN_CTRL2_EACEN BIT(16)
99 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
101 /* FLEXCAN memory error control register (MECR) bits */
102 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
103 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
104 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
105 #define FLEXCAN_MECR_CEI_MSK BIT(16)
106 #define FLEXCAN_MECR_HAERRIE BIT(15)
107 #define FLEXCAN_MECR_FAERRIE BIT(14)
108 #define FLEXCAN_MECR_EXTERRIE BIT(13)
109 #define FLEXCAN_MECR_RERRDIS BIT(9)
110 #define FLEXCAN_MECR_ECCDIS BIT(8)
111 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
113 /* FLEXCAN error and status register (ESR) bits */
114 #define FLEXCAN_ESR_TWRN_INT BIT(17)
115 #define FLEXCAN_ESR_RWRN_INT BIT(16)
116 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
117 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
118 #define FLEXCAN_ESR_ACK_ERR BIT(13)
119 #define FLEXCAN_ESR_CRC_ERR BIT(12)
120 #define FLEXCAN_ESR_FRM_ERR BIT(11)
121 #define FLEXCAN_ESR_STF_ERR BIT(10)
122 #define FLEXCAN_ESR_TX_WRN BIT(9)
123 #define FLEXCAN_ESR_RX_WRN BIT(8)
124 #define FLEXCAN_ESR_IDLE BIT(7)
125 #define FLEXCAN_ESR_TXRX BIT(6)
126 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
127 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
128 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
129 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_BOFF_INT BIT(2)
131 #define FLEXCAN_ESR_ERR_INT BIT(1)
132 #define FLEXCAN_ESR_WAK_INT BIT(0)
133 #define FLEXCAN_ESR_ERR_BUS \
134 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
135 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
136 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
137 #define FLEXCAN_ESR_ERR_STATE \
138 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
139 #define FLEXCAN_ESR_ERR_ALL \
140 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
141 #define FLEXCAN_ESR_ALL_INT \
142 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
143 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
145 /* FLEXCAN Bit Timing register (CBT) bits */
146 #define FLEXCAN_CBT_BTF BIT(31)
147 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
148 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
149 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
150 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
151 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
153 /* FLEXCAN FD control register (FDCTRL) bits */
154 #define FLEXCAN_FDCTRL_FDRATE BIT(31)
155 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
156 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
157 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
158 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
159 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
160 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
161 #define FLEXCAN_FDCTRL_TDCEN BIT(15)
162 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
163 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
164 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
166 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
167 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
168 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
169 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
170 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
171 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
173 /* FLEXCAN interrupt flag register (IFLAG) bits */
174 /* Errata ERR005829 step7: Reserve first valid MB */
175 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
176 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
177 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
178 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
179 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
180 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
181 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
183 /* FLEXCAN message buffers */
184 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
185 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
186 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
187 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
188 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
189 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
190 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
192 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
193 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
194 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
195 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
197 #define FLEXCAN_MB_CNT_EDL BIT(31)
198 #define FLEXCAN_MB_CNT_BRS BIT(30)
199 #define FLEXCAN_MB_CNT_ESI BIT(29)
200 #define FLEXCAN_MB_CNT_SRR BIT(22)
201 #define FLEXCAN_MB_CNT_IDE BIT(21)
202 #define FLEXCAN_MB_CNT_RTR BIT(20)
203 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
204 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
206 #define FLEXCAN_TIMEOUT_US (250)
208 /* FLEXCAN hardware feature flags
210 * Below is some version info we got:
211 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
212 * Filter? connected? Passive detection ption in MB Supported?
213 * MX25 FlexCAN2 03.00.00.00 no no no no no no
214 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no
215 * MX35 FlexCAN2 03.00.00.00 no no no no no no
216 * MX53 FlexCAN2 03.00.00.00 yes no no no no no
217 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
218 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
219 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
220 * VF610 FlexCAN3 ? no yes no yes yes? no
221 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
222 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
224 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
227 /* [TR]WRN_INT not connected */
228 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
229 /* Disable RX FIFO Global mask */
230 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
231 /* Enable EACEN and RRS bit in ctrl2 */
232 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
233 /* Disable non-correctable errors interrupt and freeze mode */
234 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
235 /* Use timestamp based offloading */
236 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
237 /* No interrupt for error passive */
238 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
239 /* default to BE register access */
240 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
241 /* Setup stop mode with GPR to support wakeup */
242 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
243 /* Support CAN-FD mode */
244 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
245 /* support memory detection and correction */
246 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
247 /* Setup stop mode with SCU firmware to support wakeup */
248 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
250 /* Structure of the message buffer */
257 /* Structure of the hardware registers */
258 struct flexcan_regs {
260 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
261 u32 timer; /* 0x08 */
263 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
264 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
265 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
268 u32 imask2; /* 0x24 */
269 u32 imask1; /* 0x28 */
270 u32 iflag2; /* 0x2c */
271 u32 iflag1; /* 0x30 */
273 u32 gfwr_mx28; /* MX28, MX53 */
274 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
277 u32 imeur; /* 0x3c */
280 u32 rxfgmask; /* 0x48 */
281 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
282 u32 cbt; /* 0x50 - Not affected by Soft Reset */
283 u32 _reserved2; /* 0x54 */
286 u32 _reserved3[8]; /* 0x60 */
287 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
290 * 0x080...0x08f 0 RX message buffer
291 * 0x090...0x0df 1-5 reserved
292 * 0x0e0...0x0ff 6-7 8 entry ID table
293 * (mx25, mx28, mx35, mx53)
294 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
295 * size conf'ed via ctrl2::RFFN
298 u32 _reserved4[256]; /* 0x480 */
299 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
300 u32 _reserved5[24]; /* 0x980 */
301 u32 gfwr_mx6; /* 0x9e0 - MX6 */
302 u32 _reserved6[39]; /* 0x9e4 */
303 u32 _rxfir[6]; /* 0xa80 */
304 u32 _reserved8[2]; /* 0xa98 */
305 u32 _rxmgmask; /* 0xaa0 */
306 u32 _rxfgmask; /* 0xaa4 */
307 u32 _rx14mask; /* 0xaa8 */
308 u32 _rx15mask; /* 0xaac */
309 u32 tx_smb[4]; /* 0xab0 */
310 u32 rx_smb0[4]; /* 0xac0 */
311 u32 rx_smb1[4]; /* 0xad0 */
312 u32 mecr; /* 0xae0 */
313 u32 erriar; /* 0xae4 */
314 u32 erridpr; /* 0xae8 */
315 u32 errippr; /* 0xaec */
316 u32 rerrar; /* 0xaf0 */
317 u32 rerrdr; /* 0xaf4 */
318 u32 rerrsynr; /* 0xaf8 */
319 u32 errsr; /* 0xafc */
320 u32 _reserved7[64]; /* 0xb00 */
321 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
322 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
323 u32 fdcrc; /* 0xc08 */
324 u32 _reserved9[199]; /* 0xc0c */
325 u32 tx_smb_fd[18]; /* 0xf28 */
326 u32 rx_smb0_fd[18]; /* 0xf70 */
327 u32 rx_smb1_fd[18]; /* 0xfb8 */
330 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
332 struct flexcan_devtype_data {
333 u32 quirks; /* quirks needed for different IP cores */
336 struct flexcan_stop_mode {
342 struct flexcan_priv {
344 struct can_rx_offload offload;
347 struct flexcan_regs __iomem *regs;
348 struct flexcan_mb __iomem *tx_mb;
349 struct flexcan_mb __iomem *tx_mb_reserved;
353 u8 clk_src; /* clock source of CAN Protocol Engine */
358 u32 reg_ctrl_default;
362 const struct flexcan_devtype_data *devtype_data;
363 struct regulator *reg_xceiver;
364 struct flexcan_stop_mode stm;
366 /* IPC handle when setup stop mode by System Controller firmware(scfw) */
367 struct imx_sc_ipc *sc_ipc_handle;
369 /* Read and Write APIs */
370 u32 (*read)(void __iomem *addr);
371 void (*write)(u32 val, void __iomem *addr);
374 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
375 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
376 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
377 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
380 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
381 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
382 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
385 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
386 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
389 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
390 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
391 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
392 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR,
395 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
396 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
397 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
398 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW,
401 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
402 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
403 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
404 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
405 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
408 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
409 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
410 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
411 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
414 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
415 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
416 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
419 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
420 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
421 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
422 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
423 FLEXCAN_QUIRK_SUPPORT_ECC,
426 static const struct can_bittiming_const flexcan_bittiming_const = {
438 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
450 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
462 /* FlexCAN module is essentially modelled as a little-endian IP in most
463 * SoCs, i.e the registers as well as the message buffer areas are
464 * implemented in a little-endian fashion.
466 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
467 * module in a big-endian fashion (i.e the registers as well as the
468 * message buffer areas are implemented in a big-endian way).
470 * In addition, the FlexCAN module can be found on SoCs having ARM or
471 * PPC cores. So, we need to abstract off the register read/write
472 * functions, ensuring that these cater to all the combinations of module
473 * endianness and underlying CPU endianness.
475 static inline u32 flexcan_read_be(void __iomem *addr)
477 return ioread32be(addr);
480 static inline void flexcan_write_be(u32 val, void __iomem *addr)
482 iowrite32be(val, addr);
485 static inline u32 flexcan_read_le(void __iomem *addr)
487 return ioread32(addr);
490 static inline void flexcan_write_le(u32 val, void __iomem *addr)
492 iowrite32(val, addr);
495 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
501 if (WARN_ON(mb_index >= priv->mb_count))
504 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
506 bank = mb_index >= bank_size;
508 mb_index -= bank_size;
510 return (struct flexcan_mb __iomem *)
511 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
514 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
516 struct flexcan_regs __iomem *regs = priv->regs;
517 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
519 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
522 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
528 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
530 struct flexcan_regs __iomem *regs = priv->regs;
531 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
533 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
536 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
542 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
544 struct flexcan_regs __iomem *regs = priv->regs;
547 reg_mcr = priv->read(®s->mcr);
550 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
552 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
554 priv->write(reg_mcr, ®s->mcr);
557 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
559 u8 idx = priv->scu_idx;
562 rsrc_id = IMX_SC_R_CAN(idx);
569 /* stop mode request via scu firmware */
570 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
571 IMX_SC_C_IPG_STOP, val);
574 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
576 struct flexcan_regs __iomem *regs = priv->regs;
580 reg_mcr = priv->read(®s->mcr);
581 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
582 priv->write(reg_mcr, ®s->mcr);
584 /* enable stop request */
585 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
586 ret = flexcan_stop_mode_enable_scfw(priv, true);
590 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
591 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
594 return flexcan_low_power_enter_ack(priv);
597 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
599 struct flexcan_regs __iomem *regs = priv->regs;
603 /* remove stop request */
604 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
605 ret = flexcan_stop_mode_enable_scfw(priv, false);
609 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
610 1 << priv->stm.req_bit, 0);
613 reg_mcr = priv->read(®s->mcr);
614 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
615 priv->write(reg_mcr, ®s->mcr);
617 return flexcan_low_power_exit_ack(priv);
620 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
622 struct flexcan_regs __iomem *regs = priv->regs;
623 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
625 priv->write(reg_ctrl, ®s->ctrl);
628 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
630 struct flexcan_regs __iomem *regs = priv->regs;
631 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
633 priv->write(reg_ctrl, ®s->ctrl);
636 static int flexcan_clks_enable(const struct flexcan_priv *priv)
640 err = clk_prepare_enable(priv->clk_ipg);
644 err = clk_prepare_enable(priv->clk_per);
646 clk_disable_unprepare(priv->clk_ipg);
651 static void flexcan_clks_disable(const struct flexcan_priv *priv)
653 clk_disable_unprepare(priv->clk_per);
654 clk_disable_unprepare(priv->clk_ipg);
657 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
659 if (!priv->reg_xceiver)
662 return regulator_enable(priv->reg_xceiver);
665 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
667 if (!priv->reg_xceiver)
670 return regulator_disable(priv->reg_xceiver);
673 static int flexcan_chip_enable(struct flexcan_priv *priv)
675 struct flexcan_regs __iomem *regs = priv->regs;
678 reg = priv->read(®s->mcr);
679 reg &= ~FLEXCAN_MCR_MDIS;
680 priv->write(reg, ®s->mcr);
682 return flexcan_low_power_exit_ack(priv);
685 static int flexcan_chip_disable(struct flexcan_priv *priv)
687 struct flexcan_regs __iomem *regs = priv->regs;
690 reg = priv->read(®s->mcr);
691 reg |= FLEXCAN_MCR_MDIS;
692 priv->write(reg, ®s->mcr);
694 return flexcan_low_power_enter_ack(priv);
697 static int flexcan_chip_freeze(struct flexcan_priv *priv)
699 struct flexcan_regs __iomem *regs = priv->regs;
700 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
703 reg = priv->read(®s->mcr);
704 reg |= FLEXCAN_MCR_HALT;
705 priv->write(reg, ®s->mcr);
707 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
710 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
716 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
718 struct flexcan_regs __iomem *regs = priv->regs;
719 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
722 reg = priv->read(®s->mcr);
723 reg &= ~FLEXCAN_MCR_HALT;
724 priv->write(reg, ®s->mcr);
726 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
729 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
735 static int flexcan_chip_softreset(struct flexcan_priv *priv)
737 struct flexcan_regs __iomem *regs = priv->regs;
738 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
740 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
741 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
744 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
750 static int __flexcan_get_berr_counter(const struct net_device *dev,
751 struct can_berr_counter *bec)
753 const struct flexcan_priv *priv = netdev_priv(dev);
754 struct flexcan_regs __iomem *regs = priv->regs;
755 u32 reg = priv->read(®s->ecr);
757 bec->txerr = (reg >> 0) & 0xff;
758 bec->rxerr = (reg >> 8) & 0xff;
763 static int flexcan_get_berr_counter(const struct net_device *dev,
764 struct can_berr_counter *bec)
766 const struct flexcan_priv *priv = netdev_priv(dev);
769 err = pm_runtime_get_sync(priv->dev);
771 pm_runtime_put_noidle(priv->dev);
775 err = __flexcan_get_berr_counter(dev, bec);
777 pm_runtime_put(priv->dev);
782 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
784 const struct flexcan_priv *priv = netdev_priv(dev);
785 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
788 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
791 if (can_dropped_invalid_skb(dev, skb))
794 netif_stop_queue(dev);
796 if (cfd->can_id & CAN_EFF_FLAG) {
797 can_id = cfd->can_id & CAN_EFF_MASK;
798 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
800 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
803 if (cfd->can_id & CAN_RTR_FLAG)
804 ctrl |= FLEXCAN_MB_CNT_RTR;
806 if (can_is_canfd_skb(skb)) {
807 ctrl |= FLEXCAN_MB_CNT_EDL;
809 if (cfd->flags & CANFD_BRS)
810 ctrl |= FLEXCAN_MB_CNT_BRS;
813 for (i = 0; i < cfd->len; i += sizeof(u32)) {
814 data = be32_to_cpup((__be32 *)&cfd->data[i]);
815 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
818 can_put_echo_skb(skb, dev, 0);
820 priv->write(can_id, &priv->tx_mb->can_id);
821 priv->write(ctrl, &priv->tx_mb->can_ctrl);
823 /* Errata ERR005829 step8:
824 * Write twice INACTIVE(0x8) code to first MB.
826 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
827 &priv->tx_mb_reserved->can_ctrl);
828 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
829 &priv->tx_mb_reserved->can_ctrl);
834 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
836 struct flexcan_priv *priv = netdev_priv(dev);
837 struct flexcan_regs __iomem *regs = priv->regs;
839 struct can_frame *cf;
840 bool rx_errors = false, tx_errors = false;
844 timestamp = priv->read(®s->timer) << 16;
846 skb = alloc_can_err_skb(dev, &cf);
850 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
852 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
853 netdev_dbg(dev, "BIT1_ERR irq\n");
854 cf->data[2] |= CAN_ERR_PROT_BIT1;
857 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
858 netdev_dbg(dev, "BIT0_ERR irq\n");
859 cf->data[2] |= CAN_ERR_PROT_BIT0;
862 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
863 netdev_dbg(dev, "ACK_ERR irq\n");
864 cf->can_id |= CAN_ERR_ACK;
865 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
868 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
869 netdev_dbg(dev, "CRC_ERR irq\n");
870 cf->data[2] |= CAN_ERR_PROT_BIT;
871 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
874 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
875 netdev_dbg(dev, "FRM_ERR irq\n");
876 cf->data[2] |= CAN_ERR_PROT_FORM;
879 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
880 netdev_dbg(dev, "STF_ERR irq\n");
881 cf->data[2] |= CAN_ERR_PROT_STUFF;
885 priv->can.can_stats.bus_error++;
887 dev->stats.rx_errors++;
889 dev->stats.tx_errors++;
891 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
893 dev->stats.rx_fifo_errors++;
896 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
898 struct flexcan_priv *priv = netdev_priv(dev);
899 struct flexcan_regs __iomem *regs = priv->regs;
901 struct can_frame *cf;
902 enum can_state new_state, rx_state, tx_state;
904 struct can_berr_counter bec;
908 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
909 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
910 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
911 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
912 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
913 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
914 new_state = max(tx_state, rx_state);
916 __flexcan_get_berr_counter(dev, &bec);
917 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
918 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
919 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
920 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
923 /* state hasn't changed */
924 if (likely(new_state == priv->can.state))
927 timestamp = priv->read(®s->timer) << 16;
929 skb = alloc_can_err_skb(dev, &cf);
933 can_change_state(dev, cf, tx_state, rx_state);
935 if (unlikely(new_state == CAN_STATE_BUS_OFF))
938 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
940 dev->stats.rx_fifo_errors++;
943 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
947 if (upper_32_bits(mask))
948 reg = (u64)priv->read(addr - 4) << 32;
949 if (lower_32_bits(mask))
950 reg |= priv->read(addr);
955 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
957 if (upper_32_bits(val))
958 priv->write(upper_32_bits(val), addr - 4);
959 if (lower_32_bits(val))
960 priv->write(lower_32_bits(val), addr);
963 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
965 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
968 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
970 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
973 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
975 return container_of(offload, struct flexcan_priv, offload);
978 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
979 unsigned int n, u32 *timestamp,
982 struct flexcan_priv *priv = rx_offload_to_priv(offload);
983 struct flexcan_regs __iomem *regs = priv->regs;
984 struct flexcan_mb __iomem *mb;
986 struct canfd_frame *cfd;
987 u32 reg_ctrl, reg_id, reg_iflag1;
990 if (unlikely(drop)) {
991 skb = ERR_PTR(-ENOBUFS);
995 mb = flexcan_get_mb(priv, n);
997 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1001 reg_ctrl = priv->read(&mb->can_ctrl);
1002 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
1004 /* is this MB empty? */
1005 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
1006 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
1007 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
1010 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
1011 /* This MB was overrun, we lost data */
1012 offload->dev->stats.rx_over_errors++;
1013 offload->dev->stats.rx_errors++;
1016 reg_iflag1 = priv->read(®s->iflag1);
1017 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
1020 reg_ctrl = priv->read(&mb->can_ctrl);
1023 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1024 skb = alloc_canfd_skb(offload->dev, &cfd);
1026 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1027 if (unlikely(!skb)) {
1028 skb = ERR_PTR(-ENOMEM);
1032 /* increase timstamp to full 32 bit */
1033 *timestamp = reg_ctrl << 16;
1035 reg_id = priv->read(&mb->can_id);
1036 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1037 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1039 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1041 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1042 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1044 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1045 cfd->flags |= CANFD_BRS;
1047 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1049 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1050 cfd->can_id |= CAN_RTR_FLAG;
1053 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1054 cfd->flags |= CANFD_ESI;
1056 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1057 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1058 *(__be32 *)(cfd->data + i) = data;
1062 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1063 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1065 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1067 /* Read the Free Running Timer. It is optional but recommended
1068 * to unlock Mailbox as soon as possible and make it available
1071 priv->read(®s->timer);
1076 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1078 struct net_device *dev = dev_id;
1079 struct net_device_stats *stats = &dev->stats;
1080 struct flexcan_priv *priv = netdev_priv(dev);
1081 struct flexcan_regs __iomem *regs = priv->regs;
1082 irqreturn_t handled = IRQ_NONE;
1085 enum can_state last_state = priv->can.state;
1087 /* reception interrupt */
1088 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1092 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1093 handled = IRQ_HANDLED;
1094 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1102 reg_iflag1 = priv->read(®s->iflag1);
1103 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1104 handled = IRQ_HANDLED;
1105 can_rx_offload_irq_offload_fifo(&priv->offload);
1108 /* FIFO overflow interrupt */
1109 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1110 handled = IRQ_HANDLED;
1111 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1113 dev->stats.rx_over_errors++;
1114 dev->stats.rx_errors++;
1118 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1120 /* transmission complete interrupt */
1121 if (reg_iflag_tx & priv->tx_mask) {
1122 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1124 handled = IRQ_HANDLED;
1125 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
1127 stats->tx_packets++;
1128 can_led_event(dev, CAN_LED_EVENT_TX);
1130 /* after sending a RTR frame MB is in RX mode */
1131 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1132 &priv->tx_mb->can_ctrl);
1133 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1134 netif_wake_queue(dev);
1137 reg_esr = priv->read(®s->esr);
1139 /* ACK all bus error, state change and wake IRQ sources */
1140 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1141 handled = IRQ_HANDLED;
1142 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1145 /* state change interrupt or broken error state quirk fix is enabled */
1146 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1147 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1148 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1149 flexcan_irq_state(dev, reg_esr);
1151 /* bus error IRQ - handle if bus error reporting is activated */
1152 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1153 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1154 flexcan_irq_bus_err(dev, reg_esr);
1156 /* availability of error interrupt among state transitions in case
1157 * bus error reporting is de-activated and
1158 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1159 * +--------------------------------------------------------------+
1160 * | +----------------------------------------------+ [stopped / |
1161 * | | | sleeping] -+
1162 * +-+-> active <-> warning <-> passive -> bus off -+
1163 * ___________^^^^^^^^^^^^_______________________________
1164 * disabled(1) enabled disabled
1166 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1168 if ((last_state != priv->can.state) &&
1169 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1170 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1171 switch (priv->can.state) {
1172 case CAN_STATE_ERROR_ACTIVE:
1173 if (priv->devtype_data->quirks &
1174 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1175 flexcan_error_irq_enable(priv);
1177 flexcan_error_irq_disable(priv);
1180 case CAN_STATE_ERROR_WARNING:
1181 flexcan_error_irq_enable(priv);
1184 case CAN_STATE_ERROR_PASSIVE:
1185 case CAN_STATE_BUS_OFF:
1186 flexcan_error_irq_disable(priv);
1197 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1199 const struct flexcan_priv *priv = netdev_priv(dev);
1200 const struct can_bittiming *bt = &priv->can.bittiming;
1201 struct flexcan_regs __iomem *regs = priv->regs;
1204 reg = priv->read(®s->ctrl);
1205 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1206 FLEXCAN_CTRL_RJW(0x3) |
1207 FLEXCAN_CTRL_PSEG1(0x7) |
1208 FLEXCAN_CTRL_PSEG2(0x7) |
1209 FLEXCAN_CTRL_PROPSEG(0x7));
1211 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1212 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1213 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1214 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1215 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1217 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1218 priv->write(reg, ®s->ctrl);
1220 /* print chip status */
1221 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1222 priv->read(®s->mcr), priv->read(®s->ctrl));
1225 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1227 struct flexcan_priv *priv = netdev_priv(dev);
1228 struct can_bittiming *bt = &priv->can.bittiming;
1229 struct can_bittiming *dbt = &priv->can.data_bittiming;
1230 struct flexcan_regs __iomem *regs = priv->regs;
1231 u32 reg_cbt, reg_fdctrl;
1234 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1235 * long. The can_calc_bittiming() tries to divide the tseg1
1236 * equally between phase_seg1 and prop_seg, which may not fit
1237 * in CBT register. Therefore, if phase_seg1 is more than
1238 * possible value, increase prop_seg and decrease phase_seg1.
1240 if (bt->phase_seg1 > 0x20) {
1241 bt->prop_seg += (bt->phase_seg1 - 0x20);
1242 bt->phase_seg1 = 0x20;
1245 reg_cbt = FLEXCAN_CBT_BTF |
1246 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1247 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1248 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1249 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1250 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1252 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1253 priv->write(reg_cbt, ®s->cbt);
1255 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1256 u32 reg_fdcbt, reg_ctrl2;
1258 if (bt->brp != dbt->brp)
1259 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1263 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1264 * 5 bit long. The can_calc_bittiming tries to divide
1265 * the tseg1 equally between phase_seg1 and prop_seg,
1266 * which may not fit in FDCBT register. Therefore, if
1267 * phase_seg1 is more than possible value, increase
1268 * prop_seg and decrease phase_seg1
1270 if (dbt->phase_seg1 > 0x8) {
1271 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1272 dbt->phase_seg1 = 0x8;
1275 reg_fdcbt = priv->read(®s->fdcbt);
1276 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1277 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1278 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1279 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1280 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1282 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1283 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1284 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1285 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1286 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1288 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1289 priv->write(reg_fdcbt, ®s->fdcbt);
1292 reg_ctrl2 = priv->read(®s->ctrl2);
1293 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1294 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1295 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1297 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1298 priv->write(reg_ctrl2, ®s->ctrl2);
1302 reg_fdctrl = priv->read(®s->fdctrl);
1303 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1304 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1306 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1307 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1309 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1310 /* TDC must be disabled for Loop Back mode */
1311 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1313 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1314 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1315 ((dbt->phase_seg1 - 1) +
1316 dbt->prop_seg + 2) *
1317 ((dbt->brp - 1 ) + 1));
1321 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1322 priv->write(reg_fdctrl, ®s->fdctrl);
1324 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1326 priv->read(®s->mcr), priv->read(®s->ctrl),
1327 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1328 priv->read(®s->cbt), priv->read(®s->fdcbt));
1331 static void flexcan_set_bittiming(struct net_device *dev)
1333 const struct flexcan_priv *priv = netdev_priv(dev);
1334 struct flexcan_regs __iomem *regs = priv->regs;
1337 reg = priv->read(®s->ctrl);
1338 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1341 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1342 reg |= FLEXCAN_CTRL_LPB;
1343 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1344 reg |= FLEXCAN_CTRL_LOM;
1345 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1346 reg |= FLEXCAN_CTRL_SMP;
1348 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1349 priv->write(reg, ®s->ctrl);
1351 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1352 return flexcan_set_bittiming_cbt(dev);
1354 return flexcan_set_bittiming_ctrl(dev);
1357 static void flexcan_ram_init(struct net_device *dev)
1359 struct flexcan_priv *priv = netdev_priv(dev);
1360 struct flexcan_regs __iomem *regs = priv->regs;
1363 /* 11.8.3.13 Detection and correction of memory errors:
1364 * CTRL2[WRMFRZ] grants write access to all memory positions
1365 * that require initialization, ranging from 0x080 to 0xADF
1366 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1367 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1368 * need to be initialized as well. MCR[RFEN] must not be set
1369 * during memory initialization.
1371 reg_ctrl2 = priv->read(®s->ctrl2);
1372 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1373 priv->write(reg_ctrl2, ®s->ctrl2);
1375 memset_io(®s->mb[0][0], 0,
1376 offsetof(struct flexcan_regs, rx_smb1[3]) -
1377 offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1379 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1380 memset_io(®s->tx_smb_fd[0], 0,
1381 offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1382 offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1384 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1385 priv->write(reg_ctrl2, ®s->ctrl2);
1388 static int flexcan_rx_offload_setup(struct net_device *dev)
1390 struct flexcan_priv *priv = netdev_priv(dev);
1393 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1394 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1396 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1397 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1398 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1400 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1401 priv->tx_mb_reserved =
1402 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1404 priv->tx_mb_reserved =
1405 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1406 priv->tx_mb_idx = priv->mb_count - 1;
1407 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1408 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1410 priv->offload.mailbox_read = flexcan_mailbox_read;
1412 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1413 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1414 priv->offload.mb_last = priv->mb_count - 2;
1416 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1417 priv->offload.mb_first);
1418 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1420 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1421 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1422 err = can_rx_offload_add_fifo(dev, &priv->offload,
1423 FLEXCAN_NAPI_WEIGHT);
1429 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1431 const struct flexcan_priv *priv = netdev_priv(dev);
1432 struct flexcan_regs __iomem *regs = priv->regs;
1435 disable_irq(dev->irq);
1436 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1437 reg_imask = priv->rx_mask | priv->tx_mask;
1438 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1439 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1440 enable_irq(dev->irq);
1443 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1445 const struct flexcan_priv *priv = netdev_priv(dev);
1446 struct flexcan_regs __iomem *regs = priv->regs;
1448 priv->write(0, ®s->imask2);
1449 priv->write(0, ®s->imask1);
1450 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1454 /* flexcan_chip_start
1456 * this functions is entered with clocks enabled
1459 static int flexcan_chip_start(struct net_device *dev)
1461 struct flexcan_priv *priv = netdev_priv(dev);
1462 struct flexcan_regs __iomem *regs = priv->regs;
1463 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1465 struct flexcan_mb __iomem *mb;
1468 err = flexcan_chip_enable(priv);
1473 err = flexcan_chip_softreset(priv);
1475 goto out_chip_disable;
1477 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1478 flexcan_ram_init(dev);
1480 flexcan_set_bittiming(dev);
1486 * only supervisor access
1487 * enable warning int
1488 * enable individual RX masking
1490 * set max mailbox number
1492 reg_mcr = priv->read(®s->mcr);
1493 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1494 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1495 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1496 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1501 * - disable for timestamp mode
1502 * - enable for FIFO mode
1504 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1505 reg_mcr &= ~FLEXCAN_MCR_FEN;
1507 reg_mcr |= FLEXCAN_MCR_FEN;
1511 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1512 * asserted because this will impede the self reception
1513 * of a transmitted message. This is not documented in
1514 * earlier versions of flexcan block guide.
1517 * - enable Self Reception for loopback mode
1518 * (by clearing "Self Reception Disable" bit)
1519 * - disable for normal operation
1521 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1522 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1524 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1527 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1528 reg_mcr |= FLEXCAN_MCR_FDEN;
1530 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1532 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1533 priv->write(reg_mcr, ®s->mcr);
1537 * disable timer sync feature
1539 * disable auto busoff recovery
1540 * transmit lowest buffer first
1542 * enable tx and rx warning interrupt
1543 * enable bus off interrupt
1544 * (== FLEXCAN_CTRL_ERR_STATE)
1546 reg_ctrl = priv->read(®s->ctrl);
1547 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1548 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1549 FLEXCAN_CTRL_ERR_STATE;
1551 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1552 * on most Flexcan cores, too. Otherwise we don't get
1553 * any error warning or passive interrupts.
1555 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1556 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1557 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1559 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1561 /* save for later use */
1562 priv->reg_ctrl_default = reg_ctrl;
1563 /* leave interrupts disabled for now */
1564 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1565 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1566 priv->write(reg_ctrl, ®s->ctrl);
1568 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1569 reg_ctrl2 = priv->read(®s->ctrl2);
1570 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1571 priv->write(reg_ctrl2, ®s->ctrl2);
1574 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1577 reg_fdctrl = priv->read(®s->fdctrl);
1578 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1579 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1581 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1583 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1584 FLEXCAN_FDCTRL_MBDSR_64) |
1585 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1586 FLEXCAN_FDCTRL_MBDSR_64);
1589 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1590 FLEXCAN_FDCTRL_MBDSR_8) |
1591 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1592 FLEXCAN_FDCTRL_MBDSR_8);
1595 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1596 __func__, reg_fdctrl);
1597 priv->write(reg_fdctrl, ®s->fdctrl);
1600 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1601 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1602 mb = flexcan_get_mb(priv, i);
1603 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1607 /* clear and invalidate unused mailboxes first */
1608 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1609 mb = flexcan_get_mb(priv, i);
1610 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1615 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1616 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1617 &priv->tx_mb_reserved->can_ctrl);
1619 /* mark TX mailbox as INACTIVE */
1620 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1621 &priv->tx_mb->can_ctrl);
1623 /* acceptance mask/acceptance code (accept everything) */
1624 priv->write(0x0, ®s->rxgmask);
1625 priv->write(0x0, ®s->rx14mask);
1626 priv->write(0x0, ®s->rx15mask);
1628 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1629 priv->write(0x0, ®s->rxfgmask);
1631 /* clear acceptance filters */
1632 for (i = 0; i < priv->mb_count; i++)
1633 priv->write(0, ®s->rximr[i]);
1635 /* On Vybrid, disable non-correctable errors interrupt and
1636 * freeze mode. It still can correct the correctable errors
1637 * when HW supports ECC.
1639 * This also works around errata e5295 which generates false
1640 * positive memory errors and put the device in freeze mode.
1642 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1643 /* Follow the protocol as described in "Detection
1644 * and Correction of Memory Errors" to write to
1645 * MECR register (step 1 - 5)
1647 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1648 * 2. set CTRL2[ECRWRE]
1650 reg_ctrl2 = priv->read(®s->ctrl2);
1651 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1652 priv->write(reg_ctrl2, ®s->ctrl2);
1654 /* 3. clear MECR[ECRWRDIS] */
1655 reg_mecr = priv->read(®s->mecr);
1656 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1657 priv->write(reg_mecr, ®s->mecr);
1659 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1660 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1661 FLEXCAN_MECR_FANCEI_MSK);
1662 priv->write(reg_mecr, ®s->mecr);
1664 /* 5. after configuration done, lock MECR by either
1665 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1667 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1668 priv->write(reg_mecr, ®s->mecr);
1670 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1671 priv->write(reg_ctrl2, ®s->ctrl2);
1674 /* synchronize with the can bus */
1675 err = flexcan_chip_unfreeze(priv);
1677 goto out_chip_disable;
1679 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1681 /* print chip status */
1682 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1683 priv->read(®s->mcr), priv->read(®s->ctrl));
1688 flexcan_chip_disable(priv);
1692 /* __flexcan_chip_stop
1694 * this function is entered with clocks enabled
1696 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1698 struct flexcan_priv *priv = netdev_priv(dev);
1701 /* freeze + disable module */
1702 err = flexcan_chip_freeze(priv);
1703 if (err && !disable_on_error)
1705 err = flexcan_chip_disable(priv);
1706 if (err && !disable_on_error)
1707 goto out_chip_unfreeze;
1709 priv->can.state = CAN_STATE_STOPPED;
1714 flexcan_chip_unfreeze(priv);
1719 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1721 return __flexcan_chip_stop(dev, true);
1724 static inline int flexcan_chip_stop(struct net_device *dev)
1726 return __flexcan_chip_stop(dev, false);
1729 static int flexcan_open(struct net_device *dev)
1731 struct flexcan_priv *priv = netdev_priv(dev);
1734 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1735 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1736 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1740 err = pm_runtime_get_sync(priv->dev);
1742 pm_runtime_put_noidle(priv->dev);
1746 err = open_candev(dev);
1748 goto out_runtime_put;
1750 err = flexcan_transceiver_enable(priv);
1754 err = flexcan_rx_offload_setup(dev);
1756 goto out_transceiver_disable;
1758 err = flexcan_chip_start(dev);
1760 goto out_can_rx_offload_del;
1762 can_rx_offload_enable(&priv->offload);
1764 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1766 goto out_can_rx_offload_disable;
1768 flexcan_chip_interrupts_enable(dev);
1770 can_led_event(dev, CAN_LED_EVENT_OPEN);
1772 netif_start_queue(dev);
1776 out_can_rx_offload_disable:
1777 can_rx_offload_disable(&priv->offload);
1778 flexcan_chip_stop(dev);
1779 out_can_rx_offload_del:
1780 can_rx_offload_del(&priv->offload);
1781 out_transceiver_disable:
1782 flexcan_transceiver_disable(priv);
1786 pm_runtime_put(priv->dev);
1791 static int flexcan_close(struct net_device *dev)
1793 struct flexcan_priv *priv = netdev_priv(dev);
1795 netif_stop_queue(dev);
1796 flexcan_chip_interrupts_disable(dev);
1797 free_irq(dev->irq, dev);
1798 can_rx_offload_disable(&priv->offload);
1799 flexcan_chip_stop_disable_on_error(dev);
1801 can_rx_offload_del(&priv->offload);
1802 flexcan_transceiver_disable(priv);
1805 pm_runtime_put(priv->dev);
1807 can_led_event(dev, CAN_LED_EVENT_STOP);
1812 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1817 case CAN_MODE_START:
1818 err = flexcan_chip_start(dev);
1822 flexcan_chip_interrupts_enable(dev);
1824 netif_wake_queue(dev);
1834 static const struct net_device_ops flexcan_netdev_ops = {
1835 .ndo_open = flexcan_open,
1836 .ndo_stop = flexcan_close,
1837 .ndo_start_xmit = flexcan_start_xmit,
1838 .ndo_change_mtu = can_change_mtu,
1841 static int register_flexcandev(struct net_device *dev)
1843 struct flexcan_priv *priv = netdev_priv(dev);
1844 struct flexcan_regs __iomem *regs = priv->regs;
1847 err = flexcan_clks_enable(priv);
1851 /* select "bus clock", chip must be disabled */
1852 err = flexcan_chip_disable(priv);
1854 goto out_clks_disable;
1856 reg = priv->read(®s->ctrl);
1858 reg |= FLEXCAN_CTRL_CLK_SRC;
1860 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1861 priv->write(reg, ®s->ctrl);
1863 err = flexcan_chip_enable(priv);
1865 goto out_chip_disable;
1867 /* set freeze, halt and activate FIFO, restrict register access */
1868 reg = priv->read(®s->mcr);
1869 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1870 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1871 priv->write(reg, ®s->mcr);
1873 /* Currently we only support newer versions of this core
1874 * featuring a RX hardware FIFO (although this driver doesn't
1875 * make use of it on some cores). Older cores, found on some
1876 * Coldfire derivates are not tested.
1878 reg = priv->read(®s->mcr);
1879 if (!(reg & FLEXCAN_MCR_FEN)) {
1880 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1882 goto out_chip_disable;
1885 err = register_candev(dev);
1887 goto out_chip_disable;
1889 /* Disable core and let pm_runtime_put() disable the clocks.
1890 * If CONFIG_PM is not enabled, the clocks will stay powered.
1892 flexcan_chip_disable(priv);
1893 pm_runtime_put(priv->dev);
1898 flexcan_chip_disable(priv);
1900 flexcan_clks_disable(priv);
1904 static void unregister_flexcandev(struct net_device *dev)
1906 unregister_candev(dev);
1909 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1911 struct net_device *dev = platform_get_drvdata(pdev);
1912 struct device_node *np = pdev->dev.of_node;
1913 struct device_node *gpr_np;
1914 struct flexcan_priv *priv;
1922 /* stop mode property format is:
1923 * <&gpr req_gpr req_bit>.
1925 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1926 ARRAY_SIZE(out_val));
1928 dev_dbg(&pdev->dev, "no stop-mode property\n");
1933 gpr_np = of_find_node_by_phandle(phandle);
1935 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1939 priv = netdev_priv(dev);
1940 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1941 if (IS_ERR(priv->stm.gpr)) {
1942 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1943 ret = PTR_ERR(priv->stm.gpr);
1947 priv->stm.req_gpr = out_val[1];
1948 priv->stm.req_bit = out_val[2];
1951 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1952 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1957 of_node_put(gpr_np);
1961 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1963 struct net_device *dev = platform_get_drvdata(pdev);
1964 struct flexcan_priv *priv;
1968 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1970 dev_dbg(&pdev->dev, "failed to get scu index\n");
1974 priv = netdev_priv(dev);
1975 priv->scu_idx = scu_idx;
1977 /* this function could be defered probe, return -EPROBE_DEFER */
1978 return imx_scu_get_handle(&priv->sc_ipc_handle);
1981 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1983 * Return: = 0 setup stop mode successfully or doesn't support this feature
1984 * < 0 fail to setup stop mode (could be defered probe)
1986 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1988 struct net_device *dev = platform_get_drvdata(pdev);
1989 struct flexcan_priv *priv;
1992 priv = netdev_priv(dev);
1994 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1995 ret = flexcan_setup_stop_mode_scfw(pdev);
1996 else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1997 ret = flexcan_setup_stop_mode_gpr(pdev);
1999 /* return 0 directly if doesn't support stop mode feature */
2005 device_set_wakeup_capable(&pdev->dev, true);
2007 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2008 device_set_wakeup_enable(&pdev->dev, true);
2013 static const struct of_device_id flexcan_of_match[] = {
2014 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2015 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2016 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2017 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2018 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2019 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2020 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2021 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2022 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2023 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2024 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2027 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2029 static int flexcan_probe(struct platform_device *pdev)
2031 const struct flexcan_devtype_data *devtype_data;
2032 struct net_device *dev;
2033 struct flexcan_priv *priv;
2034 struct regulator *reg_xceiver;
2035 struct clk *clk_ipg = NULL, *clk_per = NULL;
2036 struct flexcan_regs __iomem *regs;
2041 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2042 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2043 return -EPROBE_DEFER;
2044 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2046 else if (IS_ERR(reg_xceiver))
2047 return PTR_ERR(reg_xceiver);
2049 if (pdev->dev.of_node) {
2050 of_property_read_u32(pdev->dev.of_node,
2051 "clock-frequency", &clock_freq);
2052 of_property_read_u8(pdev->dev.of_node,
2053 "fsl,clk-source", &clk_src);
2057 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2058 if (IS_ERR(clk_ipg)) {
2059 dev_err(&pdev->dev, "no ipg clock defined\n");
2060 return PTR_ERR(clk_ipg);
2063 clk_per = devm_clk_get(&pdev->dev, "per");
2064 if (IS_ERR(clk_per)) {
2065 dev_err(&pdev->dev, "no per clock defined\n");
2066 return PTR_ERR(clk_per);
2068 clock_freq = clk_get_rate(clk_per);
2071 irq = platform_get_irq(pdev, 0);
2075 regs = devm_platform_ioremap_resource(pdev, 0);
2077 return PTR_ERR(regs);
2079 devtype_data = of_device_get_match_data(&pdev->dev);
2081 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2082 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
2083 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
2087 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2091 platform_set_drvdata(pdev, dev);
2092 SET_NETDEV_DEV(dev, &pdev->dev);
2094 dev->netdev_ops = &flexcan_netdev_ops;
2096 dev->flags |= IFF_ECHO;
2098 priv = netdev_priv(dev);
2100 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2101 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2102 priv->read = flexcan_read_be;
2103 priv->write = flexcan_write_be;
2105 priv->read = flexcan_read_le;
2106 priv->write = flexcan_write_le;
2109 priv->dev = &pdev->dev;
2110 priv->can.clock.freq = clock_freq;
2111 priv->can.do_set_mode = flexcan_set_mode;
2112 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2113 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2114 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2115 CAN_CTRLMODE_BERR_REPORTING;
2117 priv->clk_ipg = clk_ipg;
2118 priv->clk_per = clk_per;
2119 priv->clk_src = clk_src;
2120 priv->devtype_data = devtype_data;
2121 priv->reg_xceiver = reg_xceiver;
2123 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2124 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2125 CAN_CTRLMODE_FD_NON_ISO;
2126 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2127 priv->can.data_bittiming_const =
2128 &flexcan_fd_data_bittiming_const;
2130 priv->can.bittiming_const = &flexcan_bittiming_const;
2133 pm_runtime_get_noresume(&pdev->dev);
2134 pm_runtime_set_active(&pdev->dev);
2135 pm_runtime_enable(&pdev->dev);
2137 err = register_flexcandev(dev);
2139 dev_err(&pdev->dev, "registering netdev failed\n");
2140 goto failed_register;
2143 err = flexcan_setup_stop_mode(pdev);
2145 if (err != -EPROBE_DEFER)
2146 dev_err(&pdev->dev, "setup stop mode failed\n");
2147 goto failed_setup_stop_mode;
2150 of_can_transceiver(dev);
2151 devm_can_led_init(dev);
2155 failed_setup_stop_mode:
2156 unregister_flexcandev(dev);
2158 pm_runtime_put_noidle(&pdev->dev);
2159 pm_runtime_disable(&pdev->dev);
2164 static int flexcan_remove(struct platform_device *pdev)
2166 struct net_device *dev = platform_get_drvdata(pdev);
2168 device_set_wakeup_enable(&pdev->dev, false);
2169 device_set_wakeup_capable(&pdev->dev, false);
2170 unregister_flexcandev(dev);
2171 pm_runtime_disable(&pdev->dev);
2177 static int __maybe_unused flexcan_suspend(struct device *device)
2179 struct net_device *dev = dev_get_drvdata(device);
2180 struct flexcan_priv *priv = netdev_priv(dev);
2183 if (netif_running(dev)) {
2184 /* if wakeup is enabled, enter stop mode
2185 * else enter disabled mode.
2187 if (device_may_wakeup(device)) {
2188 enable_irq_wake(dev->irq);
2189 err = flexcan_enter_stop_mode(priv);
2193 err = flexcan_chip_stop(dev);
2197 flexcan_chip_interrupts_disable(dev);
2199 err = pinctrl_pm_select_sleep_state(device);
2203 netif_stop_queue(dev);
2204 netif_device_detach(dev);
2206 priv->can.state = CAN_STATE_SLEEPING;
2211 static int __maybe_unused flexcan_resume(struct device *device)
2213 struct net_device *dev = dev_get_drvdata(device);
2214 struct flexcan_priv *priv = netdev_priv(dev);
2217 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2218 if (netif_running(dev)) {
2219 netif_device_attach(dev);
2220 netif_start_queue(dev);
2221 if (device_may_wakeup(device)) {
2222 disable_irq_wake(dev->irq);
2223 err = flexcan_exit_stop_mode(priv);
2227 err = pinctrl_pm_select_default_state(device);
2231 err = flexcan_chip_start(dev);
2235 flexcan_chip_interrupts_enable(dev);
2242 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2244 struct net_device *dev = dev_get_drvdata(device);
2245 struct flexcan_priv *priv = netdev_priv(dev);
2247 flexcan_clks_disable(priv);
2252 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2254 struct net_device *dev = dev_get_drvdata(device);
2255 struct flexcan_priv *priv = netdev_priv(dev);
2257 return flexcan_clks_enable(priv);
2260 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2262 struct net_device *dev = dev_get_drvdata(device);
2263 struct flexcan_priv *priv = netdev_priv(dev);
2265 if (netif_running(dev)) {
2268 if (device_may_wakeup(device))
2269 flexcan_enable_wakeup_irq(priv, true);
2271 err = pm_runtime_force_suspend(device);
2279 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2281 struct net_device *dev = dev_get_drvdata(device);
2282 struct flexcan_priv *priv = netdev_priv(dev);
2284 if (netif_running(dev)) {
2287 err = pm_runtime_force_resume(device);
2291 if (device_may_wakeup(device))
2292 flexcan_enable_wakeup_irq(priv, false);
2298 static const struct dev_pm_ops flexcan_pm_ops = {
2299 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2300 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2301 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2304 static struct platform_driver flexcan_driver = {
2307 .pm = &flexcan_pm_ops,
2308 .of_match_table = flexcan_of_match,
2310 .probe = flexcan_probe,
2311 .remove = flexcan_remove,
2314 module_platform_driver(flexcan_driver);
2316 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2317 "Marc Kleine-Budde <kernel@pengutronix.de>");
2318 MODULE_LICENSE("GPL v2");
2319 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");