drivers/net/can/flexcan.c

   1 /*
   2  * flexcan.c - FLEXCAN CAN controller driver
   3  *
   4  * Copyright (c) 2005-2006 Varma Electronics Oy
   5  * Copyright (c) 2009 Sascha Hauer, Pengutronix
   6  * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   7  * Copyright (c) 2014 David Jander, Protonic Holland
   8  *
   9  * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  10  *
  11  * LICENCE:
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation version 2.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  */
  22
  23 #include <linux/netdevice.h>
  24 #include <linux/can.h>
  25 #include <linux/can/dev.h>
  26 #include <linux/can/error.h>
  27 #include <linux/can/led.h>
  28 #include <linux/can/rx-offload.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/io.h>
  33 #include <linux/module.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/regulator/consumer.h>
  38
  39 #define DRV_NAME                        "flexcan"
  40
  41 /* 8 for RX fifo and 2 error handling */
  42 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  43
  44 /* FLEXCAN module configuration register (CANMCR) bits */
  45 #define FLEXCAN_MCR_MDIS                BIT(31)
  46 #define FLEXCAN_MCR_FRZ                 BIT(30)
  47 #define FLEXCAN_MCR_FEN                 BIT(29)
  48 #define FLEXCAN_MCR_HALT                BIT(28)
  49 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  50 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  51 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  52 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  53 #define FLEXCAN_MCR_SUPV                BIT(23)
  54 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  55 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  56 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  57 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  58 #define FLEXCAN_MCR_DOZE                BIT(18)
  59 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  60 #define FLEXCAN_MCR_IRMQ                BIT(16)
  61 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  62 #define FLEXCAN_MCR_AEN                 BIT(12)
  63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  64 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  65 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  66 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  67 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  68 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  69
  70 /* FLEXCAN control register (CANCTRL) bits */
  71 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  72 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  73 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  74 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  75 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  76 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  77 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  78 #define FLEXCAN_CTRL_LPB                BIT(12)
  79 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  80 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  81 #define FLEXCAN_CTRL_SMP                BIT(7)
  82 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  83 #define FLEXCAN_CTRL_TSYN               BIT(5)
  84 #define FLEXCAN_CTRL_LBUF               BIT(4)
  85 #define FLEXCAN_CTRL_LOM                BIT(3)
  86 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  87 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  88 #define FLEXCAN_CTRL_ERR_STATE \
  89         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  90          FLEXCAN_CTRL_BOFF_MSK)
  91 #define FLEXCAN_CTRL_ERR_ALL \
  92         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  93
  94 /* FLEXCAN control register 2 (CTRL2) bits */
  95 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  96 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  97 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  98 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  99 #define FLEXCAN_CTRL2_MRP               BIT(18)
 100 #define FLEXCAN_CTRL2_RRS               BIT(17)
 101 #define FLEXCAN_CTRL2_EACEN             BIT(16)
 102
 103 /* FLEXCAN memory error control register (MECR) bits */
 104 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
 105 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
 106 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
 107 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 108 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 109 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 110 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 111 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 112 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 113 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 114
 115 /* FLEXCAN error and status register (ESR) bits */
 116 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 117 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 118 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 119 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 120 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 121 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 122 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 123 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 124 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 125 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 126 #define FLEXCAN_ESR_IDLE                BIT(7)
 127 #define FLEXCAN_ESR_TXRX                BIT(6)
 128 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 129 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 132 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 133 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 134 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 135 #define FLEXCAN_ESR_ERR_BUS \
 136         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 137          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 138          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 139 #define FLEXCAN_ESR_ERR_STATE \
 140         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 141 #define FLEXCAN_ESR_ERR_ALL \
 142         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 143 #define FLEXCAN_ESR_ALL_INT \
 144         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 145          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 146
 147 /* FLEXCAN interrupt flag register (IFLAG) bits */
 148 /* Errata ERR005829 step7: Reserve first valid MB */
 149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
 150 #define FLEXCAN_TX_MB_OFF_FIFO          9
 151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP             1
 153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
 154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST        63
 155 #define FLEXCAN_IFLAG_MB(x)             BIT(x)
 156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 157 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 159
 160 /* FLEXCAN message buffers */
 161 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 163 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 164 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 165 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 166 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 167 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 168
 169 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 170 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 171 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 172 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 173
 174 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 175 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 176 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 177 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 178 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 179
 180 #define FLEXCAN_TIMEOUT_US              (50)
 181
 182 /* FLEXCAN hardware feature flags
 183  *
 184  * Below is some version info we got:
 185  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 186  *                                Filter? connected?  Passive detection  ception in MB
 187  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 188  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 189  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 190  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 191  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 192  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 193  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 194  *
 195  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 196  */
 197 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 198 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 199 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 200 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 201 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 202 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 203
 204 /* Structure of the message buffer */
 205 struct flexcan_mb {
 206         u32 can_ctrl;
 207         u32 can_id;
 208         u32 data[2];
 209 };
 210
 211 /* Structure of the hardware registers */
 212 struct flexcan_regs {
 213         u32 mcr;                /* 0x00 */
 214         u32 ctrl;               /* 0x04 */
 215         u32 timer;              /* 0x08 */
 216         u32 _reserved1;         /* 0x0c */
 217         u32 rxgmask;            /* 0x10 */
 218         u32 rx14mask;           /* 0x14 */
 219         u32 rx15mask;           /* 0x18 */
 220         u32 ecr;                /* 0x1c */
 221         u32 esr;                /* 0x20 */
 222         u32 imask2;             /* 0x24 */
 223         u32 imask1;             /* 0x28 */
 224         u32 iflag2;             /* 0x2c */
 225         u32 iflag1;             /* 0x30 */
 226         union {                 /* 0x34 */
 227                 u32 gfwr_mx28;  /* MX28, MX53 */
 228                 u32 ctrl2;      /* MX6, VF610 */
 229         };
 230         u32 esr2;               /* 0x38 */
 231         u32 imeur;              /* 0x3c */
 232         u32 lrfr;               /* 0x40 */
 233         u32 crcr;               /* 0x44 */
 234         u32 rxfgmask;           /* 0x48 */
 235         u32 rxfir;              /* 0x4c */
 236         u32 _reserved3[12];     /* 0x50 */
 237         struct flexcan_mb mb[64];       /* 0x80 */
 238         /* FIFO-mode:
 239          *                      MB
 240          * 0x080...0x08f        0       RX message buffer
 241          * 0x090...0x0df        1-5     reserverd
 242          * 0x0e0...0x0ff        6-7     8 entry ID table
 243          *                              (mx25, mx28, mx35, mx53)
 244          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 245          *                              size conf'ed via ctrl2::RFFN
 246          *                              (mx6, vf610)
 247          */
 248         u32 _reserved4[256];    /* 0x480 */
 249         u32 rximr[64];          /* 0x880 */
 250         u32 _reserved5[24];     /* 0x980 */
 251         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 252         u32 _reserved6[63];     /* 0x9e4 */
 253         u32 mecr;               /* 0xae0 */
 254         u32 erriar;             /* 0xae4 */
 255         u32 erridpr;            /* 0xae8 */
 256         u32 errippr;            /* 0xaec */
 257         u32 rerrar;             /* 0xaf0 */
 258         u32 rerrdr;             /* 0xaf4 */
 259         u32 rerrsynr;           /* 0xaf8 */
 260         u32 errsr;              /* 0xafc */
 261 };
 262
 263 struct flexcan_devtype_data {
 264         u32 quirks;             /* quirks needed for different IP cores */
 265 };
 266
 267 struct flexcan_priv {
 268         struct can_priv can;
 269         struct can_rx_offload offload;
 270
 271         struct flexcan_regs __iomem *regs;
 272         struct flexcan_mb __iomem *tx_mb;
 273         struct flexcan_mb __iomem *tx_mb_reserved;
 274         u8 tx_mb_idx;
 275         u32 reg_ctrl_default;
 276         u32 reg_imask1_default;
 277         u32 reg_imask2_default;
 278
 279         struct clk *clk_ipg;
 280         struct clk *clk_per;
 281         const struct flexcan_devtype_data *devtype_data;
 282         struct regulator *reg_xceiver;
 283
 284         /* Read and Write APIs */
 285         u32 (*read)(void __iomem *addr);
 286         void (*write)(u32 val, void __iomem *addr);
 287 };
 288
 289 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 290         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 291                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 292 };
 293
 294 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 295         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 296 };
 297
 298 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 299         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 300                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 301 };
 302
 303 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 304         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 305                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 306                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 307 };
 308
 309 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 310         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 311                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 312                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 313 };
 314
 315 static const struct can_bittiming_const flexcan_bittiming_const = {
 316         .name = DRV_NAME,
 317         .tseg1_min = 4,
 318         .tseg1_max = 16,
 319         .tseg2_min = 2,
 320         .tseg2_max = 8,
 321         .sjw_max = 4,
 322         .brp_min = 1,
 323         .brp_max = 256,
 324         .brp_inc = 1,
 325 };
 326
 327 /* FlexCAN module is essentially modelled as a little-endian IP in most
 328  * SoCs, i.e the registers as well as the message buffer areas are
 329  * implemented in a little-endian fashion.
 330  *
 331  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 332  * module in a big-endian fashion (i.e the registers as well as the
 333  * message buffer areas are implemented in a big-endian way).
 334  *
 335  * In addition, the FlexCAN module can be found on SoCs having ARM or
 336  * PPC cores. So, we need to abstract off the register read/write
 337  * functions, ensuring that these cater to all the combinations of module
 338  * endianness and underlying CPU endianness.
 339  */
 340 static inline u32 flexcan_read_be(void __iomem *addr)
 341 {
 342         return ioread32be(addr);
 343 }
 344
 345 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 346 {
 347         iowrite32be(val, addr);
 348 }
 349
 350 static inline u32 flexcan_read_le(void __iomem *addr)
 351 {
 352         return ioread32(addr);
 353 }
 354
 355 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 356 {
 357         iowrite32(val, addr);
 358 }
 359
 360 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 361 {
 362         struct flexcan_regs __iomem *regs = priv->regs;
 363         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 364
 365         priv->write(reg_ctrl, &regs->ctrl);
 366 }
 367
 368 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 369 {
 370         struct flexcan_regs __iomem *regs = priv->regs;
 371         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 372
 373         priv->write(reg_ctrl, &regs->ctrl);
 374 }
 375
 376 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 377 {
 378         if (!priv->reg_xceiver)
 379                 return 0;
 380
 381         return regulator_enable(priv->reg_xceiver);
 382 }
 383
 384 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 385 {
 386         if (!priv->reg_xceiver)
 387                 return 0;
 388
 389         return regulator_disable(priv->reg_xceiver);
 390 }
 391
 392 static int flexcan_chip_enable(struct flexcan_priv *priv)
 393 {
 394         struct flexcan_regs __iomem *regs = priv->regs;
 395         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 396         u32 reg;
 397
 398         reg = priv->read(&regs->mcr);
 399         reg &= ~FLEXCAN_MCR_MDIS;
 400         priv->write(reg, &regs->mcr);
 401
 402         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 403                 udelay(10);
 404
 405         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 406                 return -ETIMEDOUT;
 407
 408         return 0;
 409 }
 410
 411 static int flexcan_chip_disable(struct flexcan_priv *priv)
 412 {
 413         struct flexcan_regs __iomem *regs = priv->regs;
 414         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 415         u32 reg;
 416
 417         reg = priv->read(&regs->mcr);
 418         reg |= FLEXCAN_MCR_MDIS;
 419         priv->write(reg, &regs->mcr);
 420
 421         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 422                 udelay(10);
 423
 424         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 425                 return -ETIMEDOUT;
 426
 427         return 0;
 428 }
 429
 430 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 431 {
 432         struct flexcan_regs __iomem *regs = priv->regs;
 433         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 434         u32 reg;
 435
 436         reg = priv->read(&regs->mcr);
 437         reg |= FLEXCAN_MCR_HALT;
 438         priv->write(reg, &regs->mcr);
 439
 440         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 441                 udelay(100);
 442
 443         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 444                 return -ETIMEDOUT;
 445
 446         return 0;
 447 }
 448
 449 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 450 {
 451         struct flexcan_regs __iomem *regs = priv->regs;
 452         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 453         u32 reg;
 454
 455         reg = priv->read(&regs->mcr);
 456         reg &= ~FLEXCAN_MCR_HALT;
 457         priv->write(reg, &regs->mcr);
 458
 459         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 460                 udelay(10);
 461
 462         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 463                 return -ETIMEDOUT;
 464
 465         return 0;
 466 }
 467
 468 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 469 {
 470         struct flexcan_regs __iomem *regs = priv->regs;
 471         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 472
 473         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 474         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 475                 udelay(10);
 476
 477         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 478                 return -ETIMEDOUT;
 479
 480         return 0;
 481 }
 482
 483 static int __flexcan_get_berr_counter(const struct net_device *dev,
 484                                       struct can_berr_counter *bec)
 485 {
 486         const struct flexcan_priv *priv = netdev_priv(dev);
 487         struct flexcan_regs __iomem *regs = priv->regs;
 488         u32 reg = priv->read(&regs->ecr);
 489
 490         bec->txerr = (reg >> 0) & 0xff;
 491         bec->rxerr = (reg >> 8) & 0xff;
 492
 493         return 0;
 494 }
 495
 496 static int flexcan_get_berr_counter(const struct net_device *dev,
 497                                     struct can_berr_counter *bec)
 498 {
 499         const struct flexcan_priv *priv = netdev_priv(dev);
 500         int err;
 501
 502         err = clk_prepare_enable(priv->clk_ipg);
 503         if (err)
 504                 return err;
 505
 506         err = clk_prepare_enable(priv->clk_per);
 507         if (err)
 508                 goto out_disable_ipg;
 509
 510         err = __flexcan_get_berr_counter(dev, bec);
 511
 512         clk_disable_unprepare(priv->clk_per);
 513  out_disable_ipg:
 514         clk_disable_unprepare(priv->clk_ipg);
 515
 516         return err;
 517 }
 518
 519 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 520 {
 521         const struct flexcan_priv *priv = netdev_priv(dev);
 522         struct can_frame *cf = (struct can_frame *)skb->data;
 523         u32 can_id;
 524         u32 data;
 525         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 526
 527         if (can_dropped_invalid_skb(dev, skb))
 528                 return NETDEV_TX_OK;
 529
 530         netif_stop_queue(dev);
 531
 532         if (cf->can_id & CAN_EFF_FLAG) {
 533                 can_id = cf->can_id & CAN_EFF_MASK;
 534                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 535         } else {
 536                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 537         }
 538
 539         if (cf->can_id & CAN_RTR_FLAG)
 540                 ctrl |= FLEXCAN_MB_CNT_RTR;
 541
 542         if (cf->can_dlc > 0) {
 543                 data = be32_to_cpup((__be32 *)&cf->data[0]);
 544                 priv->write(data, &priv->tx_mb->data[0]);
 545         }
 546         if (cf->can_dlc > 4) {
 547                 data = be32_to_cpup((__be32 *)&cf->data[4]);
 548                 priv->write(data, &priv->tx_mb->data[1]);
 549         }
 550
 551         can_put_echo_skb(skb, dev, 0);
 552
 553         priv->write(can_id, &priv->tx_mb->can_id);
 554         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 555
 556         /* Errata ERR005829 step8:
 557          * Write twice INACTIVE(0x8) code to first MB.
 558          */
 559         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 560                       &priv->tx_mb_reserved->can_ctrl);
 561         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 562                       &priv->tx_mb_reserved->can_ctrl);
 563
 564         return NETDEV_TX_OK;
 565 }
 566
 567 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 568 {
 569         struct flexcan_priv *priv = netdev_priv(dev);
 570         struct sk_buff *skb;
 571         struct can_frame *cf;
 572         bool rx_errors = false, tx_errors = false;
 573
 574         skb = alloc_can_err_skb(dev, &cf);
 575         if (unlikely(!skb))
 576                 return;
 577
 578         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 579
 580         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 581                 netdev_dbg(dev, "BIT1_ERR irq\n");
 582                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 583                 tx_errors = true;
 584         }
 585         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 586                 netdev_dbg(dev, "BIT0_ERR irq\n");
 587                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 588                 tx_errors = true;
 589         }
 590         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 591                 netdev_dbg(dev, "ACK_ERR irq\n");
 592                 cf->can_id |= CAN_ERR_ACK;
 593                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 594                 tx_errors = true;
 595         }
 596         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 597                 netdev_dbg(dev, "CRC_ERR irq\n");
 598                 cf->data[2] |= CAN_ERR_PROT_BIT;
 599                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 600                 rx_errors = true;
 601         }
 602         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 603                 netdev_dbg(dev, "FRM_ERR irq\n");
 604                 cf->data[2] |= CAN_ERR_PROT_FORM;
 605                 rx_errors = true;
 606         }
 607         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 608                 netdev_dbg(dev, "STF_ERR irq\n");
 609                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 610                 rx_errors = true;
 611         }
 612
 613         priv->can.can_stats.bus_error++;
 614         if (rx_errors)
 615                 dev->stats.rx_errors++;
 616         if (tx_errors)
 617                 dev->stats.tx_errors++;
 618
 619         can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
 620 }
 621
 622 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 623 {
 624         struct flexcan_priv *priv = netdev_priv(dev);
 625         struct sk_buff *skb;
 626         struct can_frame *cf;
 627         enum can_state new_state, rx_state, tx_state;
 628         int flt;
 629         struct can_berr_counter bec;
 630
 631         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 632         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 633                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 634                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 635                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 636                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 637                 new_state = max(tx_state, rx_state);
 638         } else {
 639                 __flexcan_get_berr_counter(dev, &bec);
 640                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 641                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 642                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 643                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 644         }
 645
 646         /* state hasn't changed */
 647         if (likely(new_state == priv->can.state))
 648                 return;
 649
 650         skb = alloc_can_err_skb(dev, &cf);
 651         if (unlikely(!skb))
 652                 return;
 653
 654         can_change_state(dev, cf, tx_state, rx_state);
 655
 656         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 657                 can_bus_off(dev);
 658
 659         can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
 660 }
 661
 662 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 663 {
 664         return container_of(offload, struct flexcan_priv, offload);
 665 }
 666
 667 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 668                                          struct can_frame *cf,
 669                                          u32 *timestamp, unsigned int n)
 670 {
 671         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 672         struct flexcan_regs __iomem *regs = priv->regs;
 673         struct flexcan_mb __iomem *mb = &regs->mb[n];
 674         u32 reg_ctrl, reg_id, reg_iflag1;
 675
 676         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 677                 u32 code;
 678
 679                 do {
 680                         reg_ctrl = priv->read(&mb->can_ctrl);
 681                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 682
 683                 /* is this MB empty? */
 684                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 685                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 686                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 687                         return 0;
 688
 689                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 690                         /* This MB was overrun, we lost data */
 691                         offload->dev->stats.rx_over_errors++;
 692                         offload->dev->stats.rx_errors++;
 693                 }
 694         } else {
 695                 reg_iflag1 = priv->read(&regs->iflag1);
 696                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 697                         return 0;
 698
 699                 reg_ctrl = priv->read(&mb->can_ctrl);
 700         }
 701
 702         /* increase timstamp to full 32 bit */
 703         *timestamp = reg_ctrl << 16;
 704
 705         reg_id = priv->read(&mb->can_id);
 706         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 707                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 708         else
 709                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 710
 711         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 712                 cf->can_id |= CAN_RTR_FLAG;
 713         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 714
 715         *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
 716         *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
 717
 718         /* mark as read */
 719         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 720                 /* Clear IRQ */
 721                 if (n < 32)
 722                         priv->write(BIT(n), &regs->iflag1);
 723                 else
 724                         priv->write(BIT(n - 32), &regs->iflag2);
 725         } else {
 726                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 727                 priv->read(&regs->timer);
 728         }
 729
 730         return 1;
 731 }
 732
 733
 734 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 735 {
 736         struct flexcan_regs __iomem *regs = priv->regs;
 737         u32 iflag1, iflag2;
 738
 739         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default;
 740         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default &
 741                 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 742
 743         return (u64)iflag2 << 32 | iflag1;
 744 }
 745
 746 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 747 {
 748         struct net_device *dev = dev_id;
 749         struct net_device_stats *stats = &dev->stats;
 750         struct flexcan_priv *priv = netdev_priv(dev);
 751         struct flexcan_regs __iomem *regs = priv->regs;
 752         irqreturn_t handled = IRQ_NONE;
 753         u32 reg_iflag1, reg_esr;
 754         enum can_state last_state = priv->can.state;
 755
 756         reg_iflag1 = priv->read(&regs->iflag1);
 757
 758         /* reception interrupt */
 759         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 760                 u64 reg_iflag;
 761                 int ret;
 762
 763                 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 764                         handled = IRQ_HANDLED;
 765                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 766                                                                    reg_iflag);
 767                         if (!ret)
 768                                 break;
 769                 }
 770         } else {
 771                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 772                         handled = IRQ_HANDLED;
 773                         can_rx_offload_irq_offload_fifo(&priv->offload);
 774                 }
 775
 776                 /* FIFO overflow interrupt */
 777                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 778                         handled = IRQ_HANDLED;
 779                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 780                                     &regs->iflag1);
 781                         dev->stats.rx_over_errors++;
 782                         dev->stats.rx_errors++;
 783                 }
 784         }
 785
 786         /* transmission complete interrupt */
 787         if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
 788                 handled = IRQ_HANDLED;
 789                 stats->tx_bytes += can_get_echo_skb(dev, 0);
 790                 stats->tx_packets++;
 791                 can_led_event(dev, CAN_LED_EVENT_TX);
 792
 793                 /* after sending a RTR frame MB is in RX mode */
 794                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 795                             &priv->tx_mb->can_ctrl);
 796                 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
 797                 netif_wake_queue(dev);
 798         }
 799
 800         reg_esr = priv->read(&regs->esr);
 801
 802         /* ACK all bus error and state change IRQ sources */
 803         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 804                 handled = IRQ_HANDLED;
 805                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 806         }
 807
 808         /* state change interrupt or broken error state quirk fix is enabled */
 809         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 810             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 811                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 812                 flexcan_irq_state(dev, reg_esr);
 813
 814         /* bus error IRQ - handle if bus error reporting is activated */
 815         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 816             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 817                 flexcan_irq_bus_err(dev, reg_esr);
 818
 819         /* availability of error interrupt among state transitions in case
 820          * bus error reporting is de-activated and
 821          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 822          *  +--------------------------------------------------------------+
 823          *  | +----------------------------------------------+ [stopped /  |
 824          *  | |                                              |  sleeping] -+
 825          *  +-+-> active <-> warning <-> passive -> bus off -+
 826          *        ___________^^^^^^^^^^^^_______________________________
 827          *        disabled(1)  enabled             disabled
 828          *
 829          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 830          */
 831         if ((last_state != priv->can.state) &&
 832             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 833             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 834                 switch (priv->can.state) {
 835                 case CAN_STATE_ERROR_ACTIVE:
 836                         if (priv->devtype_data->quirks &
 837                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 838                                 flexcan_error_irq_enable(priv);
 839                         else
 840                                 flexcan_error_irq_disable(priv);
 841                         break;
 842
 843                 case CAN_STATE_ERROR_WARNING:
 844                         flexcan_error_irq_enable(priv);
 845                         break;
 846
 847                 case CAN_STATE_ERROR_PASSIVE:
 848                 case CAN_STATE_BUS_OFF:
 849                         flexcan_error_irq_disable(priv);
 850                         break;
 851
 852                 default:
 853                         break;
 854                 }
 855         }
 856
 857         return handled;
 858 }
 859
 860 static void flexcan_set_bittiming(struct net_device *dev)
 861 {
 862         const struct flexcan_priv *priv = netdev_priv(dev);
 863         const struct can_bittiming *bt = &priv->can.bittiming;
 864         struct flexcan_regs __iomem *regs = priv->regs;
 865         u32 reg;
 866
 867         reg = priv->read(&regs->ctrl);
 868         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 869                  FLEXCAN_CTRL_RJW(0x3) |
 870                  FLEXCAN_CTRL_PSEG1(0x7) |
 871                  FLEXCAN_CTRL_PSEG2(0x7) |
 872                  FLEXCAN_CTRL_PROPSEG(0x7) |
 873                  FLEXCAN_CTRL_LPB |
 874                  FLEXCAN_CTRL_SMP |
 875                  FLEXCAN_CTRL_LOM);
 876
 877         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 878                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 879                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 880                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 881                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 882
 883         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 884                 reg |= FLEXCAN_CTRL_LPB;
 885         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 886                 reg |= FLEXCAN_CTRL_LOM;
 887         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 888                 reg |= FLEXCAN_CTRL_SMP;
 889
 890         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
 891         priv->write(reg, &regs->ctrl);
 892
 893         /* print chip status */
 894         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 895                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
 896 }
 897
 898 /* flexcan_chip_start
 899  *
 900  * this functions is entered with clocks enabled
 901  *
 902  */
 903 static int flexcan_chip_start(struct net_device *dev)
 904 {
 905         struct flexcan_priv *priv = netdev_priv(dev);
 906         struct flexcan_regs __iomem *regs = priv->regs;
 907         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
 908         int err, i;
 909
 910         /* enable module */
 911         err = flexcan_chip_enable(priv);
 912         if (err)
 913                 return err;
 914
 915         /* soft reset */
 916         err = flexcan_chip_softreset(priv);
 917         if (err)
 918                 goto out_chip_disable;
 919
 920         flexcan_set_bittiming(dev);
 921
 922         /* MCR
 923          *
 924          * enable freeze
 925          * enable fifo
 926          * halt now
 927          * only supervisor access
 928          * enable warning int
 929          * disable local echo
 930          * enable individual RX masking
 931          * choose format C
 932          * set max mailbox number
 933          */
 934         reg_mcr = priv->read(&regs->mcr);
 935         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 936         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
 937                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
 938                 FLEXCAN_MCR_IDAM_C;
 939
 940         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 941                 reg_mcr &= ~FLEXCAN_MCR_FEN;
 942                 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
 943         } else {
 944                 reg_mcr |= FLEXCAN_MCR_FEN |
 945                         FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
 946         }
 947         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 948         priv->write(reg_mcr, &regs->mcr);
 949
 950         /* CTRL
 951          *
 952          * disable timer sync feature
 953          *
 954          * disable auto busoff recovery
 955          * transmit lowest buffer first
 956          *
 957          * enable tx and rx warning interrupt
 958          * enable bus off interrupt
 959          * (== FLEXCAN_CTRL_ERR_STATE)
 960          */
 961         reg_ctrl = priv->read(&regs->ctrl);
 962         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 963         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 964                 FLEXCAN_CTRL_ERR_STATE;
 965
 966         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
 967          * on most Flexcan cores, too. Otherwise we don't get
 968          * any error warning or passive interrupts.
 969          */
 970         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
 971             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
 972                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
 973         else
 974                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
 975
 976         /* save for later use */
 977         priv->reg_ctrl_default = reg_ctrl;
 978         /* leave interrupts disabled for now */
 979         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
 980         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 981         priv->write(reg_ctrl, &regs->ctrl);
 982
 983         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
 984                 reg_ctrl2 = priv->read(&regs->ctrl2);
 985                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
 986                 priv->write(reg_ctrl2, &regs->ctrl2);
 987         }
 988
 989         /* clear and invalidate all mailboxes first */
 990         for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
 991                 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
 992                             &regs->mb[i].can_ctrl);
 993         }
 994
 995         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 996                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
 997                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
 998                                     &regs->mb[i].can_ctrl);
 999         }
1000
1001         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1002         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1003                     &priv->tx_mb_reserved->can_ctrl);
1004
1005         /* mark TX mailbox as INACTIVE */
1006         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1007                     &priv->tx_mb->can_ctrl);
1008
1009         /* acceptance mask/acceptance code (accept everything) */
1010         priv->write(0x0, &regs->rxgmask);
1011         priv->write(0x0, &regs->rx14mask);
1012         priv->write(0x0, &regs->rx15mask);
1013
1014         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1015                 priv->write(0x0, &regs->rxfgmask);
1016
1017         /* clear acceptance filters */
1018         for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1019                 priv->write(0, &regs->rximr[i]);
1020
1021         /* On Vybrid, disable memory error detection interrupts
1022          * and freeze mode.
1023          * This also works around errata e5295 which generates
1024          * false positive memory errors and put the device in
1025          * freeze mode.
1026          */
1027         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1028                 /* Follow the protocol as described in "Detection
1029                  * and Correction of Memory Errors" to write to
1030                  * MECR register
1031                  */
1032                 reg_ctrl2 = priv->read(&regs->ctrl2);
1033                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1034                 priv->write(reg_ctrl2, &regs->ctrl2);
1035
1036                 reg_mecr = priv->read(&regs->mecr);
1037                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1038                 priv->write(reg_mecr, &regs->mecr);
1039                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1040                               FLEXCAN_MECR_FANCEI_MSK);
1041                 priv->write(reg_mecr, &regs->mecr);
1042         }
1043
1044         err = flexcan_transceiver_enable(priv);
1045         if (err)
1046                 goto out_chip_disable;
1047
1048         /* synchronize with the can bus */
1049         err = flexcan_chip_unfreeze(priv);
1050         if (err)
1051                 goto out_transceiver_disable;
1052
1053         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1054
1055         /* enable interrupts atomically */
1056         disable_irq(dev->irq);
1057         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1058         priv->write(priv->reg_imask1_default, &regs->imask1);
1059         priv->write(priv->reg_imask2_default, &regs->imask2);
1060         enable_irq(dev->irq);
1061
1062         /* print chip status */
1063         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1064                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1065
1066         return 0;
1067
1068  out_transceiver_disable:
1069         flexcan_transceiver_disable(priv);
1070  out_chip_disable:
1071         flexcan_chip_disable(priv);
1072         return err;
1073 }
1074
1075 /* flexcan_chip_stop
1076  *
1077  * this functions is entered with clocks enabled
1078  */
1079 static void flexcan_chip_stop(struct net_device *dev)
1080 {
1081         struct flexcan_priv *priv = netdev_priv(dev);
1082         struct flexcan_regs __iomem *regs = priv->regs;
1083
1084         /* freeze + disable module */
1085         flexcan_chip_freeze(priv);
1086         flexcan_chip_disable(priv);
1087
1088         /* Disable all interrupts */
1089         priv->write(0, &regs->imask2);
1090         priv->write(0, &regs->imask1);
1091         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1092                     &regs->ctrl);
1093
1094         flexcan_transceiver_disable(priv);
1095         priv->can.state = CAN_STATE_STOPPED;
1096 }
1097
1098 static int flexcan_open(struct net_device *dev)
1099 {
1100         struct flexcan_priv *priv = netdev_priv(dev);
1101         int err;
1102
1103         err = clk_prepare_enable(priv->clk_ipg);
1104         if (err)
1105                 return err;
1106
1107         err = clk_prepare_enable(priv->clk_per);
1108         if (err)
1109                 goto out_disable_ipg;
1110
1111         err = open_candev(dev);
1112         if (err)
1113                 goto out_disable_per;
1114
1115         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1116         if (err)
1117                 goto out_close;
1118
1119         /* start chip and queuing */
1120         err = flexcan_chip_start(dev);
1121         if (err)
1122                 goto out_free_irq;
1123
1124         can_led_event(dev, CAN_LED_EVENT_OPEN);
1125
1126         can_rx_offload_enable(&priv->offload);
1127         netif_start_queue(dev);
1128
1129         return 0;
1130
1131  out_free_irq:
1132         free_irq(dev->irq, dev);
1133  out_close:
1134         close_candev(dev);
1135  out_disable_per:
1136         clk_disable_unprepare(priv->clk_per);
1137  out_disable_ipg:
1138         clk_disable_unprepare(priv->clk_ipg);
1139
1140         return err;
1141 }
1142
1143 static int flexcan_close(struct net_device *dev)
1144 {
1145         struct flexcan_priv *priv = netdev_priv(dev);
1146
1147         netif_stop_queue(dev);
1148         can_rx_offload_disable(&priv->offload);
1149         flexcan_chip_stop(dev);
1150
1151         free_irq(dev->irq, dev);
1152         clk_disable_unprepare(priv->clk_per);
1153         clk_disable_unprepare(priv->clk_ipg);
1154
1155         close_candev(dev);
1156
1157         can_led_event(dev, CAN_LED_EVENT_STOP);
1158
1159         return 0;
1160 }
1161
1162 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1163 {
1164         int err;
1165
1166         switch (mode) {
1167         case CAN_MODE_START:
1168                 err = flexcan_chip_start(dev);
1169                 if (err)
1170                         return err;
1171
1172                 netif_wake_queue(dev);
1173                 break;
1174
1175         default:
1176                 return -EOPNOTSUPP;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static const struct net_device_ops flexcan_netdev_ops = {
1183         .ndo_open       = flexcan_open,
1184         .ndo_stop       = flexcan_close,
1185         .ndo_start_xmit = flexcan_start_xmit,
1186         .ndo_change_mtu = can_change_mtu,
1187 };
1188
1189 static int register_flexcandev(struct net_device *dev)
1190 {
1191         struct flexcan_priv *priv = netdev_priv(dev);
1192         struct flexcan_regs __iomem *regs = priv->regs;
1193         u32 reg, err;
1194
1195         err = clk_prepare_enable(priv->clk_ipg);
1196         if (err)
1197                 return err;
1198
1199         err = clk_prepare_enable(priv->clk_per);
1200         if (err)
1201                 goto out_disable_ipg;
1202
1203         /* select "bus clock", chip must be disabled */
1204         err = flexcan_chip_disable(priv);
1205         if (err)
1206                 goto out_disable_per;
1207         reg = priv->read(&regs->ctrl);
1208         reg |= FLEXCAN_CTRL_CLK_SRC;
1209         priv->write(reg, &regs->ctrl);
1210
1211         err = flexcan_chip_enable(priv);
1212         if (err)
1213                 goto out_chip_disable;
1214
1215         /* set freeze, halt and activate FIFO, restrict register access */
1216         reg = priv->read(&regs->mcr);
1217         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1218                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1219         priv->write(reg, &regs->mcr);
1220
1221         /* Currently we only support newer versions of this core
1222          * featuring a RX hardware FIFO (although this driver doesn't
1223          * make use of it on some cores). Older cores, found on some
1224          * Coldfire derivates are not tested.
1225          */
1226         reg = priv->read(&regs->mcr);
1227         if (!(reg & FLEXCAN_MCR_FEN)) {
1228                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1229                 err = -ENODEV;
1230                 goto out_chip_disable;
1231         }
1232
1233         err = register_candev(dev);
1234
1235         /* disable core and turn off clocks */
1236  out_chip_disable:
1237         flexcan_chip_disable(priv);
1238  out_disable_per:
1239         clk_disable_unprepare(priv->clk_per);
1240  out_disable_ipg:
1241         clk_disable_unprepare(priv->clk_ipg);
1242
1243         return err;
1244 }
1245
1246 static void unregister_flexcandev(struct net_device *dev)
1247 {
1248         unregister_candev(dev);
1249 }
1250
1251 static const struct of_device_id flexcan_of_match[] = {
1252         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1253         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1254         { .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
1255         { .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
1256         { .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
1257         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1258         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1259         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1260         { /* sentinel */ },
1261 };
1262 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1263
1264 static const struct platform_device_id flexcan_id_table[] = {
1265         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1266         { /* sentinel */ },
1267 };
1268 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1269
1270 static int flexcan_probe(struct platform_device *pdev)
1271 {
1272         const struct of_device_id *of_id;
1273         const struct flexcan_devtype_data *devtype_data;
1274         struct net_device *dev;
1275         struct flexcan_priv *priv;
1276         struct regulator *reg_xceiver;
1277         struct resource *mem;
1278         struct clk *clk_ipg = NULL, *clk_per = NULL;
1279         struct flexcan_regs __iomem *regs;
1280         int err, irq;
1281         u32 clock_freq = 0;
1282
1283         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1284         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1285                 return -EPROBE_DEFER;
1286         else if (IS_ERR(reg_xceiver))
1287                 reg_xceiver = NULL;
1288
1289         if (pdev->dev.of_node)
1290                 of_property_read_u32(pdev->dev.of_node,
1291                                      "clock-frequency", &clock_freq);
1292
1293         if (!clock_freq) {
1294                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1295                 if (IS_ERR(clk_ipg)) {
1296                         dev_err(&pdev->dev, "no ipg clock defined\n");
1297                         return PTR_ERR(clk_ipg);
1298                 }
1299
1300                 clk_per = devm_clk_get(&pdev->dev, "per");
1301                 if (IS_ERR(clk_per)) {
1302                         dev_err(&pdev->dev, "no per clock defined\n");
1303                         return PTR_ERR(clk_per);
1304                 }
1305                 clock_freq = clk_get_rate(clk_per);
1306         }
1307
1308         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1309         irq = platform_get_irq(pdev, 0);
1310         if (irq <= 0)
1311                 return -ENODEV;
1312
1313         regs = devm_ioremap_resource(&pdev->dev, mem);
1314         if (IS_ERR(regs))
1315                 return PTR_ERR(regs);
1316
1317         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1318         if (of_id) {
1319                 devtype_data = of_id->data;
1320         } else if (platform_get_device_id(pdev)->driver_data) {
1321                 devtype_data = (struct flexcan_devtype_data *)
1322                         platform_get_device_id(pdev)->driver_data;
1323         } else {
1324                 return -ENODEV;
1325         }
1326
1327         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1328         if (!dev)
1329                 return -ENOMEM;
1330
1331         platform_set_drvdata(pdev, dev);
1332         SET_NETDEV_DEV(dev, &pdev->dev);
1333
1334         dev->netdev_ops = &flexcan_netdev_ops;
1335         dev->irq = irq;
1336         dev->flags |= IFF_ECHO;
1337
1338         priv = netdev_priv(dev);
1339
1340         if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
1341                 priv->read = flexcan_read_be;
1342                 priv->write = flexcan_write_be;
1343         } else {
1344                 if (of_device_is_compatible(pdev->dev.of_node,
1345                                             "fsl,p1010-flexcan")) {
1346                         priv->read = flexcan_read_be;
1347                         priv->write = flexcan_write_be;
1348                 } else {
1349                         priv->read = flexcan_read_le;
1350                         priv->write = flexcan_write_le;
1351                 }
1352         }
1353
1354         priv->can.clock.freq = clock_freq;
1355         priv->can.bittiming_const = &flexcan_bittiming_const;
1356         priv->can.do_set_mode = flexcan_set_mode;
1357         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1358         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1359                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1360                 CAN_CTRLMODE_BERR_REPORTING;
1361         priv->regs = regs;
1362         priv->clk_ipg = clk_ipg;
1363         priv->clk_per = clk_per;
1364         priv->devtype_data = devtype_data;
1365         priv->reg_xceiver = reg_xceiver;
1366
1367         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1368                 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1369                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1370         } else {
1371                 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1372                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1373         }
1374         priv->tx_mb = &regs->mb[priv->tx_mb_idx];
1375
1376         priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1377         priv->reg_imask2_default = 0;
1378
1379         priv->offload.mailbox_read = flexcan_mailbox_read;
1380
1381         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1382                 u64 imask;
1383
1384                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1385                 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1386
1387                 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1388                 priv->reg_imask1_default |= imask;
1389                 priv->reg_imask2_default |= imask >> 32;
1390
1391                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1392         } else {
1393                 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1394                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1395                 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1396         }
1397         if (err)
1398                 goto failed_offload;
1399
1400         err = register_flexcandev(dev);
1401         if (err) {
1402                 dev_err(&pdev->dev, "registering netdev failed\n");
1403                 goto failed_register;
1404         }
1405
1406         devm_can_led_init(dev);
1407
1408         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1409                  priv->regs, dev->irq);
1410
1411         return 0;
1412
1413  failed_offload:
1414  failed_register:
1415         free_candev(dev);
1416         return err;
1417 }
1418
1419 static int flexcan_remove(struct platform_device *pdev)
1420 {
1421         struct net_device *dev = platform_get_drvdata(pdev);
1422         struct flexcan_priv *priv = netdev_priv(dev);
1423
1424         unregister_flexcandev(dev);
1425         can_rx_offload_del(&priv->offload);
1426         free_candev(dev);
1427
1428         return 0;
1429 }
1430
1431 static int __maybe_unused flexcan_suspend(struct device *device)
1432 {
1433         struct net_device *dev = dev_get_drvdata(device);
1434         struct flexcan_priv *priv = netdev_priv(dev);
1435         int err;
1436
1437         if (netif_running(dev)) {
1438                 err = flexcan_chip_disable(priv);
1439                 if (err)
1440                         return err;
1441                 netif_stop_queue(dev);
1442                 netif_device_detach(dev);
1443         }
1444         priv->can.state = CAN_STATE_SLEEPING;
1445
1446         return 0;
1447 }
1448
1449 static int __maybe_unused flexcan_resume(struct device *device)
1450 {
1451         struct net_device *dev = dev_get_drvdata(device);
1452         struct flexcan_priv *priv = netdev_priv(dev);
1453         int err;
1454
1455         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1456         if (netif_running(dev)) {
1457                 netif_device_attach(dev);
1458                 netif_start_queue(dev);
1459                 err = flexcan_chip_enable(priv);
1460                 if (err)
1461                         return err;
1462         }
1463         return 0;
1464 }
1465
1466 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1467
1468 static struct platform_driver flexcan_driver = {
1469         .driver = {
1470                 .name = DRV_NAME,
1471                 .pm = &flexcan_pm_ops,
1472                 .of_match_table = flexcan_of_match,
1473         },
1474         .probe = flexcan_probe,
1475         .remove = flexcan_remove,
1476         .id_table = flexcan_id_table,
1477 };
1478
1479 module_platform_driver(flexcan_driver);
1480
1481 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1482               "Marc Kleine-Budde <kernel@pengutronix.de>");
1483 MODULE_LICENSE("GPL v2");
1484 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");