2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 #include <linux/netdevice.h>
24 #include <linux/can.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/can/rx-offload.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
33 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
39 #define DRV_NAME "flexcan"
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_IRMQ BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94 /* FLEXCAN control register 2 (CTRL2) bits */
95 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
96 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99 #define FLEXCAN_CTRL2_MRP BIT(18)
100 #define FLEXCAN_CTRL2_RRS BIT(17)
101 #define FLEXCAN_CTRL2_EACEN BIT(16)
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
147 /* FLEXCAN interrupt flag register (IFLAG) bits */
148 /* Errata ERR005829 step7: Reserve first valid MB */
149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150 #define FLEXCAN_TX_MB_OFF_FIFO 9
151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155 #define FLEXCAN_IFLAG_MB(x) BIT(x)
156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
169 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
174 #define FLEXCAN_MB_CNT_SRR BIT(22)
175 #define FLEXCAN_MB_CNT_IDE BIT(21)
176 #define FLEXCAN_MB_CNT_RTR BIT(20)
177 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
180 #define FLEXCAN_TIMEOUT_US (50)
182 /* FLEXCAN hardware feature flags
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
186 * Filter? connected? detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no
189 * MX35 FlexCAN2 03.00.00.00 no no no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
192 * VF610 FlexCAN3 ? no yes yes yes?
194 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
196 #define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
197 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
198 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
199 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
200 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
202 /* Structure of the message buffer */
209 /* Structure of the hardware registers */
210 struct flexcan_regs {
213 u32 timer; /* 0x08 */
214 u32 _reserved1; /* 0x0c */
215 u32 rxgmask; /* 0x10 */
216 u32 rx14mask; /* 0x14 */
217 u32 rx15mask; /* 0x18 */
220 u32 imask2; /* 0x24 */
221 u32 imask1; /* 0x28 */
222 u32 iflag2; /* 0x2c */
223 u32 iflag1; /* 0x30 */
225 u32 gfwr_mx28; /* MX28, MX53 */
226 u32 ctrl2; /* MX6, VF610 */
229 u32 imeur; /* 0x3c */
232 u32 rxfgmask; /* 0x48 */
233 u32 rxfir; /* 0x4c */
234 u32 _reserved3[12]; /* 0x50 */
235 struct flexcan_mb mb[64]; /* 0x80 */
238 * 0x080...0x08f 0 RX message buffer
239 * 0x090...0x0df 1-5 reserverd
240 * 0x0e0...0x0ff 6-7 8 entry ID table
241 * (mx25, mx28, mx35, mx53)
242 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
243 * size conf'ed via ctrl2::RFFN
246 u32 _reserved4[256]; /* 0x480 */
247 u32 rximr[64]; /* 0x880 */
248 u32 _reserved5[24]; /* 0x980 */
249 u32 gfwr_mx6; /* 0x9e0 - MX6 */
250 u32 _reserved6[63]; /* 0x9e4 */
251 u32 mecr; /* 0xae0 */
252 u32 erriar; /* 0xae4 */
253 u32 erridpr; /* 0xae8 */
254 u32 errippr; /* 0xaec */
255 u32 rerrar; /* 0xaf0 */
256 u32 rerrdr; /* 0xaf4 */
257 u32 rerrsynr; /* 0xaf8 */
258 u32 errsr; /* 0xafc */
261 struct flexcan_devtype_data {
262 u32 quirks; /* quirks needed for different IP cores */
265 struct flexcan_priv {
267 struct can_rx_offload offload;
269 struct flexcan_regs __iomem *regs;
270 struct flexcan_mb __iomem *tx_mb;
271 struct flexcan_mb __iomem *tx_mb_reserved;
273 u32 reg_ctrl_default;
274 u32 reg_imask1_default;
275 u32 reg_imask2_default;
279 const struct flexcan_devtype_data *devtype_data;
280 struct regulator *reg_xceiver;
283 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
284 .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
287 static const struct flexcan_devtype_data fsl_imx28_devtype_data;
289 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
290 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
291 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
294 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
295 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
296 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
299 static const struct can_bittiming_const flexcan_bittiming_const = {
311 /* Abstract off the read/write for arm versus ppc. This
312 * assumes that PPC uses big-endian registers and everything
313 * else uses little-endian registers, independent of CPU
316 #if defined(CONFIG_PPC)
317 static inline u32 flexcan_read(void __iomem *addr)
319 return in_be32(addr);
322 static inline void flexcan_write(u32 val, void __iomem *addr)
327 static inline u32 flexcan_read(void __iomem *addr)
332 static inline void flexcan_write(u32 val, void __iomem *addr)
338 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
340 if (!priv->reg_xceiver)
343 return regulator_enable(priv->reg_xceiver);
346 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
348 if (!priv->reg_xceiver)
351 return regulator_disable(priv->reg_xceiver);
354 static int flexcan_chip_enable(struct flexcan_priv *priv)
356 struct flexcan_regs __iomem *regs = priv->regs;
357 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
360 reg = flexcan_read(®s->mcr);
361 reg &= ~FLEXCAN_MCR_MDIS;
362 flexcan_write(reg, ®s->mcr);
364 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
367 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
373 static int flexcan_chip_disable(struct flexcan_priv *priv)
375 struct flexcan_regs __iomem *regs = priv->regs;
376 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
379 reg = flexcan_read(®s->mcr);
380 reg |= FLEXCAN_MCR_MDIS;
381 flexcan_write(reg, ®s->mcr);
383 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
386 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
392 static int flexcan_chip_freeze(struct flexcan_priv *priv)
394 struct flexcan_regs __iomem *regs = priv->regs;
395 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
398 reg = flexcan_read(®s->mcr);
399 reg |= FLEXCAN_MCR_HALT;
400 flexcan_write(reg, ®s->mcr);
402 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
405 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
411 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
413 struct flexcan_regs __iomem *regs = priv->regs;
414 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
417 reg = flexcan_read(®s->mcr);
418 reg &= ~FLEXCAN_MCR_HALT;
419 flexcan_write(reg, ®s->mcr);
421 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
424 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
430 static int flexcan_chip_softreset(struct flexcan_priv *priv)
432 struct flexcan_regs __iomem *regs = priv->regs;
433 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
435 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
436 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
439 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
445 static int __flexcan_get_berr_counter(const struct net_device *dev,
446 struct can_berr_counter *bec)
448 const struct flexcan_priv *priv = netdev_priv(dev);
449 struct flexcan_regs __iomem *regs = priv->regs;
450 u32 reg = flexcan_read(®s->ecr);
452 bec->txerr = (reg >> 0) & 0xff;
453 bec->rxerr = (reg >> 8) & 0xff;
458 static int flexcan_get_berr_counter(const struct net_device *dev,
459 struct can_berr_counter *bec)
461 const struct flexcan_priv *priv = netdev_priv(dev);
464 err = clk_prepare_enable(priv->clk_ipg);
468 err = clk_prepare_enable(priv->clk_per);
470 goto out_disable_ipg;
472 err = __flexcan_get_berr_counter(dev, bec);
474 clk_disable_unprepare(priv->clk_per);
476 clk_disable_unprepare(priv->clk_ipg);
481 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
483 const struct flexcan_priv *priv = netdev_priv(dev);
484 struct can_frame *cf = (struct can_frame *)skb->data;
487 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
489 if (can_dropped_invalid_skb(dev, skb))
492 netif_stop_queue(dev);
494 if (cf->can_id & CAN_EFF_FLAG) {
495 can_id = cf->can_id & CAN_EFF_MASK;
496 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
498 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
501 if (cf->can_id & CAN_RTR_FLAG)
502 ctrl |= FLEXCAN_MB_CNT_RTR;
504 if (cf->can_dlc > 0) {
505 data = be32_to_cpup((__be32 *)&cf->data[0]);
506 flexcan_write(data, &priv->tx_mb->data[0]);
508 if (cf->can_dlc > 3) {
509 data = be32_to_cpup((__be32 *)&cf->data[4]);
510 flexcan_write(data, &priv->tx_mb->data[1]);
513 can_put_echo_skb(skb, dev, 0);
515 flexcan_write(can_id, &priv->tx_mb->can_id);
516 flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
518 /* Errata ERR005829 step8:
519 * Write twice INACTIVE(0x8) code to first MB.
521 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
522 &priv->tx_mb_reserved->can_ctrl);
523 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
524 &priv->tx_mb_reserved->can_ctrl);
529 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
531 struct flexcan_priv *priv = netdev_priv(dev);
533 struct can_frame *cf;
534 bool rx_errors = false, tx_errors = false;
536 skb = alloc_can_err_skb(dev, &cf);
540 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
542 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
543 netdev_dbg(dev, "BIT1_ERR irq\n");
544 cf->data[2] |= CAN_ERR_PROT_BIT1;
547 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
548 netdev_dbg(dev, "BIT0_ERR irq\n");
549 cf->data[2] |= CAN_ERR_PROT_BIT0;
552 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
553 netdev_dbg(dev, "ACK_ERR irq\n");
554 cf->can_id |= CAN_ERR_ACK;
555 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
558 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
559 netdev_dbg(dev, "CRC_ERR irq\n");
560 cf->data[2] |= CAN_ERR_PROT_BIT;
561 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
564 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
565 netdev_dbg(dev, "FRM_ERR irq\n");
566 cf->data[2] |= CAN_ERR_PROT_FORM;
569 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
570 netdev_dbg(dev, "STF_ERR irq\n");
571 cf->data[2] |= CAN_ERR_PROT_STUFF;
575 priv->can.can_stats.bus_error++;
577 dev->stats.rx_errors++;
579 dev->stats.tx_errors++;
581 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
584 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
586 struct flexcan_priv *priv = netdev_priv(dev);
588 struct can_frame *cf;
589 enum can_state new_state, rx_state, tx_state;
591 struct can_berr_counter bec;
593 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
594 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
595 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
596 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
597 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
598 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
599 new_state = max(tx_state, rx_state);
601 __flexcan_get_berr_counter(dev, &bec);
602 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
603 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
604 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
605 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
608 /* state hasn't changed */
609 if (likely(new_state == priv->can.state))
612 skb = alloc_can_err_skb(dev, &cf);
616 can_change_state(dev, cf, tx_state, rx_state);
618 if (unlikely(new_state == CAN_STATE_BUS_OFF))
621 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
624 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
626 return container_of(offload, struct flexcan_priv, offload);
629 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
630 struct can_frame *cf,
631 u32 *timestamp, unsigned int n)
633 struct flexcan_priv *priv = rx_offload_to_priv(offload);
634 struct flexcan_regs __iomem *regs = priv->regs;
635 struct flexcan_mb __iomem *mb = ®s->mb[n];
636 u32 reg_ctrl, reg_id, reg_iflag1;
638 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
642 reg_ctrl = flexcan_read(&mb->can_ctrl);
643 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
645 /* is this MB empty? */
646 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
647 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
648 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
651 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
652 /* This MB was overrun, we lost data */
653 offload->dev->stats.rx_over_errors++;
654 offload->dev->stats.rx_errors++;
657 reg_iflag1 = flexcan_read(®s->iflag1);
658 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
661 reg_ctrl = flexcan_read(&mb->can_ctrl);
664 /* increase timstamp to full 32 bit */
665 *timestamp = reg_ctrl << 16;
667 reg_id = flexcan_read(&mb->can_id);
668 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
669 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
671 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
673 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
674 cf->can_id |= CAN_RTR_FLAG;
675 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
677 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
678 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
681 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
684 flexcan_write(BIT(n), ®s->iflag1);
686 flexcan_write(BIT(n - 32), ®s->iflag2);
688 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
689 flexcan_read(®s->timer);
696 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
698 struct flexcan_regs __iomem *regs = priv->regs;
701 iflag2 = flexcan_read(®s->iflag2) & priv->reg_imask2_default;
702 iflag1 = flexcan_read(®s->iflag1) & priv->reg_imask1_default &
703 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
705 return (u64)iflag2 << 32 | iflag1;
708 static irqreturn_t flexcan_irq(int irq, void *dev_id)
710 struct net_device *dev = dev_id;
711 struct net_device_stats *stats = &dev->stats;
712 struct flexcan_priv *priv = netdev_priv(dev);
713 struct flexcan_regs __iomem *regs = priv->regs;
714 irqreturn_t handled = IRQ_NONE;
715 u32 reg_iflag1, reg_esr;
717 reg_iflag1 = flexcan_read(®s->iflag1);
719 /* reception interrupt */
720 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
724 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
725 handled = IRQ_HANDLED;
726 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
732 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
733 handled = IRQ_HANDLED;
734 can_rx_offload_irq_offload_fifo(&priv->offload);
737 /* FIFO overflow interrupt */
738 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
739 handled = IRQ_HANDLED;
740 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
741 dev->stats.rx_over_errors++;
742 dev->stats.rx_errors++;
746 /* transmission complete interrupt */
747 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
748 handled = IRQ_HANDLED;
749 stats->tx_bytes += can_get_echo_skb(dev, 0);
751 can_led_event(dev, CAN_LED_EVENT_TX);
753 /* after sending a RTR frame MB is in RX mode */
754 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
755 &priv->tx_mb->can_ctrl);
756 flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
757 netif_wake_queue(dev);
760 reg_esr = flexcan_read(®s->esr);
762 /* ACK all bus error and state change IRQ sources */
763 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
764 handled = IRQ_HANDLED;
765 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
768 /* state change interrupt */
769 if (reg_esr & FLEXCAN_ESR_ERR_STATE)
770 flexcan_irq_state(dev, reg_esr);
772 /* bus error IRQ - handle if bus error reporting is activated */
773 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
774 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
775 flexcan_irq_bus_err(dev, reg_esr);
780 static void flexcan_set_bittiming(struct net_device *dev)
782 const struct flexcan_priv *priv = netdev_priv(dev);
783 const struct can_bittiming *bt = &priv->can.bittiming;
784 struct flexcan_regs __iomem *regs = priv->regs;
787 reg = flexcan_read(®s->ctrl);
788 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
789 FLEXCAN_CTRL_RJW(0x3) |
790 FLEXCAN_CTRL_PSEG1(0x7) |
791 FLEXCAN_CTRL_PSEG2(0x7) |
792 FLEXCAN_CTRL_PROPSEG(0x7) |
797 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
798 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
799 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
800 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
801 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
803 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
804 reg |= FLEXCAN_CTRL_LPB;
805 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
806 reg |= FLEXCAN_CTRL_LOM;
807 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
808 reg |= FLEXCAN_CTRL_SMP;
810 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
811 flexcan_write(reg, ®s->ctrl);
813 /* print chip status */
814 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
815 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
818 /* flexcan_chip_start
820 * this functions is entered with clocks enabled
823 static int flexcan_chip_start(struct net_device *dev)
825 struct flexcan_priv *priv = netdev_priv(dev);
826 struct flexcan_regs __iomem *regs = priv->regs;
827 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
831 err = flexcan_chip_enable(priv);
836 err = flexcan_chip_softreset(priv);
838 goto out_chip_disable;
840 flexcan_set_bittiming(dev);
847 * only supervisor access
850 * enable individual RX masking
852 * set max mailbox number
854 reg_mcr = flexcan_read(®s->mcr);
855 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
856 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
857 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
860 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
861 reg_mcr &= ~FLEXCAN_MCR_FEN;
862 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
864 reg_mcr |= FLEXCAN_MCR_FEN |
865 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
867 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
868 flexcan_write(reg_mcr, ®s->mcr);
872 * disable timer sync feature
874 * disable auto busoff recovery
875 * transmit lowest buffer first
877 * enable tx and rx warning interrupt
878 * enable bus off interrupt
879 * (== FLEXCAN_CTRL_ERR_STATE)
881 reg_ctrl = flexcan_read(®s->ctrl);
882 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
883 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
884 FLEXCAN_CTRL_ERR_STATE;
886 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
887 * on most Flexcan cores, too. Otherwise we don't get
888 * any error warning or passive interrupts.
890 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
891 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
892 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
894 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
896 /* save for later use */
897 priv->reg_ctrl_default = reg_ctrl;
898 /* leave interrupts disabled for now */
899 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
900 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
901 flexcan_write(reg_ctrl, ®s->ctrl);
903 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
904 reg_ctrl2 = flexcan_read(®s->ctrl2);
905 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
906 flexcan_write(reg_ctrl2, ®s->ctrl2);
909 /* clear and invalidate all mailboxes first */
910 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
911 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
912 ®s->mb[i].can_ctrl);
915 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
916 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
917 flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
918 ®s->mb[i].can_ctrl);
921 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
922 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
923 &priv->tx_mb_reserved->can_ctrl);
925 /* mark TX mailbox as INACTIVE */
926 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
927 &priv->tx_mb->can_ctrl);
929 /* acceptance mask/acceptance code (accept everything) */
930 flexcan_write(0x0, ®s->rxgmask);
931 flexcan_write(0x0, ®s->rx14mask);
932 flexcan_write(0x0, ®s->rx15mask);
934 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
935 flexcan_write(0x0, ®s->rxfgmask);
937 /* clear acceptance filters */
938 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
939 flexcan_write(0, ®s->rximr[i]);
941 /* On Vybrid, disable memory error detection interrupts
943 * This also works around errata e5295 which generates
944 * false positive memory errors and put the device in
947 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
948 /* Follow the protocol as described in "Detection
949 * and Correction of Memory Errors" to write to
952 reg_ctrl2 = flexcan_read(®s->ctrl2);
953 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
954 flexcan_write(reg_ctrl2, ®s->ctrl2);
956 reg_mecr = flexcan_read(®s->mecr);
957 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
958 flexcan_write(reg_mecr, ®s->mecr);
959 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
960 FLEXCAN_MECR_FANCEI_MSK);
961 flexcan_write(reg_mecr, ®s->mecr);
964 err = flexcan_transceiver_enable(priv);
966 goto out_chip_disable;
968 /* synchronize with the can bus */
969 err = flexcan_chip_unfreeze(priv);
971 goto out_transceiver_disable;
973 priv->can.state = CAN_STATE_ERROR_ACTIVE;
975 /* enable interrupts atomically */
976 disable_irq(dev->irq);
977 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
978 flexcan_write(priv->reg_imask1_default, ®s->imask1);
979 flexcan_write(priv->reg_imask2_default, ®s->imask2);
980 enable_irq(dev->irq);
982 /* print chip status */
983 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
984 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
988 out_transceiver_disable:
989 flexcan_transceiver_disable(priv);
991 flexcan_chip_disable(priv);
997 * this functions is entered with clocks enabled
999 static void flexcan_chip_stop(struct net_device *dev)
1001 struct flexcan_priv *priv = netdev_priv(dev);
1002 struct flexcan_regs __iomem *regs = priv->regs;
1004 /* freeze + disable module */
1005 flexcan_chip_freeze(priv);
1006 flexcan_chip_disable(priv);
1008 /* Disable all interrupts */
1009 flexcan_write(0, ®s->imask2);
1010 flexcan_write(0, ®s->imask1);
1011 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1014 flexcan_transceiver_disable(priv);
1015 priv->can.state = CAN_STATE_STOPPED;
1018 static int flexcan_open(struct net_device *dev)
1020 struct flexcan_priv *priv = netdev_priv(dev);
1023 err = clk_prepare_enable(priv->clk_ipg);
1027 err = clk_prepare_enable(priv->clk_per);
1029 goto out_disable_ipg;
1031 err = open_candev(dev);
1033 goto out_disable_per;
1035 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1039 /* start chip and queuing */
1040 err = flexcan_chip_start(dev);
1044 can_led_event(dev, CAN_LED_EVENT_OPEN);
1046 can_rx_offload_enable(&priv->offload);
1047 netif_start_queue(dev);
1052 free_irq(dev->irq, dev);
1056 clk_disable_unprepare(priv->clk_per);
1058 clk_disable_unprepare(priv->clk_ipg);
1063 static int flexcan_close(struct net_device *dev)
1065 struct flexcan_priv *priv = netdev_priv(dev);
1067 netif_stop_queue(dev);
1068 can_rx_offload_disable(&priv->offload);
1069 flexcan_chip_stop(dev);
1071 free_irq(dev->irq, dev);
1072 clk_disable_unprepare(priv->clk_per);
1073 clk_disable_unprepare(priv->clk_ipg);
1077 can_led_event(dev, CAN_LED_EVENT_STOP);
1082 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1087 case CAN_MODE_START:
1088 err = flexcan_chip_start(dev);
1092 netif_wake_queue(dev);
1102 static const struct net_device_ops flexcan_netdev_ops = {
1103 .ndo_open = flexcan_open,
1104 .ndo_stop = flexcan_close,
1105 .ndo_start_xmit = flexcan_start_xmit,
1106 .ndo_change_mtu = can_change_mtu,
1109 static int register_flexcandev(struct net_device *dev)
1111 struct flexcan_priv *priv = netdev_priv(dev);
1112 struct flexcan_regs __iomem *regs = priv->regs;
1115 err = clk_prepare_enable(priv->clk_ipg);
1119 err = clk_prepare_enable(priv->clk_per);
1121 goto out_disable_ipg;
1123 /* select "bus clock", chip must be disabled */
1124 err = flexcan_chip_disable(priv);
1126 goto out_disable_per;
1127 reg = flexcan_read(®s->ctrl);
1128 reg |= FLEXCAN_CTRL_CLK_SRC;
1129 flexcan_write(reg, ®s->ctrl);
1131 err = flexcan_chip_enable(priv);
1133 goto out_chip_disable;
1135 /* set freeze, halt and activate FIFO, restrict register access */
1136 reg = flexcan_read(®s->mcr);
1137 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1138 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1139 flexcan_write(reg, ®s->mcr);
1141 /* Currently we only support newer versions of this core
1142 * featuring a RX hardware FIFO (although this driver doesn't
1143 * make use of it on some cores). Older cores, found on some
1144 * Coldfire derivates are not tested.
1146 reg = flexcan_read(®s->mcr);
1147 if (!(reg & FLEXCAN_MCR_FEN)) {
1148 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1150 goto out_chip_disable;
1153 err = register_candev(dev);
1155 /* disable core and turn off clocks */
1157 flexcan_chip_disable(priv);
1159 clk_disable_unprepare(priv->clk_per);
1161 clk_disable_unprepare(priv->clk_ipg);
1166 static void unregister_flexcandev(struct net_device *dev)
1168 unregister_candev(dev);
1171 static const struct of_device_id flexcan_of_match[] = {
1172 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1173 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1174 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1175 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1178 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1180 static const struct platform_device_id flexcan_id_table[] = {
1181 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1184 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1186 static int flexcan_probe(struct platform_device *pdev)
1188 const struct of_device_id *of_id;
1189 const struct flexcan_devtype_data *devtype_data;
1190 struct net_device *dev;
1191 struct flexcan_priv *priv;
1192 struct regulator *reg_xceiver;
1193 struct resource *mem;
1194 struct clk *clk_ipg = NULL, *clk_per = NULL;
1195 struct flexcan_regs __iomem *regs;
1199 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1200 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1201 return -EPROBE_DEFER;
1202 else if (IS_ERR(reg_xceiver))
1205 if (pdev->dev.of_node)
1206 of_property_read_u32(pdev->dev.of_node,
1207 "clock-frequency", &clock_freq);
1210 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1211 if (IS_ERR(clk_ipg)) {
1212 dev_err(&pdev->dev, "no ipg clock defined\n");
1213 return PTR_ERR(clk_ipg);
1216 clk_per = devm_clk_get(&pdev->dev, "per");
1217 if (IS_ERR(clk_per)) {
1218 dev_err(&pdev->dev, "no per clock defined\n");
1219 return PTR_ERR(clk_per);
1221 clock_freq = clk_get_rate(clk_per);
1224 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1225 irq = platform_get_irq(pdev, 0);
1229 regs = devm_ioremap_resource(&pdev->dev, mem);
1231 return PTR_ERR(regs);
1233 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1235 devtype_data = of_id->data;
1236 } else if (platform_get_device_id(pdev)->driver_data) {
1237 devtype_data = (struct flexcan_devtype_data *)
1238 platform_get_device_id(pdev)->driver_data;
1243 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1247 platform_set_drvdata(pdev, dev);
1248 SET_NETDEV_DEV(dev, &pdev->dev);
1250 dev->netdev_ops = &flexcan_netdev_ops;
1252 dev->flags |= IFF_ECHO;
1254 priv = netdev_priv(dev);
1255 priv->can.clock.freq = clock_freq;
1256 priv->can.bittiming_const = &flexcan_bittiming_const;
1257 priv->can.do_set_mode = flexcan_set_mode;
1258 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1259 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1260 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1261 CAN_CTRLMODE_BERR_REPORTING;
1263 priv->clk_ipg = clk_ipg;
1264 priv->clk_per = clk_per;
1265 priv->devtype_data = devtype_data;
1266 priv->reg_xceiver = reg_xceiver;
1268 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1269 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1270 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1272 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1273 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1275 priv->tx_mb = ®s->mb[priv->tx_mb_idx];
1277 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1278 priv->reg_imask2_default = 0;
1280 priv->offload.mailbox_read = flexcan_mailbox_read;
1282 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1285 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1286 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1288 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1289 priv->reg_imask1_default |= imask;
1290 priv->reg_imask2_default |= imask >> 32;
1292 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1294 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1295 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1296 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1299 goto failed_offload;
1301 err = register_flexcandev(dev);
1303 dev_err(&pdev->dev, "registering netdev failed\n");
1304 goto failed_register;
1307 devm_can_led_init(dev);
1309 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1310 priv->regs, dev->irq);
1320 static int flexcan_remove(struct platform_device *pdev)
1322 struct net_device *dev = platform_get_drvdata(pdev);
1323 struct flexcan_priv *priv = netdev_priv(dev);
1325 unregister_flexcandev(dev);
1326 can_rx_offload_del(&priv->offload);
1332 static int __maybe_unused flexcan_suspend(struct device *device)
1334 struct net_device *dev = dev_get_drvdata(device);
1335 struct flexcan_priv *priv = netdev_priv(dev);
1338 if (netif_running(dev)) {
1339 err = flexcan_chip_disable(priv);
1342 netif_stop_queue(dev);
1343 netif_device_detach(dev);
1345 priv->can.state = CAN_STATE_SLEEPING;
1350 static int __maybe_unused flexcan_resume(struct device *device)
1352 struct net_device *dev = dev_get_drvdata(device);
1353 struct flexcan_priv *priv = netdev_priv(dev);
1356 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1357 if (netif_running(dev)) {
1358 netif_device_attach(dev);
1359 netif_start_queue(dev);
1360 err = flexcan_chip_enable(priv);
1367 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1369 static struct platform_driver flexcan_driver = {
1372 .pm = &flexcan_pm_ops,
1373 .of_match_table = flexcan_of_match,
1375 .probe = flexcan_probe,
1376 .remove = flexcan_remove,
1377 .id_table = flexcan_id_table,
1380 module_platform_driver(flexcan_driver);
1382 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1383 "Marc Kleine-Budde <kernel@pengutronix.de>");
1384 MODULE_LICENSE("GPL v2");
1385 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");