1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 #include <dt-bindings/firmware/imx/rsrc.h>
13 #include <linux/bitfield.h>
14 #include <linux/can.h>
15 #include <linux/can/dev.h>
16 #include <linux/can/error.h>
17 #include <linux/can/led.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/firmware/imx/sci.h>
21 #include <linux/interrupt.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/netdevice.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_device.h>
30 #include <linux/can/platform/flexcan.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/regulator/consumer.h>
37 #define DRV_NAME "flexcan"
39 /* 8 for RX fifo and 2 error handling */
40 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
42 /* FLEXCAN module configuration register (CANMCR) bits */
43 #define FLEXCAN_MCR_MDIS BIT(31)
44 #define FLEXCAN_MCR_FRZ BIT(30)
45 #define FLEXCAN_MCR_FEN BIT(29)
46 #define FLEXCAN_MCR_HALT BIT(28)
47 #define FLEXCAN_MCR_NOT_RDY BIT(27)
48 #define FLEXCAN_MCR_WAK_MSK BIT(26)
49 #define FLEXCAN_MCR_SOFTRST BIT(25)
50 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
51 #define FLEXCAN_MCR_SUPV BIT(23)
52 #define FLEXCAN_MCR_SLF_WAK BIT(22)
53 #define FLEXCAN_MCR_WRN_EN BIT(21)
54 #define FLEXCAN_MCR_LPM_ACK BIT(20)
55 #define FLEXCAN_MCR_WAK_SRC BIT(19)
56 #define FLEXCAN_MCR_DOZE BIT(18)
57 #define FLEXCAN_MCR_SRX_DIS BIT(17)
58 #define FLEXCAN_MCR_IRMQ BIT(16)
59 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
60 #define FLEXCAN_MCR_AEN BIT(12)
61 #define FLEXCAN_MCR_FDEN BIT(11)
62 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
63 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
64 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
65 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
66 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
67 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69 /* FLEXCAN control register (CANCTRL) bits */
70 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
71 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
72 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
73 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
74 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
75 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
76 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
77 #define FLEXCAN_CTRL_LPB BIT(12)
78 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
79 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
80 #define FLEXCAN_CTRL_SMP BIT(7)
81 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
82 #define FLEXCAN_CTRL_TSYN BIT(5)
83 #define FLEXCAN_CTRL_LBUF BIT(4)
84 #define FLEXCAN_CTRL_LOM BIT(3)
85 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
86 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
87 #define FLEXCAN_CTRL_ERR_STATE \
88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
89 FLEXCAN_CTRL_BOFF_MSK)
90 #define FLEXCAN_CTRL_ERR_ALL \
91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93 /* FLEXCAN control register 2 (CTRL2) bits */
94 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
95 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
96 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
97 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
98 #define FLEXCAN_CTRL2_MRP BIT(18)
99 #define FLEXCAN_CTRL2_RRS BIT(17)
100 #define FLEXCAN_CTRL2_EACEN BIT(16)
101 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
147 /* FLEXCAN Bit Timing register (CBT) bits */
148 #define FLEXCAN_CBT_BTF BIT(31)
149 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
150 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
151 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
152 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
153 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
155 /* FLEXCAN FD control register (FDCTRL) bits */
156 #define FLEXCAN_FDCTRL_FDRATE BIT(31)
157 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
158 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
159 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
160 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
161 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
162 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
163 #define FLEXCAN_FDCTRL_TDCEN BIT(15)
164 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
165 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
166 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
168 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
169 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
170 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
171 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
172 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
173 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
175 /* FLEXCAN interrupt flag register (IFLAG) bits */
176 /* Errata ERR005829 step7: Reserve first valid MB */
177 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8
178 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0
179 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
180 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
181 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
182 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
183 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
185 /* FLEXCAN message buffers */
186 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
187 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
188 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
189 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
190 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
191 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
192 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
194 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
195 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
196 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
197 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
199 #define FLEXCAN_MB_CNT_EDL BIT(31)
200 #define FLEXCAN_MB_CNT_BRS BIT(30)
201 #define FLEXCAN_MB_CNT_ESI BIT(29)
202 #define FLEXCAN_MB_CNT_SRR BIT(22)
203 #define FLEXCAN_MB_CNT_IDE BIT(21)
204 #define FLEXCAN_MB_CNT_RTR BIT(20)
205 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
206 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
208 #define FLEXCAN_TIMEOUT_US (250)
210 /* Structure of the message buffer */
217 /* Structure of the hardware registers */
218 struct flexcan_regs {
220 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
221 u32 timer; /* 0x08 */
223 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
224 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
225 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
228 u32 imask2; /* 0x24 */
229 u32 imask1; /* 0x28 */
230 u32 iflag2; /* 0x2c */
231 u32 iflag1; /* 0x30 */
233 u32 gfwr_mx28; /* MX28, MX53 */
234 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
237 u32 imeur; /* 0x3c */
240 u32 rxfgmask; /* 0x48 */
241 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
242 u32 cbt; /* 0x50 - Not affected by Soft Reset */
243 u32 _reserved2; /* 0x54 */
246 u32 _reserved3[8]; /* 0x60 */
248 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
251 * 0x080...0x08f 0 RX message buffer
252 * 0x090...0x0df 1-5 reserved
253 * 0x0e0...0x0ff 6-7 8 entry ID table
254 * (mx25, mx28, mx35, mx53)
255 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
256 * size conf'ed via ctrl2::RFFN
259 u32 _reserved4[256]; /* 0x480 */
260 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
261 u32 _reserved5[24]; /* 0x980 */
262 u32 gfwr_mx6; /* 0x9e0 - MX6 */
263 u32 _reserved6[39]; /* 0x9e4 */
264 u32 _rxfir[6]; /* 0xa80 */
265 u32 _reserved8[2]; /* 0xa98 */
266 u32 _rxmgmask; /* 0xaa0 */
267 u32 _rxfgmask; /* 0xaa4 */
268 u32 _rx14mask; /* 0xaa8 */
269 u32 _rx15mask; /* 0xaac */
270 u32 tx_smb[4]; /* 0xab0 */
271 u32 rx_smb0[4]; /* 0xac0 */
272 u32 rx_smb1[4]; /* 0xad0 */
274 u32 mecr; /* 0xae0 */
275 u32 erriar; /* 0xae4 */
276 u32 erridpr; /* 0xae8 */
277 u32 errippr; /* 0xaec */
278 u32 rerrar; /* 0xaf0 */
279 u32 rerrdr; /* 0xaf4 */
280 u32 rerrsynr; /* 0xaf8 */
281 u32 errsr; /* 0xafc */
282 u32 _reserved7[64]; /* 0xb00 */
283 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
284 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
285 u32 fdcrc; /* 0xc08 */
286 u32 _reserved9[199]; /* 0xc0c */
287 struct_group(init_fd,
288 u32 tx_smb_fd[18]; /* 0xf28 */
289 u32 rx_smb0_fd[18]; /* 0xf70 */
290 u32 rx_smb1_fd[18]; /* 0xfb8 */
294 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
296 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
297 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
299 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
300 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
303 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
304 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
305 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
306 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
307 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
308 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
311 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
312 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
313 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
314 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
315 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
318 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
319 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
320 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
321 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
324 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
325 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
326 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
327 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
328 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
329 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
332 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
333 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
334 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
335 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
336 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
337 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
340 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
341 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
342 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
343 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
344 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
345 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
346 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
349 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
350 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
351 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
352 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
353 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
354 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
357 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
358 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
359 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
360 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
361 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
364 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
365 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
366 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
367 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
368 FLEXCAN_QUIRK_SUPPORT_ECC |
369 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
370 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
373 static const struct can_bittiming_const flexcan_bittiming_const = {
385 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
397 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
409 /* FlexCAN module is essentially modelled as a little-endian IP in most
410 * SoCs, i.e the registers as well as the message buffer areas are
411 * implemented in a little-endian fashion.
413 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
414 * module in a big-endian fashion (i.e the registers as well as the
415 * message buffer areas are implemented in a big-endian way).
417 * In addition, the FlexCAN module can be found on SoCs having ARM or
418 * PPC cores. So, we need to abstract off the register read/write
419 * functions, ensuring that these cater to all the combinations of module
420 * endianness and underlying CPU endianness.
422 static inline u32 flexcan_read_be(void __iomem *addr)
424 return ioread32be(addr);
427 static inline void flexcan_write_be(u32 val, void __iomem *addr)
429 iowrite32be(val, addr);
432 static inline u32 flexcan_read_le(void __iomem *addr)
434 return ioread32(addr);
437 static inline void flexcan_write_le(u32 val, void __iomem *addr)
439 iowrite32(val, addr);
442 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
448 if (WARN_ON(mb_index >= priv->mb_count))
451 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
453 bank = mb_index >= bank_size;
455 mb_index -= bank_size;
457 return (struct flexcan_mb __iomem *)
458 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
461 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
463 struct flexcan_regs __iomem *regs = priv->regs;
464 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
466 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
469 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
475 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
477 struct flexcan_regs __iomem *regs = priv->regs;
478 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
480 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
483 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
489 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
491 struct flexcan_regs __iomem *regs = priv->regs;
494 reg_mcr = priv->read(®s->mcr);
497 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
499 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
501 priv->write(reg_mcr, ®s->mcr);
504 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
506 u8 idx = priv->scu_idx;
509 rsrc_id = IMX_SC_R_CAN(idx);
516 /* stop mode request via scu firmware */
517 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
518 IMX_SC_C_IPG_STOP, val);
521 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
523 struct flexcan_regs __iomem *regs = priv->regs;
527 reg_mcr = priv->read(®s->mcr);
528 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
529 priv->write(reg_mcr, ®s->mcr);
531 /* enable stop request */
532 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
533 ret = flexcan_stop_mode_enable_scfw(priv, true);
537 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
538 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
541 return flexcan_low_power_enter_ack(priv);
544 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
546 struct flexcan_regs __iomem *regs = priv->regs;
550 /* remove stop request */
551 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
552 ret = flexcan_stop_mode_enable_scfw(priv, false);
556 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
557 1 << priv->stm.req_bit, 0);
560 reg_mcr = priv->read(®s->mcr);
561 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
562 priv->write(reg_mcr, ®s->mcr);
564 return flexcan_low_power_exit_ack(priv);
567 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
569 struct flexcan_regs __iomem *regs = priv->regs;
570 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
572 priv->write(reg_ctrl, ®s->ctrl);
575 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
577 struct flexcan_regs __iomem *regs = priv->regs;
578 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
580 priv->write(reg_ctrl, ®s->ctrl);
583 static int flexcan_clks_enable(const struct flexcan_priv *priv)
588 err = clk_prepare_enable(priv->clk_ipg);
594 err = clk_prepare_enable(priv->clk_per);
596 clk_disable_unprepare(priv->clk_ipg);
602 static void flexcan_clks_disable(const struct flexcan_priv *priv)
604 clk_disable_unprepare(priv->clk_per);
605 clk_disable_unprepare(priv->clk_ipg);
608 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
610 if (!priv->reg_xceiver)
613 return regulator_enable(priv->reg_xceiver);
616 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
618 if (!priv->reg_xceiver)
621 return regulator_disable(priv->reg_xceiver);
624 static int flexcan_chip_enable(struct flexcan_priv *priv)
626 struct flexcan_regs __iomem *regs = priv->regs;
629 reg = priv->read(®s->mcr);
630 reg &= ~FLEXCAN_MCR_MDIS;
631 priv->write(reg, ®s->mcr);
633 return flexcan_low_power_exit_ack(priv);
636 static int flexcan_chip_disable(struct flexcan_priv *priv)
638 struct flexcan_regs __iomem *regs = priv->regs;
641 reg = priv->read(®s->mcr);
642 reg |= FLEXCAN_MCR_MDIS;
643 priv->write(reg, ®s->mcr);
645 return flexcan_low_power_enter_ack(priv);
648 static int flexcan_chip_freeze(struct flexcan_priv *priv)
650 struct flexcan_regs __iomem *regs = priv->regs;
651 unsigned int timeout;
652 u32 bitrate = priv->can.bittiming.bitrate;
656 timeout = 1000 * 1000 * 10 / bitrate;
658 timeout = FLEXCAN_TIMEOUT_US / 10;
660 reg = priv->read(®s->mcr);
661 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
662 priv->write(reg, ®s->mcr);
664 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
667 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
673 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
675 struct flexcan_regs __iomem *regs = priv->regs;
676 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
679 reg = priv->read(®s->mcr);
680 reg &= ~FLEXCAN_MCR_HALT;
681 priv->write(reg, ®s->mcr);
683 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
686 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
692 static int flexcan_chip_softreset(struct flexcan_priv *priv)
694 struct flexcan_regs __iomem *regs = priv->regs;
695 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
697 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
698 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
701 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
707 static int __flexcan_get_berr_counter(const struct net_device *dev,
708 struct can_berr_counter *bec)
710 const struct flexcan_priv *priv = netdev_priv(dev);
711 struct flexcan_regs __iomem *regs = priv->regs;
712 u32 reg = priv->read(®s->ecr);
714 bec->txerr = (reg >> 0) & 0xff;
715 bec->rxerr = (reg >> 8) & 0xff;
720 static int flexcan_get_berr_counter(const struct net_device *dev,
721 struct can_berr_counter *bec)
723 const struct flexcan_priv *priv = netdev_priv(dev);
726 err = pm_runtime_get_sync(priv->dev);
728 pm_runtime_put_noidle(priv->dev);
732 err = __flexcan_get_berr_counter(dev, bec);
734 pm_runtime_put(priv->dev);
739 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
741 const struct flexcan_priv *priv = netdev_priv(dev);
742 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
745 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
748 if (can_dropped_invalid_skb(dev, skb))
751 netif_stop_queue(dev);
753 if (cfd->can_id & CAN_EFF_FLAG) {
754 can_id = cfd->can_id & CAN_EFF_MASK;
755 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
757 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
760 if (cfd->can_id & CAN_RTR_FLAG)
761 ctrl |= FLEXCAN_MB_CNT_RTR;
763 if (can_is_canfd_skb(skb)) {
764 ctrl |= FLEXCAN_MB_CNT_EDL;
766 if (cfd->flags & CANFD_BRS)
767 ctrl |= FLEXCAN_MB_CNT_BRS;
770 for (i = 0; i < cfd->len; i += sizeof(u32)) {
771 data = be32_to_cpup((__be32 *)&cfd->data[i]);
772 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
775 can_put_echo_skb(skb, dev, 0, 0);
777 priv->write(can_id, &priv->tx_mb->can_id);
778 priv->write(ctrl, &priv->tx_mb->can_ctrl);
780 /* Errata ERR005829 step8:
781 * Write twice INACTIVE(0x8) code to first MB.
783 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
784 &priv->tx_mb_reserved->can_ctrl);
785 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
786 &priv->tx_mb_reserved->can_ctrl);
791 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
793 struct flexcan_priv *priv = netdev_priv(dev);
794 struct flexcan_regs __iomem *regs = priv->regs;
796 struct can_frame *cf;
797 bool rx_errors = false, tx_errors = false;
801 timestamp = priv->read(®s->timer) << 16;
803 skb = alloc_can_err_skb(dev, &cf);
807 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
809 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
810 netdev_dbg(dev, "BIT1_ERR irq\n");
811 cf->data[2] |= CAN_ERR_PROT_BIT1;
814 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
815 netdev_dbg(dev, "BIT0_ERR irq\n");
816 cf->data[2] |= CAN_ERR_PROT_BIT0;
819 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
820 netdev_dbg(dev, "ACK_ERR irq\n");
821 cf->can_id |= CAN_ERR_ACK;
822 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
825 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
826 netdev_dbg(dev, "CRC_ERR irq\n");
827 cf->data[2] |= CAN_ERR_PROT_BIT;
828 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
831 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
832 netdev_dbg(dev, "FRM_ERR irq\n");
833 cf->data[2] |= CAN_ERR_PROT_FORM;
836 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
837 netdev_dbg(dev, "STF_ERR irq\n");
838 cf->data[2] |= CAN_ERR_PROT_STUFF;
842 priv->can.can_stats.bus_error++;
844 dev->stats.rx_errors++;
846 dev->stats.tx_errors++;
848 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
850 dev->stats.rx_fifo_errors++;
853 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
855 struct flexcan_priv *priv = netdev_priv(dev);
856 struct flexcan_regs __iomem *regs = priv->regs;
858 struct can_frame *cf;
859 enum can_state new_state, rx_state, tx_state;
861 struct can_berr_counter bec;
865 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
866 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
867 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
868 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
869 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
870 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
871 new_state = max(tx_state, rx_state);
873 __flexcan_get_berr_counter(dev, &bec);
874 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
875 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
876 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
877 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
880 /* state hasn't changed */
881 if (likely(new_state == priv->can.state))
884 timestamp = priv->read(®s->timer) << 16;
886 skb = alloc_can_err_skb(dev, &cf);
890 can_change_state(dev, cf, tx_state, rx_state);
892 if (unlikely(new_state == CAN_STATE_BUS_OFF))
895 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
897 dev->stats.rx_fifo_errors++;
900 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
904 if (upper_32_bits(mask))
905 reg = (u64)priv->read(addr - 4) << 32;
906 if (lower_32_bits(mask))
907 reg |= priv->read(addr);
912 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
914 if (upper_32_bits(val))
915 priv->write(upper_32_bits(val), addr - 4);
916 if (lower_32_bits(val))
917 priv->write(lower_32_bits(val), addr);
920 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
922 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
925 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
927 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
930 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
932 return container_of(offload, struct flexcan_priv, offload);
935 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
936 unsigned int n, u32 *timestamp,
939 struct flexcan_priv *priv = rx_offload_to_priv(offload);
940 struct flexcan_regs __iomem *regs = priv->regs;
941 struct flexcan_mb __iomem *mb;
943 struct canfd_frame *cfd;
944 u32 reg_ctrl, reg_id, reg_iflag1;
947 if (unlikely(drop)) {
948 skb = ERR_PTR(-ENOBUFS);
952 mb = flexcan_get_mb(priv, n);
954 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
958 reg_ctrl = priv->read(&mb->can_ctrl);
959 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
961 /* is this MB empty? */
962 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
963 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
964 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
967 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
968 /* This MB was overrun, we lost data */
969 offload->dev->stats.rx_over_errors++;
970 offload->dev->stats.rx_errors++;
973 reg_iflag1 = priv->read(®s->iflag1);
974 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
977 reg_ctrl = priv->read(&mb->can_ctrl);
980 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
981 skb = alloc_canfd_skb(offload->dev, &cfd);
983 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
984 if (unlikely(!skb)) {
985 skb = ERR_PTR(-ENOMEM);
989 /* increase timstamp to full 32 bit */
990 *timestamp = reg_ctrl << 16;
992 reg_id = priv->read(&mb->can_id);
993 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
994 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
996 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
998 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
999 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1001 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1002 cfd->flags |= CANFD_BRS;
1004 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1006 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1007 cfd->can_id |= CAN_RTR_FLAG;
1010 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1011 cfd->flags |= CANFD_ESI;
1013 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1014 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1015 *(__be32 *)(cfd->data + i) = data;
1019 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1020 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1022 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1024 /* Read the Free Running Timer. It is optional but recommended
1025 * to unlock Mailbox as soon as possible and make it available
1028 priv->read(®s->timer);
1033 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1035 struct net_device *dev = dev_id;
1036 struct net_device_stats *stats = &dev->stats;
1037 struct flexcan_priv *priv = netdev_priv(dev);
1038 struct flexcan_regs __iomem *regs = priv->regs;
1039 irqreturn_t handled = IRQ_NONE;
1042 enum can_state last_state = priv->can.state;
1044 /* reception interrupt */
1045 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1049 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1050 handled = IRQ_HANDLED;
1051 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1059 reg_iflag1 = priv->read(®s->iflag1);
1060 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1061 handled = IRQ_HANDLED;
1062 can_rx_offload_irq_offload_fifo(&priv->offload);
1065 /* FIFO overflow interrupt */
1066 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1067 handled = IRQ_HANDLED;
1068 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1070 dev->stats.rx_over_errors++;
1071 dev->stats.rx_errors++;
1075 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1077 /* transmission complete interrupt */
1078 if (reg_iflag_tx & priv->tx_mask) {
1079 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1081 handled = IRQ_HANDLED;
1083 can_rx_offload_get_echo_skb(&priv->offload, 0,
1084 reg_ctrl << 16, NULL);
1085 stats->tx_packets++;
1086 can_led_event(dev, CAN_LED_EVENT_TX);
1088 /* after sending a RTR frame MB is in RX mode */
1089 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1090 &priv->tx_mb->can_ctrl);
1091 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1092 netif_wake_queue(dev);
1095 reg_esr = priv->read(®s->esr);
1097 /* ACK all bus error, state change and wake IRQ sources */
1098 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1099 handled = IRQ_HANDLED;
1100 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1103 /* state change interrupt or broken error state quirk fix is enabled */
1104 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1105 (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1106 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1107 flexcan_irq_state(dev, reg_esr);
1109 /* bus error IRQ - handle if bus error reporting is activated */
1110 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1111 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1112 flexcan_irq_bus_err(dev, reg_esr);
1114 /* availability of error interrupt among state transitions in case
1115 * bus error reporting is de-activated and
1116 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1117 * +--------------------------------------------------------------+
1118 * | +----------------------------------------------+ [stopped / |
1119 * | | | sleeping] -+
1120 * +-+-> active <-> warning <-> passive -> bus off -+
1121 * ___________^^^^^^^^^^^^_______________________________
1122 * disabled(1) enabled disabled
1124 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1126 if ((last_state != priv->can.state) &&
1127 (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1128 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1129 switch (priv->can.state) {
1130 case CAN_STATE_ERROR_ACTIVE:
1131 if (priv->devtype_data.quirks &
1132 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1133 flexcan_error_irq_enable(priv);
1135 flexcan_error_irq_disable(priv);
1138 case CAN_STATE_ERROR_WARNING:
1139 flexcan_error_irq_enable(priv);
1142 case CAN_STATE_ERROR_PASSIVE:
1143 case CAN_STATE_BUS_OFF:
1144 flexcan_error_irq_disable(priv);
1153 can_rx_offload_irq_finish(&priv->offload);
1158 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1160 const struct flexcan_priv *priv = netdev_priv(dev);
1161 const struct can_bittiming *bt = &priv->can.bittiming;
1162 struct flexcan_regs __iomem *regs = priv->regs;
1165 reg = priv->read(®s->ctrl);
1166 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1167 FLEXCAN_CTRL_RJW(0x3) |
1168 FLEXCAN_CTRL_PSEG1(0x7) |
1169 FLEXCAN_CTRL_PSEG2(0x7) |
1170 FLEXCAN_CTRL_PROPSEG(0x7));
1172 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1173 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1174 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1175 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1176 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1178 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1179 priv->write(reg, ®s->ctrl);
1181 /* print chip status */
1182 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1183 priv->read(®s->mcr), priv->read(®s->ctrl));
1186 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1188 struct flexcan_priv *priv = netdev_priv(dev);
1189 struct can_bittiming *bt = &priv->can.bittiming;
1190 struct can_bittiming *dbt = &priv->can.data_bittiming;
1191 struct flexcan_regs __iomem *regs = priv->regs;
1192 u32 reg_cbt, reg_fdctrl;
1195 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1196 * long. The can_calc_bittiming() tries to divide the tseg1
1197 * equally between phase_seg1 and prop_seg, which may not fit
1198 * in CBT register. Therefore, if phase_seg1 is more than
1199 * possible value, increase prop_seg and decrease phase_seg1.
1201 if (bt->phase_seg1 > 0x20) {
1202 bt->prop_seg += (bt->phase_seg1 - 0x20);
1203 bt->phase_seg1 = 0x20;
1206 reg_cbt = FLEXCAN_CBT_BTF |
1207 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1208 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1209 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1210 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1211 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1213 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1214 priv->write(reg_cbt, ®s->cbt);
1216 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1217 u32 reg_fdcbt, reg_ctrl2;
1219 if (bt->brp != dbt->brp)
1220 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1224 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1225 * 5 bit long. The can_calc_bittiming tries to divide
1226 * the tseg1 equally between phase_seg1 and prop_seg,
1227 * which may not fit in FDCBT register. Therefore, if
1228 * phase_seg1 is more than possible value, increase
1229 * prop_seg and decrease phase_seg1
1231 if (dbt->phase_seg1 > 0x8) {
1232 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1233 dbt->phase_seg1 = 0x8;
1236 reg_fdcbt = priv->read(®s->fdcbt);
1237 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1238 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1239 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1240 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1241 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1243 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1244 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1245 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1246 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1247 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1249 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1250 priv->write(reg_fdcbt, ®s->fdcbt);
1253 reg_ctrl2 = priv->read(®s->ctrl2);
1254 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1255 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1256 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1258 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1259 priv->write(reg_ctrl2, ®s->ctrl2);
1263 reg_fdctrl = priv->read(®s->fdctrl);
1264 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1265 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1267 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1268 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1270 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1271 /* TDC must be disabled for Loop Back mode */
1272 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1274 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1275 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1276 ((dbt->phase_seg1 - 1) +
1277 dbt->prop_seg + 2) *
1278 ((dbt->brp - 1 ) + 1));
1282 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1283 priv->write(reg_fdctrl, ®s->fdctrl);
1285 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1287 priv->read(®s->mcr), priv->read(®s->ctrl),
1288 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1289 priv->read(®s->cbt), priv->read(®s->fdcbt));
1292 static void flexcan_set_bittiming(struct net_device *dev)
1294 const struct flexcan_priv *priv = netdev_priv(dev);
1295 struct flexcan_regs __iomem *regs = priv->regs;
1298 reg = priv->read(®s->ctrl);
1299 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1302 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1303 reg |= FLEXCAN_CTRL_LPB;
1304 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1305 reg |= FLEXCAN_CTRL_LOM;
1306 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1307 reg |= FLEXCAN_CTRL_SMP;
1309 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1310 priv->write(reg, ®s->ctrl);
1312 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1313 return flexcan_set_bittiming_cbt(dev);
1315 return flexcan_set_bittiming_ctrl(dev);
1318 static void flexcan_ram_init(struct net_device *dev)
1320 struct flexcan_priv *priv = netdev_priv(dev);
1321 struct flexcan_regs __iomem *regs = priv->regs;
1324 /* 11.8.3.13 Detection and correction of memory errors:
1325 * CTRL2[WRMFRZ] grants write access to all memory positions
1326 * that require initialization, ranging from 0x080 to 0xADF
1327 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1328 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1329 * need to be initialized as well. MCR[RFEN] must not be set
1330 * during memory initialization.
1332 reg_ctrl2 = priv->read(®s->ctrl2);
1333 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1334 priv->write(reg_ctrl2, ®s->ctrl2);
1336 memset_io(®s->init, 0, sizeof(regs->init));
1338 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1339 memset_io(®s->init_fd, 0, sizeof(regs->init_fd));
1341 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1342 priv->write(reg_ctrl2, ®s->ctrl2);
1345 static int flexcan_rx_offload_setup(struct net_device *dev)
1347 struct flexcan_priv *priv = netdev_priv(dev);
1350 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1351 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1353 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1355 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1356 priv->mb_count = 16;
1358 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1359 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1361 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1362 priv->tx_mb_reserved =
1363 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1365 priv->tx_mb_reserved =
1366 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1367 priv->tx_mb_idx = priv->mb_count - 1;
1368 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1369 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1371 priv->offload.mailbox_read = flexcan_mailbox_read;
1373 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1374 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1375 priv->offload.mb_last = priv->mb_count - 2;
1377 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1378 priv->offload.mb_first);
1379 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1381 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1382 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1383 err = can_rx_offload_add_fifo(dev, &priv->offload,
1384 FLEXCAN_NAPI_WEIGHT);
1390 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1392 const struct flexcan_priv *priv = netdev_priv(dev);
1393 struct flexcan_regs __iomem *regs = priv->regs;
1396 disable_irq(dev->irq);
1397 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1398 reg_imask = priv->rx_mask | priv->tx_mask;
1399 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1400 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1401 enable_irq(dev->irq);
1404 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1406 const struct flexcan_priv *priv = netdev_priv(dev);
1407 struct flexcan_regs __iomem *regs = priv->regs;
1409 priv->write(0, ®s->imask2);
1410 priv->write(0, ®s->imask1);
1411 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1415 /* flexcan_chip_start
1417 * this functions is entered with clocks enabled
1420 static int flexcan_chip_start(struct net_device *dev)
1422 struct flexcan_priv *priv = netdev_priv(dev);
1423 struct flexcan_regs __iomem *regs = priv->regs;
1424 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1426 struct flexcan_mb __iomem *mb;
1429 err = flexcan_chip_enable(priv);
1434 err = flexcan_chip_softreset(priv);
1436 goto out_chip_disable;
1438 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1439 flexcan_ram_init(dev);
1441 flexcan_set_bittiming(dev);
1443 /* set freeze, halt */
1444 err = flexcan_chip_freeze(priv);
1446 goto out_chip_disable;
1450 * only supervisor access
1451 * enable warning int
1452 * enable individual RX masking
1454 * set max mailbox number
1456 reg_mcr = priv->read(®s->mcr);
1457 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1458 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1459 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1464 * - disable for mailbox mode
1465 * - enable for FIFO mode
1467 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1468 reg_mcr &= ~FLEXCAN_MCR_FEN;
1470 reg_mcr |= FLEXCAN_MCR_FEN;
1474 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1475 * asserted because this will impede the self reception
1476 * of a transmitted message. This is not documented in
1477 * earlier versions of flexcan block guide.
1480 * - enable Self Reception for loopback mode
1481 * (by clearing "Self Reception Disable" bit)
1482 * - disable for normal operation
1484 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1485 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1487 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1490 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1491 reg_mcr |= FLEXCAN_MCR_FDEN;
1493 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1495 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1496 priv->write(reg_mcr, ®s->mcr);
1500 * disable timer sync feature
1502 * disable auto busoff recovery
1503 * transmit lowest buffer first
1505 * enable tx and rx warning interrupt
1506 * enable bus off interrupt
1507 * (== FLEXCAN_CTRL_ERR_STATE)
1509 reg_ctrl = priv->read(®s->ctrl);
1510 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1511 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1512 FLEXCAN_CTRL_ERR_STATE;
1514 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1515 * on most Flexcan cores, too. Otherwise we don't get
1516 * any error warning or passive interrupts.
1518 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1519 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1520 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1522 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1524 /* save for later use */
1525 priv->reg_ctrl_default = reg_ctrl;
1526 /* leave interrupts disabled for now */
1527 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1528 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1529 priv->write(reg_ctrl, ®s->ctrl);
1531 if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1532 reg_ctrl2 = priv->read(®s->ctrl2);
1533 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1534 priv->write(reg_ctrl2, ®s->ctrl2);
1537 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1540 reg_fdctrl = priv->read(®s->fdctrl);
1541 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1542 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1544 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1546 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1547 FLEXCAN_FDCTRL_MBDSR_64) |
1548 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1549 FLEXCAN_FDCTRL_MBDSR_64);
1552 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1553 FLEXCAN_FDCTRL_MBDSR_8) |
1554 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1555 FLEXCAN_FDCTRL_MBDSR_8);
1558 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1559 __func__, reg_fdctrl);
1560 priv->write(reg_fdctrl, ®s->fdctrl);
1563 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1564 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1565 mb = flexcan_get_mb(priv, i);
1566 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1570 /* clear and invalidate unused mailboxes first */
1571 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1572 mb = flexcan_get_mb(priv, i);
1573 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1578 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1579 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1580 &priv->tx_mb_reserved->can_ctrl);
1582 /* mark TX mailbox as INACTIVE */
1583 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1584 &priv->tx_mb->can_ctrl);
1586 /* acceptance mask/acceptance code (accept everything) */
1587 priv->write(0x0, ®s->rxgmask);
1588 priv->write(0x0, ®s->rx14mask);
1589 priv->write(0x0, ®s->rx15mask);
1591 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1592 priv->write(0x0, ®s->rxfgmask);
1594 /* clear acceptance filters */
1595 for (i = 0; i < priv->mb_count; i++)
1596 priv->write(0, ®s->rximr[i]);
1598 /* On Vybrid, disable non-correctable errors interrupt and
1599 * freeze mode. It still can correct the correctable errors
1600 * when HW supports ECC.
1602 * This also works around errata e5295 which generates false
1603 * positive memory errors and put the device in freeze mode.
1605 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1606 /* Follow the protocol as described in "Detection
1607 * and Correction of Memory Errors" to write to
1608 * MECR register (step 1 - 5)
1610 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1611 * 2. set CTRL2[ECRWRE]
1613 reg_ctrl2 = priv->read(®s->ctrl2);
1614 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1615 priv->write(reg_ctrl2, ®s->ctrl2);
1617 /* 3. clear MECR[ECRWRDIS] */
1618 reg_mecr = priv->read(®s->mecr);
1619 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1620 priv->write(reg_mecr, ®s->mecr);
1622 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1623 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1624 FLEXCAN_MECR_FANCEI_MSK);
1625 priv->write(reg_mecr, ®s->mecr);
1627 /* 5. after configuration done, lock MECR by either
1628 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1630 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1631 priv->write(reg_mecr, ®s->mecr);
1633 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1634 priv->write(reg_ctrl2, ®s->ctrl2);
1637 /* synchronize with the can bus */
1638 err = flexcan_chip_unfreeze(priv);
1640 goto out_chip_disable;
1642 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1644 /* print chip status */
1645 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1646 priv->read(®s->mcr), priv->read(®s->ctrl));
1651 flexcan_chip_disable(priv);
1655 /* __flexcan_chip_stop
1657 * this function is entered with clocks enabled
1659 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1661 struct flexcan_priv *priv = netdev_priv(dev);
1664 /* freeze + disable module */
1665 err = flexcan_chip_freeze(priv);
1666 if (err && !disable_on_error)
1668 err = flexcan_chip_disable(priv);
1669 if (err && !disable_on_error)
1670 goto out_chip_unfreeze;
1672 priv->can.state = CAN_STATE_STOPPED;
1677 flexcan_chip_unfreeze(priv);
1682 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1684 return __flexcan_chip_stop(dev, true);
1687 static inline int flexcan_chip_stop(struct net_device *dev)
1689 return __flexcan_chip_stop(dev, false);
1692 static int flexcan_open(struct net_device *dev)
1694 struct flexcan_priv *priv = netdev_priv(dev);
1697 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1698 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1699 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1703 err = pm_runtime_get_sync(priv->dev);
1705 pm_runtime_put_noidle(priv->dev);
1709 err = open_candev(dev);
1711 goto out_runtime_put;
1713 err = flexcan_transceiver_enable(priv);
1717 err = flexcan_rx_offload_setup(dev);
1719 goto out_transceiver_disable;
1721 err = flexcan_chip_start(dev);
1723 goto out_can_rx_offload_del;
1725 can_rx_offload_enable(&priv->offload);
1727 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1729 goto out_can_rx_offload_disable;
1731 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1732 err = request_irq(priv->irq_boff,
1733 flexcan_irq, IRQF_SHARED, dev->name, dev);
1737 err = request_irq(priv->irq_err,
1738 flexcan_irq, IRQF_SHARED, dev->name, dev);
1740 goto out_free_irq_boff;
1743 flexcan_chip_interrupts_enable(dev);
1745 can_led_event(dev, CAN_LED_EVENT_OPEN);
1747 netif_start_queue(dev);
1752 free_irq(priv->irq_boff, dev);
1754 free_irq(dev->irq, dev);
1755 out_can_rx_offload_disable:
1756 can_rx_offload_disable(&priv->offload);
1757 flexcan_chip_stop(dev);
1758 out_can_rx_offload_del:
1759 can_rx_offload_del(&priv->offload);
1760 out_transceiver_disable:
1761 flexcan_transceiver_disable(priv);
1765 pm_runtime_put(priv->dev);
1770 static int flexcan_close(struct net_device *dev)
1772 struct flexcan_priv *priv = netdev_priv(dev);
1774 netif_stop_queue(dev);
1775 flexcan_chip_interrupts_disable(dev);
1777 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1778 free_irq(priv->irq_err, dev);
1779 free_irq(priv->irq_boff, dev);
1782 free_irq(dev->irq, dev);
1783 can_rx_offload_disable(&priv->offload);
1784 flexcan_chip_stop_disable_on_error(dev);
1786 can_rx_offload_del(&priv->offload);
1787 flexcan_transceiver_disable(priv);
1790 pm_runtime_put(priv->dev);
1792 can_led_event(dev, CAN_LED_EVENT_STOP);
1797 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1802 case CAN_MODE_START:
1803 err = flexcan_chip_start(dev);
1807 flexcan_chip_interrupts_enable(dev);
1809 netif_wake_queue(dev);
1819 static const struct net_device_ops flexcan_netdev_ops = {
1820 .ndo_open = flexcan_open,
1821 .ndo_stop = flexcan_close,
1822 .ndo_start_xmit = flexcan_start_xmit,
1823 .ndo_change_mtu = can_change_mtu,
1826 static int register_flexcandev(struct net_device *dev)
1828 struct flexcan_priv *priv = netdev_priv(dev);
1829 struct flexcan_regs __iomem *regs = priv->regs;
1832 err = flexcan_clks_enable(priv);
1836 /* select "bus clock", chip must be disabled */
1837 err = flexcan_chip_disable(priv);
1839 goto out_clks_disable;
1841 reg = priv->read(®s->ctrl);
1843 reg |= FLEXCAN_CTRL_CLK_SRC;
1845 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1846 priv->write(reg, ®s->ctrl);
1848 err = flexcan_chip_enable(priv);
1850 goto out_chip_disable;
1852 /* set freeze, halt */
1853 err = flexcan_chip_freeze(priv);
1855 goto out_chip_disable;
1857 /* activate FIFO, restrict register access */
1858 reg = priv->read(®s->mcr);
1859 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1860 priv->write(reg, ®s->mcr);
1862 /* Currently we only support newer versions of this core
1863 * featuring a RX hardware FIFO (although this driver doesn't
1864 * make use of it on some cores). Older cores, found on some
1865 * Coldfire derivates are not tested.
1867 reg = priv->read(®s->mcr);
1868 if (!(reg & FLEXCAN_MCR_FEN)) {
1869 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1871 goto out_chip_disable;
1874 err = register_candev(dev);
1876 goto out_chip_disable;
1878 /* Disable core and let pm_runtime_put() disable the clocks.
1879 * If CONFIG_PM is not enabled, the clocks will stay powered.
1881 flexcan_chip_disable(priv);
1882 pm_runtime_put(priv->dev);
1887 flexcan_chip_disable(priv);
1889 flexcan_clks_disable(priv);
1893 static void unregister_flexcandev(struct net_device *dev)
1895 unregister_candev(dev);
1898 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1900 struct net_device *dev = platform_get_drvdata(pdev);
1901 struct device_node *np = pdev->dev.of_node;
1902 struct device_node *gpr_np;
1903 struct flexcan_priv *priv;
1911 /* stop mode property format is:
1912 * <&gpr req_gpr req_bit>.
1914 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1915 ARRAY_SIZE(out_val));
1917 dev_dbg(&pdev->dev, "no stop-mode property\n");
1922 gpr_np = of_find_node_by_phandle(phandle);
1924 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1928 priv = netdev_priv(dev);
1929 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1930 if (IS_ERR(priv->stm.gpr)) {
1931 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1932 ret = PTR_ERR(priv->stm.gpr);
1936 priv->stm.req_gpr = out_val[1];
1937 priv->stm.req_bit = out_val[2];
1940 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1941 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1946 of_node_put(gpr_np);
1950 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1952 struct net_device *dev = platform_get_drvdata(pdev);
1953 struct flexcan_priv *priv;
1957 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1959 dev_dbg(&pdev->dev, "failed to get scu index\n");
1963 priv = netdev_priv(dev);
1964 priv->scu_idx = scu_idx;
1966 /* this function could be deferred probe, return -EPROBE_DEFER */
1967 return imx_scu_get_handle(&priv->sc_ipc_handle);
1970 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1972 * Return: = 0 setup stop mode successfully or doesn't support this feature
1973 * < 0 fail to setup stop mode (could be deferred probe)
1975 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1977 struct net_device *dev = platform_get_drvdata(pdev);
1978 struct flexcan_priv *priv;
1981 priv = netdev_priv(dev);
1983 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1984 ret = flexcan_setup_stop_mode_scfw(pdev);
1985 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1986 ret = flexcan_setup_stop_mode_gpr(pdev);
1988 /* return 0 directly if doesn't support stop mode feature */
1994 device_set_wakeup_capable(&pdev->dev, true);
1996 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
1997 device_set_wakeup_enable(&pdev->dev, true);
2002 static const struct of_device_id flexcan_of_match[] = {
2003 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2004 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2005 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2006 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2007 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2008 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2009 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2010 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2011 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2012 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2013 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2016 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2018 static const struct platform_device_id flexcan_id_table[] = {
2020 .name = "flexcan-mcf5441x",
2021 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2026 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2028 static int flexcan_probe(struct platform_device *pdev)
2030 const struct of_device_id *of_id;
2031 const struct flexcan_devtype_data *devtype_data;
2032 struct net_device *dev;
2033 struct flexcan_priv *priv;
2034 struct regulator *reg_xceiver;
2035 struct clk *clk_ipg = NULL, *clk_per = NULL;
2036 struct flexcan_regs __iomem *regs;
2037 struct flexcan_platform_data *pdata;
2042 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2043 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2044 return -EPROBE_DEFER;
2045 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2047 else if (IS_ERR(reg_xceiver))
2048 return PTR_ERR(reg_xceiver);
2050 if (pdev->dev.of_node) {
2051 of_property_read_u32(pdev->dev.of_node,
2052 "clock-frequency", &clock_freq);
2053 of_property_read_u8(pdev->dev.of_node,
2054 "fsl,clk-source", &clk_src);
2056 pdata = dev_get_platdata(&pdev->dev);
2058 clock_freq = pdata->clock_frequency;
2059 clk_src = pdata->clk_src;
2064 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2065 if (IS_ERR(clk_ipg)) {
2066 dev_err(&pdev->dev, "no ipg clock defined\n");
2067 return PTR_ERR(clk_ipg);
2070 clk_per = devm_clk_get(&pdev->dev, "per");
2071 if (IS_ERR(clk_per)) {
2072 dev_err(&pdev->dev, "no per clock defined\n");
2073 return PTR_ERR(clk_per);
2075 clock_freq = clk_get_rate(clk_per);
2078 irq = platform_get_irq(pdev, 0);
2082 regs = devm_platform_ioremap_resource(pdev, 0);
2084 return PTR_ERR(regs);
2086 of_id = of_match_device(flexcan_of_match, &pdev->dev);
2088 devtype_data = of_id->data;
2089 else if (platform_get_device_id(pdev)->driver_data)
2090 devtype_data = (struct flexcan_devtype_data *)
2091 platform_get_device_id(pdev)->driver_data;
2095 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2096 !((devtype_data->quirks &
2097 (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2098 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2099 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR |
2100 FLEXCAN_QUIRK_SUPPPORT_RX_FIFO)) ==
2101 (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2102 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2103 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR))) {
2104 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2108 if ((devtype_data->quirks &
2109 (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2110 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
2111 FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR) {
2113 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2114 devtype_data->quirks);
2118 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2122 platform_set_drvdata(pdev, dev);
2123 SET_NETDEV_DEV(dev, &pdev->dev);
2125 dev->netdev_ops = &flexcan_netdev_ops;
2126 flexcan_set_ethtool_ops(dev);
2128 dev->flags |= IFF_ECHO;
2130 priv = netdev_priv(dev);
2131 priv->devtype_data = *devtype_data;
2133 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2134 priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2135 priv->read = flexcan_read_be;
2136 priv->write = flexcan_write_be;
2138 priv->read = flexcan_read_le;
2139 priv->write = flexcan_write_le;
2142 priv->dev = &pdev->dev;
2143 priv->can.clock.freq = clock_freq;
2144 priv->can.do_set_mode = flexcan_set_mode;
2145 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2146 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2147 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2148 CAN_CTRLMODE_BERR_REPORTING;
2150 priv->clk_ipg = clk_ipg;
2151 priv->clk_per = clk_per;
2152 priv->clk_src = clk_src;
2153 priv->reg_xceiver = reg_xceiver;
2155 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2156 priv->irq_boff = platform_get_irq(pdev, 1);
2157 if (priv->irq_boff <= 0) {
2159 goto failed_platform_get_irq;
2161 priv->irq_err = platform_get_irq(pdev, 2);
2162 if (priv->irq_err <= 0) {
2164 goto failed_platform_get_irq;
2168 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2169 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2170 CAN_CTRLMODE_FD_NON_ISO;
2171 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2172 priv->can.data_bittiming_const =
2173 &flexcan_fd_data_bittiming_const;
2175 priv->can.bittiming_const = &flexcan_bittiming_const;
2178 pm_runtime_get_noresume(&pdev->dev);
2179 pm_runtime_set_active(&pdev->dev);
2180 pm_runtime_enable(&pdev->dev);
2182 err = register_flexcandev(dev);
2184 dev_err(&pdev->dev, "registering netdev failed\n");
2185 goto failed_register;
2188 err = flexcan_setup_stop_mode(pdev);
2190 if (err != -EPROBE_DEFER)
2191 dev_err(&pdev->dev, "setup stop mode failed\n");
2192 goto failed_setup_stop_mode;
2195 of_can_transceiver(dev);
2196 devm_can_led_init(dev);
2200 failed_setup_stop_mode:
2201 unregister_flexcandev(dev);
2203 pm_runtime_put_noidle(&pdev->dev);
2204 pm_runtime_disable(&pdev->dev);
2205 failed_platform_get_irq:
2210 static int flexcan_remove(struct platform_device *pdev)
2212 struct net_device *dev = platform_get_drvdata(pdev);
2214 device_set_wakeup_enable(&pdev->dev, false);
2215 device_set_wakeup_capable(&pdev->dev, false);
2216 unregister_flexcandev(dev);
2217 pm_runtime_disable(&pdev->dev);
2223 static int __maybe_unused flexcan_suspend(struct device *device)
2225 struct net_device *dev = dev_get_drvdata(device);
2226 struct flexcan_priv *priv = netdev_priv(dev);
2229 if (netif_running(dev)) {
2230 /* if wakeup is enabled, enter stop mode
2231 * else enter disabled mode.
2233 if (device_may_wakeup(device)) {
2234 enable_irq_wake(dev->irq);
2235 err = flexcan_enter_stop_mode(priv);
2239 err = flexcan_chip_stop(dev);
2243 flexcan_chip_interrupts_disable(dev);
2245 err = pinctrl_pm_select_sleep_state(device);
2249 netif_stop_queue(dev);
2250 netif_device_detach(dev);
2252 priv->can.state = CAN_STATE_SLEEPING;
2257 static int __maybe_unused flexcan_resume(struct device *device)
2259 struct net_device *dev = dev_get_drvdata(device);
2260 struct flexcan_priv *priv = netdev_priv(dev);
2263 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2264 if (netif_running(dev)) {
2265 netif_device_attach(dev);
2266 netif_start_queue(dev);
2267 if (device_may_wakeup(device)) {
2268 disable_irq_wake(dev->irq);
2269 err = flexcan_exit_stop_mode(priv);
2273 err = pinctrl_pm_select_default_state(device);
2277 err = flexcan_chip_start(dev);
2281 flexcan_chip_interrupts_enable(dev);
2288 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2290 struct net_device *dev = dev_get_drvdata(device);
2291 struct flexcan_priv *priv = netdev_priv(dev);
2293 flexcan_clks_disable(priv);
2298 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2300 struct net_device *dev = dev_get_drvdata(device);
2301 struct flexcan_priv *priv = netdev_priv(dev);
2303 return flexcan_clks_enable(priv);
2306 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2308 struct net_device *dev = dev_get_drvdata(device);
2309 struct flexcan_priv *priv = netdev_priv(dev);
2311 if (netif_running(dev)) {
2314 if (device_may_wakeup(device))
2315 flexcan_enable_wakeup_irq(priv, true);
2317 err = pm_runtime_force_suspend(device);
2325 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2327 struct net_device *dev = dev_get_drvdata(device);
2328 struct flexcan_priv *priv = netdev_priv(dev);
2330 if (netif_running(dev)) {
2333 err = pm_runtime_force_resume(device);
2337 if (device_may_wakeup(device))
2338 flexcan_enable_wakeup_irq(priv, false);
2344 static const struct dev_pm_ops flexcan_pm_ops = {
2345 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2346 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2347 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2350 static struct platform_driver flexcan_driver = {
2353 .pm = &flexcan_pm_ops,
2354 .of_match_table = flexcan_of_match,
2356 .probe = flexcan_probe,
2357 .remove = flexcan_remove,
2358 .id_table = flexcan_id_table,
2361 module_platform_driver(flexcan_driver);
2363 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2364 "Marc Kleine-Budde <kernel@pengutronix.de>");
2365 MODULE_LICENSE("GPL v2");
2366 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");