2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/pinctrl/consumer.h>
40 #include <linux/can.h>
41 #include <linux/can/dev.h>
42 #include <linux/can/error.h>
43 #include <linux/can/led.h>
47 /* Number of interface registers */
48 #define IF_ENUM_REG_LEN 11
49 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
51 /* control extension register D_CAN specific */
52 #define CONTROL_EX_PDR BIT(8)
54 /* control register */
55 #define CONTROL_SWR BIT(15)
56 #define CONTROL_TEST BIT(7)
57 #define CONTROL_CCE BIT(6)
58 #define CONTROL_DISABLE_AR BIT(5)
59 #define CONTROL_ENABLE_AR (0 << 5)
60 #define CONTROL_EIE BIT(3)
61 #define CONTROL_SIE BIT(2)
62 #define CONTROL_IE BIT(1)
63 #define CONTROL_INIT BIT(0)
65 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
68 #define TEST_RX BIT(7)
69 #define TEST_TX1 BIT(6)
70 #define TEST_TX2 BIT(5)
71 #define TEST_LBACK BIT(4)
72 #define TEST_SILENT BIT(3)
73 #define TEST_BASIC BIT(2)
76 #define STATUS_PDA BIT(10)
77 #define STATUS_BOFF BIT(7)
78 #define STATUS_EWARN BIT(6)
79 #define STATUS_EPASS BIT(5)
80 #define STATUS_RXOK BIT(4)
81 #define STATUS_TXOK BIT(3)
83 /* error counter register */
84 #define ERR_CNT_TEC_MASK 0xff
85 #define ERR_CNT_TEC_SHIFT 0
86 #define ERR_CNT_REC_SHIFT 8
87 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
88 #define ERR_CNT_RP_SHIFT 15
89 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
91 /* bit-timing register */
92 #define BTR_BRP_MASK 0x3f
93 #define BTR_BRP_SHIFT 0
94 #define BTR_SJW_SHIFT 6
95 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
96 #define BTR_TSEG1_SHIFT 8
97 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
98 #define BTR_TSEG2_SHIFT 12
99 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
101 /* interrupt register */
102 #define INT_STS_PENDING 0x8000
104 /* brp extension register */
105 #define BRP_EXT_BRPE_MASK 0x0f
106 #define BRP_EXT_BRPE_SHIFT 0
108 /* IFx command request */
109 #define IF_COMR_BUSY BIT(15)
111 /* IFx command mask */
112 #define IF_COMM_WR BIT(7)
113 #define IF_COMM_MASK BIT(6)
114 #define IF_COMM_ARB BIT(5)
115 #define IF_COMM_CONTROL BIT(4)
116 #define IF_COMM_CLR_INT_PND BIT(3)
117 #define IF_COMM_TXRQST BIT(2)
118 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
119 #define IF_COMM_DATAA BIT(1)
120 #define IF_COMM_DATAB BIT(0)
122 /* TX buffer setup */
123 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
125 IF_COMM_DATAA | IF_COMM_DATAB)
127 /* For the low buffers we clear the interrupt bit, but keep newdat */
128 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
130 IF_COMM_DATAA | IF_COMM_DATAB)
132 /* For the high buffers we clear the interrupt bit and newdat */
133 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
136 /* Receive setup of message objects */
137 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
139 /* Invalidation of message objects */
140 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
142 /* IFx arbitration */
143 #define IF_ARB_MSGVAL BIT(31)
144 #define IF_ARB_MSGXTD BIT(30)
145 #define IF_ARB_TRANSMIT BIT(29)
147 /* IFx message control */
148 #define IF_MCONT_NEWDAT BIT(15)
149 #define IF_MCONT_MSGLST BIT(14)
150 #define IF_MCONT_INTPND BIT(13)
151 #define IF_MCONT_UMASK BIT(12)
152 #define IF_MCONT_TXIE BIT(11)
153 #define IF_MCONT_RXIE BIT(10)
154 #define IF_MCONT_RMTEN BIT(9)
155 #define IF_MCONT_TXRQST BIT(8)
156 #define IF_MCONT_EOB BIT(7)
157 #define IF_MCONT_DLC_MASK 0xf
159 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
160 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
162 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
165 * Use IF1 for RX and IF2 for TX
170 /* minimum timeout for checking BUSY status */
171 #define MIN_TIMEOUT_VALUE 6
173 /* Wait for ~1 sec for INIT bit */
174 #define INIT_WAIT_MS 1000
177 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
179 /* c_can lec values */
180 enum c_can_lec_type {
189 LEC_MASK = LEC_UNUSED,
194 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
196 enum c_can_bus_error_types {
203 static const struct can_bittiming_const c_can_bittiming_const = {
204 .name = KBUILD_MODNAME,
205 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
207 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
211 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
215 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
218 pm_runtime_enable(priv->device);
221 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
224 pm_runtime_disable(priv->device);
227 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
230 pm_runtime_get_sync(priv->device);
233 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
236 pm_runtime_put_sync(priv->device);
239 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
242 priv->raminit(priv, enable);
245 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
247 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
250 ctrl |= CONTROL_IRQMSK;
252 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
255 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
257 struct c_can_priv *priv = netdev_priv(dev);
258 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
260 priv->write_reg32(priv, reg, (cmd << 16) | obj);
262 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
263 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
267 netdev_err(dev, "Updating object timed out\n");
271 static inline void c_can_object_get(struct net_device *dev, int iface,
274 c_can_obj_update(dev, iface, cmd, obj);
277 static inline void c_can_object_put(struct net_device *dev, int iface,
280 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
284 * Note: According to documentation clearing TXIE while MSGVAL is set
285 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
286 * load significantly.
288 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
290 struct c_can_priv *priv = netdev_priv(dev);
292 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
293 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
296 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
298 struct c_can_priv *priv = netdev_priv(dev);
300 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
301 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
302 c_can_inval_tx_object(dev, iface, obj);
305 static void c_can_setup_tx_object(struct net_device *dev, int iface,
306 struct can_frame *frame, int idx)
308 struct c_can_priv *priv = netdev_priv(dev);
309 u16 ctrl = IF_MCONT_TX | frame->len;
310 bool rtr = frame->can_id & CAN_RTR_FLAG;
311 u32 arb = IF_ARB_MSGVAL;
314 if (frame->can_id & CAN_EFF_FLAG) {
315 arb |= frame->can_id & CAN_EFF_MASK;
316 arb |= IF_ARB_MSGXTD;
318 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
322 arb |= IF_ARB_TRANSMIT;
325 * If we change the DIR bit, we need to invalidate the buffer
326 * first, i.e. clear the MSGVAL flag in the arbiter.
328 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
329 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
331 c_can_inval_msg_object(dev, iface, obj);
332 change_bit(idx, &priv->tx_dir);
335 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
337 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
339 if (priv->type == BOSCH_D_CAN) {
340 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
342 for (i = 0; i < frame->len; i += 4, dreg += 2) {
343 data = (u32)frame->data[i];
344 data |= (u32)frame->data[i + 1] << 8;
345 data |= (u32)frame->data[i + 2] << 16;
346 data |= (u32)frame->data[i + 3] << 24;
347 priv->write_reg32(priv, dreg, data);
350 for (i = 0; i < frame->len; i += 2) {
351 priv->write_reg(priv,
352 C_CAN_IFACE(DATA1_REG, iface) + i / 2,
354 (frame->data[i + 1] << 8));
359 static int c_can_handle_lost_msg_obj(struct net_device *dev,
360 int iface, int objno, u32 ctrl)
362 struct net_device_stats *stats = &dev->stats;
363 struct c_can_priv *priv = netdev_priv(dev);
364 struct can_frame *frame;
367 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
368 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
369 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
372 stats->rx_over_errors++;
374 /* create an error msg */
375 skb = alloc_can_err_skb(dev, &frame);
379 frame->can_id |= CAN_ERR_CRTL;
380 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
382 netif_receive_skb(skb);
386 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
388 struct net_device_stats *stats = &dev->stats;
389 struct c_can_priv *priv = netdev_priv(dev);
390 struct can_frame *frame;
394 skb = alloc_can_skb(dev, &frame);
400 frame->len = can_cc_dlc2len(ctrl & 0x0F);
402 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
404 if (arb & IF_ARB_MSGXTD)
405 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
407 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
409 if (arb & IF_ARB_TRANSMIT) {
410 frame->can_id |= CAN_RTR_FLAG;
412 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
414 if (priv->type == BOSCH_D_CAN) {
415 for (i = 0; i < frame->len; i += 4, dreg += 2) {
416 data = priv->read_reg32(priv, dreg);
417 frame->data[i] = data;
418 frame->data[i + 1] = data >> 8;
419 frame->data[i + 2] = data >> 16;
420 frame->data[i + 3] = data >> 24;
423 for (i = 0; i < frame->len; i += 2, dreg++) {
424 data = priv->read_reg(priv, dreg);
425 frame->data[i] = data;
426 frame->data[i + 1] = data >> 8;
432 stats->rx_bytes += frame->len;
434 netif_receive_skb(skb);
438 static void c_can_setup_receive_object(struct net_device *dev, int iface,
439 u32 obj, u32 mask, u32 id, u32 mcont)
441 struct c_can_priv *priv = netdev_priv(dev);
444 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
447 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
449 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
450 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
453 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
454 struct net_device *dev)
456 struct can_frame *frame = (struct can_frame *)skb->data;
457 struct c_can_priv *priv = netdev_priv(dev);
460 if (can_dropped_invalid_skb(dev, skb))
463 * This is not a FIFO. C/D_CAN sends out the buffers
464 * prioritized. The lowest buffer number wins.
466 idx = fls(atomic_read(&priv->tx_active));
467 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
469 /* If this is the last buffer, stop the xmit queue */
470 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1)
471 netif_stop_queue(dev);
473 * Store the message in the interface so we can call
474 * can_put_echo_skb(). We must do this before we enable
475 * transmit as we might race against do_tx().
477 c_can_setup_tx_object(dev, IF_TX, frame, idx);
478 priv->dlc[idx] = frame->len;
479 can_put_echo_skb(skb, dev, idx, 0);
481 /* Update the active bits */
482 atomic_add((1 << idx), &priv->tx_active);
483 /* Start transmission */
484 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
489 static int c_can_wait_for_ctrl_init(struct net_device *dev,
490 struct c_can_priv *priv, u32 init)
494 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
496 if (retry++ > 1000) {
497 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
504 static int c_can_set_bittiming(struct net_device *dev)
506 unsigned int reg_btr, reg_brpe, ctrl_save;
507 u8 brp, brpe, sjw, tseg1, tseg2;
509 struct c_can_priv *priv = netdev_priv(dev);
510 const struct can_bittiming *bt = &priv->can.bittiming;
513 /* c_can provides a 6-bit brp and 4-bit brpe fields */
514 ten_bit_brp = bt->brp - 1;
515 brp = ten_bit_brp & BTR_BRP_MASK;
516 brpe = ten_bit_brp >> 6;
519 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
520 tseg2 = bt->phase_seg2 - 1;
521 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
522 (tseg2 << BTR_TSEG2_SHIFT);
523 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
526 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
528 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
529 ctrl_save &= ~CONTROL_INIT;
530 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
531 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
535 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
536 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
537 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
539 return c_can_wait_for_ctrl_init(dev, priv, 0);
543 * Configure C_CAN message objects for Tx and Rx purposes:
544 * C_CAN provides a total of 32 message objects that can be configured
545 * either for Tx or Rx purposes. Here the first 16 message objects are used as
546 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
547 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
548 * See user guide document for further details on configuring message
551 static void c_can_configure_msg_objects(struct net_device *dev)
555 /* first invalidate all message objects */
556 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
557 c_can_inval_msg_object(dev, IF_RX, i);
559 /* setup receive message objects */
560 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
561 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
563 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
567 static int c_can_software_reset(struct net_device *dev)
569 struct c_can_priv *priv = netdev_priv(dev);
572 if (priv->type != BOSCH_D_CAN)
575 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
576 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
579 netdev_err(dev, "CCTRL: software reset failed\n");
588 * Configure C_CAN chip:
589 * - enable/disable auto-retransmission
590 * - set operating mode
591 * - configure message objects
593 static int c_can_chip_config(struct net_device *dev)
595 struct c_can_priv *priv = netdev_priv(dev);
598 err = c_can_software_reset(dev);
602 /* enable automatic retransmission */
603 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
605 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
606 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
607 /* loopback + silent mode : useful for hot self-test */
608 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
609 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
610 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
611 /* loopback mode : useful for self-test function */
612 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
613 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
614 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
615 /* silent mode : bus-monitoring mode */
616 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
617 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
620 /* configure message objects */
621 c_can_configure_msg_objects(dev);
623 /* set a `lec` value so that we can check for updates later */
624 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
626 /* Clear all internal status */
627 atomic_set(&priv->tx_active, 0);
631 /* set bittiming params */
632 return c_can_set_bittiming(dev);
635 static int c_can_start(struct net_device *dev)
637 struct c_can_priv *priv = netdev_priv(dev);
641 /* basic c_can configuration */
642 err = c_can_chip_config(dev);
646 /* Setup the command for new messages */
647 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
648 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
650 priv->can.state = CAN_STATE_ERROR_ACTIVE;
652 /* Attempt to use "active" if available else use "default" */
653 p = pinctrl_get_select(priv->device, "active");
657 pinctrl_pm_select_default_state(priv->device);
662 static void c_can_stop(struct net_device *dev)
664 struct c_can_priv *priv = netdev_priv(dev);
666 c_can_irq_control(priv, false);
668 /* put ctrl to init on stop to end ongoing transmission */
669 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
671 /* deactivate pins */
672 pinctrl_pm_select_sleep_state(dev->dev.parent);
673 priv->can.state = CAN_STATE_STOPPED;
676 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
678 struct c_can_priv *priv = netdev_priv(dev);
683 err = c_can_start(dev);
686 netif_wake_queue(dev);
687 c_can_irq_control(priv, true);
696 static int __c_can_get_berr_counter(const struct net_device *dev,
697 struct can_berr_counter *bec)
699 unsigned int reg_err_counter;
700 struct c_can_priv *priv = netdev_priv(dev);
702 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
703 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
705 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
710 static int c_can_get_berr_counter(const struct net_device *dev,
711 struct can_berr_counter *bec)
713 struct c_can_priv *priv = netdev_priv(dev);
716 c_can_pm_runtime_get_sync(priv);
717 err = __c_can_get_berr_counter(dev, bec);
718 c_can_pm_runtime_put_sync(priv);
723 static void c_can_do_tx(struct net_device *dev)
725 struct c_can_priv *priv = netdev_priv(dev);
726 struct net_device_stats *stats = &dev->stats;
727 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
729 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
731 while ((idx = ffs(pend))) {
734 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
735 c_can_inval_tx_object(dev, IF_RX, obj);
736 can_get_echo_skb(dev, idx);
737 bytes += priv->dlc[idx];
741 /* Clear the bits in the tx_active mask */
742 atomic_sub(clr, &priv->tx_active);
744 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1)))
745 netif_wake_queue(dev);
748 stats->tx_bytes += bytes;
749 stats->tx_packets += pkts;
750 can_led_event(dev, CAN_LED_EVENT_TX);
755 * If we have a gap in the pending bits, that means we either
756 * raced with the hardware or failed to readout all upper
757 * objects in the last run due to quota limit.
759 static u32 c_can_adjust_pending(u32 pend)
763 if (pend == RECEIVE_OBJECT_BITS)
767 * If the last set bit is larger than the number of pending
768 * bits we have a gap.
770 weight = hweight32(pend);
773 /* If the bits are linear, nothing to do */
778 * Find the first set bit after the gap. We walk backwards
779 * from the last set bit.
781 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
783 return pend & ~((1 << lasts) - 1);
786 static inline void c_can_rx_object_get(struct net_device *dev,
787 struct c_can_priv *priv, u32 obj)
789 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
792 static inline void c_can_rx_finalize(struct net_device *dev,
793 struct c_can_priv *priv, u32 obj)
795 if (priv->type != BOSCH_D_CAN)
796 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
799 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
802 u32 pkts = 0, ctrl, obj;
804 while ((obj = ffs(pend)) && quota > 0) {
805 pend &= ~BIT(obj - 1);
807 c_can_rx_object_get(dev, priv, obj);
808 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
810 if (ctrl & IF_MCONT_MSGLST) {
811 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
819 * This really should not happen, but this covers some
820 * odd HW behaviour. Do not remove that unless you
821 * want to brick your machine.
823 if (!(ctrl & IF_MCONT_NEWDAT))
826 /* read the data from the message object */
827 c_can_read_msg_object(dev, IF_RX, ctrl);
829 c_can_rx_finalize(dev, priv, obj);
838 static inline u32 c_can_get_pending(struct c_can_priv *priv)
840 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
846 * theory of operation:
848 * c_can core saves a received CAN message into the first free message
849 * object it finds free (starting with the lowest). Bits NEWDAT and
850 * INTPND are set for this message object indicating that a new message
851 * has arrived. To work-around this issue, we keep two groups of message
852 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
854 * We clear the newdat bit right away.
856 * This can result in packet reordering when the readout is slow.
858 static int c_can_do_rx_poll(struct net_device *dev, int quota)
860 struct c_can_priv *priv = netdev_priv(dev);
861 u32 pkts = 0, pend = 0, toread, n;
864 * It is faster to read only one 16bit register. This is only possible
865 * for a maximum number of 16 objects.
867 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
868 "Implementation does not support more message objects than 16");
872 pend = c_can_get_pending(priv);
876 * If the pending field has a gap, handle the
877 * bits above the gap first.
879 toread = c_can_adjust_pending(pend);
883 /* Remove the bits from pend */
885 /* Read the objects */
886 n = c_can_read_objects(dev, priv, toread, quota);
892 can_led_event(dev, CAN_LED_EVENT_RX);
897 static int c_can_handle_state_change(struct net_device *dev,
898 enum c_can_bus_error_types error_type)
900 unsigned int reg_err_counter;
901 unsigned int rx_err_passive;
902 struct c_can_priv *priv = netdev_priv(dev);
903 struct net_device_stats *stats = &dev->stats;
904 struct can_frame *cf;
906 struct can_berr_counter bec;
908 switch (error_type) {
910 priv->can.state = CAN_STATE_ERROR_ACTIVE;
912 case C_CAN_ERROR_WARNING:
913 /* error warning state */
914 priv->can.can_stats.error_warning++;
915 priv->can.state = CAN_STATE_ERROR_WARNING;
917 case C_CAN_ERROR_PASSIVE:
918 /* error passive state */
919 priv->can.can_stats.error_passive++;
920 priv->can.state = CAN_STATE_ERROR_PASSIVE;
924 priv->can.state = CAN_STATE_BUS_OFF;
925 priv->can.can_stats.bus_off++;
931 /* propagate the error condition to the CAN stack */
932 skb = alloc_can_err_skb(dev, &cf);
936 __c_can_get_berr_counter(dev, &bec);
937 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
938 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
941 switch (error_type) {
943 /* error warning state */
944 cf->can_id |= CAN_ERR_CRTL;
945 cf->data[1] = CAN_ERR_CRTL_ACTIVE;
946 cf->data[6] = bec.txerr;
947 cf->data[7] = bec.rxerr;
949 case C_CAN_ERROR_WARNING:
950 /* error warning state */
951 cf->can_id |= CAN_ERR_CRTL;
952 cf->data[1] = (bec.txerr > bec.rxerr) ?
953 CAN_ERR_CRTL_TX_WARNING :
954 CAN_ERR_CRTL_RX_WARNING;
955 cf->data[6] = bec.txerr;
956 cf->data[7] = bec.rxerr;
959 case C_CAN_ERROR_PASSIVE:
960 /* error passive state */
961 cf->can_id |= CAN_ERR_CRTL;
963 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
965 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
967 cf->data[6] = bec.txerr;
968 cf->data[7] = bec.rxerr;
972 cf->can_id |= CAN_ERR_BUSOFF;
980 stats->rx_bytes += cf->len;
981 netif_receive_skb(skb);
986 static int c_can_handle_bus_err(struct net_device *dev,
987 enum c_can_lec_type lec_type)
989 struct c_can_priv *priv = netdev_priv(dev);
990 struct net_device_stats *stats = &dev->stats;
991 struct can_frame *cf;
995 * early exit if no lec update or no error.
996 * no lec update means that no CAN bus event has been detected
997 * since CPU wrote 0x7 value to status reg.
999 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1002 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1005 /* common for all type of bus errors */
1006 priv->can.can_stats.bus_error++;
1009 /* propagate the error condition to the CAN stack */
1010 skb = alloc_can_err_skb(dev, &cf);
1015 * check for 'last error code' which tells us the
1016 * type of the last error to occur on the CAN bus
1018 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1021 case LEC_STUFF_ERROR:
1022 netdev_dbg(dev, "stuff error\n");
1023 cf->data[2] |= CAN_ERR_PROT_STUFF;
1025 case LEC_FORM_ERROR:
1026 netdev_dbg(dev, "form error\n");
1027 cf->data[2] |= CAN_ERR_PROT_FORM;
1030 netdev_dbg(dev, "ack error\n");
1031 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1033 case LEC_BIT1_ERROR:
1034 netdev_dbg(dev, "bit1 error\n");
1035 cf->data[2] |= CAN_ERR_PROT_BIT1;
1037 case LEC_BIT0_ERROR:
1038 netdev_dbg(dev, "bit0 error\n");
1039 cf->data[2] |= CAN_ERR_PROT_BIT0;
1042 netdev_dbg(dev, "CRC error\n");
1043 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1049 stats->rx_packets++;
1050 stats->rx_bytes += cf->len;
1051 netif_receive_skb(skb);
1055 static int c_can_poll(struct napi_struct *napi, int quota)
1057 struct net_device *dev = napi->dev;
1058 struct c_can_priv *priv = netdev_priv(dev);
1059 u16 curr, last = priv->last_status;
1062 /* Only read the status register if a status interrupt was pending */
1063 if (atomic_xchg(&priv->sie_pending, 0)) {
1064 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
1065 /* Ack status on C_CAN. D_CAN is self clearing */
1066 if (priv->type != BOSCH_D_CAN)
1067 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1069 /* no change detected ... */
1073 /* handle state changes */
1074 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1075 netdev_dbg(dev, "entered error warning state\n");
1076 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1079 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1080 netdev_dbg(dev, "entered error passive state\n");
1081 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1084 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1085 netdev_dbg(dev, "entered bus off state\n");
1086 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1090 /* handle bus recovery events */
1091 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1092 netdev_dbg(dev, "left bus off state\n");
1093 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1096 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1097 netdev_dbg(dev, "left error passive state\n");
1098 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1101 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1102 netdev_dbg(dev, "left error warning state\n");
1103 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1106 /* handle lec errors on the bus */
1107 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1109 /* Handle Tx/Rx events. We do this unconditionally */
1110 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1114 if (work_done < quota) {
1115 napi_complete_done(napi, work_done);
1116 /* enable all IRQs if we are not in bus off state */
1117 if (priv->can.state != CAN_STATE_BUS_OFF)
1118 c_can_irq_control(priv, true);
1124 static irqreturn_t c_can_isr(int irq, void *dev_id)
1126 struct net_device *dev = (struct net_device *)dev_id;
1127 struct c_can_priv *priv = netdev_priv(dev);
1130 reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1134 /* save for later use */
1135 if (reg_int & INT_STS_PENDING)
1136 atomic_set(&priv->sie_pending, 1);
1138 /* disable all interrupts and schedule the NAPI */
1139 c_can_irq_control(priv, false);
1140 napi_schedule(&priv->napi);
1145 static int c_can_open(struct net_device *dev)
1148 struct c_can_priv *priv = netdev_priv(dev);
1150 c_can_pm_runtime_get_sync(priv);
1151 c_can_reset_ram(priv, true);
1153 /* open the can device */
1154 err = open_candev(dev);
1156 netdev_err(dev, "failed to open can device\n");
1157 goto exit_open_fail;
1160 /* register interrupt handler */
1161 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1164 netdev_err(dev, "failed to request interrupt\n");
1168 /* start the c_can controller */
1169 err = c_can_start(dev);
1171 goto exit_start_fail;
1173 can_led_event(dev, CAN_LED_EVENT_OPEN);
1175 napi_enable(&priv->napi);
1176 /* enable status change, error and module interrupts */
1177 c_can_irq_control(priv, true);
1178 netif_start_queue(dev);
1183 free_irq(dev->irq, dev);
1187 c_can_reset_ram(priv, false);
1188 c_can_pm_runtime_put_sync(priv);
1192 static int c_can_close(struct net_device *dev)
1194 struct c_can_priv *priv = netdev_priv(dev);
1196 netif_stop_queue(dev);
1197 napi_disable(&priv->napi);
1199 free_irq(dev->irq, dev);
1202 c_can_reset_ram(priv, false);
1203 c_can_pm_runtime_put_sync(priv);
1205 can_led_event(dev, CAN_LED_EVENT_STOP);
1210 struct net_device *alloc_c_can_dev(void)
1212 struct net_device *dev;
1213 struct c_can_priv *priv;
1215 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1219 priv = netdev_priv(dev);
1220 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1223 priv->can.bittiming_const = &c_can_bittiming_const;
1224 priv->can.do_set_mode = c_can_set_mode;
1225 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1226 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1227 CAN_CTRLMODE_LISTENONLY |
1228 CAN_CTRLMODE_BERR_REPORTING;
1232 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1235 int c_can_power_down(struct net_device *dev)
1238 unsigned long time_out;
1239 struct c_can_priv *priv = netdev_priv(dev);
1241 if (!(dev->flags & IFF_UP))
1244 WARN_ON(priv->type != BOSCH_D_CAN);
1246 /* set PDR value so the device goes to power down mode */
1247 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1248 val |= CONTROL_EX_PDR;
1249 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1251 /* Wait for the PDA bit to get set */
1252 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1253 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1254 time_after(time_out, jiffies))
1257 if (time_after(jiffies, time_out))
1262 c_can_reset_ram(priv, false);
1263 c_can_pm_runtime_put_sync(priv);
1267 EXPORT_SYMBOL_GPL(c_can_power_down);
1269 int c_can_power_up(struct net_device *dev)
1272 unsigned long time_out;
1273 struct c_can_priv *priv = netdev_priv(dev);
1276 if (!(dev->flags & IFF_UP))
1279 WARN_ON(priv->type != BOSCH_D_CAN);
1281 c_can_pm_runtime_get_sync(priv);
1282 c_can_reset_ram(priv, true);
1284 /* Clear PDR and INIT bits */
1285 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1286 val &= ~CONTROL_EX_PDR;
1287 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1288 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1289 val &= ~CONTROL_INIT;
1290 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1292 /* Wait for the PDA bit to get clear */
1293 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1294 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1295 time_after(time_out, jiffies))
1298 if (time_after(jiffies, time_out)) {
1303 ret = c_can_start(dev);
1307 c_can_irq_control(priv, true);
1312 c_can_reset_ram(priv, false);
1313 c_can_pm_runtime_put_sync(priv);
1317 EXPORT_SYMBOL_GPL(c_can_power_up);
1320 void free_c_can_dev(struct net_device *dev)
1322 struct c_can_priv *priv = netdev_priv(dev);
1324 netif_napi_del(&priv->napi);
1327 EXPORT_SYMBOL_GPL(free_c_can_dev);
1329 static const struct net_device_ops c_can_netdev_ops = {
1330 .ndo_open = c_can_open,
1331 .ndo_stop = c_can_close,
1332 .ndo_start_xmit = c_can_start_xmit,
1333 .ndo_change_mtu = can_change_mtu,
1336 int register_c_can_dev(struct net_device *dev)
1338 struct c_can_priv *priv = netdev_priv(dev);
1341 /* Deactivate pins to prevent DRA7 DCAN IP from being
1342 * stuck in transition when module is disabled.
1343 * Pins are activated in c_can_start() and deactivated
1346 pinctrl_pm_select_sleep_state(dev->dev.parent);
1348 c_can_pm_runtime_enable(priv);
1350 dev->flags |= IFF_ECHO; /* we support local echo */
1351 dev->netdev_ops = &c_can_netdev_ops;
1353 err = register_candev(dev);
1355 c_can_pm_runtime_disable(priv);
1357 devm_can_led_init(dev);
1361 EXPORT_SYMBOL_GPL(register_c_can_dev);
1363 void unregister_c_can_dev(struct net_device *dev)
1365 struct c_can_priv *priv = netdev_priv(dev);
1367 unregister_candev(dev);
1369 c_can_pm_runtime_disable(priv);
1371 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1373 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1374 MODULE_LICENSE("GPL v2");
1375 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");