1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 #include <linux/mtd/spi-nor.h>
11 static const struct flash_info winbond_parts[] = {
12 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
13 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
14 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
15 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
16 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
17 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
18 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
19 { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
20 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
21 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
22 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
23 { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
24 SECT_4K | SPI_NOR_DUAL_READ |
25 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
27 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
28 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
29 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
30 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
31 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
32 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
33 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
34 { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
35 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
36 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
38 { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64,
39 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
40 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
41 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
42 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
43 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
44 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
45 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
46 { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
47 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
48 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
49 { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
50 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
51 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
52 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
53 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
54 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
55 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
56 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
57 SPI_NOR_4B_OPCODES) },
58 { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
59 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
60 { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
61 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
62 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
63 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
67 * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
68 * @nor: pointer to 'struct spi_nor'.
69 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
72 * Return: 0 on success, -errno otherwise.
74 static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
78 ret = spi_nor_set_4byte_addr_mode(nor, enable);
83 * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
84 * Register to be set to 1, so all 3-byte-address reads come from the
85 * second 16M. We must clear the register to enable normal behavior.
87 ret = spi_nor_write_enable(nor);
91 ret = spi_nor_write_ear(nor, 0);
95 return spi_nor_write_disable(nor);
98 static void winbond_default_init(struct spi_nor *nor)
100 nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
103 static const struct spi_nor_fixups winbond_fixups = {
104 .default_init = winbond_default_init,
107 const struct spi_nor_manufacturer spi_nor_winbond = {
109 .parts = winbond_parts,
110 .nparts = ARRAY_SIZE(winbond_parts),
111 .fixups = &winbond_fixups,