1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/math64.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/sort.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/of_platform.h>
22 #include <linux/sched/task_stack.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
43 struct sfdp_parameter_header {
47 u8 length; /* in double words */
48 u8 parameter_table_pointer[3]; /* byte address */
52 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
53 #define SFDP_PARAM_HEADER_PTP(p) \
54 (((p)->parameter_table_pointer[2] << 16) | \
55 ((p)->parameter_table_pointer[1] << 8) | \
56 ((p)->parameter_table_pointer[0] << 0))
58 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
59 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
60 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
62 #define SFDP_SIGNATURE 0x50444653U
63 #define SFDP_JESD216_MAJOR 1
64 #define SFDP_JESD216_MINOR 0
65 #define SFDP_JESD216A_MINOR 5
66 #define SFDP_JESD216B_MINOR 6
69 u32 signature; /* Ox50444653U <=> "SFDP" */
72 u8 nph; /* 0-base number of parameter headers */
75 /* Basic Flash Parameter Table. */
76 struct sfdp_parameter_header bfpt_header;
79 /* Basic Flash Parameter Table */
82 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
83 * They are indexed from 1 but C arrays are indexed from 0.
85 #define BFPT_DWORD(i) ((i) - 1)
86 #define BFPT_DWORD_MAX 16
88 /* The first version of JESB216 defined only 9 DWORDs. */
89 #define BFPT_DWORD_MAX_JESD216 9
92 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
93 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
94 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
95 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
96 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
97 #define BFPT_DWORD1_DTR BIT(19)
98 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
99 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
100 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
103 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
104 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
107 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
108 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
113 * (from JESD216 rev B)
114 * Quad Enable Requirements (QER):
115 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
116 * reads based on instruction. DQ3/HOLD# functions are hold during
118 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
119 * two data bytes where bit 1 of the second byte is one.
121 * Writing only one byte to the status register has the side-effect of
122 * clearing status register 2, including the QE bit. The 100b code is
123 * used if writing one byte to the status register does not modify
125 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
126 * one data byte where bit 6 is one.
128 * - 011b: QE is bit 7 of status register 2. It is set via Write status
129 * register 2 instruction 3Eh with one data byte where bit 7 is one.
131 * The status register 2 is read using instruction 3Fh.
132 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
133 * two data bytes where bit 1 of the second byte is one.
135 * In contrast to the 001b code, writing one byte to the status
136 * register does not modify status register 2.
137 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
138 * Read Status instruction 05h. Status register2 is read using
139 * instruction 35h. QE is set via Write Status instruction 01h with
140 * two data bytes where bit 1 of the second byte is one.
143 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
144 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
145 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
146 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
147 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
148 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
149 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
152 u32 dwords[BFPT_DWORD_MAX];
156 * struct spi_nor_fixups - SPI NOR fixup hooks
157 * @default_init: called after default flash parameters init. Used to tweak
158 * flash parameters when information provided by the flash_info
159 * table is incomplete or wrong.
160 * @post_bfpt: called after the BFPT table has been parsed
161 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
162 * that do not support RDSFDP). Typically used to tweak various
163 * parameters that could not be extracted by other means (i.e.
164 * when information provided by the SFDP/flash_info tables are
165 * incomplete or wrong).
167 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
168 * table is broken or not available.
170 struct spi_nor_fixups {
171 void (*default_init)(struct spi_nor *nor);
172 int (*post_bfpt)(struct spi_nor *nor,
173 const struct sfdp_parameter_header *bfpt_header,
174 const struct sfdp_bfpt *bfpt,
175 struct spi_nor_flash_parameter *params);
176 void (*post_sfdp)(struct spi_nor *nor);
183 * This array stores the ID bytes.
184 * The first three bytes are the JEDIC ID.
185 * JEDEC ID zero means "no ID" (mostly older chips).
187 u8 id[SPI_NOR_MAX_ID_LEN];
190 /* The size listed here is what works with SPINOR_OP_SE, which isn't
191 * necessarily called a "sector" by the vendor.
193 unsigned sector_size;
200 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
201 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
202 #define SST_WRITE BIT(2) /* use SST byte programming */
203 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
204 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
205 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
206 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
207 #define USE_FSR BIT(7) /* use flag status register */
208 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
209 #define SPI_NOR_HAS_TB BIT(9) /*
210 * Flash SR has Top/Bottom (TB) protect
211 * bit. Must be used with
214 #define SPI_NOR_XSR_RDY BIT(10) /*
215 * S3AN flashes have specific opcode to
216 * read the status register.
217 * Flags SPI_NOR_XSR_RDY and SPI_S3AN
218 * use the same bit as one implies the
219 * other, but we will get rid of
222 #define SPI_S3AN BIT(10) /*
223 * Xilinx Spartan 3AN In-System Flash
224 * (MFR cannot be used for probing
225 * because it has the same value as
228 #define SPI_NOR_4B_OPCODES BIT(11) /*
229 * Use dedicated 4byte address op codes
230 * to support memory size above 128Mib.
232 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
233 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
234 #define USE_CLSR BIT(14) /* use CLSR command */
235 #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
237 /* Part specific fixup hooks. */
238 const struct spi_nor_fixups *fixups;
241 #define JEDEC_MFR(info) ((info)->id[0])
244 * spi_nor_spimem_xfer_data() - helper function to read/write data to
245 * flash's memory region
246 * @nor: pointer to 'struct spi_nor'
247 * @op: pointer to 'struct spi_mem_op' template for transfer
249 * Return: number of bytes transferred on success, -errno otherwise
251 static ssize_t spi_nor_spimem_xfer_data(struct spi_nor *nor,
252 struct spi_mem_op *op)
254 bool usebouncebuf = false;
259 if (op->data.dir == SPI_MEM_DATA_IN)
260 buf = op->data.buf.in;
262 buf = op->data.buf.out;
264 if (object_is_on_stack(buf) || !virt_addr_valid(buf))
268 if (op->data.nbytes > nor->bouncebuf_size)
269 op->data.nbytes = nor->bouncebuf_size;
271 if (op->data.dir == SPI_MEM_DATA_IN) {
272 rdbuf = op->data.buf.in;
273 op->data.buf.in = nor->bouncebuf;
275 op->data.buf.out = nor->bouncebuf;
276 memcpy(nor->bouncebuf, buf,
281 ret = spi_mem_adjust_op_size(nor->spimem, op);
285 ret = spi_mem_exec_op(nor->spimem, op);
289 if (usebouncebuf && op->data.dir == SPI_MEM_DATA_IN)
290 memcpy(rdbuf, nor->bouncebuf, op->data.nbytes);
292 return op->data.nbytes;
296 * spi_nor_spimem_read_data() - read data from flash's memory region via
298 * @nor: pointer to 'struct spi_nor'
299 * @from: offset to read from
300 * @len: number of bytes to read
301 * @buf: pointer to dst buffer
303 * Return: number of bytes read successfully, -errno otherwise
305 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
308 struct spi_mem_op op =
309 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
310 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
311 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
312 SPI_MEM_OP_DATA_IN(len, buf, 1));
314 /* get transfer protocols. */
315 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
316 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
317 op.dummy.buswidth = op.addr.buswidth;
318 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
320 /* convert the dummy cycles to the number of bytes */
321 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
323 return spi_nor_spimem_xfer_data(nor, &op);
327 * spi_nor_read_data() - read data from flash memory
328 * @nor: pointer to 'struct spi_nor'
329 * @from: offset to read from
330 * @len: number of bytes to read
331 * @buf: pointer to dst buffer
333 * Return: number of bytes read successfully, -errno otherwise
335 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
339 return spi_nor_spimem_read_data(nor, from, len, buf);
341 return nor->controller_ops->read(nor, from, len, buf);
345 * spi_nor_spimem_write_data() - write data to flash memory via
347 * @nor: pointer to 'struct spi_nor'
348 * @to: offset to write to
349 * @len: number of bytes to write
350 * @buf: pointer to src buffer
352 * Return: number of bytes written successfully, -errno otherwise
354 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
355 size_t len, const u8 *buf)
357 struct spi_mem_op op =
358 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
359 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
361 SPI_MEM_OP_DATA_OUT(len, buf, 1));
363 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
364 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
365 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
367 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
370 return spi_nor_spimem_xfer_data(nor, &op);
374 * spi_nor_write_data() - write data to flash memory
375 * @nor: pointer to 'struct spi_nor'
376 * @to: offset to write to
377 * @len: number of bytes to write
378 * @buf: pointer to src buffer
380 * Return: number of bytes written successfully, -errno otherwise
382 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
386 return spi_nor_spimem_write_data(nor, to, len, buf);
388 return nor->controller_ops->write(nor, to, len, buf);
392 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
393 * @nor: pointer to 'struct spi_nor'.
395 * Return: 0 on success, -errno otherwise.
397 static int spi_nor_write_enable(struct spi_nor *nor)
402 struct spi_mem_op op =
403 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
408 ret = spi_mem_exec_op(nor->spimem, &op);
410 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
415 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
421 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
422 * @nor: pointer to 'struct spi_nor'.
424 * Return: 0 on success, -errno otherwise.
426 static int spi_nor_write_disable(struct spi_nor *nor)
431 struct spi_mem_op op =
432 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
437 ret = spi_mem_exec_op(nor->spimem, &op);
439 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
444 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
450 * spi_nor_read_sr() - Read the Status Register.
451 * @nor: pointer to 'struct spi_nor'.
452 * @sr: pointer to a DMA-able buffer where the value of the
453 * Status Register will be written.
455 * Return: 0 on success, -errno otherwise.
457 static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
462 struct spi_mem_op op =
463 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
466 SPI_MEM_OP_DATA_IN(1, sr, 1));
468 ret = spi_mem_exec_op(nor->spimem, &op);
470 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
475 dev_dbg(nor->dev, "error %d reading SR\n", ret);
481 * spi_nor_read_fsr() - Read the Flag Status Register.
482 * @nor: pointer to 'struct spi_nor'
483 * @fsr: pointer to a DMA-able buffer where the value of the
484 * Flag Status Register will be written.
486 * Return: 0 on success, -errno otherwise.
488 static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
493 struct spi_mem_op op =
494 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
497 SPI_MEM_OP_DATA_IN(1, fsr, 1));
499 ret = spi_mem_exec_op(nor->spimem, &op);
501 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
506 dev_dbg(nor->dev, "error %d reading FSR\n", ret);
512 * spi_nor_read_cr() - Read the Configuration Register using the
513 * SPINOR_OP_RDCR (35h) command.
514 * @nor: pointer to 'struct spi_nor'
515 * @cr: pointer to a DMA-able buffer where the value of the
516 * Configuration Register will be written.
518 * Return: 0 on success, -errno otherwise.
520 static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
525 struct spi_mem_op op =
526 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
529 SPI_MEM_OP_DATA_IN(1, cr, 1));
531 ret = spi_mem_exec_op(nor->spimem, &op);
533 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
537 dev_dbg(nor->dev, "error %d reading CR\n", ret);
543 * macronix_set_4byte() - Set 4-byte address mode for Macronix flashes.
544 * @nor: pointer to 'struct spi_nor'.
545 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
548 * Return: 0 on success, -errno otherwise.
550 static int macronix_set_4byte(struct spi_nor *nor, bool enable)
555 struct spi_mem_op op =
556 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
564 ret = spi_mem_exec_op(nor->spimem, &op);
566 ret = nor->controller_ops->write_reg(nor,
567 enable ? SPINOR_OP_EN4B :
573 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
579 * st_micron_set_4byte() - Set 4-byte address mode for ST and Micron flashes.
580 * @nor: pointer to 'struct spi_nor'.
581 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
584 * Return: 0 on success, -errno otherwise.
586 static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
590 ret = spi_nor_write_enable(nor);
594 ret = macronix_set_4byte(nor, enable);
598 return spi_nor_write_disable(nor);
602 * spansion_set_4byte() - Set 4-byte address mode for Spansion flashes.
603 * @nor: pointer to 'struct spi_nor'.
604 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
607 * Return: 0 on success, -errno otherwise.
609 static int spansion_set_4byte(struct spi_nor *nor, bool enable)
613 nor->bouncebuf[0] = enable << 7;
616 struct spi_mem_op op =
617 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 1),
620 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
622 ret = spi_mem_exec_op(nor->spimem, &op);
624 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
629 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
635 * spi_nor_write_ear() - Write Extended Address Register.
636 * @nor: pointer to 'struct spi_nor'.
637 * @ear: value to write to the Extended Address Register.
639 * Return: 0 on success, -errno otherwise.
641 static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
645 nor->bouncebuf[0] = ear;
648 struct spi_mem_op op =
649 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 1),
652 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1));
654 ret = spi_mem_exec_op(nor->spimem, &op);
656 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
661 dev_dbg(nor->dev, "error %d writing EAR\n", ret);
667 * winbond_set_4byte() - Set 4-byte address mode for Winbond flashes.
668 * @nor: pointer to 'struct spi_nor'.
669 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
672 * Return: 0 on success, -errno otherwise.
674 static int winbond_set_4byte(struct spi_nor *nor, bool enable)
678 ret = macronix_set_4byte(nor, enable);
683 * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
684 * Register to be set to 1, so all 3-byte-address reads come from the
685 * second 16M. We must clear the register to enable normal behavior.
687 ret = spi_nor_write_enable(nor);
691 ret = spi_nor_write_ear(nor, 0);
695 return spi_nor_write_disable(nor);
699 * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
700 * @nor: pointer to 'struct spi_nor'.
701 * @sr: pointer to a DMA-able buffer where the value of the
702 * Status Register will be written.
704 * Return: 0 on success, -errno otherwise.
706 static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
711 struct spi_mem_op op =
712 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
715 SPI_MEM_OP_DATA_IN(1, sr, 1));
717 ret = spi_mem_exec_op(nor->spimem, &op);
719 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
724 dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
730 * s3an_sr_ready() - Query the Status Register of the S3AN flash to see if the
731 * flash is ready for new commands.
732 * @nor: pointer to 'struct spi_nor'.
734 * Return: 0 on success, -errno otherwise.
736 static int s3an_sr_ready(struct spi_nor *nor)
740 ret = spi_nor_xread_sr(nor, nor->bouncebuf);
744 return !!(nor->bouncebuf[0] & XSR_RDY);
748 * spi_nor_clear_sr() - Clear the Status Register.
749 * @nor: pointer to 'struct spi_nor'.
751 static void spi_nor_clear_sr(struct spi_nor *nor)
756 struct spi_mem_op op =
757 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
762 ret = spi_mem_exec_op(nor->spimem, &op);
764 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
769 dev_dbg(nor->dev, "error %d clearing SR\n", ret);
773 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
775 * @nor: pointer to 'struct spi_nor'.
777 * Return: 0 on success, -errno otherwise.
779 static int spi_nor_sr_ready(struct spi_nor *nor)
781 int ret = spi_nor_read_sr(nor, nor->bouncebuf);
786 if (nor->flags & SNOR_F_USE_CLSR &&
787 nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
788 if (nor->bouncebuf[0] & SR_E_ERR)
789 dev_err(nor->dev, "Erase Error occurred\n");
791 dev_err(nor->dev, "Programming Error occurred\n");
793 spi_nor_clear_sr(nor);
797 return !(nor->bouncebuf[0] & SR_WIP);
801 * spi_nor_clear_fsr() - Clear the Flag Status Register.
802 * @nor: pointer to 'struct spi_nor'.
804 static void spi_nor_clear_fsr(struct spi_nor *nor)
809 struct spi_mem_op op =
810 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
815 ret = spi_mem_exec_op(nor->spimem, &op);
817 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
822 dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
826 * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
827 * ready for new commands.
828 * @nor: pointer to 'struct spi_nor'.
830 * Return: 0 on success, -errno otherwise.
832 static int spi_nor_fsr_ready(struct spi_nor *nor)
834 int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
839 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
840 if (nor->bouncebuf[0] & FSR_E_ERR)
841 dev_err(nor->dev, "Erase operation failed.\n");
843 dev_err(nor->dev, "Program operation failed.\n");
845 if (nor->bouncebuf[0] & FSR_PT_ERR)
847 "Attempted to modify a protected sector.\n");
849 spi_nor_clear_fsr(nor);
853 return nor->bouncebuf[0] & FSR_READY;
857 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
858 * @nor: pointer to 'struct spi_nor'.
860 * Return: 0 on success, -errno otherwise.
862 static int spi_nor_ready(struct spi_nor *nor)
866 if (nor->flags & SNOR_F_READY_XSR_RDY)
867 sr = s3an_sr_ready(nor);
869 sr = spi_nor_sr_ready(nor);
872 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
879 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
880 * Status Register until ready, or timeout occurs.
881 * @nor: pointer to "struct spi_nor".
882 * @timeout_jiffies: jiffies to wait until timeout.
884 * Return: 0 on success, -errno otherwise.
886 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
887 unsigned long timeout_jiffies)
889 unsigned long deadline;
890 int timeout = 0, ret;
892 deadline = jiffies + timeout_jiffies;
895 if (time_after_eq(jiffies, deadline))
898 ret = spi_nor_ready(nor);
907 dev_dbg(nor->dev, "flash operation timed out\n");
913 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
914 * flash to be ready, or timeout occurs.
915 * @nor: pointer to "struct spi_nor".
917 * Return: 0 on success, -errno otherwise.
919 static int spi_nor_wait_till_ready(struct spi_nor *nor)
921 return spi_nor_wait_till_ready_with_timeout(nor,
922 DEFAULT_READY_WAIT_JIFFIES);
926 * spi_nor_write_sr() - Write the Status Register.
927 * @nor: pointer to 'struct spi_nor'.
928 * @sr: pointer to DMA-able buffer to write to the Status Register.
929 * @len: number of bytes to write to the Status Register.
931 * Return: 0 on success, -errno otherwise.
933 static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
937 ret = spi_nor_write_enable(nor);
942 struct spi_mem_op op =
943 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
946 SPI_MEM_OP_DATA_OUT(len, sr, 1));
948 ret = spi_mem_exec_op(nor->spimem, &op);
950 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
955 dev_dbg(nor->dev, "error %d writing SR\n", ret);
959 return spi_nor_wait_till_ready(nor);
962 /* Write status register and ensure bits in mask match written values */
963 static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new)
967 nor->bouncebuf[0] = status_new;
969 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
973 ret = spi_nor_read_sr(nor, nor->bouncebuf);
977 return (nor->bouncebuf[0] != status_new) ? -EIO : 0;
981 * spi_nor_write_sr2() - Write the Status Register 2 using the
982 * SPINOR_OP_WRSR2 (3eh) command.
983 * @nor: pointer to 'struct spi_nor'.
984 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
986 * Return: 0 on success, -errno otherwise.
988 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
992 ret = spi_nor_write_enable(nor);
997 struct spi_mem_op op =
998 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
1000 SPI_MEM_OP_NO_DUMMY,
1001 SPI_MEM_OP_DATA_OUT(1, sr2, 1));
1003 ret = spi_mem_exec_op(nor->spimem, &op);
1005 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
1010 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
1014 return spi_nor_wait_till_ready(nor);
1018 * spi_nor_read_sr2() - Read the Status Register 2 using the
1019 * SPINOR_OP_RDSR2 (3fh) command.
1020 * @nor: pointer to 'struct spi_nor'.
1021 * @sr2: pointer to DMA-able buffer where the value of the
1022 * Status Register 2 will be written.
1024 * Return: 0 on success, -errno otherwise.
1026 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1031 struct spi_mem_op op =
1032 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
1034 SPI_MEM_OP_NO_DUMMY,
1035 SPI_MEM_OP_DATA_IN(1, sr2, 1));
1037 ret = spi_mem_exec_op(nor->spimem, &op);
1039 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
1044 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1050 * spi_nor_erase_chip() - Erase the entire flash memory.
1051 * @nor: pointer to 'struct spi_nor'.
1053 * Return: 0 on success, -errno otherwise.
1055 static int spi_nor_erase_chip(struct spi_nor *nor)
1059 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
1062 struct spi_mem_op op =
1063 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1),
1065 SPI_MEM_OP_NO_DUMMY,
1066 SPI_MEM_OP_NO_DATA);
1068 ret = spi_mem_exec_op(nor->spimem, &op);
1070 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
1075 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1080 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
1085 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1089 for (i = 0; i < size; i++)
1090 if (table[i][0] == opcode)
1093 /* No conversion found, keep input op code. */
1097 static u8 spi_nor_convert_3to4_read(u8 opcode)
1099 static const u8 spi_nor_3to4_read[][2] = {
1100 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1101 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1102 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1103 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1104 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1105 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1106 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1107 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1109 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1110 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1111 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1114 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1115 ARRAY_SIZE(spi_nor_3to4_read));
1118 static u8 spi_nor_convert_3to4_program(u8 opcode)
1120 static const u8 spi_nor_3to4_program[][2] = {
1121 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1122 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1123 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1124 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1125 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1128 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1129 ARRAY_SIZE(spi_nor_3to4_program));
1132 static u8 spi_nor_convert_3to4_erase(u8 opcode)
1134 static const u8 spi_nor_3to4_erase[][2] = {
1135 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1136 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1137 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1140 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1141 ARRAY_SIZE(spi_nor_3to4_erase));
1144 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1146 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1147 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1148 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1150 if (!spi_nor_has_uniform_erase(nor)) {
1151 struct spi_nor_erase_map *map = &nor->params.erase_map;
1152 struct spi_nor_erase_type *erase;
1155 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1156 erase = &map->erase_type[i];
1158 spi_nor_convert_3to4_erase(erase->opcode);
1163 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1167 mutex_lock(&nor->lock);
1169 if (nor->controller_ops && nor->controller_ops->prepare) {
1170 ret = nor->controller_ops->prepare(nor, ops);
1172 mutex_unlock(&nor->lock);
1179 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1181 if (nor->controller_ops && nor->controller_ops->unprepare)
1182 nor->controller_ops->unprepare(nor, ops);
1183 mutex_unlock(&nor->lock);
1187 * This code converts an address to the Default Address Mode, that has non
1188 * power of two page sizes. We must support this mode because it is the default
1189 * mode supported by Xilinx tools, it can access the whole flash area and
1190 * changing over to the Power-of-two mode is irreversible and corrupts the
1192 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
1195 static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
1199 offset = addr % nor->page_size;
1200 page = addr / nor->page_size;
1201 page <<= (nor->page_size > 512) ? 10 : 9;
1203 return page | offset;
1206 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1208 if (!nor->params.convert_addr)
1211 return nor->params.convert_addr(nor, addr);
1215 * Initiate the erasure of a single sector
1217 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1221 addr = spi_nor_convert_addr(nor, addr);
1223 if (nor->controller_ops && nor->controller_ops->erase)
1224 return nor->controller_ops->erase(nor, addr);
1227 struct spi_mem_op op =
1228 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
1229 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
1230 SPI_MEM_OP_NO_DUMMY,
1231 SPI_MEM_OP_NO_DATA);
1233 return spi_mem_exec_op(nor->spimem, &op);
1237 * Default implementation, if driver doesn't have a specialized HW
1240 for (i = nor->addr_width - 1; i >= 0; i--) {
1241 nor->bouncebuf[i] = addr & 0xff;
1245 return nor->controller_ops->write_reg(nor, nor->erase_opcode,
1246 nor->bouncebuf, nor->addr_width);
1250 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1251 * @erase: pointer to a structure that describes a SPI NOR erase type
1252 * @dividend: dividend value
1253 * @remainder: pointer to u32 remainder (will be updated)
1255 * Return: the result of the division
1257 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1258 u64 dividend, u32 *remainder)
1260 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1261 *remainder = (u32)dividend & erase->size_mask;
1262 return dividend >> erase->size_shift;
1266 * spi_nor_find_best_erase_type() - find the best erase type for the given
1267 * offset in the serial flash memory and the
1268 * number of bytes to erase. The region in
1269 * which the address fits is expected to be
1271 * @map: the erase map of the SPI NOR
1272 * @region: pointer to a structure that describes a SPI NOR erase region
1273 * @addr: offset in the serial flash memory
1274 * @len: number of bytes to erase
1276 * Return: a pointer to the best fitted erase type, NULL otherwise.
1278 static const struct spi_nor_erase_type *
1279 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1280 const struct spi_nor_erase_region *region,
1283 const struct spi_nor_erase_type *erase;
1286 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
1289 * Erase types are ordered by size, with the smallest erase type at
1292 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1293 /* Does the erase region support the tested erase type? */
1294 if (!(erase_mask & BIT(i)))
1297 erase = &map->erase_type[i];
1299 /* Don't erase more than what the user has asked for. */
1300 if (erase->size > len)
1303 /* Alignment is not mandatory for overlaid regions */
1304 if (region->offset & SNOR_OVERLAID_REGION)
1307 spi_nor_div_by_erase_size(erase, addr, &rem);
1318 * spi_nor_region_next() - get the next spi nor region
1319 * @region: pointer to a structure that describes a SPI NOR erase region
1321 * Return: the next spi nor region or NULL if last region.
1323 static struct spi_nor_erase_region *
1324 spi_nor_region_next(struct spi_nor_erase_region *region)
1326 if (spi_nor_region_is_last(region))
1333 * spi_nor_find_erase_region() - find the region of the serial flash memory in
1334 * which the offset fits
1335 * @map: the erase map of the SPI NOR
1336 * @addr: offset in the serial flash memory
1338 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno)
1341 static struct spi_nor_erase_region *
1342 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr)
1344 struct spi_nor_erase_region *region = map->regions;
1345 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1346 u64 region_end = region_start + region->size;
1348 while (addr < region_start || addr >= region_end) {
1349 region = spi_nor_region_next(region);
1351 return ERR_PTR(-EINVAL);
1353 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK;
1354 region_end = region_start + region->size;
1361 * spi_nor_init_erase_cmd() - initialize an erase command
1362 * @region: pointer to a structure that describes a SPI NOR erase region
1363 * @erase: pointer to a structure that describes a SPI NOR erase type
1365 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1368 static struct spi_nor_erase_command *
1369 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1370 const struct spi_nor_erase_type *erase)
1372 struct spi_nor_erase_command *cmd;
1374 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1376 return ERR_PTR(-ENOMEM);
1378 INIT_LIST_HEAD(&cmd->list);
1379 cmd->opcode = erase->opcode;
1382 if (region->offset & SNOR_OVERLAID_REGION)
1383 cmd->size = region->size;
1385 cmd->size = erase->size;
1391 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1392 * @erase_list: list of erase commands
1394 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1396 struct spi_nor_erase_command *cmd, *next;
1398 list_for_each_entry_safe(cmd, next, erase_list, list) {
1399 list_del(&cmd->list);
1405 * spi_nor_init_erase_cmd_list() - initialize erase command list
1406 * @nor: pointer to a 'struct spi_nor'
1407 * @erase_list: list of erase commands to be executed once we validate that the
1408 * erase can be performed
1409 * @addr: offset in the serial flash memory
1410 * @len: number of bytes to erase
1412 * Builds the list of best fitted erase commands and verifies if the erase can
1415 * Return: 0 on success, -errno otherwise.
1417 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1418 struct list_head *erase_list,
1421 const struct spi_nor_erase_map *map = &nor->params.erase_map;
1422 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1423 struct spi_nor_erase_region *region;
1424 struct spi_nor_erase_command *cmd = NULL;
1428 region = spi_nor_find_erase_region(map, addr);
1430 return PTR_ERR(region);
1432 region_end = spi_nor_region_end(region);
1435 erase = spi_nor_find_best_erase_type(map, region, addr, len);
1437 goto destroy_erase_cmd_list;
1439 if (prev_erase != erase ||
1440 region->offset & SNOR_OVERLAID_REGION) {
1441 cmd = spi_nor_init_erase_cmd(region, erase);
1444 goto destroy_erase_cmd_list;
1447 list_add_tail(&cmd->list, erase_list);
1455 if (len && addr >= region_end) {
1456 region = spi_nor_region_next(region);
1458 goto destroy_erase_cmd_list;
1459 region_end = spi_nor_region_end(region);
1467 destroy_erase_cmd_list:
1468 spi_nor_destroy_erase_cmd_list(erase_list);
1473 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1474 * @nor: pointer to a 'struct spi_nor'
1475 * @addr: offset in the serial flash memory
1476 * @len: number of bytes to erase
1478 * Build a list of best fitted erase commands and execute it once we validate
1479 * that the erase can be performed.
1481 * Return: 0 on success, -errno otherwise.
1483 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1485 LIST_HEAD(erase_list);
1486 struct spi_nor_erase_command *cmd, *next;
1489 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1493 list_for_each_entry_safe(cmd, next, &erase_list, list) {
1494 nor->erase_opcode = cmd->opcode;
1495 while (cmd->count) {
1496 ret = spi_nor_write_enable(nor);
1498 goto destroy_erase_cmd_list;
1500 ret = spi_nor_erase_sector(nor, addr);
1502 goto destroy_erase_cmd_list;
1507 ret = spi_nor_wait_till_ready(nor);
1509 goto destroy_erase_cmd_list;
1511 list_del(&cmd->list);
1517 destroy_erase_cmd_list:
1518 spi_nor_destroy_erase_cmd_list(&erase_list);
1523 * Erase an address range on the nor chip. The address range may extend
1524 * one or more erase sectors. Return an error is there is a problem erasing.
1526 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1528 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1533 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1534 (long long)instr->len);
1536 if (spi_nor_has_uniform_erase(nor)) {
1537 div_u64_rem(instr->len, mtd->erasesize, &rem);
1545 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
1549 /* whole-chip erase? */
1550 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
1551 unsigned long timeout;
1553 ret = spi_nor_write_enable(nor);
1557 ret = spi_nor_erase_chip(nor);
1562 * Scale the timeout linearly with the size of the flash, with
1563 * a minimum calibrated to an old 2MB flash. We could try to
1564 * pull these from CFI/SFDP, but these values should be good
1567 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1568 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1569 (unsigned long)(mtd->size / SZ_2M));
1570 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1574 /* REVISIT in some cases we could speed up erasing large regions
1575 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1576 * to use "small sector erase", but that's not always optimal.
1579 /* "sector"-at-a-time erase */
1580 } else if (spi_nor_has_uniform_erase(nor)) {
1582 ret = spi_nor_write_enable(nor);
1586 ret = spi_nor_erase_sector(nor, addr);
1590 addr += mtd->erasesize;
1591 len -= mtd->erasesize;
1593 ret = spi_nor_wait_till_ready(nor);
1598 /* erase multiple sectors */
1600 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1605 ret = spi_nor_write_disable(nor);
1608 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
1613 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
1616 struct mtd_info *mtd = &nor->mtd;
1617 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1618 int shift = ffs(mask) - 1;
1626 pow = ((sr & mask) ^ mask) >> shift;
1627 *len = mtd->size >> pow;
1628 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
1631 *ofs = mtd->size - *len;
1636 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
1637 * @locked is false); 0 otherwise
1639 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1648 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
1651 /* Requested range is a sub-range of locked range */
1652 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
1654 /* Requested range does not overlap with locked range */
1655 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
1658 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1661 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
1664 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
1667 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
1671 * Lock a region of the flash. Compatible with ST Micro and similar flash.
1672 * Supports the block protection bits BP{0,1,2} in the status register
1673 * (SR). Does not support these features found in newer SR bitfields:
1674 * - SEC: sector/block protect - only handle SEC=0 (block protect)
1675 * - CMP: complement protect - only support CMP=0 (range is not complemented)
1677 * Support for the following is provided conditionally for some flash:
1678 * - TB: top/bottom protect
1680 * Sample table portion for 8MB flash (Winbond w25q64fw):
1682 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
1683 * --------------------------------------------------------------------------
1684 * X | X | 0 | 0 | 0 | NONE | NONE
1685 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
1686 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
1687 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
1688 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
1689 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
1690 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
1691 * X | X | 1 | 1 | 1 | 8 MB | ALL
1692 * ------|-------|-------|-------|-------|---------------|-------------------
1693 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
1694 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
1695 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
1696 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
1697 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
1698 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
1700 * Returns negative on errors, 0 on success.
1702 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1704 struct mtd_info *mtd = &nor->mtd;
1705 int ret, status_old, status_new;
1706 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1707 u8 shift = ffs(mask) - 1, pow, val;
1709 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1712 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1716 status_old = nor->bouncebuf[0];
1718 /* If nothing in our range is unlocked, we don't need to do anything */
1719 if (stm_is_locked_sr(nor, ofs, len, status_old))
1722 /* If anything below us is unlocked, we can't use 'bottom' protection */
1723 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
1724 can_be_bottom = false;
1726 /* If anything above us is unlocked, we can't use 'top' protection */
1727 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
1731 if (!can_be_bottom && !can_be_top)
1734 /* Prefer top, if both are valid */
1735 use_top = can_be_top;
1737 /* lock_len: length of region that should end up locked */
1739 lock_len = mtd->size - ofs;
1741 lock_len = ofs + len;
1744 * Need smallest pow such that:
1746 * 1 / (2^pow) <= (len / size)
1748 * so (assuming power-of-2 size) we do:
1750 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
1752 pow = ilog2(mtd->size) - ilog2(lock_len);
1753 val = mask - (pow << shift);
1756 /* Don't "lock" with no region! */
1760 status_new = (status_old & ~mask & ~SR_TB) | val;
1762 /* Disallow further writes if WP pin is asserted */
1763 status_new |= SR_SRWD;
1766 status_new |= SR_TB;
1768 /* Don't bother if they're the same */
1769 if (status_new == status_old)
1772 /* Only modify protection if it will not unlock other areas */
1773 if ((status_new & mask) < (status_old & mask))
1776 return spi_nor_write_sr_and_check(nor, status_new);
1780 * Unlock a region of the flash. See stm_lock() for more info
1782 * Returns negative on errors, 0 on success.
1784 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1786 struct mtd_info *mtd = &nor->mtd;
1787 int ret, status_old, status_new;
1788 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
1789 u8 shift = ffs(mask) - 1, pow, val;
1791 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
1794 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1798 status_old = nor->bouncebuf[0];
1800 /* If nothing in our range is locked, we don't need to do anything */
1801 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
1804 /* If anything below us is locked, we can't use 'top' protection */
1805 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
1808 /* If anything above us is locked, we can't use 'bottom' protection */
1809 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
1811 can_be_bottom = false;
1813 if (!can_be_bottom && !can_be_top)
1816 /* Prefer top, if both are valid */
1817 use_top = can_be_top;
1819 /* lock_len: length of region that should remain locked */
1821 lock_len = mtd->size - (ofs + len);
1826 * Need largest pow such that:
1828 * 1 / (2^pow) >= (len / size)
1830 * so (assuming power-of-2 size) we do:
1832 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
1834 pow = ilog2(mtd->size) - order_base_2(lock_len);
1835 if (lock_len == 0) {
1836 val = 0; /* fully unlocked */
1838 val = mask - (pow << shift);
1839 /* Some power-of-two sizes are not supported */
1844 status_new = (status_old & ~mask & ~SR_TB) | val;
1846 /* Don't protect status register if we're fully unlocked */
1848 status_new &= ~SR_SRWD;
1851 status_new |= SR_TB;
1853 /* Don't bother if they're the same */
1854 if (status_new == status_old)
1857 /* Only modify protection if it will not lock other areas */
1858 if ((status_new & mask) > (status_old & mask))
1861 return spi_nor_write_sr_and_check(nor, status_new);
1865 * Check if a region of the flash is (completely) locked. See stm_lock() for
1868 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
1869 * negative on errors.
1871 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1875 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1879 return stm_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
1882 static const struct spi_nor_locking_ops stm_locking_ops = {
1884 .unlock = stm_unlock,
1885 .is_locked = stm_is_locked,
1888 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1890 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1893 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
1897 ret = nor->params.locking_ops->lock(nor, ofs, len);
1899 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1903 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1905 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1908 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1912 ret = nor->params.locking_ops->unlock(nor, ofs, len);
1914 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1918 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1920 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1923 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1927 ret = nor->params.locking_ops->is_locked(nor, ofs, len);
1929 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1934 * macronix_quad_enable() - set QE bit in Status Register.
1935 * @nor: pointer to a 'struct spi_nor'
1937 * Set the Quad Enable (QE) bit in the Status Register.
1939 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1941 * Return: 0 on success, -errno otherwise.
1943 static int macronix_quad_enable(struct spi_nor *nor)
1947 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1951 if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
1954 nor->bouncebuf[0] |= SR_QUAD_EN_MX;
1956 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
1960 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1964 if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
1965 dev_dbg(nor->dev, "Macronix Quad bit not set\n");
1973 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1974 * @nor: pointer to a 'struct spi_nor'
1976 * Set the Quad Enable (QE) bit in the Configuration Register.
1977 * This function should be used with QSPI memories not supporting the Read
1978 * Configuration Register (35h) instruction.
1980 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1983 * Return: 0 on success, -errno otherwise.
1985 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1987 u8 *sr_cr = nor->bouncebuf;
1990 /* Keep the current value of the Status Register. */
1991 ret = spi_nor_read_sr(nor, sr_cr);
1995 sr_cr[1] = CR_QUAD_EN_SPAN;
1997 return spi_nor_write_sr(nor, sr_cr, 2);
2001 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
2002 * @nor: pointer to a 'struct spi_nor'
2004 * Set the Quad Enable (QE) bit in the Configuration Register.
2005 * This function should be used with QSPI memories supporting the Read
2006 * Configuration Register (35h) instruction.
2008 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
2011 * Return: 0 on success, -errno otherwise.
2013 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
2015 u8 *sr_cr = nor->bouncebuf;
2018 /* Check current Quad Enable bit value. */
2019 ret = spi_nor_read_cr(nor, &sr_cr[1]);
2023 if (sr_cr[1] & CR_QUAD_EN_SPAN)
2026 sr_cr[1] |= CR_QUAD_EN_SPAN;
2028 /* Keep the current value of the Status Register. */
2029 ret = spi_nor_read_sr(nor, sr_cr);
2033 ret = spi_nor_write_sr(nor, sr_cr, 2);
2037 /* Read back and check it. */
2038 ret = spi_nor_read_cr(nor, &sr_cr[1]);
2042 if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
2043 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
2051 * sr2_bit7_quad_enable() - set QE bit in Status Register 2.
2052 * @nor: pointer to a 'struct spi_nor'
2054 * Set the Quad Enable (QE) bit in the Status Register 2.
2056 * This is one of the procedures to set the QE bit described in the SFDP
2057 * (JESD216 rev B) specification but no manufacturer using this procedure has
2058 * been identified yet, hence the name of the function.
2060 * Return: 0 on success, -errno otherwise.
2062 static int sr2_bit7_quad_enable(struct spi_nor *nor)
2064 u8 *sr2 = nor->bouncebuf;
2067 /* Check current Quad Enable bit value. */
2068 ret = spi_nor_read_sr2(nor, sr2);
2071 if (*sr2 & SR2_QUAD_EN_BIT7)
2074 /* Update the Quad Enable bit. */
2075 *sr2 |= SR2_QUAD_EN_BIT7;
2077 ret = spi_nor_write_sr2(nor, sr2);
2081 /* Read back and check it. */
2082 ret = spi_nor_read_sr2(nor, sr2);
2086 if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
2087 dev_dbg(nor->dev, "SR2 Quad bit not set\n");
2095 * spi_nor_clear_sr_bp() - clear the Status Register Block Protection bits.
2096 * @nor: pointer to a 'struct spi_nor'
2098 * Read-modify-write function that clears the Block Protection bits from the
2099 * Status Register without affecting other bits.
2101 * Return: 0 on success, -errno otherwise.
2103 static int spi_nor_clear_sr_bp(struct spi_nor *nor)
2106 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
2108 ret = spi_nor_read_sr(nor, nor->bouncebuf);
2112 nor->bouncebuf[0] &= ~mask;
2114 return spi_nor_write_sr(nor, nor->bouncebuf, 1);
2118 * spi_nor_spansion_clear_sr_bp() - clear the Status Register Block Protection
2119 * bits on spansion flashes.
2120 * @nor: pointer to a 'struct spi_nor'
2122 * Read-modify-write function that clears the Block Protection bits from the
2123 * Status Register without affecting other bits. The function is tightly
2124 * coupled with the spansion_read_cr_quad_enable() function. Both assume that
2125 * the Write Register with 16 bits, together with the Read Configuration
2126 * Register (35h) instructions are supported.
2128 * Return: 0 on success, -errno otherwise.
2130 static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
2133 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
2134 u8 *sr_cr = nor->bouncebuf;
2136 /* Check current Quad Enable bit value. */
2137 ret = spi_nor_read_cr(nor, &sr_cr[1]);
2142 * When the configuration register Quad Enable bit is one, only the
2143 * Write Status (01h) command with two data bytes may be used.
2145 if (sr_cr[1] & CR_QUAD_EN_SPAN) {
2146 ret = spi_nor_read_sr(nor, sr_cr);
2152 return spi_nor_write_sr(nor, sr_cr, 2);
2156 * If the Quad Enable bit is zero, use the Write Status (01h) command
2157 * with one data byte.
2159 return spi_nor_clear_sr_bp(nor);
2162 /* Used when the "_ext_id" is two bytes at most */
2163 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
2165 ((_jedec_id) >> 16) & 0xff, \
2166 ((_jedec_id) >> 8) & 0xff, \
2167 (_jedec_id) & 0xff, \
2168 ((_ext_id) >> 8) & 0xff, \
2171 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
2172 .sector_size = (_sector_size), \
2173 .n_sectors = (_n_sectors), \
2177 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
2179 ((_jedec_id) >> 16) & 0xff, \
2180 ((_jedec_id) >> 8) & 0xff, \
2181 (_jedec_id) & 0xff, \
2182 ((_ext_id) >> 16) & 0xff, \
2183 ((_ext_id) >> 8) & 0xff, \
2187 .sector_size = (_sector_size), \
2188 .n_sectors = (_n_sectors), \
2192 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
2193 .sector_size = (_sector_size), \
2194 .n_sectors = (_n_sectors), \
2195 .page_size = (_page_size), \
2196 .addr_width = (_addr_width), \
2199 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
2201 ((_jedec_id) >> 16) & 0xff, \
2202 ((_jedec_id) >> 8) & 0xff, \
2203 (_jedec_id) & 0xff \
2206 .sector_size = (8*_page_size), \
2207 .n_sectors = (_n_sectors), \
2208 .page_size = _page_size, \
2210 .flags = SPI_NOR_NO_FR | SPI_S3AN,
2213 is25lp256_post_bfpt_fixups(struct spi_nor *nor,
2214 const struct sfdp_parameter_header *bfpt_header,
2215 const struct sfdp_bfpt *bfpt,
2216 struct spi_nor_flash_parameter *params)
2219 * IS25LP256 supports 4B opcodes, but the BFPT advertises a
2220 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
2221 * Overwrite the address width advertised by the BFPT.
2223 if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
2224 BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
2225 nor->addr_width = 4;
2230 static struct spi_nor_fixups is25lp256_fixups = {
2231 .post_bfpt = is25lp256_post_bfpt_fixups,
2235 mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
2236 const struct sfdp_parameter_header *bfpt_header,
2237 const struct sfdp_bfpt *bfpt,
2238 struct spi_nor_flash_parameter *params)
2241 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
2242 * Unfortunately, Macronix has re-used the same JEDEC ID for both
2243 * variants which prevents us from defining a new entry in the parts
2245 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
2246 * seems that the F version advertises support for Fast Read 4-4-4 in
2249 if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
2250 nor->flags |= SNOR_F_4B_OPCODES;
2255 static struct spi_nor_fixups mx25l25635_fixups = {
2256 .post_bfpt = mx25l25635_post_bfpt_fixups,
2259 static void gd25q256_default_init(struct spi_nor *nor)
2262 * Some manufacturer like GigaDevice may use different
2263 * bit to set QE on different memories, so the MFR can't
2264 * indicate the quad_enable method for this case, we need
2265 * to set it in the default_init fixup hook.
2267 nor->params.quad_enable = macronix_quad_enable;
2270 static struct spi_nor_fixups gd25q256_fixups = {
2271 .default_init = gd25q256_default_init,
2274 /* NOTE: double check command sets and memory organization when you add
2275 * more nor chips. This current list focusses on newer chips, which
2276 * have been converging on command sets which including JEDEC ID.
2278 * All newly added entries should describe *hardware* and should use SECT_4K
2279 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
2280 * scenarios excluding small sectors there is config option that can be
2281 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
2282 * For historical (and compatibility) reasons (before we got above config) some
2283 * old entries may be missing 4K flag.
2285 static const struct flash_info spi_nor_ids[] = {
2286 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
2287 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
2288 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
2290 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
2291 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
2292 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
2293 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
2295 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
2296 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
2297 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
2298 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
2300 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
2302 /* EON -- en25xxx */
2303 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
2304 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
2305 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
2306 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
2307 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
2308 { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
2309 SECT_4K | SPI_NOR_DUAL_READ) },
2310 { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32,
2311 SECT_4K | SPI_NOR_DUAL_READ) },
2312 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
2313 { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128,
2314 SECT_4K | SPI_NOR_DUAL_READ) },
2315 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
2316 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
2317 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
2320 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
2321 { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
2322 { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
2325 { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2326 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2327 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2328 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2331 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
2335 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
2336 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2337 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2340 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
2341 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2342 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2345 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
2346 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2347 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2350 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
2351 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2352 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2355 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
2356 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2357 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2360 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
2361 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2362 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2365 "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
2366 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2367 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2368 .fixups = &gd25q256_fixups,
2371 /* Intel/Numonyx -- xxxs33b */
2372 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
2373 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
2374 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
2377 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
2378 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
2379 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2380 { "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
2381 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2382 { "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
2383 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2384 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
2385 SECT_4K | SPI_NOR_DUAL_READ) },
2386 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
2387 SECT_4K | SPI_NOR_DUAL_READ) },
2388 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
2389 SECT_4K | SPI_NOR_DUAL_READ) },
2390 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
2391 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2393 .fixups = &is25lp256_fixups },
2394 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
2395 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2396 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
2397 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2398 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
2399 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2402 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
2403 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
2404 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
2405 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
2406 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
2407 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
2408 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
2409 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
2410 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
2411 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
2412 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2413 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
2414 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
2415 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
2416 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
2417 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
2418 { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
2419 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2420 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
2421 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
2422 .fixups = &mx25l25635_fixups },
2423 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
2424 { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
2425 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2426 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
2427 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2428 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2429 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2430 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
2432 /* Micron <--> ST Micro */
2433 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
2434 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2435 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
2436 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2437 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
2438 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
2439 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
2440 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2441 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
2442 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
2443 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2444 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2445 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
2446 SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
2448 { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
2449 SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
2451 SPI_NOR_4B_OPCODES) },
2452 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
2456 "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
2457 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2460 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
2461 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
2462 SPI_NOR_4B_OPCODES) },
2465 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
2466 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
2467 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
2469 /* Spansion/Cypress -- single (large) sector size only, at least
2470 * for the chips listed here (without boot sectors).
2472 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2473 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2474 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
2475 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2476 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
2477 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2478 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
2479 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2480 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
2481 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2482 SPI_NOR_HAS_LOCK | USE_CLSR) },
2483 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2484 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
2485 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
2486 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
2487 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2488 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
2489 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
2490 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
2491 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
2492 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
2493 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
2494 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2495 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2496 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2497 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2498 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2499 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
2500 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
2501 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
2502 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
2503 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2504 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2505 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
2507 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
2508 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2509 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2510 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
2511 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
2512 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
2513 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
2514 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
2515 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
2516 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
2517 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
2518 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
2519 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
2520 { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K |
2521 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2522 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2524 /* ST Microelectronics -- newer production may have feature updates */
2525 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
2526 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
2527 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
2528 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
2529 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
2530 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
2531 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
2532 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
2533 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
2535 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
2536 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
2537 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
2538 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
2539 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
2540 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
2541 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
2542 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
2543 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
2545 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
2546 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
2547 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
2549 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
2550 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
2551 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
2553 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
2554 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
2555 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
2556 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
2557 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
2558 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
2560 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
2561 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
2562 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
2563 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
2564 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
2565 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
2566 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
2568 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
2569 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2570 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2572 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
2574 "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
2575 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2576 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2578 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
2579 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
2580 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
2581 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
2583 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
2584 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2585 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2588 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
2589 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2590 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2592 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
2593 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
2595 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
2596 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2597 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2600 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
2601 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2602 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2605 "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
2606 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
2607 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
2609 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
2610 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
2611 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
2612 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2613 { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
2614 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2615 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
2616 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
2618 /* Catalyst / On Semiconductor -- non-JEDEC */
2619 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2620 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2621 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2622 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2623 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
2625 /* Xilinx S3AN Internal Flash */
2626 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
2627 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
2628 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
2629 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
2630 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
2632 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
2633 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2634 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
2638 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
2641 u8 *id = nor->bouncebuf;
2642 const struct flash_info *info;
2645 struct spi_mem_op op =
2646 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
2648 SPI_MEM_OP_NO_DUMMY,
2649 SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1));
2651 tmp = spi_mem_exec_op(nor->spimem, &op);
2653 tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
2654 SPI_NOR_MAX_ID_LEN);
2657 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
2658 return ERR_PTR(tmp);
2661 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
2662 info = &spi_nor_ids[tmp];
2664 if (!memcmp(info->id, id, info->id_len))
2665 return &spi_nor_ids[tmp];
2668 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2669 SPI_NOR_MAX_ID_LEN, id);
2670 return ERR_PTR(-ENODEV);
2673 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2674 size_t *retlen, u_char *buf)
2676 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2679 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2681 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
2688 addr = spi_nor_convert_addr(nor, addr);
2690 ret = spi_nor_read_data(nor, addr, len, buf);
2692 /* We shouldn't see 0-length reads */
2708 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
2712 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
2713 size_t *retlen, const u_char *buf)
2715 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2719 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2721 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2725 ret = spi_nor_write_enable(nor);
2729 nor->sst_write_second = false;
2731 /* Start write from odd address. */
2733 nor->program_opcode = SPINOR_OP_BP;
2735 /* write one byte. */
2736 ret = spi_nor_write_data(nor, to, 1, buf);
2739 WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
2740 ret = spi_nor_wait_till_ready(nor);
2748 /* Write out most of the data here. */
2749 for (; actual < len - 1; actual += 2) {
2750 nor->program_opcode = SPINOR_OP_AAI_WP;
2752 /* write two bytes. */
2753 ret = spi_nor_write_data(nor, to, 2, buf + actual);
2756 WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
2757 ret = spi_nor_wait_till_ready(nor);
2761 nor->sst_write_second = true;
2763 nor->sst_write_second = false;
2765 ret = spi_nor_write_disable(nor);
2769 ret = spi_nor_wait_till_ready(nor);
2773 /* Write out trailing byte if it exists. */
2774 if (actual != len) {
2775 ret = spi_nor_write_enable(nor);
2779 nor->program_opcode = SPINOR_OP_BP;
2780 ret = spi_nor_write_data(nor, to, 1, buf + actual);
2783 WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
2784 ret = spi_nor_wait_till_ready(nor);
2790 ret = spi_nor_write_disable(nor);
2794 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2799 * Write an address range to the nor chip. Data must be written in
2800 * FLASH_PAGESIZE chunks. The address range may be any size provided
2801 * it is within the physical boundaries.
2803 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2804 size_t *retlen, const u_char *buf)
2806 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2807 size_t page_offset, page_remain, i;
2810 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2812 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
2816 for (i = 0; i < len; ) {
2818 loff_t addr = to + i;
2821 * If page_size is a power of two, the offset can be quickly
2822 * calculated with an AND operation. On the other cases we
2823 * need to do a modulus operation (more expensive).
2824 * Power of two numbers have only one bit set and we can use
2825 * the instruction hweight32 to detect if we need to do a
2826 * modulus (do_div()) or not.
2828 if (hweight32(nor->page_size) == 1) {
2829 page_offset = addr & (nor->page_size - 1);
2831 uint64_t aux = addr;
2833 page_offset = do_div(aux, nor->page_size);
2835 /* the size of data remaining on the first page */
2836 page_remain = min_t(size_t,
2837 nor->page_size - page_offset, len - i);
2839 addr = spi_nor_convert_addr(nor, addr);
2841 ret = spi_nor_write_enable(nor);
2845 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2850 ret = spi_nor_wait_till_ready(nor);
2858 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
2862 static int spi_nor_check(struct spi_nor *nor)
2865 (!nor->spimem && nor->controller_ops &&
2866 (!nor->controller_ops->read ||
2867 !nor->controller_ops->write ||
2868 !nor->controller_ops->read_reg ||
2869 !nor->controller_ops->write_reg))) {
2870 pr_err("spi-nor: please fill all the necessary fields!\n");
2877 static int s3an_nor_setup(struct spi_nor *nor,
2878 const struct spi_nor_hwcaps *hwcaps)
2882 ret = spi_nor_xread_sr(nor, nor->bouncebuf);
2886 nor->erase_opcode = SPINOR_OP_XSE;
2887 nor->program_opcode = SPINOR_OP_XPP;
2888 nor->read_opcode = SPINOR_OP_READ;
2889 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2892 * This flashes have a page size of 264 or 528 bytes (known as
2893 * Default addressing mode). It can be changed to a more standard
2894 * Power of two mode where the page size is 256/512. This comes
2895 * with a price: there is 3% less of space, the data is corrupted
2896 * and the page size cannot be changed back to default addressing
2899 * The current addressing mode can be read from the XRDSR register
2900 * and should not be changed, because is a destructive operation.
2902 if (nor->bouncebuf[0] & XSR_PAGESIZE) {
2903 /* Flash in Power of 2 mode */
2904 nor->page_size = (nor->page_size == 264) ? 256 : 512;
2905 nor->mtd.writebufsize = nor->page_size;
2906 nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
2907 nor->mtd.erasesize = 8 * nor->page_size;
2909 /* Flash in Default addressing mode */
2910 nor->params.convert_addr = s3an_convert_addr;
2911 nor->mtd.erasesize = nor->info->sector_size;
2918 spi_nor_set_read_settings(struct spi_nor_read_command *read,
2922 enum spi_nor_protocol proto)
2924 read->num_mode_clocks = num_mode_clocks;
2925 read->num_wait_states = num_wait_states;
2926 read->opcode = opcode;
2927 read->proto = proto;
2931 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
2933 enum spi_nor_protocol proto)
2935 pp->opcode = opcode;
2939 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2943 for (i = 0; i < size; i++)
2944 if (table[i][0] == (int)hwcaps)
2950 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2952 static const int hwcaps_read2cmd[][2] = {
2953 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2954 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2955 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2956 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2957 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2958 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2959 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2960 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2961 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2962 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2963 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2964 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2965 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2966 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2967 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2970 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2971 ARRAY_SIZE(hwcaps_read2cmd));
2974 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2976 static const int hwcaps_pp2cmd[][2] = {
2977 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2978 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2979 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2980 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2981 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2982 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2983 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2986 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2987 ARRAY_SIZE(hwcaps_pp2cmd));
2991 * Serial Flash Discoverable Parameters (SFDP) parsing.
2995 * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
2996 * addr_width and read_dummy members of the struct spi_nor
2997 * should be previously
2999 * @nor: pointer to a 'struct spi_nor'
3000 * @addr: offset in the serial flash memory
3001 * @len: number of bytes to read
3002 * @buf: buffer where the data is copied into (dma-safe memory)
3004 * Return: 0 on success, -errno otherwise.
3006 static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
3011 ret = spi_nor_read_data(nor, addr, len, buf);
3014 if (!ret || ret > len)
3025 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
3026 * @nor: pointer to a 'struct spi_nor'
3027 * @addr: offset in the SFDP area to start reading data from
3028 * @len: number of bytes to read
3029 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
3031 * Whatever the actual numbers of bytes for address and dummy cycles are
3032 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
3033 * followed by a 3-byte address and 8 dummy clock cycles.
3035 * Return: 0 on success, -errno otherwise.
3037 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
3038 size_t len, void *buf)
3040 u8 addr_width, read_opcode, read_dummy;
3043 read_opcode = nor->read_opcode;
3044 addr_width = nor->addr_width;
3045 read_dummy = nor->read_dummy;
3047 nor->read_opcode = SPINOR_OP_RDSFDP;
3048 nor->addr_width = 3;
3049 nor->read_dummy = 8;
3051 ret = spi_nor_read_raw(nor, addr, len, buf);
3053 nor->read_opcode = read_opcode;
3054 nor->addr_width = addr_width;
3055 nor->read_dummy = read_dummy;
3061 * spi_nor_spimem_check_op - check if the operation is supported
3063 *@nor: pointer to a 'struct spi_nor'
3064 *@op: pointer to op template to be checked
3066 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3068 static int spi_nor_spimem_check_op(struct spi_nor *nor,
3069 struct spi_mem_op *op)
3072 * First test with 4 address bytes. The opcode itself might
3073 * be a 3B addressing opcode but we don't care, because
3074 * SPI controller implementation should not check the opcode,
3075 * but just the sequence.
3077 op->addr.nbytes = 4;
3078 if (!spi_mem_supports_op(nor->spimem, op)) {
3079 if (nor->mtd.size > SZ_16M)
3082 /* If flash size <= 16MB, 3 address bytes are sufficient */
3083 op->addr.nbytes = 3;
3084 if (!spi_mem_supports_op(nor->spimem, op))
3092 * spi_nor_spimem_check_readop - check if the read op is supported
3094 *@nor: pointer to a 'struct spi_nor'
3095 *@read: pointer to op template to be checked
3097 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3099 static int spi_nor_spimem_check_readop(struct spi_nor *nor,
3100 const struct spi_nor_read_command *read)
3102 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1),
3103 SPI_MEM_OP_ADDR(3, 0, 1),
3104 SPI_MEM_OP_DUMMY(0, 1),
3105 SPI_MEM_OP_DATA_IN(0, NULL, 1));
3107 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto);
3108 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto);
3109 op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto);
3110 op.dummy.buswidth = op.addr.buswidth;
3111 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
3112 op.dummy.buswidth / 8;
3114 return spi_nor_spimem_check_op(nor, &op);
3118 * spi_nor_spimem_check_pp - check if the page program op is supported
3120 *@nor: pointer to a 'struct spi_nor'
3121 *@pp: pointer to op template to be checked
3123 * Returns 0 if operation is supported, -ENOTSUPP otherwise.
3125 static int spi_nor_spimem_check_pp(struct spi_nor *nor,
3126 const struct spi_nor_pp_command *pp)
3128 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1),
3129 SPI_MEM_OP_ADDR(3, 0, 1),
3130 SPI_MEM_OP_NO_DUMMY,
3131 SPI_MEM_OP_DATA_OUT(0, NULL, 1));
3133 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto);
3134 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
3135 op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
3137 return spi_nor_spimem_check_op(nor, &op);
3141 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
3142 * based on SPI controller capabilities
3143 * @nor: pointer to a 'struct spi_nor'
3144 * @hwcaps: pointer to resulting capabilities after adjusting
3145 * according to controller and flash's capability
3148 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
3150 struct spi_nor_flash_parameter *params = &nor->params;
3153 /* DTR modes are not supported yet, mask them all. */
3154 *hwcaps &= ~SNOR_HWCAPS_DTR;
3156 /* X-X-X modes are not supported yet, mask them all. */
3157 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
3159 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
3162 if (!(*hwcaps & BIT(cap)))
3165 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
3167 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
3168 *hwcaps &= ~BIT(cap);
3170 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
3174 if (spi_nor_spimem_check_pp(nor,
3175 ¶ms->page_programs[ppidx]))
3176 *hwcaps &= ~BIT(cap);
3181 * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters.
3182 * @nor: pointer to a 'struct spi_nor'
3183 * @addr: offset in the SFDP area to start reading data from
3184 * @len: number of bytes to read
3185 * @buf: buffer where the SFDP data are copied into
3187 * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not
3188 * guaranteed to be dma-safe.
3190 * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp()
3193 static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
3194 size_t len, void *buf)
3199 dma_safe_buf = kmalloc(len, GFP_KERNEL);
3203 ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf);
3204 memcpy(buf, dma_safe_buf, len);
3205 kfree(dma_safe_buf);
3210 /* Fast Read settings. */
3213 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
3215 enum spi_nor_protocol proto)
3217 read->num_mode_clocks = (half >> 5) & 0x07;
3218 read->num_wait_states = (half >> 0) & 0x1f;
3219 read->opcode = (half >> 8) & 0xff;
3220 read->proto = proto;
3223 struct sfdp_bfpt_read {
3224 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
3228 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
3229 * whether the Fast Read x-y-z command is supported.
3231 u32 supported_dword;
3235 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
3236 * encodes the op code, the number of mode clocks and the number of wait
3237 * states to be used by Fast Read x-y-z command.
3242 /* The SPI protocol for this Fast Read x-y-z command. */
3243 enum spi_nor_protocol proto;
3246 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
3247 /* Fast Read 1-1-2 */
3249 SNOR_HWCAPS_READ_1_1_2,
3250 BFPT_DWORD(1), BIT(16), /* Supported bit */
3251 BFPT_DWORD(4), 0, /* Settings */
3255 /* Fast Read 1-2-2 */
3257 SNOR_HWCAPS_READ_1_2_2,
3258 BFPT_DWORD(1), BIT(20), /* Supported bit */
3259 BFPT_DWORD(4), 16, /* Settings */
3263 /* Fast Read 2-2-2 */
3265 SNOR_HWCAPS_READ_2_2_2,
3266 BFPT_DWORD(5), BIT(0), /* Supported bit */
3267 BFPT_DWORD(6), 16, /* Settings */
3271 /* Fast Read 1-1-4 */
3273 SNOR_HWCAPS_READ_1_1_4,
3274 BFPT_DWORD(1), BIT(22), /* Supported bit */
3275 BFPT_DWORD(3), 16, /* Settings */
3279 /* Fast Read 1-4-4 */
3281 SNOR_HWCAPS_READ_1_4_4,
3282 BFPT_DWORD(1), BIT(21), /* Supported bit */
3283 BFPT_DWORD(3), 0, /* Settings */
3287 /* Fast Read 4-4-4 */
3289 SNOR_HWCAPS_READ_4_4_4,
3290 BFPT_DWORD(5), BIT(4), /* Supported bit */
3291 BFPT_DWORD(7), 16, /* Settings */
3296 struct sfdp_bfpt_erase {
3298 * The half-word at offset <shift> in DWORD <dwoard> encodes the
3299 * op code and erase sector size to be used by Sector Erase commands.
3305 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
3306 /* Erase Type 1 in DWORD8 bits[15:0] */
3309 /* Erase Type 2 in DWORD8 bits[31:16] */
3310 {BFPT_DWORD(8), 16},
3312 /* Erase Type 3 in DWORD9 bits[15:0] */
3315 /* Erase Type 4 in DWORD9 bits[31:16] */
3316 {BFPT_DWORD(9), 16},
3320 * spi_nor_set_erase_type() - set a SPI NOR erase type
3321 * @erase: pointer to a structure that describes a SPI NOR erase type
3322 * @size: the size of the sector/block erased by the erase type
3323 * @opcode: the SPI command op code to erase the sector/block
3325 static void spi_nor_set_erase_type(struct spi_nor_erase_type *erase,
3326 u32 size, u8 opcode)
3329 erase->opcode = opcode;
3330 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
3331 erase->size_shift = ffs(erase->size) - 1;
3332 erase->size_mask = (1 << erase->size_shift) - 1;
3336 * spi_nor_set_erase_settings_from_bfpt() - set erase type settings from BFPT
3337 * @erase: pointer to a structure that describes a SPI NOR erase type
3338 * @size: the size of the sector/block erased by the erase type
3339 * @opcode: the SPI command op code to erase the sector/block
3340 * @i: erase type index as sorted in the Basic Flash Parameter Table
3342 * The supported Erase Types will be sorted at init in ascending order, with
3343 * the smallest Erase Type size being the first member in the erase_type array
3344 * of the spi_nor_erase_map structure. Save the Erase Type index as sorted in
3345 * the Basic Flash Parameter Table since it will be used later on to
3346 * synchronize with the supported Erase Types defined in SFDP optional tables.
3349 spi_nor_set_erase_settings_from_bfpt(struct spi_nor_erase_type *erase,
3350 u32 size, u8 opcode, u8 i)
3353 spi_nor_set_erase_type(erase, size, opcode);
3357 * spi_nor_map_cmp_erase_type() - compare the map's erase types by size
3358 * @l: member in the left half of the map's erase_type array
3359 * @r: member in the right half of the map's erase_type array
3361 * Comparison function used in the sort() call to sort in ascending order the
3362 * map's erase types, the smallest erase type size being the first member in the
3363 * sorted erase_type array.
3365 * Return: the result of @l->size - @r->size
3367 static int spi_nor_map_cmp_erase_type(const void *l, const void *r)
3369 const struct spi_nor_erase_type *left = l, *right = r;
3371 return left->size - right->size;
3375 * spi_nor_sort_erase_mask() - sort erase mask
3376 * @map: the erase map of the SPI NOR
3377 * @erase_mask: the erase type mask to be sorted
3379 * Replicate the sort done for the map's erase types in BFPT: sort the erase
3380 * mask in ascending order with the smallest erase type size starting from
3381 * BIT(0) in the sorted erase mask.
3383 * Return: sorted erase mask.
3385 static u8 spi_nor_sort_erase_mask(struct spi_nor_erase_map *map, u8 erase_mask)
3387 struct spi_nor_erase_type *erase_type = map->erase_type;
3389 u8 sorted_erase_mask = 0;
3394 /* Replicate the sort done for the map's erase types. */
3395 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3396 if (erase_type[i].size && erase_mask & BIT(erase_type[i].idx))
3397 sorted_erase_mask |= BIT(i);
3399 return sorted_erase_mask;
3403 * spi_nor_regions_sort_erase_types() - sort erase types in each region
3404 * @map: the erase map of the SPI NOR
3406 * Function assumes that the erase types defined in the erase map are already
3407 * sorted in ascending order, with the smallest erase type size being the first
3408 * member in the erase_type array. It replicates the sort done for the map's
3409 * erase types. Each region's erase bitmask will indicate which erase types are
3410 * supported from the sorted erase types defined in the erase map.
3411 * Sort the all region's erase type at init in order to speed up the process of
3412 * finding the best erase command at runtime.
3414 static void spi_nor_regions_sort_erase_types(struct spi_nor_erase_map *map)
3416 struct spi_nor_erase_region *region = map->regions;
3417 u8 region_erase_mask, sorted_erase_mask;
3420 region_erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
3422 sorted_erase_mask = spi_nor_sort_erase_mask(map,
3425 /* Overwrite erase mask. */
3426 region->offset = (region->offset & ~SNOR_ERASE_TYPE_MASK) |
3429 region = spi_nor_region_next(region);
3434 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
3435 * @map: the erase map of the SPI NOR
3436 * @erase_mask: bitmask encoding erase types that can erase the entire
3438 * @flash_size: the spi nor flash memory size
3440 static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
3441 u8 erase_mask, u64 flash_size)
3443 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */
3444 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) |
3446 map->uniform_region.size = flash_size;
3447 map->regions = &map->uniform_region;
3448 map->uniform_erase_type = erase_mask;
3452 spi_nor_post_bfpt_fixups(struct spi_nor *nor,
3453 const struct sfdp_parameter_header *bfpt_header,
3454 const struct sfdp_bfpt *bfpt,
3455 struct spi_nor_flash_parameter *params)
3457 if (nor->info->fixups && nor->info->fixups->post_bfpt)
3458 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
3465 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
3466 * @nor: pointer to a 'struct spi_nor'
3467 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
3468 * the Basic Flash Parameter Table length and version
3469 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
3472 * The Basic Flash Parameter Table is the main and only mandatory table as
3473 * defined by the SFDP (JESD216) specification.
3474 * It provides us with the total size (memory density) of the data array and
3475 * the number of address bytes for Fast Read, Page Program and Sector Erase
3477 * For Fast READ commands, it also gives the number of mode clock cycles and
3478 * wait states (regrouped in the number of dummy clock cycles) for each
3479 * supported instruction op code.
3480 * For Page Program, the page size is now available since JESD216 rev A, however
3481 * the supported instruction op codes are still not provided.
3482 * For Sector Erase commands, this table stores the supported instruction op
3483 * codes and the associated sector sizes.
3484 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
3485 * rev A. The QER bits encode the manufacturer dependent procedure to be
3486 * executed to set the Quad Enable (QE) bit in some internal register of the
3487 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
3488 * sending any Quad SPI command to the memory. Actually, setting the QE bit
3489 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
3490 * and IO3 hence enabling 4 (Quad) I/O lines.
3492 * Return: 0 on success, -errno otherwise.
3494 static int spi_nor_parse_bfpt(struct spi_nor *nor,
3495 const struct sfdp_parameter_header *bfpt_header,
3496 struct spi_nor_flash_parameter *params)
3498 struct spi_nor_erase_map *map = ¶ms->erase_map;
3499 struct spi_nor_erase_type *erase_type = map->erase_type;
3500 struct sfdp_bfpt bfpt;
3507 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
3508 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
3511 /* Read the Basic Flash Parameter Table. */
3512 len = min_t(size_t, sizeof(bfpt),
3513 bfpt_header->length * sizeof(u32));
3514 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
3515 memset(&bfpt, 0, sizeof(bfpt));
3516 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
3520 /* Fix endianness of the BFPT DWORDs. */
3521 for (i = 0; i < BFPT_DWORD_MAX; i++)
3522 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
3524 /* Number of address bytes. */
3525 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
3526 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
3527 nor->addr_width = 3;
3530 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
3531 nor->addr_width = 4;
3538 /* Flash Memory Density (in bits). */
3539 params->size = bfpt.dwords[BFPT_DWORD(2)];
3540 if (params->size & BIT(31)) {
3541 params->size &= ~BIT(31);
3544 * Prevent overflows on params->size. Anyway, a NOR of 2^64
3545 * bits is unlikely to exist so this error probably means
3546 * the BFPT we are reading is corrupted/wrong.
3548 if (params->size > 63)
3551 params->size = 1ULL << params->size;
3555 params->size >>= 3; /* Convert to bytes. */
3557 /* Fast Read settings. */
3558 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
3559 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
3560 struct spi_nor_read_command *read;
3562 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
3563 params->hwcaps.mask &= ~rd->hwcaps;
3567 params->hwcaps.mask |= rd->hwcaps;
3568 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
3569 read = ¶ms->reads[cmd];
3570 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
3571 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
3575 * Sector Erase settings. Reinitialize the uniform erase map using the
3576 * Erase Types defined in the bfpt table.
3579 memset(¶ms->erase_map, 0, sizeof(params->erase_map));
3580 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
3581 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
3585 half = bfpt.dwords[er->dword] >> er->shift;
3586 erasesize = half & 0xff;
3588 /* erasesize == 0 means this Erase Type is not supported. */
3592 erasesize = 1U << erasesize;
3593 opcode = (half >> 8) & 0xff;
3594 erase_mask |= BIT(i);
3595 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
3598 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
3600 * Sort all the map's Erase Types in ascending order with the smallest
3601 * erase size being the first member in the erase_type array.
3603 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
3604 spi_nor_map_cmp_erase_type, NULL);
3606 * Sort the erase types in the uniform region in order to update the
3607 * uniform_erase_type bitmask. The bitmask will be used later on when
3608 * selecting the uniform erase.
3610 spi_nor_regions_sort_erase_types(map);
3611 map->uniform_erase_type = map->uniform_region.offset &
3612 SNOR_ERASE_TYPE_MASK;
3614 /* Stop here if not JESD216 rev A or later. */
3615 if (bfpt_header->length < BFPT_DWORD_MAX)
3616 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
3619 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
3620 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
3621 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
3622 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
3623 params->page_size = 1U << params->page_size;
3625 /* Quad Enable Requirements. */
3626 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
3627 case BFPT_DWORD15_QER_NONE:
3628 params->quad_enable = NULL;
3631 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
3632 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
3633 params->quad_enable = spansion_no_read_cr_quad_enable;
3636 case BFPT_DWORD15_QER_SR1_BIT6:
3637 params->quad_enable = macronix_quad_enable;
3640 case BFPT_DWORD15_QER_SR2_BIT7:
3641 params->quad_enable = sr2_bit7_quad_enable;
3644 case BFPT_DWORD15_QER_SR2_BIT1:
3645 params->quad_enable = spansion_read_cr_quad_enable;
3652 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
3655 #define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
3656 #define SMPT_CMD_ADDRESS_LEN_0 (0x0UL << 22)
3657 #define SMPT_CMD_ADDRESS_LEN_3 (0x1UL << 22)
3658 #define SMPT_CMD_ADDRESS_LEN_4 (0x2UL << 22)
3659 #define SMPT_CMD_ADDRESS_LEN_USE_CURRENT (0x3UL << 22)
3661 #define SMPT_CMD_READ_DUMMY_MASK GENMASK(19, 16)
3662 #define SMPT_CMD_READ_DUMMY_SHIFT 16
3663 #define SMPT_CMD_READ_DUMMY(_cmd) \
3664 (((_cmd) & SMPT_CMD_READ_DUMMY_MASK) >> SMPT_CMD_READ_DUMMY_SHIFT)
3665 #define SMPT_CMD_READ_DUMMY_IS_VARIABLE 0xfUL
3667 #define SMPT_CMD_READ_DATA_MASK GENMASK(31, 24)
3668 #define SMPT_CMD_READ_DATA_SHIFT 24
3669 #define SMPT_CMD_READ_DATA(_cmd) \
3670 (((_cmd) & SMPT_CMD_READ_DATA_MASK) >> SMPT_CMD_READ_DATA_SHIFT)
3672 #define SMPT_CMD_OPCODE_MASK GENMASK(15, 8)
3673 #define SMPT_CMD_OPCODE_SHIFT 8
3674 #define SMPT_CMD_OPCODE(_cmd) \
3675 (((_cmd) & SMPT_CMD_OPCODE_MASK) >> SMPT_CMD_OPCODE_SHIFT)
3677 #define SMPT_MAP_REGION_COUNT_MASK GENMASK(23, 16)
3678 #define SMPT_MAP_REGION_COUNT_SHIFT 16
3679 #define SMPT_MAP_REGION_COUNT(_header) \
3680 ((((_header) & SMPT_MAP_REGION_COUNT_MASK) >> \
3681 SMPT_MAP_REGION_COUNT_SHIFT) + 1)
3683 #define SMPT_MAP_ID_MASK GENMASK(15, 8)
3684 #define SMPT_MAP_ID_SHIFT 8
3685 #define SMPT_MAP_ID(_header) \
3686 (((_header) & SMPT_MAP_ID_MASK) >> SMPT_MAP_ID_SHIFT)
3688 #define SMPT_MAP_REGION_SIZE_MASK GENMASK(31, 8)
3689 #define SMPT_MAP_REGION_SIZE_SHIFT 8
3690 #define SMPT_MAP_REGION_SIZE(_region) \
3691 (((((_region) & SMPT_MAP_REGION_SIZE_MASK) >> \
3692 SMPT_MAP_REGION_SIZE_SHIFT) + 1) * 256)
3694 #define SMPT_MAP_REGION_ERASE_TYPE_MASK GENMASK(3, 0)
3695 #define SMPT_MAP_REGION_ERASE_TYPE(_region) \
3696 ((_region) & SMPT_MAP_REGION_ERASE_TYPE_MASK)
3698 #define SMPT_DESC_TYPE_MAP BIT(1)
3699 #define SMPT_DESC_END BIT(0)
3702 * spi_nor_smpt_addr_width() - return the address width used in the
3703 * configuration detection command.
3704 * @nor: pointer to a 'struct spi_nor'
3705 * @settings: configuration detection command descriptor, dword1
3707 static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
3709 switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
3710 case SMPT_CMD_ADDRESS_LEN_0:
3712 case SMPT_CMD_ADDRESS_LEN_3:
3714 case SMPT_CMD_ADDRESS_LEN_4:
3716 case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
3719 return nor->addr_width;
3724 * spi_nor_smpt_read_dummy() - return the configuration detection command read
3725 * latency, in clock cycles.
3726 * @nor: pointer to a 'struct spi_nor'
3727 * @settings: configuration detection command descriptor, dword1
3729 * Return: the number of dummy cycles for an SMPT read
3731 static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
3733 u8 read_dummy = SMPT_CMD_READ_DUMMY(settings);
3735 if (read_dummy == SMPT_CMD_READ_DUMMY_IS_VARIABLE)
3736 return nor->read_dummy;
3741 * spi_nor_get_map_in_use() - get the configuration map in use
3742 * @nor: pointer to a 'struct spi_nor'
3743 * @smpt: pointer to the sector map parameter table
3744 * @smpt_len: sector map parameter table length
3746 * Return: pointer to the map in use, ERR_PTR(-errno) otherwise.
3748 static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
3756 u8 addr_width, read_opcode, read_dummy;
3757 u8 read_data_mask, map_id;
3759 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
3760 buf = kmalloc(sizeof(*buf), GFP_KERNEL);
3762 return ERR_PTR(-ENOMEM);
3764 addr_width = nor->addr_width;
3765 read_dummy = nor->read_dummy;
3766 read_opcode = nor->read_opcode;
3769 /* Determine if there are any optional Detection Command Descriptors */
3770 for (i = 0; i < smpt_len; i += 2) {
3771 if (smpt[i] & SMPT_DESC_TYPE_MAP)
3774 read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
3775 nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
3776 nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
3777 nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
3780 err = spi_nor_read_raw(nor, addr, 1, buf);
3787 * Build an index value that is used to select the Sector Map
3788 * Configuration that is currently in use.
3790 map_id = map_id << 1 | !!(*buf & read_data_mask);
3794 * If command descriptors are provided, they always precede map
3795 * descriptors in the table. There is no need to start the iteration
3796 * over smpt array all over again.
3798 * Find the matching configuration map.
3800 ret = ERR_PTR(-EINVAL);
3801 while (i < smpt_len) {
3802 if (SMPT_MAP_ID(smpt[i]) == map_id) {
3808 * If there are no more configuration map descriptors and no
3809 * configuration ID matched the configuration identifier, the
3810 * sector address map is unknown.
3812 if (smpt[i] & SMPT_DESC_END)
3815 /* increment the table index to the next map */
3816 i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
3822 nor->addr_width = addr_width;
3823 nor->read_dummy = read_dummy;
3824 nor->read_opcode = read_opcode;
3829 * spi_nor_region_check_overlay() - set overlay bit when the region is overlaid
3830 * @region: pointer to a structure that describes a SPI NOR erase region
3831 * @erase: pointer to a structure that describes a SPI NOR erase type
3832 * @erase_type: erase type bitmask
3835 spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
3836 const struct spi_nor_erase_type *erase,
3837 const u8 erase_type)
3841 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
3842 if (!(erase_type & BIT(i)))
3844 if (region->size & erase[i].size_mask) {
3845 spi_nor_region_mark_overlay(region);
3852 * spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
3853 * @nor: pointer to a 'struct spi_nor'
3854 * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
3855 * used for storing SFDP parsed data
3856 * @smpt: pointer to the sector map parameter table
3858 * Return: 0 on success, -errno otherwise.
3861 spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
3862 struct spi_nor_flash_parameter *params,
3865 struct spi_nor_erase_map *map = ¶ms->erase_map;
3866 struct spi_nor_erase_type *erase = map->erase_type;
3867 struct spi_nor_erase_region *region;
3871 u8 uniform_erase_type, save_uniform_erase_type;
3872 u8 erase_type, regions_erase_type;
3874 region_count = SMPT_MAP_REGION_COUNT(*smpt);
3876 * The regions will be freed when the driver detaches from the
3879 region = devm_kcalloc(nor->dev, region_count, sizeof(*region),
3883 map->regions = region;
3885 uniform_erase_type = 0xff;
3886 regions_erase_type = 0;
3888 /* Populate regions. */
3889 for (i = 0; i < region_count; i++) {
3890 j = i + 1; /* index for the region dword */
3891 region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
3892 erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
3893 region[i].offset = offset | erase_type;
3895 spi_nor_region_check_overlay(®ion[i], erase, erase_type);
3898 * Save the erase types that are supported in all regions and
3899 * can erase the entire flash memory.
3901 uniform_erase_type &= erase_type;
3904 * regions_erase_type mask will indicate all the erase types
3905 * supported in this configuration map.
3907 regions_erase_type |= erase_type;
3909 offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) +
3913 save_uniform_erase_type = map->uniform_erase_type;
3914 map->uniform_erase_type = spi_nor_sort_erase_mask(map,
3915 uniform_erase_type);
3917 if (!regions_erase_type) {
3919 * Roll back to the previous uniform_erase_type mask, SMPT is
3922 map->uniform_erase_type = save_uniform_erase_type;
3927 * BFPT advertises all the erase types supported by all the possible
3928 * map configurations. Mask out the erase types that are not supported
3929 * by the current map configuration.
3931 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
3932 if (!(regions_erase_type & BIT(erase[i].idx)))
3933 spi_nor_set_erase_type(&erase[i], 0, 0xFF);
3935 spi_nor_region_mark_end(®ion[i - 1]);
3941 * spi_nor_parse_smpt() - parse Sector Map Parameter Table
3942 * @nor: pointer to a 'struct spi_nor'
3943 * @smpt_header: sector map parameter table header
3944 * @params: pointer to a duplicate 'struct spi_nor_flash_parameter'
3945 * that is used for storing SFDP parsed data
3947 * This table is optional, but when available, we parse it to identify the
3948 * location and size of sectors within the main data array of the flash memory
3949 * device and to identify which Erase Types are supported by each sector.
3951 * Return: 0 on success, -errno otherwise.
3953 static int spi_nor_parse_smpt(struct spi_nor *nor,
3954 const struct sfdp_parameter_header *smpt_header,
3955 struct spi_nor_flash_parameter *params)
3957 const u32 *sector_map;
3963 /* Read the Sector Map Parameter Table. */
3964 len = smpt_header->length * sizeof(*smpt);
3965 smpt = kmalloc(len, GFP_KERNEL);
3969 addr = SFDP_PARAM_HEADER_PTP(smpt_header);
3970 ret = spi_nor_read_sfdp(nor, addr, len, smpt);
3974 /* Fix endianness of the SMPT DWORDs. */
3975 for (i = 0; i < smpt_header->length; i++)
3976 smpt[i] = le32_to_cpu(smpt[i]);
3978 sector_map = spi_nor_get_map_in_use(nor, smpt, smpt_header->length);
3979 if (IS_ERR(sector_map)) {
3980 ret = PTR_ERR(sector_map);
3984 ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map);
3988 spi_nor_regions_sort_erase_types(¶ms->erase_map);
3995 #define SFDP_4BAIT_DWORD_MAX 2
3998 /* The hardware capability. */
4002 * The <supported_bit> bit in DWORD1 of the 4BAIT tells us whether
4003 * the associated 4-byte address op code is supported.
4009 * spi_nor_parse_4bait() - parse the 4-Byte Address Instruction Table
4010 * @nor: pointer to a 'struct spi_nor'.
4011 * @param_header: pointer to the 'struct sfdp_parameter_header' describing
4012 * the 4-Byte Address Instruction Table length and version.
4013 * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
4015 * Return: 0 on success, -errno otherwise.
4017 static int spi_nor_parse_4bait(struct spi_nor *nor,
4018 const struct sfdp_parameter_header *param_header,
4019 struct spi_nor_flash_parameter *params)
4021 static const struct sfdp_4bait reads[] = {
4022 { SNOR_HWCAPS_READ, BIT(0) },
4023 { SNOR_HWCAPS_READ_FAST, BIT(1) },
4024 { SNOR_HWCAPS_READ_1_1_2, BIT(2) },
4025 { SNOR_HWCAPS_READ_1_2_2, BIT(3) },
4026 { SNOR_HWCAPS_READ_1_1_4, BIT(4) },
4027 { SNOR_HWCAPS_READ_1_4_4, BIT(5) },
4028 { SNOR_HWCAPS_READ_1_1_1_DTR, BIT(13) },
4029 { SNOR_HWCAPS_READ_1_2_2_DTR, BIT(14) },
4030 { SNOR_HWCAPS_READ_1_4_4_DTR, BIT(15) },
4032 static const struct sfdp_4bait programs[] = {
4033 { SNOR_HWCAPS_PP, BIT(6) },
4034 { SNOR_HWCAPS_PP_1_1_4, BIT(7) },
4035 { SNOR_HWCAPS_PP_1_4_4, BIT(8) },
4037 static const struct sfdp_4bait erases[SNOR_ERASE_TYPE_MAX] = {
4038 { 0u /* not used */, BIT(9) },
4039 { 0u /* not used */, BIT(10) },
4040 { 0u /* not used */, BIT(11) },
4041 { 0u /* not used */, BIT(12) },
4043 struct spi_nor_pp_command *params_pp = params->page_programs;
4044 struct spi_nor_erase_map *map = ¶ms->erase_map;
4045 struct spi_nor_erase_type *erase_type = map->erase_type;
4048 u32 addr, discard_hwcaps, read_hwcaps, pp_hwcaps, erase_mask;
4051 if (param_header->major != SFDP_JESD216_MAJOR ||
4052 param_header->length < SFDP_4BAIT_DWORD_MAX)
4055 /* Read the 4-byte Address Instruction Table. */
4056 len = sizeof(*dwords) * SFDP_4BAIT_DWORD_MAX;
4058 /* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
4059 dwords = kmalloc(len, GFP_KERNEL);
4063 addr = SFDP_PARAM_HEADER_PTP(param_header);
4064 ret = spi_nor_read_sfdp(nor, addr, len, dwords);
4068 /* Fix endianness of the 4BAIT DWORDs. */
4069 for (i = 0; i < SFDP_4BAIT_DWORD_MAX; i++)
4070 dwords[i] = le32_to_cpu(dwords[i]);
4073 * Compute the subset of (Fast) Read commands for which the 4-byte
4074 * version is supported.
4078 for (i = 0; i < ARRAY_SIZE(reads); i++) {
4079 const struct sfdp_4bait *read = &reads[i];
4081 discard_hwcaps |= read->hwcaps;
4082 if ((params->hwcaps.mask & read->hwcaps) &&
4083 (dwords[0] & read->supported_bit))
4084 read_hwcaps |= read->hwcaps;
4088 * Compute the subset of Page Program commands for which the 4-byte
4089 * version is supported.
4092 for (i = 0; i < ARRAY_SIZE(programs); i++) {
4093 const struct sfdp_4bait *program = &programs[i];
4096 * The 4 Byte Address Instruction (Optional) Table is the only
4097 * SFDP table that indicates support for Page Program Commands.
4098 * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
4099 * authority for specifying Page Program support.
4101 discard_hwcaps |= program->hwcaps;
4102 if (dwords[0] & program->supported_bit)
4103 pp_hwcaps |= program->hwcaps;
4107 * Compute the subset of Sector Erase commands for which the 4-byte
4108 * version is supported.
4111 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
4112 const struct sfdp_4bait *erase = &erases[i];
4114 if (dwords[0] & erase->supported_bit)
4115 erase_mask |= BIT(i);
4118 /* Replicate the sort done for the map's erase types in BFPT. */
4119 erase_mask = spi_nor_sort_erase_mask(map, erase_mask);
4122 * We need at least one 4-byte op code per read, program and erase
4123 * operation; the .read(), .write() and .erase() hooks share the
4124 * nor->addr_width value.
4126 if (!read_hwcaps || !pp_hwcaps || !erase_mask)
4130 * Discard all operations from the 4-byte instruction set which are
4131 * not supported by this memory.
4133 params->hwcaps.mask &= ~discard_hwcaps;
4134 params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
4136 /* Use the 4-byte address instruction set. */
4137 for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
4138 struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
4140 read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
4143 /* 4BAIT is the only SFDP table that indicates page program support. */
4144 if (pp_hwcaps & SNOR_HWCAPS_PP)
4145 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
4146 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
4147 if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
4148 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
4149 SPINOR_OP_PP_1_1_4_4B,
4151 if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
4152 spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
4153 SPINOR_OP_PP_1_4_4_4B,
4156 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
4157 if (erase_mask & BIT(i))
4158 erase_type[i].opcode = (dwords[1] >>
4159 erase_type[i].idx * 8) & 0xFF;
4161 spi_nor_set_erase_type(&erase_type[i], 0u, 0xFF);
4165 * We set SNOR_F_HAS_4BAIT in order to skip spi_nor_set_4byte_opcodes()
4166 * later because we already did the conversion to 4byte opcodes. Also,
4167 * this latest function implements a legacy quirk for the erase size of
4168 * Spansion memory. However this quirk is no longer needed with new
4169 * SFDP compliant memories.
4171 nor->addr_width = 4;
4172 nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
4181 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
4182 * @nor: pointer to a 'struct spi_nor'
4183 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
4186 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
4187 * specification. This is a standard which tends to supported by almost all
4188 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
4189 * runtime the main parameters needed to perform basic SPI flash operations such
4190 * as Fast Read, Page Program or Sector Erase commands.
4192 * Return: 0 on success, -errno otherwise.
4194 static int spi_nor_parse_sfdp(struct spi_nor *nor,
4195 struct spi_nor_flash_parameter *params)
4197 const struct sfdp_parameter_header *param_header, *bfpt_header;
4198 struct sfdp_parameter_header *param_headers = NULL;
4199 struct sfdp_header header;
4200 struct device *dev = nor->dev;
4204 /* Get the SFDP header. */
4205 err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header);
4209 /* Check the SFDP header version. */
4210 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
4211 header.major != SFDP_JESD216_MAJOR)
4215 * Verify that the first and only mandatory parameter header is a
4216 * Basic Flash Parameter Table header as specified in JESD216.
4218 bfpt_header = &header.bfpt_header;
4219 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
4220 bfpt_header->major != SFDP_JESD216_MAJOR)
4224 * Allocate memory then read all parameter headers with a single
4225 * Read SFDP command. These parameter headers will actually be parsed
4226 * twice: a first time to get the latest revision of the basic flash
4227 * parameter table, then a second time to handle the supported optional
4229 * Hence we read the parameter headers once for all to reduce the
4230 * processing time. Also we use kmalloc() instead of devm_kmalloc()
4231 * because we don't need to keep these parameter headers: the allocated
4232 * memory is always released with kfree() before exiting this function.
4235 psize = header.nph * sizeof(*param_headers);
4237 param_headers = kmalloc(psize, GFP_KERNEL);
4241 err = spi_nor_read_sfdp(nor, sizeof(header),
4242 psize, param_headers);
4244 dev_dbg(dev, "failed to read SFDP parameter headers\n");
4250 * Check other parameter headers to get the latest revision of
4251 * the basic flash parameter table.
4253 for (i = 0; i < header.nph; i++) {
4254 param_header = ¶m_headers[i];
4256 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
4257 param_header->major == SFDP_JESD216_MAJOR &&
4258 (param_header->minor > bfpt_header->minor ||
4259 (param_header->minor == bfpt_header->minor &&
4260 param_header->length > bfpt_header->length)))
4261 bfpt_header = param_header;
4264 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
4268 /* Parse optional parameter tables. */
4269 for (i = 0; i < header.nph; i++) {
4270 param_header = ¶m_headers[i];
4272 switch (SFDP_PARAM_HEADER_ID(param_header)) {
4273 case SFDP_SECTOR_MAP_ID:
4274 err = spi_nor_parse_smpt(nor, param_header, params);
4278 err = spi_nor_parse_4bait(nor, param_header, params);
4286 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
4287 SFDP_PARAM_HEADER_ID(param_header));
4289 * Let's not drop all information we extracted so far
4290 * if optional table parsers fail. In case of failing,
4291 * each optional parser is responsible to roll back to
4292 * the previously known spi_nor data.
4299 kfree(param_headers);
4303 static int spi_nor_select_read(struct spi_nor *nor,
4306 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
4307 const struct spi_nor_read_command *read;
4312 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
4316 read = &nor->params.reads[cmd];
4317 nor->read_opcode = read->opcode;
4318 nor->read_proto = read->proto;
4321 * In the spi-nor framework, we don't need to make the difference
4322 * between mode clock cycles and wait state clock cycles.
4323 * Indeed, the value of the mode clock cycles is used by a QSPI
4324 * flash memory to know whether it should enter or leave its 0-4-4
4325 * (Continuous Read / XIP) mode.
4326 * eXecution In Place is out of the scope of the mtd sub-system.
4327 * Hence we choose to merge both mode and wait state clock cycles
4328 * into the so called dummy clock cycles.
4330 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
4334 static int spi_nor_select_pp(struct spi_nor *nor,
4337 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
4338 const struct spi_nor_pp_command *pp;
4343 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
4347 pp = &nor->params.page_programs[cmd];
4348 nor->program_opcode = pp->opcode;
4349 nor->write_proto = pp->proto;
4354 * spi_nor_select_uniform_erase() - select optimum uniform erase type
4355 * @map: the erase map of the SPI NOR
4356 * @wanted_size: the erase type size to search for. Contains the value of
4357 * info->sector_size or of the "small sector" size in case
4358 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
4360 * Once the optimum uniform sector erase command is found, disable all the
4363 * Return: pointer to erase type on success, NULL otherwise.
4365 static const struct spi_nor_erase_type *
4366 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
4367 const u32 wanted_size)
4369 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
4371 u8 uniform_erase_type = map->uniform_erase_type;
4373 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
4374 if (!(uniform_erase_type & BIT(i)))
4377 tested_erase = &map->erase_type[i];
4380 * If the current erase size is the one, stop here:
4381 * we have found the right uniform Sector Erase command.
4383 if (tested_erase->size == wanted_size) {
4384 erase = tested_erase;
4389 * Otherwise, the current erase size is still a valid canditate.
4390 * Select the biggest valid candidate.
4392 if (!erase && tested_erase->size)
4393 erase = tested_erase;
4394 /* keep iterating to find the wanted_size */
4400 /* Disable all other Sector Erase commands. */
4401 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK;
4402 map->uniform_erase_type |= BIT(erase - map->erase_type);
4406 static int spi_nor_select_erase(struct spi_nor *nor)
4408 struct spi_nor_erase_map *map = &nor->params.erase_map;
4409 const struct spi_nor_erase_type *erase = NULL;
4410 struct mtd_info *mtd = &nor->mtd;
4411 u32 wanted_size = nor->info->sector_size;
4415 * The previous implementation handling Sector Erase commands assumed
4416 * that the SPI flash memory has an uniform layout then used only one
4417 * of the supported erase sizes for all Sector Erase commands.
4418 * So to be backward compatible, the new implementation also tries to
4419 * manage the SPI flash memory as uniform with a single erase sector
4420 * size, when possible.
4422 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
4423 /* prefer "small sector" erase if possible */
4424 wanted_size = 4096u;
4427 if (spi_nor_has_uniform_erase(nor)) {
4428 erase = spi_nor_select_uniform_erase(map, wanted_size);
4431 nor->erase_opcode = erase->opcode;
4432 mtd->erasesize = erase->size;
4437 * For non-uniform SPI flash memory, set mtd->erasesize to the
4438 * maximum erase sector size. No need to set nor->erase_opcode.
4440 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
4441 if (map->erase_type[i].size) {
4442 erase = &map->erase_type[i];
4450 mtd->erasesize = erase->size;
4454 static int spi_nor_default_setup(struct spi_nor *nor,
4455 const struct spi_nor_hwcaps *hwcaps)
4457 struct spi_nor_flash_parameter *params = &nor->params;
4458 u32 ignored_mask, shared_mask;
4462 * Keep only the hardware capabilities supported by both the SPI
4463 * controller and the SPI flash memory.
4465 shared_mask = hwcaps->mask & params->hwcaps.mask;
4469 * When called from spi_nor_probe(), all caps are set and we
4470 * need to discard some of them based on what the SPI
4471 * controller actually supports (using spi_mem_supports_op()).
4473 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
4476 * SPI n-n-n protocols are not supported when the SPI
4477 * controller directly implements the spi_nor interface.
4478 * Yet another reason to switch to spi-mem.
4480 ignored_mask = SNOR_HWCAPS_X_X_X;
4481 if (shared_mask & ignored_mask) {
4483 "SPI n-n-n protocols are not supported.\n");
4484 shared_mask &= ~ignored_mask;
4488 /* Select the (Fast) Read command. */
4489 err = spi_nor_select_read(nor, shared_mask);
4492 "can't select read settings supported by both the SPI controller and memory.\n");
4496 /* Select the Page Program command. */
4497 err = spi_nor_select_pp(nor, shared_mask);
4500 "can't select write settings supported by both the SPI controller and memory.\n");
4504 /* Select the Sector Erase command. */
4505 err = spi_nor_select_erase(nor);
4508 "can't select erase settings supported by both the SPI controller and memory.\n");
4515 static int spi_nor_setup(struct spi_nor *nor,
4516 const struct spi_nor_hwcaps *hwcaps)
4518 if (!nor->params.setup)
4521 return nor->params.setup(nor, hwcaps);
4524 static void macronix_set_default_init(struct spi_nor *nor)
4526 nor->params.quad_enable = macronix_quad_enable;
4527 nor->params.set_4byte = macronix_set_4byte;
4530 static void st_micron_set_default_init(struct spi_nor *nor)
4532 nor->flags |= SNOR_F_HAS_LOCK;
4533 nor->params.quad_enable = NULL;
4534 nor->params.set_4byte = st_micron_set_4byte;
4537 static void winbond_set_default_init(struct spi_nor *nor)
4539 nor->params.set_4byte = winbond_set_4byte;
4543 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
4544 * settings based on MFR register and ->default_init() hook.
4545 * @nor: pointer to a 'struct spi-nor'.
4547 static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
4549 /* Init flash parameters based on MFR */
4550 switch (JEDEC_MFR(nor->info)) {
4551 case SNOR_MFR_MACRONIX:
4552 macronix_set_default_init(nor);
4556 case SNOR_MFR_MICRON:
4557 st_micron_set_default_init(nor);
4560 case SNOR_MFR_WINBOND:
4561 winbond_set_default_init(nor);
4568 if (nor->info->fixups && nor->info->fixups->default_init)
4569 nor->info->fixups->default_init(nor);
4573 * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
4574 * based on JESD216 SFDP standard.
4575 * @nor: pointer to a 'struct spi-nor'.
4577 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
4578 * legacy flash parameters and settings will be restored.
4580 static void spi_nor_sfdp_init_params(struct spi_nor *nor)
4582 struct spi_nor_flash_parameter sfdp_params;
4584 memcpy(&sfdp_params, &nor->params, sizeof(sfdp_params));
4586 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
4587 nor->addr_width = 0;
4588 nor->flags &= ~SNOR_F_4B_OPCODES;
4590 memcpy(&nor->params, &sfdp_params, sizeof(nor->params));
4595 * spi_nor_info_init_params() - Initialize the flash's parameters and settings
4596 * based on nor->info data.
4597 * @nor: pointer to a 'struct spi-nor'.
4599 static void spi_nor_info_init_params(struct spi_nor *nor)
4601 struct spi_nor_flash_parameter *params = &nor->params;
4602 struct spi_nor_erase_map *map = ¶ms->erase_map;
4603 const struct flash_info *info = nor->info;
4604 struct device_node *np = spi_nor_get_flash_node(nor);
4607 /* Initialize legacy flash parameters and settings. */
4608 params->quad_enable = spansion_read_cr_quad_enable;
4609 params->set_4byte = spansion_set_4byte;
4610 params->setup = spi_nor_default_setup;
4612 /* Set SPI NOR sizes. */
4613 params->size = (u64)info->sector_size * info->n_sectors;
4614 params->page_size = info->page_size;
4616 if (!(info->flags & SPI_NOR_NO_FR)) {
4617 /* Default to Fast Read for DT and non-DT platform devices. */
4618 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
4620 /* Mask out Fast Read if not requested at DT instantiation. */
4621 if (np && !of_property_read_bool(np, "m25p,fast-read"))
4622 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
4625 /* (Fast) Read settings. */
4626 params->hwcaps.mask |= SNOR_HWCAPS_READ;
4627 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
4628 0, 0, SPINOR_OP_READ,
4631 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
4632 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
4633 0, 8, SPINOR_OP_READ_FAST,
4636 if (info->flags & SPI_NOR_DUAL_READ) {
4637 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
4638 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
4639 0, 8, SPINOR_OP_READ_1_1_2,
4643 if (info->flags & SPI_NOR_QUAD_READ) {
4644 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
4645 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
4646 0, 8, SPINOR_OP_READ_1_1_4,
4650 if (info->flags & SPI_NOR_OCTAL_READ) {
4651 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
4652 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
4653 0, 8, SPINOR_OP_READ_1_1_8,
4657 /* Page Program settings. */
4658 params->hwcaps.mask |= SNOR_HWCAPS_PP;
4659 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
4660 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
4663 * Sector Erase settings. Sort Erase Types in ascending order, with the
4664 * smallest erase size starting at BIT(0).
4668 if (info->flags & SECT_4K_PMC) {
4669 erase_mask |= BIT(i);
4670 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
4671 SPINOR_OP_BE_4K_PMC);
4673 } else if (info->flags & SECT_4K) {
4674 erase_mask |= BIT(i);
4675 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
4679 erase_mask |= BIT(i);
4680 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
4682 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
4685 static void spansion_post_sfdp_fixups(struct spi_nor *nor)
4687 struct mtd_info *mtd = &nor->mtd;
4689 if (mtd->size <= SZ_16M)
4692 nor->flags |= SNOR_F_4B_OPCODES;
4693 /* No small sector erase for 4-byte command set */
4694 nor->erase_opcode = SPINOR_OP_SE;
4695 nor->mtd.erasesize = nor->info->sector_size;
4698 static void s3an_post_sfdp_fixups(struct spi_nor *nor)
4700 nor->params.setup = s3an_nor_setup;
4704 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
4705 * after SFDP has been parsed (is also called for SPI NORs that do not
4707 * @nor: pointer to a 'struct spi_nor'
4709 * Typically used to tweak various parameters that could not be extracted by
4710 * other means (i.e. when information provided by the SFDP/flash_info tables
4711 * are incomplete or wrong).
4713 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
4715 switch (JEDEC_MFR(nor->info)) {
4716 case SNOR_MFR_SPANSION:
4717 spansion_post_sfdp_fixups(nor);
4724 if (nor->info->flags & SPI_S3AN)
4725 s3an_post_sfdp_fixups(nor);
4727 if (nor->info->fixups && nor->info->fixups->post_sfdp)
4728 nor->info->fixups->post_sfdp(nor);
4732 * spi_nor_late_init_params() - Late initialization of default flash parameters.
4733 * @nor: pointer to a 'struct spi_nor'
4735 * Used to set default flash parameters and settings when the ->default_init()
4736 * hook or the SFDP parser let voids.
4738 static void spi_nor_late_init_params(struct spi_nor *nor)
4741 * NOR protection support. When locking_ops are not provided, we pick
4744 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops)
4745 nor->params.locking_ops = &stm_locking_ops;
4749 * spi_nor_init_params() - Initialize the flash's parameters and settings.
4750 * @nor: pointer to a 'struct spi-nor'.
4752 * The flash parameters and settings are initialized based on a sequence of
4753 * calls that are ordered by priority:
4755 * 1/ Default flash parameters initialization. The initializations are done
4756 * based on nor->info data:
4757 * spi_nor_info_init_params()
4759 * which can be overwritten by:
4760 * 2/ Manufacturer flash parameters initialization. The initializations are
4761 * done based on MFR register, or when the decisions can not be done solely
4762 * based on MFR, by using specific flash_info tweeks, ->default_init():
4763 * spi_nor_manufacturer_init_params()
4765 * which can be overwritten by:
4766 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
4767 * should be more accurate that the above.
4768 * spi_nor_sfdp_init_params()
4770 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
4771 * the flash parameters and settings immediately after parsing the Basic
4772 * Flash Parameter Table.
4774 * which can be overwritten by:
4775 * 4/ Post SFDP flash parameters initialization. Used to tweak various
4776 * parameters that could not be extracted by other means (i.e. when
4777 * information provided by the SFDP/flash_info tables are incomplete or
4779 * spi_nor_post_sfdp_fixups()
4781 * 5/ Late default flash parameters initialization, used when the
4782 * ->default_init() hook or the SFDP parser do not set specific params.
4783 * spi_nor_late_init_params()
4785 static void spi_nor_init_params(struct spi_nor *nor)
4787 spi_nor_info_init_params(nor);
4789 spi_nor_manufacturer_init_params(nor);
4791 if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
4792 !(nor->info->flags & SPI_NOR_SKIP_SFDP))
4793 spi_nor_sfdp_init_params(nor);
4795 spi_nor_post_sfdp_fixups(nor);
4797 spi_nor_late_init_params(nor);
4801 * spi_nor_quad_enable() - enable Quad I/O if needed.
4802 * @nor: pointer to a 'struct spi_nor'
4804 * Return: 0 on success, -errno otherwise.
4806 static int spi_nor_quad_enable(struct spi_nor *nor)
4808 if (!nor->params.quad_enable)
4811 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
4812 spi_nor_get_protocol_width(nor->write_proto) == 4))
4815 return nor->params.quad_enable(nor);
4818 static int spi_nor_init(struct spi_nor *nor)
4822 if (nor->clear_sr_bp) {
4823 if (nor->params.quad_enable == spansion_read_cr_quad_enable)
4824 nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
4826 err = nor->clear_sr_bp(nor);
4829 "fail to clear block protection bits\n");
4834 err = spi_nor_quad_enable(nor);
4836 dev_dbg(nor->dev, "quad mode not supported\n");
4840 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES)) {
4842 * If the RESET# pin isn't hooked up properly, or the system
4843 * otherwise doesn't perform a reset command in the boot
4844 * sequence, it's impossible to 100% protect against unexpected
4845 * reboots (e.g., crashes). Warn the user (or hopefully, system
4846 * designer) that this is bad.
4848 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
4849 "enabling reset hack; may not recover from unexpected reboots\n");
4850 nor->params.set_4byte(nor, true);
4856 /* mtd resume handler */
4857 static void spi_nor_resume(struct mtd_info *mtd)
4859 struct spi_nor *nor = mtd_to_spi_nor(mtd);
4860 struct device *dev = nor->dev;
4863 /* re-initialize the nor chip */
4864 ret = spi_nor_init(nor);
4866 dev_err(dev, "resume() failed\n");
4869 void spi_nor_restore(struct spi_nor *nor)
4871 /* restore the addressing mode */
4872 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
4873 nor->flags & SNOR_F_BROKEN_RESET)
4874 nor->params.set_4byte(nor, false);
4876 EXPORT_SYMBOL_GPL(spi_nor_restore);
4878 static const struct flash_info *spi_nor_match_id(const char *name)
4880 const struct flash_info *id = spi_nor_ids;
4883 if (!strcmp(name, id->name))
4890 static int spi_nor_set_addr_width(struct spi_nor *nor)
4892 if (nor->addr_width) {
4893 /* already configured from SFDP */
4894 } else if (nor->info->addr_width) {
4895 nor->addr_width = nor->info->addr_width;
4896 } else if (nor->mtd.size > 0x1000000) {
4897 /* enable 4-byte addressing if the device exceeds 16MiB */
4898 nor->addr_width = 4;
4900 nor->addr_width = 3;
4903 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
4904 dev_dbg(nor->dev, "address width is too large: %u\n",
4909 /* Set 4byte opcodes when possible. */
4910 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
4911 !(nor->flags & SNOR_F_HAS_4BAIT))
4912 spi_nor_set_4byte_opcodes(nor);
4917 static void spi_nor_debugfs_init(struct spi_nor *nor,
4918 const struct flash_info *info)
4920 struct mtd_info *mtd = &nor->mtd;
4922 mtd->dbg.partname = info->name;
4923 mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN",
4924 info->id_len, info->id);
4927 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
4930 const struct flash_info *info = NULL;
4933 info = spi_nor_match_id(name);
4934 /* Try to auto-detect if chip name wasn't specified or not found */
4936 info = spi_nor_read_id(nor);
4937 if (IS_ERR_OR_NULL(info))
4938 return ERR_PTR(-ENOENT);
4941 * If caller has specified name of flash model that can normally be
4942 * detected using JEDEC, let's verify it.
4944 if (name && info->id_len) {
4945 const struct flash_info *jinfo;
4947 jinfo = spi_nor_read_id(nor);
4948 if (IS_ERR(jinfo)) {
4950 } else if (jinfo != info) {
4952 * JEDEC knows better, so overwrite platform ID. We
4953 * can't trust partitions any longer, but we'll let
4954 * mtd apply them anyway, since some partitions may be
4955 * marked read-only, and we don't want to lose that
4956 * information, even if it's not 100% accurate.
4958 dev_warn(nor->dev, "found %s, expected %s\n",
4959 jinfo->name, info->name);
4967 int spi_nor_scan(struct spi_nor *nor, const char *name,
4968 const struct spi_nor_hwcaps *hwcaps)
4970 const struct flash_info *info;
4971 struct device *dev = nor->dev;
4972 struct mtd_info *mtd = &nor->mtd;
4973 struct device_node *np = spi_nor_get_flash_node(nor);
4974 struct spi_nor_flash_parameter *params = &nor->params;
4978 ret = spi_nor_check(nor);
4982 /* Reset SPI protocol for all commands. */
4983 nor->reg_proto = SNOR_PROTO_1_1_1;
4984 nor->read_proto = SNOR_PROTO_1_1_1;
4985 nor->write_proto = SNOR_PROTO_1_1_1;
4988 * We need the bounce buffer early to read/write registers when going
4989 * through the spi-mem layer (buffers have to be DMA-able).
4990 * For spi-mem drivers, we'll reallocate a new buffer if
4991 * nor->page_size turns out to be greater than PAGE_SIZE (which
4992 * shouldn't happen before long since NOR pages are usually less
4993 * than 1KB) after spi_nor_scan() returns.
4995 nor->bouncebuf_size = PAGE_SIZE;
4996 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
4998 if (!nor->bouncebuf)
5001 info = spi_nor_get_flash_info(nor, name);
5003 return PTR_ERR(info);
5007 spi_nor_debugfs_init(nor, info);
5009 mutex_init(&nor->lock);
5012 * Make sure the XSR_RDY flag is set before calling
5013 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
5014 * with Atmel spi-nor
5016 if (info->flags & SPI_NOR_XSR_RDY)
5017 nor->flags |= SNOR_F_READY_XSR_RDY;
5019 if (info->flags & SPI_NOR_HAS_LOCK)
5020 nor->flags |= SNOR_F_HAS_LOCK;
5023 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
5024 * with the software protection bits set.
5026 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
5027 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
5028 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
5029 nor->info->flags & SPI_NOR_HAS_LOCK)
5030 nor->clear_sr_bp = spi_nor_clear_sr_bp;
5032 /* Init flash parameters based on flash_info struct and SFDP */
5033 spi_nor_init_params(nor);
5036 mtd->name = dev_name(dev);
5038 mtd->type = MTD_NORFLASH;
5040 mtd->flags = MTD_CAP_NORFLASH;
5041 mtd->size = params->size;
5042 mtd->_erase = spi_nor_erase;
5043 mtd->_read = spi_nor_read;
5044 mtd->_resume = spi_nor_resume;
5046 if (nor->params.locking_ops) {
5047 mtd->_lock = spi_nor_lock;
5048 mtd->_unlock = spi_nor_unlock;
5049 mtd->_is_locked = spi_nor_is_locked;
5052 /* sst nor chips use AAI word program */
5053 if (info->flags & SST_WRITE)
5054 mtd->_write = sst_write;
5056 mtd->_write = spi_nor_write;
5058 if (info->flags & USE_FSR)
5059 nor->flags |= SNOR_F_USE_FSR;
5060 if (info->flags & SPI_NOR_HAS_TB)
5061 nor->flags |= SNOR_F_HAS_SR_TB;
5062 if (info->flags & NO_CHIP_ERASE)
5063 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
5064 if (info->flags & USE_CLSR)
5065 nor->flags |= SNOR_F_USE_CLSR;
5067 if (info->flags & SPI_NOR_NO_ERASE)
5068 mtd->flags |= MTD_NO_ERASE;
5070 mtd->dev.parent = dev;
5071 nor->page_size = params->page_size;
5072 mtd->writebufsize = nor->page_size;
5074 if (of_property_read_bool(np, "broken-flash-reset"))
5075 nor->flags |= SNOR_F_BROKEN_RESET;
5078 * Configure the SPI memory:
5079 * - select op codes for (Fast) Read, Page Program and Sector Erase.
5080 * - set the number of dummy cycles (mode cycles + wait states).
5081 * - set the SPI protocols for register and memory accesses.
5083 ret = spi_nor_setup(nor, hwcaps);
5087 if (info->flags & SPI_NOR_4B_OPCODES)
5088 nor->flags |= SNOR_F_4B_OPCODES;
5090 ret = spi_nor_set_addr_width(nor);
5094 /* Send all the required SPI flash commands to initialize device */
5095 ret = spi_nor_init(nor);
5099 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
5100 (long long)mtd->size >> 10);
5103 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
5104 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
5105 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
5106 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
5108 if (mtd->numeraseregions)
5109 for (i = 0; i < mtd->numeraseregions; i++)
5111 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
5112 ".erasesize = 0x%.8x (%uKiB), "
5113 ".numblocks = %d }\n",
5114 i, (long long)mtd->eraseregions[i].offset,
5115 mtd->eraseregions[i].erasesize,
5116 mtd->eraseregions[i].erasesize / 1024,
5117 mtd->eraseregions[i].numblocks);
5120 EXPORT_SYMBOL_GPL(spi_nor_scan);
5122 static int spi_nor_probe(struct spi_mem *spimem)
5124 struct spi_device *spi = spimem->spi;
5125 struct flash_platform_data *data = dev_get_platdata(&spi->dev);
5126 struct spi_nor *nor;
5128 * Enable all caps by default. The core will mask them after
5129 * checking what's really supported using spi_mem_supports_op().
5131 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
5135 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
5139 nor->spimem = spimem;
5140 nor->dev = &spi->dev;
5141 spi_nor_set_flash_node(nor, spi->dev.of_node);
5143 spi_mem_set_drvdata(spimem, nor);
5145 if (data && data->name)
5146 nor->mtd.name = data->name;
5149 nor->mtd.name = spi_mem_get_name(spimem);
5152 * For some (historical?) reason many platforms provide two different
5153 * names in flash_platform_data: "name" and "type". Quite often name is
5154 * set to "m25p80" and then "type" provides a real chip name.
5155 * If that's the case, respect "type" and ignore a "name".
5157 if (data && data->type)
5158 flash_name = data->type;
5159 else if (!strcmp(spi->modalias, "spi-nor"))
5160 flash_name = NULL; /* auto-detect */
5162 flash_name = spi->modalias;
5164 ret = spi_nor_scan(nor, flash_name, &hwcaps);
5169 * None of the existing parts have > 512B pages, but let's play safe
5170 * and add this logic so that if anyone ever adds support for such
5171 * a NOR we don't end up with buffer overflows.
5173 if (nor->page_size > PAGE_SIZE) {
5174 nor->bouncebuf_size = nor->page_size;
5175 devm_kfree(nor->dev, nor->bouncebuf);
5176 nor->bouncebuf = devm_kmalloc(nor->dev,
5177 nor->bouncebuf_size,
5179 if (!nor->bouncebuf)
5183 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
5184 data ? data->nr_parts : 0);
5187 static int spi_nor_remove(struct spi_mem *spimem)
5189 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
5191 spi_nor_restore(nor);
5193 /* Clean up MTD stuff. */
5194 return mtd_device_unregister(&nor->mtd);
5197 static void spi_nor_shutdown(struct spi_mem *spimem)
5199 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
5201 spi_nor_restore(nor);
5205 * Do NOT add to this array without reading the following:
5207 * Historically, many flash devices are bound to this driver by their name. But
5208 * since most of these flash are compatible to some extent, and their
5209 * differences can often be differentiated by the JEDEC read-ID command, we
5210 * encourage new users to add support to the spi-nor library, and simply bind
5211 * against a generic string here (e.g., "jedec,spi-nor").
5213 * Many flash names are kept here in this list (as well as in spi-nor.c) to
5214 * keep them available as module aliases for existing platforms.
5216 static const struct spi_device_id spi_nor_dev_ids[] = {
5218 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
5219 * hack around the fact that the SPI core does not provide uevent
5220 * matching for .of_match_table
5225 * Entries not used in DTs that should be safe to drop after replacing
5226 * them with "spi-nor" in platform data.
5228 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
5231 * Entries that were used in DTs without "jedec,spi-nor" fallback and
5232 * should be kept for backward compatibility.
5234 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
5235 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
5236 {"mx25l25635e"},{"mx66l51235l"},
5237 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
5238 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
5240 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
5241 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
5242 {"m25p64"}, {"m25p128"},
5243 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
5244 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
5246 /* Flashes that can't be detected using JEDEC */
5247 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
5248 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
5249 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
5251 /* Everspin MRAMs (non-JEDEC) */
5252 { "mr25h128" }, /* 128 Kib, 40 MHz */
5253 { "mr25h256" }, /* 256 Kib, 40 MHz */
5254 { "mr25h10" }, /* 1 Mib, 40 MHz */
5255 { "mr25h40" }, /* 4 Mib, 40 MHz */
5259 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
5261 static const struct of_device_id spi_nor_of_table[] = {
5263 * Generic compatibility for SPI NOR that can be identified by the
5264 * JEDEC READ ID opcode (0x9F). Use this, if possible.
5266 { .compatible = "jedec,spi-nor" },
5269 MODULE_DEVICE_TABLE(of, spi_nor_of_table);
5272 * REVISIT: many of these chips have deep power-down modes, which
5273 * should clearly be entered on suspend() to minimize power use.
5274 * And also when they're otherwise idle...
5276 static struct spi_mem_driver spi_nor_driver = {
5280 .of_match_table = spi_nor_of_table,
5282 .id_table = spi_nor_dev_ids,
5284 .probe = spi_nor_probe,
5285 .remove = spi_nor_remove,
5286 .shutdown = spi_nor_shutdown,
5288 module_spi_mem_driver(spi_nor_driver);
5290 MODULE_LICENSE("GPL v2");
5291 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
5292 MODULE_AUTHOR("Mike Lavender");
5293 MODULE_DESCRIPTION("framework for SPI NOR");