drivers/mtd/spi-nor/spansion.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 #define SPINOR_OP_RD_ANY_REG                    0x65    /* Read any register */
  12 #define SPINOR_OP_WR_ANY_REG                    0x71    /* Write any register */
  13 #define SPINOR_REG_CYPRESS_CFR2V                0x00800003
  14 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24   0xb
  15 #define SPINOR_REG_CYPRESS_CFR3V                0x00800004
  16 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ           BIT(4) /* Page size. */
  17 #define SPINOR_REG_CYPRESS_CFR5V                0x00800006
  18 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN     0x3
  19 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS     0
  20 #define SPINOR_OP_CYPRESS_RD_FAST               0xee
  21
  22 /**
  23  * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  24  * @nor:                pointer to a 'struct spi_nor'
  25  * @enable:              whether to enable or disable Octal DTR
  26  *
  27  * This also sets the memory access latency cycles to 24 to allow the flash to
  28  * run at up to 200MHz.
  29  *
  30  * Return: 0 on success, -errno otherwise.
  31  */
  32 static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
  33 {
  34         struct spi_mem_op op;
  35         u8 *buf = nor->bouncebuf;
  36         int ret;
  37
  38         if (enable) {
  39                 /* Use 24 dummy cycles for memory array reads. */
  40                 ret = spi_nor_write_enable(nor);
  41                 if (ret)
  42                         return ret;
  43
  44                 *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
  45                 op = (struct spi_mem_op)
  46                         SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  47                                    SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V,
  48                                                    1),
  49                                    SPI_MEM_OP_NO_DUMMY,
  50                                    SPI_MEM_OP_DATA_OUT(1, buf, 1));
  51
  52                 ret = spi_mem_exec_op(nor->spimem, &op);
  53                 if (ret)
  54                         return ret;
  55
  56                 ret = spi_nor_wait_till_ready(nor);
  57                 if (ret)
  58                         return ret;
  59
  60                 nor->read_dummy = 24;
  61         }
  62
  63         /* Set/unset the octal and DTR enable bits. */
  64         ret = spi_nor_write_enable(nor);
  65         if (ret)
  66                 return ret;
  67
  68         if (enable) {
  69                 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
  70         } else {
  71                 /*
  72                  * The register is 1-byte wide, but 1-byte transactions are not
  73                  * allowed in 8D-8D-8D mode. Since there is no register at the
  74                  * next location, just initialize the value to 0 and let the
  75                  * transaction go on.
  76                  */
  77                 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
  78                 buf[1] = 0;
  79         }
  80
  81         op = (struct spi_mem_op)
  82                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  83                            SPI_MEM_OP_ADDR(enable ? 3 : 4,
  84                                            SPINOR_REG_CYPRESS_CFR5V,
  85                                            1),
  86                            SPI_MEM_OP_NO_DUMMY,
  87                            SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
  88
  89         if (!enable)
  90                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  91
  92         ret = spi_mem_exec_op(nor->spimem, &op);
  93         if (ret)
  94                 return ret;
  95
  96         /* Read flash ID to make sure the switch was successful. */
  97         op = (struct spi_mem_op)
  98                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
  99                            SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1),
 100                            SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1),
 101                            SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2),
 102                                               buf, 1));
 103
 104         if (enable)
 105                 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
 106
 107         ret = spi_mem_exec_op(nor->spimem, &op);
 108         if (ret)
 109                 return ret;
 110
 111         if (memcmp(buf, nor->info->id, nor->info->id_len))
 112                 return -EINVAL;
 113
 114         return 0;
 115 }
 116
 117 static void s28hs512t_default_init(struct spi_nor *nor)
 118 {
 119         nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
 120         nor->params->writesize = 16;
 121 }
 122
 123 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
 124 {
 125         /*
 126          * On older versions of the flash the xSPI Profile 1.0 table has the
 127          * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
 128          */
 129         if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
 130                 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
 131                         SPINOR_OP_CYPRESS_RD_FAST;
 132
 133         /* This flash is also missing the 4-byte Page Program opcode bit. */
 134         spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
 135                                 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
 136         /*
 137          * Since xSPI Page Program opcode is backward compatible with
 138          * Legacy SPI, use Legacy SPI opcode there as well.
 139          */
 140         spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
 141                                 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
 142
 143         /*
 144          * The xSPI Profile 1.0 table advertises the number of additional
 145          * address bytes needed for Read Status Register command as 0 but the
 146          * actual value for that is 4.
 147          */
 148         nor->params->rdsr_addr_nbytes = 4;
 149 }
 150
 151 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
 152                                      const struct sfdp_parameter_header *bfpt_header,
 153                                      const struct sfdp_bfpt *bfpt)
 154 {
 155         /*
 156          * The BFPT table advertises a 512B page size but the page size is
 157          * actually configurable (with the default being 256B). Read from
 158          * CFR3V[4] and set the correct size.
 159          */
 160         struct spi_mem_op op =
 161                 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
 162                            SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1),
 163                            SPI_MEM_OP_NO_DUMMY,
 164                            SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
 165         int ret;
 166
 167         ret = spi_mem_exec_op(nor->spimem, &op);
 168         if (ret)
 169                 return ret;
 170
 171         if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
 172                 nor->params->page_size = 512;
 173         else
 174                 nor->params->page_size = 256;
 175
 176         return 0;
 177 }
 178
 179 static const struct spi_nor_fixups s28hs512t_fixups = {
 180         .default_init = s28hs512t_default_init,
 181         .post_sfdp = s28hs512t_post_sfdp_fixup,
 182         .post_bfpt = s28hs512t_post_bfpt_fixup,
 183 };
 184
 185 static int
 186 s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
 187                          const struct sfdp_parameter_header *bfpt_header,
 188                          const struct sfdp_bfpt *bfpt)
 189 {
 190         /*
 191          * The S25FS-S chip family reports 512-byte pages in BFPT but
 192          * in reality the write buffer still wraps at the safe default
 193          * of 256 bytes.  Overwrite the page size advertised by BFPT
 194          * to get the writes working.
 195          */
 196         nor->params->page_size = 256;
 197
 198         return 0;
 199 }
 200
 201 static const struct spi_nor_fixups s25fs_s_fixups = {
 202         .post_bfpt = s25fs_s_post_bfpt_fixups,
 203 };
 204
 205 static const struct flash_info spansion_parts[] = {
 206         /* Spansion/Cypress -- single (large) sector size only, at least
 207          * for the chips listed here (without boot sectors).
 208          */
 209         { "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64)
 210                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 211         { "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128)
 212                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 213         { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
 214                 FLAGS(USE_CLSR)
 215                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 216         { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
 217                 FLAGS(USE_CLSR)
 218                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 219         { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
 220                 FLAGS(USE_CLSR)
 221                 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
 222                               SPI_NOR_QUAD_READ) },
 223         { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
 224                 FLAGS(USE_CLSR)
 225                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 226         { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
 227                 FLAGS(SPI_NOR_HAS_LOCK | USE_CLSR)
 228                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 229         { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
 230                 FLAGS(USE_CLSR)
 231                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 232                 .fixups = &s25fs_s_fixups, },
 233         { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
 234                 FLAGS(USE_CLSR)
 235                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 236         { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
 237                 FLAGS(USE_CLSR)
 238                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 239         { "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
 240                 FLAGS(USE_CLSR)
 241                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 242                 .fixups = &s25fs_s_fixups, },
 243         { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64) },
 244         { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256) },
 245         { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64)
 246                 FLAGS(USE_CLSR)
 247                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 248         { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256)
 249                 FLAGS(USE_CLSR)
 250                 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 251         { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8) },
 252         { "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16) },
 253         { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32) },
 254         { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64) },
 255         { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128) },
 256         { "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8)
 257                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 258                               SPI_NOR_QUAD_READ) },
 259         { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16)
 260                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 261                               SPI_NOR_QUAD_READ) },
 262         { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32)
 263                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 264                               SPI_NOR_QUAD_READ) },
 265         { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128)
 266                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 267                               SPI_NOR_QUAD_READ) },
 268         { "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32)
 269                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
 270                               SPI_NOR_QUAD_READ) },
 271         { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64)
 272                 NO_SFDP_FLAGS(SECT_4K) },
 273         { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128)
 274                 NO_SFDP_FLAGS(SECT_4K) },
 275         { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8)
 276                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
 277         { "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16)
 278                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
 279         { "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128)
 280                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 281                 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
 282         { "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256)
 283                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 284                 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
 285         { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
 286                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 287                 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
 288         { "cy15x104q",  INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
 289                 FLAGS(SPI_NOR_NO_ERASE) },
 290         { "s28hs512t",   INFO(0x345b1a,      0, 256 * 1024, 256)
 291                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
 292                               SPI_NOR_OCTAL_DTR_PP)
 293                 .fixups = &s28hs512t_fixups,
 294         },
 295 };
 296
 297 static void spansion_late_init(struct spi_nor *nor)
 298 {
 299         if (nor->params->size <= SZ_16M)
 300                 return;
 301
 302         nor->flags |= SNOR_F_4B_OPCODES;
 303         /* No small sector erase for 4-byte command set */
 304         nor->erase_opcode = SPINOR_OP_SE;
 305         nor->mtd.erasesize = nor->info->sector_size;
 306 }
 307
 308 static const struct spi_nor_fixups spansion_fixups = {
 309         .late_init = spansion_late_init,
 310 };
 311
 312 const struct spi_nor_manufacturer spi_nor_spansion = {
 313         .name = "spansion",
 314         .parts = spansion_parts,
 315         .nparts = ARRAY_SIZE(spansion_parts),
 316         .fixups = &spansion_fixups,
 317 };