drivers/mtd/spi-nor/micron-st.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static const struct flash_info micron_parts[] = {
  12         { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
  13                                SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
  14                                SPI_NOR_4B_OPCODES) },
  15         { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
  16                             SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
  17                             SPI_NOR_4B_OPCODES) },
  18 };
  19
  20 static const struct flash_info st_parts[] = {
  21         { "n25q016a",    INFO(0x20bb15, 0, 64 * 1024,   32,
  22                               SECT_4K | SPI_NOR_QUAD_READ) },
  23         { "n25q032",     INFO(0x20ba16, 0, 64 * 1024,   64,
  24                               SPI_NOR_QUAD_READ) },
  25         { "n25q032a",    INFO(0x20bb16, 0, 64 * 1024,   64,
  26                               SPI_NOR_QUAD_READ) },
  27         { "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128,
  28                               SECT_4K | SPI_NOR_QUAD_READ) },
  29         { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128,
  30                               SECT_4K | SPI_NOR_QUAD_READ) },
  31         { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256,
  32                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  33                               SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
  34                               SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
  35         { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256,
  36                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  37         { "mt25ql256a",  INFO6(0x20ba19, 0x104400, 64 * 1024,  512,
  38                                SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
  39                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  40         { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K |
  41                               USE_FSR | SPI_NOR_DUAL_READ |
  42                               SPI_NOR_QUAD_READ) },
  43         { "mt25qu256a",  INFO6(0x20bb19, 0x104400, 64 * 1024,  512,
  44                                SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
  45                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  46         { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512,
  47                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  48         { "mt25ql512a",  INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
  49                                SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
  50                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  51         { "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024,
  52                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  53                               SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
  54                               SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
  55         { "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
  56                                SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
  57                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  58         { "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024,
  59                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  60                               SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
  61                               SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
  62         { "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048,
  63                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  64                               SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
  65                               SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 |
  66                               NO_CHIP_ERASE) },
  67         { "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048,
  68                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  69                               NO_CHIP_ERASE) },
  70         { "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
  71                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
  72                               NO_CHIP_ERASE) },
  73         { "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096,
  74                               SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
  75                               SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  76
  77         { "m25p05",  INFO(0x202010,  0,  32 * 1024,   2, 0) },
  78         { "m25p10",  INFO(0x202011,  0,  32 * 1024,   4, 0) },
  79         { "m25p20",  INFO(0x202012,  0,  64 * 1024,   4, 0) },
  80         { "m25p40",  INFO(0x202013,  0,  64 * 1024,   8, 0) },
  81         { "m25p80",  INFO(0x202014,  0,  64 * 1024,  16, 0) },
  82         { "m25p16",  INFO(0x202015,  0,  64 * 1024,  32, 0) },
  83         { "m25p32",  INFO(0x202016,  0,  64 * 1024,  64, 0) },
  84         { "m25p64",  INFO(0x202017,  0,  64 * 1024, 128, 0) },
  85         { "m25p128", INFO(0x202018,  0, 256 * 1024,  64, 0) },
  86
  87         { "m25p05-nonjedec",  INFO(0, 0,  32 * 1024,   2, 0) },
  88         { "m25p10-nonjedec",  INFO(0, 0,  32 * 1024,   4, 0) },
  89         { "m25p20-nonjedec",  INFO(0, 0,  64 * 1024,   4, 0) },
  90         { "m25p40-nonjedec",  INFO(0, 0,  64 * 1024,   8, 0) },
  91         { "m25p80-nonjedec",  INFO(0, 0,  64 * 1024,  16, 0) },
  92         { "m25p16-nonjedec",  INFO(0, 0,  64 * 1024,  32, 0) },
  93         { "m25p32-nonjedec",  INFO(0, 0,  64 * 1024,  64, 0) },
  94         { "m25p64-nonjedec",  INFO(0, 0,  64 * 1024, 128, 0) },
  95         { "m25p128-nonjedec", INFO(0, 0, 256 * 1024,  64, 0) },
  96
  97         { "m45pe10", INFO(0x204011,  0, 64 * 1024,    2, 0) },
  98         { "m45pe80", INFO(0x204014,  0, 64 * 1024,   16, 0) },
  99         { "m45pe16", INFO(0x204015,  0, 64 * 1024,   32, 0) },
 100
 101         { "m25pe20", INFO(0x208012,  0, 64 * 1024,  4,       0) },
 102         { "m25pe80", INFO(0x208014,  0, 64 * 1024, 16,       0) },
 103         { "m25pe16", INFO(0x208015,  0, 64 * 1024, 32, SECT_4K) },
 104
 105         { "m25px16",    INFO(0x207115,  0, 64 * 1024, 32, SECT_4K) },
 106         { "m25px32",    INFO(0x207116,  0, 64 * 1024, 64, SECT_4K) },
 107         { "m25px32-s0", INFO(0x207316,  0, 64 * 1024, 64, SECT_4K) },
 108         { "m25px32-s1", INFO(0x206316,  0, 64 * 1024, 64, SECT_4K) },
 109         { "m25px64",    INFO(0x207117,  0, 64 * 1024, 128, 0) },
 110         { "m25px80",    INFO(0x207114,  0, 64 * 1024, 16, 0) },
 111 };
 112
 113 /**
 114  * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
 115  * flashes.
 116  * @nor:        pointer to 'struct spi_nor'.
 117  * @enable:     true to enter the 4-byte address mode, false to exit the 4-byte
 118  *              address mode.
 119  *
 120  * Return: 0 on success, -errno otherwise.
 121  */
 122 static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
 123 {
 124         int ret;
 125
 126         ret = spi_nor_write_enable(nor);
 127         if (ret)
 128                 return ret;
 129
 130         ret = spi_nor_set_4byte_addr_mode(nor, enable);
 131         if (ret)
 132                 return ret;
 133
 134         return spi_nor_write_disable(nor);
 135 }
 136
 137 static void micron_st_default_init(struct spi_nor *nor)
 138 {
 139         nor->flags |= SNOR_F_HAS_LOCK;
 140         nor->flags &= ~SNOR_F_HAS_16BIT_SR;
 141         nor->params->quad_enable = NULL;
 142         nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
 143 }
 144
 145 static const struct spi_nor_fixups micron_st_fixups = {
 146         .default_init = micron_st_default_init,
 147 };
 148
 149 const struct spi_nor_manufacturer spi_nor_micron = {
 150         .name = "micron",
 151         .parts = micron_parts,
 152         .nparts = ARRAY_SIZE(micron_parts),
 153         .fixups = &micron_st_fixups,
 154 };
 155
 156 const struct spi_nor_manufacturer spi_nor_st = {
 157         .name = "st",
 158         .parts = st_parts,
 159         .nparts = ARRAY_SIZE(st_parts),
 160         .fixups = &micron_st_fixups,
 161 };