1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
7 #include <linux/mtd/spi-nor.h>
11 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
12 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
13 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
14 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
15 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
16 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
17 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
18 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
20 static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enable)
23 u8 *buf = nor->bouncebuf;
27 /* Use 20 dummy cycles for memory array reads. */
28 ret = spi_nor_write_enable(nor);
33 op = (struct spi_mem_op)
34 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
35 SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1),
37 SPI_MEM_OP_DATA_OUT(1, buf, 1));
39 ret = spi_mem_exec_op(nor->spimem, &op);
43 ret = spi_nor_wait_till_ready(nor);
48 ret = spi_nor_write_enable(nor);
53 buf[0] = SPINOR_MT_OCT_DTR;
56 * The register is 1-byte wide, but 1-byte transactions are not
57 * allowed in 8D-8D-8D mode. The next register is the dummy
58 * cycle configuration register. Since the transaction needs to
59 * be at least 2 bytes wide, set the next register to its
60 * default value. This also makes sense because the value was
61 * changed when enabling 8D-8D-8D mode, it should be reset when
64 buf[0] = SPINOR_MT_EXSPI;
65 buf[1] = SPINOR_REG_MT_CFR1V_DEF;
68 op = (struct spi_mem_op)
69 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
70 SPI_MEM_OP_ADDR(enable ? 3 : 4,
71 SPINOR_REG_MT_CFR0V, 1),
73 SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
76 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
78 ret = spi_mem_exec_op(nor->spimem, &op);
82 /* Read flash ID to make sure the switch was successful. */
83 op = (struct spi_mem_op)
84 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
86 SPI_MEM_OP_DUMMY(enable ? 8 : 0, 1),
87 SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2),
91 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
93 ret = spi_mem_exec_op(nor->spimem, &op);
97 if (memcmp(buf, nor->info->id, nor->info->id_len))
103 static void mt35xu512aba_default_init(struct spi_nor *nor)
105 nor->params->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
108 static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
110 /* Set the Fast Read settings. */
111 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
112 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
113 0, 20, SPINOR_OP_MT_DTR_RD,
114 SNOR_PROTO_8_8_8_DTR);
116 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
117 nor->params->rdsr_dummy = 8;
118 nor->params->rdsr_addr_nbytes = 0;
121 * The BFPT quad enable field is set to a reserved value so the quad
122 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
125 nor->params->quad_enable = NULL;
128 static const struct spi_nor_fixups mt35xu512aba_fixups = {
129 .default_init = mt35xu512aba_default_init,
130 .post_sfdp = mt35xu512aba_post_sfdp_fixup,
133 static const struct flash_info micron_parts[] = {
134 { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
136 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
137 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
138 FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
139 .fixups = &mt35xu512aba_fixups},
140 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
142 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
143 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
146 static const struct flash_info st_parts[] = {
147 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
148 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
149 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
150 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
151 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64)
152 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
153 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
154 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
155 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
156 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
157 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
158 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
159 SPI_NOR_BP3_SR_BIT6 | USE_FSR)
160 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
161 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
162 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
163 SPI_NOR_BP3_SR_BIT6 | USE_FSR)
164 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
165 { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
167 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
168 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
169 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
171 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
172 SPI_NOR_QUAD_READ) },
173 { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
175 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
176 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
177 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
179 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
180 { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
182 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
183 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
184 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
185 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
186 SPI_NOR_BP3_SR_BIT6 | USE_FSR)
187 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
188 { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
190 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
191 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
192 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
193 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
194 SPI_NOR_BP3_SR_BIT6 | USE_FSR)
195 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
196 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
197 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
198 SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE | USE_FSR)
199 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
200 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
201 FLAGS(NO_CHIP_ERASE | USE_FSR)
202 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
203 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
204 FLAGS(NO_CHIP_ERASE | USE_FSR)
205 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
206 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
207 FLAGS(NO_CHIP_ERASE | USE_FSR)
208 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
209 SPI_NOR_QUAD_READ) },
211 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
212 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
213 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) },
214 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) },
215 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) },
216 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) },
217 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) },
218 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) },
219 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) },
221 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2) },
222 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4) },
223 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4) },
224 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8) },
225 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16) },
226 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32) },
227 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64) },
228 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128) },
229 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64) },
231 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) },
232 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) },
233 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) },
235 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) },
236 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) },
237 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32)
238 NO_SFDP_FLAGS(SECT_4K) },
240 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32)
241 NO_SFDP_FLAGS(SECT_4K) },
242 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64)
243 NO_SFDP_FLAGS(SECT_4K) },
244 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64)
245 NO_SFDP_FLAGS(SECT_4K) },
246 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64)
247 NO_SFDP_FLAGS(SECT_4K) },
248 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) },
249 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) },
253 * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
255 * @nor: pointer to 'struct spi_nor'.
256 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
259 * Return: 0 on success, -errno otherwise.
261 static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
265 ret = spi_nor_write_enable(nor);
269 ret = spi_nor_set_4byte_addr_mode(nor, enable);
273 return spi_nor_write_disable(nor);
276 static void micron_st_default_init(struct spi_nor *nor)
278 nor->flags |= SNOR_F_HAS_LOCK;
279 nor->flags &= ~SNOR_F_HAS_16BIT_SR;
280 nor->params->quad_enable = NULL;
281 nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
284 static const struct spi_nor_fixups micron_st_fixups = {
285 .default_init = micron_st_default_init,
288 const struct spi_nor_manufacturer spi_nor_micron = {
290 .parts = micron_parts,
291 .nparts = ARRAY_SIZE(micron_parts),
292 .fixups = µn_st_fixups,
295 const struct spi_nor_manufacturer spi_nor_st = {
298 .nparts = ARRAY_SIZE(st_parts),
299 .fixups = µn_st_fixups,