drivers/mtd/spi-nor/gigadevice.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static int
  12 gd25q256_post_bfpt(struct spi_nor *nor,
  13                    const struct sfdp_parameter_header *bfpt_header,
  14                    const struct sfdp_bfpt *bfpt)
  15 {
  16         /*
  17          * GD25Q256C supports the first version of JESD216 which does not define
  18          * the Quad Enable methods. Overwrite the default Quad Enable method.
  19          *
  20          * GD25Q256 GENERATION | SFDP MAJOR VERSION | SFDP MINOR VERSION
  21          *      GD25Q256C      | SFDP_JESD216_MAJOR | SFDP_JESD216_MINOR
  22          *      GD25Q256D      | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
  23          *      GD25Q256E      | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
  24          */
  25         if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  26             bfpt_header->minor == SFDP_JESD216_MINOR)
  27                 nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
  28
  29         return 0;
  30 }
  31
  32 static const struct spi_nor_fixups gd25q256_fixups = {
  33         .post_bfpt = gd25q256_post_bfpt,
  34 };
  35
  36 static const struct flash_info gigadevice_nor_parts[] = {
  37         { "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32)
  38                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  39                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  40                               SPI_NOR_QUAD_READ) },
  41         { "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64)
  42                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  43                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  44                               SPI_NOR_QUAD_READ) },
  45         { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
  46                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  47                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  48                               SPI_NOR_QUAD_READ) },
  49         { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
  50                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  51                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  52                               SPI_NOR_QUAD_READ) },
  53         { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
  54                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  55                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  56                               SPI_NOR_QUAD_READ) },
  57         { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
  58                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  59                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  60                               SPI_NOR_QUAD_READ) },
  61         { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
  62                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  63                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
  64                               SPI_NOR_QUAD_READ) },
  65         { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512)
  66                 PARSE_SFDP
  67                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
  68                 FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
  69                 .fixups = &gd25q256_fixups },
  70 };
  71
  72 const struct spi_nor_manufacturer spi_nor_gigadevice = {
  73         .name = "gigadevice",
  74         .parts = gigadevice_nor_parts,
  75         .nparts = ARRAY_SIZE(gigadevice_nor_parts),
  76 };