drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/err.h>
  24 #include <linux/errno.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/mtd/spi-nor.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/sched.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/timer.h>
  40
  41 #define CQSPI_NAME                      "cadence-qspi"
  42 #define CQSPI_MAX_CHIPSELECT            16
  43
  44 /* Quirks */
  45 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  46
  47 struct cqspi_st;
  48
  49 struct cqspi_flash_pdata {
  50         struct spi_nor  nor;
  51         struct cqspi_st *cqspi;
  52         u32             clk_rate;
  53         u32             read_delay;
  54         u32             tshsl_ns;
  55         u32             tsd2d_ns;
  56         u32             tchsh_ns;
  57         u32             tslch_ns;
  58         u8              inst_width;
  59         u8              addr_width;
  60         u8              data_width;
  61         u8              cs;
  62         bool            registered;
  63         bool            use_direct_mode;
  64 };
  65
  66 struct cqspi_st {
  67         struct platform_device  *pdev;
  68
  69         struct clk              *clk;
  70         unsigned int            sclk;
  71
  72         void __iomem            *iobase;
  73         void __iomem            *ahb_base;
  74         resource_size_t         ahb_size;
  75         struct completion       transfer_complete;
  76         struct mutex            bus_mutex;
  77
  78         struct dma_chan         *rx_chan;
  79         struct completion       rx_dma_complete;
  80         dma_addr_t              mmap_phys_base;
  81
  82         int                     current_cs;
  83         int                     current_page_size;
  84         int                     current_erase_size;
  85         int                     current_addr_width;
  86         unsigned long           master_ref_clk_hz;
  87         bool                    is_decoded_cs;
  88         u32                     fifo_depth;
  89         u32                     fifo_width;
  90         bool                    rclk_en;
  91         u32                     trigger_address;
  92         u32                     wr_delay;
  93         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  94 };
  95
  96 /* Operation timeout value */
  97 #define CQSPI_TIMEOUT_MS                        500
  98 #define CQSPI_READ_TIMEOUT_MS                   10
  99
 100 /* Instruction type */
 101 #define CQSPI_INST_TYPE_SINGLE                  0
 102 #define CQSPI_INST_TYPE_DUAL                    1
 103 #define CQSPI_INST_TYPE_QUAD                    2
 104
 105 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 106 #define CQSPI_DUMMY_BYTES_MAX                   4
 107 #define CQSPI_DUMMY_CLKS_MAX                    31
 108
 109 #define CQSPI_STIG_DATA_LEN_MAX                 8
 110
 111 /* Register map */
 112 #define CQSPI_REG_CONFIG                        0x00
 113 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 114 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 115 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 116 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 117 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 118 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 119 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 120 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 121 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 122
 123 #define CQSPI_REG_RD_INSTR                      0x04
 124 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 125 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 126 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 127 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 128 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 129 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 130 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 131 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 132 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 133 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 134
 135 #define CQSPI_REG_WR_INSTR                      0x08
 136 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 137 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 138 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 139
 140 #define CQSPI_REG_DELAY                         0x0C
 141 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 142 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 143 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 144 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 145 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 146 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 147 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 148 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 149
 150 #define CQSPI_REG_READCAPTURE                   0x10
 151 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 152 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 153 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 154
 155 #define CQSPI_REG_SIZE                          0x14
 156 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 157 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 158 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 159 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 160 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 161 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 162
 163 #define CQSPI_REG_SRAMPARTITION                 0x18
 164 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 165
 166 #define CQSPI_REG_DMA                           0x20
 167 #define CQSPI_REG_DMA_SINGLE_LSB                0
 168 #define CQSPI_REG_DMA_BURST_LSB                 8
 169 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 170 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 171
 172 #define CQSPI_REG_REMAP                         0x24
 173 #define CQSPI_REG_MODE_BIT                      0x28
 174
 175 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 176 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 177 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 178 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 179 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 180
 181 #define CQSPI_REG_IRQSTATUS                     0x40
 182 #define CQSPI_REG_IRQMASK                       0x44
 183
 184 #define CQSPI_REG_INDIRECTRD                    0x60
 185 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 186 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 187 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 188
 189 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 190 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 191 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 192
 193 #define CQSPI_REG_CMDCTRL                       0x90
 194 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 195 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 196 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 197 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 199 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 200 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 201 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 202 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 203 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 204 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 205 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 206
 207 #define CQSPI_REG_INDIRECTWR                    0x70
 208 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 209 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 210 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 211
 212 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 213 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 214 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 215
 216 #define CQSPI_REG_CMDADDRESS                    0x94
 217 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 218 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 219 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 220 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 221
 222 /* Interrupt status bits */
 223 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 224 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 225 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 226 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 227 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 228 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 229 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 230 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 231
 232 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 233                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 234                                          CQSPI_REG_IRQ_IND_COMP)
 235
 236 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 237                                          CQSPI_REG_IRQ_WATERMARK        | \
 238                                          CQSPI_REG_IRQ_UNDERFLOW)
 239
 240 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 241
 242 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 243 {
 244         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 245         u32 val;
 246
 247         while (1) {
 248                 val = readl(reg);
 249                 if (clear)
 250                         val = ~val;
 251                 val &= mask;
 252
 253                 if (val == mask)
 254                         return 0;
 255
 256                 if (time_after(jiffies, end))
 257                         return -ETIMEDOUT;
 258         }
 259 }
 260
 261 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 262 {
 263         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 264
 265         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 266 }
 267
 268 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 269 {
 270         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 271
 272         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 273         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 274 }
 275
 276 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 277 {
 278         struct cqspi_st *cqspi = dev;
 279         unsigned int irq_status;
 280
 281         /* Read interrupt status */
 282         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 283
 284         /* Clear interrupt */
 285         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 286
 287         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 288
 289         if (irq_status)
 290                 complete(&cqspi->transfer_complete);
 291
 292         return IRQ_HANDLED;
 293 }
 294
 295 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 296 {
 297         struct cqspi_flash_pdata *f_pdata = nor->priv;
 298         u32 rdreg = 0;
 299
 300         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 301         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 302         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 303
 304         return rdreg;
 305 }
 306
 307 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 308 {
 309         const unsigned int poll_idle_retry = 3;
 310         unsigned int count = 0;
 311         unsigned long timeout;
 312
 313         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 314         while (1) {
 315                 /*
 316                  * Read few times in succession to ensure the controller
 317                  * is indeed idle, that is, the bit does not transition
 318                  * low again.
 319                  */
 320                 if (cqspi_is_idle(cqspi))
 321                         count++;
 322                 else
 323                         count = 0;
 324
 325                 if (count >= poll_idle_retry)
 326                         return 0;
 327
 328                 if (time_after(jiffies, timeout)) {
 329                         /* Timeout, in busy mode. */
 330                         dev_err(&cqspi->pdev->dev,
 331                                 "QSPI is still busy after %dms timeout.\n",
 332                                 CQSPI_TIMEOUT_MS);
 333                         return -ETIMEDOUT;
 334                 }
 335
 336                 cpu_relax();
 337         }
 338 }
 339
 340 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 341 {
 342         void __iomem *reg_base = cqspi->iobase;
 343         int ret;
 344
 345         /* Write the CMDCTRL without start execution. */
 346         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 347         /* Start execute */
 348         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 349         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 350
 351         /* Polling for completion. */
 352         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 353                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 354         if (ret) {
 355                 dev_err(&cqspi->pdev->dev,
 356                         "Flash command execution timed out.\n");
 357                 return ret;
 358         }
 359
 360         /* Polling QSPI idle status. */
 361         return cqspi_wait_idle(cqspi);
 362 }
 363
 364 static int cqspi_command_read(struct spi_nor *nor,
 365                               const u8 *txbuf, const unsigned n_tx,
 366                               u8 *rxbuf, const unsigned n_rx)
 367 {
 368         struct cqspi_flash_pdata *f_pdata = nor->priv;
 369         struct cqspi_st *cqspi = f_pdata->cqspi;
 370         void __iomem *reg_base = cqspi->iobase;
 371         unsigned int rdreg;
 372         unsigned int reg;
 373         unsigned int read_len;
 374         int status;
 375
 376         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 377                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 378                         n_rx, rxbuf);
 379                 return -EINVAL;
 380         }
 381
 382         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 383
 384         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 385         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 386
 387         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 388
 389         /* 0 means 1 byte. */
 390         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 391                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 392         status = cqspi_exec_flash_cmd(cqspi, reg);
 393         if (status)
 394                 return status;
 395
 396         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 397
 398         /* Put the read value into rx_buf */
 399         read_len = (n_rx > 4) ? 4 : n_rx;
 400         memcpy(rxbuf, &reg, read_len);
 401         rxbuf += read_len;
 402
 403         if (n_rx > 4) {
 404                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 405
 406                 read_len = n_rx - read_len;
 407                 memcpy(rxbuf, &reg, read_len);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 414                                const u8 *txbuf, const unsigned n_tx)
 415 {
 416         struct cqspi_flash_pdata *f_pdata = nor->priv;
 417         struct cqspi_st *cqspi = f_pdata->cqspi;
 418         void __iomem *reg_base = cqspi->iobase;
 419         unsigned int reg;
 420         unsigned int data;
 421         int ret;
 422
 423         if (n_tx > 4 || (n_tx && !txbuf)) {
 424                 dev_err(nor->dev,
 425                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 426                         n_tx, txbuf);
 427                 return -EINVAL;
 428         }
 429
 430         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 431         if (n_tx) {
 432                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 433                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 434                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 435                 data = 0;
 436                 memcpy(&data, txbuf, n_tx);
 437                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 438         }
 439
 440         ret = cqspi_exec_flash_cmd(cqspi, reg);
 441         return ret;
 442 }
 443
 444 static int cqspi_command_write_addr(struct spi_nor *nor,
 445                                     const u8 opcode, const unsigned int addr)
 446 {
 447         struct cqspi_flash_pdata *f_pdata = nor->priv;
 448         struct cqspi_st *cqspi = f_pdata->cqspi;
 449         void __iomem *reg_base = cqspi->iobase;
 450         unsigned int reg;
 451
 452         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 453         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 454         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 455                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 456
 457         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 458
 459         return cqspi_exec_flash_cmd(cqspi, reg);
 460 }
 461
 462 static int cqspi_read_setup(struct spi_nor *nor)
 463 {
 464         struct cqspi_flash_pdata *f_pdata = nor->priv;
 465         struct cqspi_st *cqspi = f_pdata->cqspi;
 466         void __iomem *reg_base = cqspi->iobase;
 467         unsigned int dummy_clk = 0;
 468         unsigned int reg;
 469
 470         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 471         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 472
 473         /* Setup dummy clock cycles */
 474         dummy_clk = nor->read_dummy;
 475         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 476                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 477
 478         if (dummy_clk / 8) {
 479                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 480                 /* Set mode bits high to ensure chip doesn't enter XIP */
 481                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 482
 483                 /* Need to subtract the mode byte (8 clocks). */
 484                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 485                         dummy_clk -= 8;
 486
 487                 if (dummy_clk)
 488                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 489                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 490         }
 491
 492         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 493
 494         /* Set address width */
 495         reg = readl(reg_base + CQSPI_REG_SIZE);
 496         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 497         reg |= (nor->addr_width - 1);
 498         writel(reg, reg_base + CQSPI_REG_SIZE);
 499         return 0;
 500 }
 501
 502 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 503                                        loff_t from_addr, const size_t n_rx)
 504 {
 505         struct cqspi_flash_pdata *f_pdata = nor->priv;
 506         struct cqspi_st *cqspi = f_pdata->cqspi;
 507         void __iomem *reg_base = cqspi->iobase;
 508         void __iomem *ahb_base = cqspi->ahb_base;
 509         unsigned int remaining = n_rx;
 510         unsigned int bytes_to_read = 0;
 511         int ret = 0;
 512
 513         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 514         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 515
 516         /* Clear all interrupts. */
 517         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 518
 519         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 520
 521         reinit_completion(&cqspi->transfer_complete);
 522         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 523                reg_base + CQSPI_REG_INDIRECTRD);
 524
 525         while (remaining > 0) {
 526                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 527                                                   msecs_to_jiffies
 528                                                   (CQSPI_READ_TIMEOUT_MS));
 529
 530                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 531
 532                 if (!ret && bytes_to_read == 0) {
 533                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 534                         ret = -ETIMEDOUT;
 535                         goto failrd;
 536                 }
 537
 538                 while (bytes_to_read != 0) {
 539                         bytes_to_read *= cqspi->fifo_width;
 540                         bytes_to_read = bytes_to_read > remaining ?
 541                                         remaining : bytes_to_read;
 542                         ioread32_rep(ahb_base, rxbuf,
 543                                      DIV_ROUND_UP(bytes_to_read, 4));
 544                         rxbuf += bytes_to_read;
 545                         remaining -= bytes_to_read;
 546                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 547                 }
 548
 549                 if (remaining > 0)
 550                         reinit_completion(&cqspi->transfer_complete);
 551         }
 552
 553         /* Check indirect done status */
 554         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 555                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 556         if (ret) {
 557                 dev_err(nor->dev,
 558                         "Indirect read completion error (%i)\n", ret);
 559                 goto failrd;
 560         }
 561
 562         /* Disable interrupt */
 563         writel(0, reg_base + CQSPI_REG_IRQMASK);
 564
 565         /* Clear indirect completion status */
 566         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 567
 568         return 0;
 569
 570 failrd:
 571         /* Disable interrupt */
 572         writel(0, reg_base + CQSPI_REG_IRQMASK);
 573
 574         /* Cancel the indirect read */
 575         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 576                reg_base + CQSPI_REG_INDIRECTRD);
 577         return ret;
 578 }
 579
 580 static int cqspi_write_setup(struct spi_nor *nor)
 581 {
 582         unsigned int reg;
 583         struct cqspi_flash_pdata *f_pdata = nor->priv;
 584         struct cqspi_st *cqspi = f_pdata->cqspi;
 585         void __iomem *reg_base = cqspi->iobase;
 586
 587         /* Set opcode. */
 588         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 589         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 590         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 591         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 592
 593         reg = readl(reg_base + CQSPI_REG_SIZE);
 594         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 595         reg |= (nor->addr_width - 1);
 596         writel(reg, reg_base + CQSPI_REG_SIZE);
 597         return 0;
 598 }
 599
 600 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 601                                         const u8 *txbuf, const size_t n_tx)
 602 {
 603         const unsigned int page_size = nor->page_size;
 604         struct cqspi_flash_pdata *f_pdata = nor->priv;
 605         struct cqspi_st *cqspi = f_pdata->cqspi;
 606         void __iomem *reg_base = cqspi->iobase;
 607         unsigned int remaining = n_tx;
 608         unsigned int write_bytes;
 609         int ret;
 610
 611         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 612         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 613
 614         /* Clear all interrupts. */
 615         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 616
 617         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 618
 619         reinit_completion(&cqspi->transfer_complete);
 620         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 621                reg_base + CQSPI_REG_INDIRECTWR);
 622         /*
 623          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 624          * Controller programming sequence, couple of cycles of
 625          * QSPI_REF_CLK delay is required for the above bit to
 626          * be internally synchronized by the QSPI module. Provide 5
 627          * cycles of delay.
 628          */
 629         if (cqspi->wr_delay)
 630                 ndelay(cqspi->wr_delay);
 631
 632         while (remaining > 0) {
 633                 write_bytes = remaining > page_size ? page_size : remaining;
 634                 iowrite32_rep(cqspi->ahb_base, txbuf,
 635                               DIV_ROUND_UP(write_bytes, 4));
 636
 637                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 638                                                   msecs_to_jiffies
 639                                                   (CQSPI_TIMEOUT_MS));
 640                 if (!ret) {
 641                         dev_err(nor->dev, "Indirect write timeout\n");
 642                         ret = -ETIMEDOUT;
 643                         goto failwr;
 644                 }
 645
 646                 txbuf += write_bytes;
 647                 remaining -= write_bytes;
 648
 649                 if (remaining > 0)
 650                         reinit_completion(&cqspi->transfer_complete);
 651         }
 652
 653         /* Check indirect done status */
 654         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 655                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 656         if (ret) {
 657                 dev_err(nor->dev,
 658                         "Indirect write completion error (%i)\n", ret);
 659                 goto failwr;
 660         }
 661
 662         /* Disable interrupt. */
 663         writel(0, reg_base + CQSPI_REG_IRQMASK);
 664
 665         /* Clear indirect completion status */
 666         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 667
 668         cqspi_wait_idle(cqspi);
 669
 670         return 0;
 671
 672 failwr:
 673         /* Disable interrupt. */
 674         writel(0, reg_base + CQSPI_REG_IRQMASK);
 675
 676         /* Cancel the indirect write */
 677         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 678                reg_base + CQSPI_REG_INDIRECTWR);
 679         return ret;
 680 }
 681
 682 static void cqspi_chipselect(struct spi_nor *nor)
 683 {
 684         struct cqspi_flash_pdata *f_pdata = nor->priv;
 685         struct cqspi_st *cqspi = f_pdata->cqspi;
 686         void __iomem *reg_base = cqspi->iobase;
 687         unsigned int chip_select = f_pdata->cs;
 688         unsigned int reg;
 689
 690         reg = readl(reg_base + CQSPI_REG_CONFIG);
 691         if (cqspi->is_decoded_cs) {
 692                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 693         } else {
 694                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 695
 696                 /* Convert CS if without decoder.
 697                  * CS0 to 4b'1110
 698                  * CS1 to 4b'1101
 699                  * CS2 to 4b'1011
 700                  * CS3 to 4b'0111
 701                  */
 702                 chip_select = 0xF & ~(1 << chip_select);
 703         }
 704
 705         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 706                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 707         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 708             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 709         writel(reg, reg_base + CQSPI_REG_CONFIG);
 710 }
 711
 712 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 713 {
 714         struct cqspi_flash_pdata *f_pdata = nor->priv;
 715         struct cqspi_st *cqspi = f_pdata->cqspi;
 716         void __iomem *iobase = cqspi->iobase;
 717         unsigned int reg;
 718
 719         /* configure page size and block size. */
 720         reg = readl(iobase + CQSPI_REG_SIZE);
 721         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 722         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 723         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 724         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 725         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 726         reg |= (nor->addr_width - 1);
 727         writel(reg, iobase + CQSPI_REG_SIZE);
 728
 729         /* configure the chip select */
 730         cqspi_chipselect(nor);
 731
 732         /* Store the new configuration of the controller */
 733         cqspi->current_page_size = nor->page_size;
 734         cqspi->current_erase_size = nor->mtd.erasesize;
 735         cqspi->current_addr_width = nor->addr_width;
 736 }
 737
 738 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 739                                            const unsigned int ns_val)
 740 {
 741         unsigned int ticks;
 742
 743         ticks = ref_clk_hz / 1000;      /* kHz */
 744         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 745
 746         return ticks;
 747 }
 748
 749 static void cqspi_delay(struct spi_nor *nor)
 750 {
 751         struct cqspi_flash_pdata *f_pdata = nor->priv;
 752         struct cqspi_st *cqspi = f_pdata->cqspi;
 753         void __iomem *iobase = cqspi->iobase;
 754         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 755         unsigned int tshsl, tchsh, tslch, tsd2d;
 756         unsigned int reg;
 757         unsigned int tsclk;
 758
 759         /* calculate the number of ref ticks for one sclk tick */
 760         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 761
 762         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 763         /* this particular value must be at least one sclk */
 764         if (tshsl < tsclk)
 765                 tshsl = tsclk;
 766
 767         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 768         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 769         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 770
 771         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 772                << CQSPI_REG_DELAY_TSHSL_LSB;
 773         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 774                 << CQSPI_REG_DELAY_TCHSH_LSB;
 775         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 776                 << CQSPI_REG_DELAY_TSLCH_LSB;
 777         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 778                 << CQSPI_REG_DELAY_TSD2D_LSB;
 779         writel(reg, iobase + CQSPI_REG_DELAY);
 780 }
 781
 782 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 783 {
 784         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 785         void __iomem *reg_base = cqspi->iobase;
 786         u32 reg, div;
 787
 788         /* Recalculate the baudrate divisor based on QSPI specification. */
 789         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 790
 791         reg = readl(reg_base + CQSPI_REG_CONFIG);
 792         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 793         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 794         writel(reg, reg_base + CQSPI_REG_CONFIG);
 795 }
 796
 797 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 798                                    const bool bypass,
 799                                    const unsigned int delay)
 800 {
 801         void __iomem *reg_base = cqspi->iobase;
 802         unsigned int reg;
 803
 804         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 805
 806         if (bypass)
 807                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 808         else
 809                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 810
 811         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 812                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 813
 814         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 815                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 816
 817         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 818 }
 819
 820 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 821 {
 822         void __iomem *reg_base = cqspi->iobase;
 823         unsigned int reg;
 824
 825         reg = readl(reg_base + CQSPI_REG_CONFIG);
 826
 827         if (enable)
 828                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 829         else
 830                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 831
 832         writel(reg, reg_base + CQSPI_REG_CONFIG);
 833 }
 834
 835 static void cqspi_configure(struct spi_nor *nor)
 836 {
 837         struct cqspi_flash_pdata *f_pdata = nor->priv;
 838         struct cqspi_st *cqspi = f_pdata->cqspi;
 839         const unsigned int sclk = f_pdata->clk_rate;
 840         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 841         int switch_ck = (cqspi->sclk != sclk);
 842
 843         if ((cqspi->current_page_size != nor->page_size) ||
 844             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 845             (cqspi->current_addr_width != nor->addr_width))
 846                 switch_cs = 1;
 847
 848         if (switch_cs || switch_ck)
 849                 cqspi_controller_enable(cqspi, 0);
 850
 851         /* Switch chip select. */
 852         if (switch_cs) {
 853                 cqspi->current_cs = f_pdata->cs;
 854                 cqspi_configure_cs_and_sizes(nor);
 855         }
 856
 857         /* Setup baudrate divisor and delays */
 858         if (switch_ck) {
 859                 cqspi->sclk = sclk;
 860                 cqspi_config_baudrate_div(cqspi);
 861                 cqspi_delay(nor);
 862                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 863                                        f_pdata->read_delay);
 864         }
 865
 866         if (switch_cs || switch_ck)
 867                 cqspi_controller_enable(cqspi, 1);
 868 }
 869
 870 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 871 {
 872         struct cqspi_flash_pdata *f_pdata = nor->priv;
 873
 874         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 875         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 876         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 877
 878         if (read) {
 879                 switch (nor->read_proto) {
 880                 case SNOR_PROTO_1_1_1:
 881                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 882                         break;
 883                 case SNOR_PROTO_1_1_2:
 884                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 885                         break;
 886                 case SNOR_PROTO_1_1_4:
 887                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 888                         break;
 889                 default:
 890                         return -EINVAL;
 891                 }
 892         }
 893
 894         cqspi_configure(nor);
 895
 896         return 0;
 897 }
 898
 899 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 900                            size_t len, const u_char *buf)
 901 {
 902         struct cqspi_flash_pdata *f_pdata = nor->priv;
 903         struct cqspi_st *cqspi = f_pdata->cqspi;
 904         int ret;
 905
 906         ret = cqspi_set_protocol(nor, 0);
 907         if (ret)
 908                 return ret;
 909
 910         ret = cqspi_write_setup(nor);
 911         if (ret)
 912                 return ret;
 913
 914         if (f_pdata->use_direct_mode)
 915                 memcpy_toio(cqspi->ahb_base + to, buf, len);
 916         else
 917                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
 918         if (ret)
 919                 return ret;
 920
 921         return len;
 922 }
 923
 924 static void cqspi_rx_dma_callback(void *param)
 925 {
 926         struct cqspi_st *cqspi = param;
 927
 928         complete(&cqspi->rx_dma_complete);
 929 }
 930
 931 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
 932                                      loff_t from, size_t len)
 933 {
 934         struct cqspi_flash_pdata *f_pdata = nor->priv;
 935         struct cqspi_st *cqspi = f_pdata->cqspi;
 936         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 937         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
 938         int ret = 0;
 939         struct dma_async_tx_descriptor *tx;
 940         dma_cookie_t cookie;
 941         dma_addr_t dma_dst;
 942
 943         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
 944                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
 945                 return 0;
 946         }
 947
 948         dma_dst = dma_map_single(nor->dev, buf, len, DMA_DEV_TO_MEM);
 949         if (dma_mapping_error(nor->dev, dma_dst)) {
 950                 dev_err(nor->dev, "dma mapping failed\n");
 951                 return -ENOMEM;
 952         }
 953         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
 954                                        len, flags);
 955         if (!tx) {
 956                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
 957                 ret = -EIO;
 958                 goto err_unmap;
 959         }
 960
 961         tx->callback = cqspi_rx_dma_callback;
 962         tx->callback_param = cqspi;
 963         cookie = tx->tx_submit(tx);
 964         reinit_completion(&cqspi->rx_dma_complete);
 965
 966         ret = dma_submit_error(cookie);
 967         if (ret) {
 968                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
 969                 ret = -EIO;
 970                 goto err_unmap;
 971         }
 972
 973         dma_async_issue_pending(cqspi->rx_chan);
 974         ret = wait_for_completion_timeout(&cqspi->rx_dma_complete,
 975                                           msecs_to_jiffies(len));
 976         if (ret <= 0) {
 977                 dmaengine_terminate_sync(cqspi->rx_chan);
 978                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
 979                 ret = -ETIMEDOUT;
 980                 goto err_unmap;
 981         }
 982
 983 err_unmap:
 984         dma_unmap_single(nor->dev, dma_dst, len, DMA_DEV_TO_MEM);
 985
 986         return 0;
 987 }
 988
 989 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 990                           size_t len, u_char *buf)
 991 {
 992         struct cqspi_flash_pdata *f_pdata = nor->priv;
 993         int ret;
 994
 995         ret = cqspi_set_protocol(nor, 1);
 996         if (ret)
 997                 return ret;
 998
 999         ret = cqspi_read_setup(nor);
1000         if (ret)
1001                 return ret;
1002
1003         if (f_pdata->use_direct_mode)
1004                 ret = cqspi_direct_read_execute(nor, buf, from, len);
1005         else
1006                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1007         if (ret)
1008                 return ret;
1009
1010         return len;
1011 }
1012
1013 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1014 {
1015         int ret;
1016
1017         ret = cqspi_set_protocol(nor, 0);
1018         if (ret)
1019                 return ret;
1020
1021         /* Send write enable, then erase commands. */
1022         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1023         if (ret)
1024                 return ret;
1025
1026         /* Set up command buffer. */
1027         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1028         if (ret)
1029                 return ret;
1030
1031         return 0;
1032 }
1033
1034 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1035 {
1036         struct cqspi_flash_pdata *f_pdata = nor->priv;
1037         struct cqspi_st *cqspi = f_pdata->cqspi;
1038
1039         mutex_lock(&cqspi->bus_mutex);
1040
1041         return 0;
1042 }
1043
1044 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1045 {
1046         struct cqspi_flash_pdata *f_pdata = nor->priv;
1047         struct cqspi_st *cqspi = f_pdata->cqspi;
1048
1049         mutex_unlock(&cqspi->bus_mutex);
1050 }
1051
1052 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1053 {
1054         int ret;
1055
1056         ret = cqspi_set_protocol(nor, 0);
1057         if (!ret)
1058                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1059
1060         return ret;
1061 }
1062
1063 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1064 {
1065         int ret;
1066
1067         ret = cqspi_set_protocol(nor, 0);
1068         if (!ret)
1069                 ret = cqspi_command_write(nor, opcode, buf, len);
1070
1071         return ret;
1072 }
1073
1074 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1075                                     struct cqspi_flash_pdata *f_pdata,
1076                                     struct device_node *np)
1077 {
1078         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1079                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1080                 return -ENXIO;
1081         }
1082
1083         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1084                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1085                 return -ENXIO;
1086         }
1087
1088         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1089                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1090                 return -ENXIO;
1091         }
1092
1093         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1094                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1095                 return -ENXIO;
1096         }
1097
1098         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1099                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1100                 return -ENXIO;
1101         }
1102
1103         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1104                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1105                 return -ENXIO;
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int cqspi_of_get_pdata(struct platform_device *pdev)
1112 {
1113         struct device_node *np = pdev->dev.of_node;
1114         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1115
1116         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1117
1118         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1119                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1120                 return -ENXIO;
1121         }
1122
1123         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1124                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1125                 return -ENXIO;
1126         }
1127
1128         if (of_property_read_u32(np, "cdns,trigger-address",
1129                                  &cqspi->trigger_address)) {
1130                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1131                 return -ENXIO;
1132         }
1133
1134         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1135
1136         return 0;
1137 }
1138
1139 static void cqspi_controller_init(struct cqspi_st *cqspi)
1140 {
1141         u32 reg;
1142
1143         cqspi_controller_enable(cqspi, 0);
1144
1145         /* Configure the remap address register, no remap */
1146         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1147
1148         /* Disable all interrupts. */
1149         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1150
1151         /* Configure the SRAM split to 1:1 . */
1152         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1153
1154         /* Load indirect trigger address. */
1155         writel(cqspi->trigger_address,
1156                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1157
1158         /* Program read watermark -- 1/2 of the FIFO. */
1159         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1160                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1161         /* Program write watermark -- 1/8 of the FIFO. */
1162         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1163                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1164
1165         /* Enable Direct Access Controller */
1166         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1167         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1168         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1169
1170         cqspi_controller_enable(cqspi, 1);
1171 }
1172
1173 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1174 {
1175         dma_cap_mask_t mask;
1176
1177         dma_cap_zero(mask);
1178         dma_cap_set(DMA_MEMCPY, mask);
1179
1180         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1181         if (IS_ERR(cqspi->rx_chan)) {
1182                 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1183                 cqspi->rx_chan = NULL;
1184         }
1185         init_completion(&cqspi->rx_dma_complete);
1186 }
1187
1188 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1189 {
1190         const struct spi_nor_hwcaps hwcaps = {
1191                 .mask = SNOR_HWCAPS_READ |
1192                         SNOR_HWCAPS_READ_FAST |
1193                         SNOR_HWCAPS_READ_1_1_2 |
1194                         SNOR_HWCAPS_READ_1_1_4 |
1195                         SNOR_HWCAPS_PP,
1196         };
1197         struct platform_device *pdev = cqspi->pdev;
1198         struct device *dev = &pdev->dev;
1199         struct cqspi_flash_pdata *f_pdata;
1200         struct spi_nor *nor;
1201         struct mtd_info *mtd;
1202         unsigned int cs;
1203         int i, ret;
1204
1205         /* Get flash device data */
1206         for_each_available_child_of_node(dev->of_node, np) {
1207                 ret = of_property_read_u32(np, "reg", &cs);
1208                 if (ret) {
1209                         dev_err(dev, "Couldn't determine chip select.\n");
1210                         goto err;
1211                 }
1212
1213                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1214                         ret = -EINVAL;
1215                         dev_err(dev, "Chip select %d out of range.\n", cs);
1216                         goto err;
1217                 }
1218
1219                 f_pdata = &cqspi->f_pdata[cs];
1220                 f_pdata->cqspi = cqspi;
1221                 f_pdata->cs = cs;
1222
1223                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1224                 if (ret)
1225                         goto err;
1226
1227                 nor = &f_pdata->nor;
1228                 mtd = &nor->mtd;
1229
1230                 mtd->priv = nor;
1231
1232                 nor->dev = dev;
1233                 spi_nor_set_flash_node(nor, np);
1234                 nor->priv = f_pdata;
1235
1236                 nor->read_reg = cqspi_read_reg;
1237                 nor->write_reg = cqspi_write_reg;
1238                 nor->read = cqspi_read;
1239                 nor->write = cqspi_write;
1240                 nor->erase = cqspi_erase;
1241                 nor->prepare = cqspi_prep;
1242                 nor->unprepare = cqspi_unprep;
1243
1244                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1245                                            dev_name(dev), cs);
1246                 if (!mtd->name) {
1247                         ret = -ENOMEM;
1248                         goto err;
1249                 }
1250
1251                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1252                 if (ret)
1253                         goto err;
1254
1255                 ret = mtd_device_register(mtd, NULL, 0);
1256                 if (ret)
1257                         goto err;
1258
1259                 f_pdata->registered = true;
1260
1261                 if (mtd->size <= cqspi->ahb_size) {
1262                         f_pdata->use_direct_mode = true;
1263                         dev_dbg(nor->dev, "using direct mode for %s\n",
1264                                 mtd->name);
1265
1266                         if (!cqspi->rx_chan)
1267                                 cqspi_request_mmap_dma(cqspi);
1268                 }
1269         }
1270
1271         return 0;
1272
1273 err:
1274         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1275                 if (cqspi->f_pdata[i].registered)
1276                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1277         return ret;
1278 }
1279
1280 static int cqspi_probe(struct platform_device *pdev)
1281 {
1282         struct device_node *np = pdev->dev.of_node;
1283         struct device *dev = &pdev->dev;
1284         struct cqspi_st *cqspi;
1285         struct resource *res;
1286         struct resource *res_ahb;
1287         unsigned long data;
1288         int ret;
1289         int irq;
1290
1291         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1292         if (!cqspi)
1293                 return -ENOMEM;
1294
1295         mutex_init(&cqspi->bus_mutex);
1296         cqspi->pdev = pdev;
1297         platform_set_drvdata(pdev, cqspi);
1298
1299         /* Obtain configuration from OF. */
1300         ret = cqspi_of_get_pdata(pdev);
1301         if (ret) {
1302                 dev_err(dev, "Cannot get mandatory OF data.\n");
1303                 return -ENODEV;
1304         }
1305
1306         /* Obtain QSPI clock. */
1307         cqspi->clk = devm_clk_get(dev, NULL);
1308         if (IS_ERR(cqspi->clk)) {
1309                 dev_err(dev, "Cannot claim QSPI clock.\n");
1310                 return PTR_ERR(cqspi->clk);
1311         }
1312
1313         /* Obtain and remap controller address. */
1314         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315         cqspi->iobase = devm_ioremap_resource(dev, res);
1316         if (IS_ERR(cqspi->iobase)) {
1317                 dev_err(dev, "Cannot remap controller address.\n");
1318                 return PTR_ERR(cqspi->iobase);
1319         }
1320
1321         /* Obtain and remap AHB address. */
1322         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1323         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1324         if (IS_ERR(cqspi->ahb_base)) {
1325                 dev_err(dev, "Cannot remap AHB address.\n");
1326                 return PTR_ERR(cqspi->ahb_base);
1327         }
1328         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1329         cqspi->ahb_size = resource_size(res_ahb);
1330
1331         init_completion(&cqspi->transfer_complete);
1332
1333         /* Obtain IRQ line. */
1334         irq = platform_get_irq(pdev, 0);
1335         if (irq < 0) {
1336                 dev_err(dev, "Cannot obtain IRQ.\n");
1337                 return -ENXIO;
1338         }
1339
1340         pm_runtime_enable(dev);
1341         ret = pm_runtime_get_sync(dev);
1342         if (ret < 0) {
1343                 pm_runtime_put_noidle(dev);
1344                 return ret;
1345         }
1346
1347         ret = clk_prepare_enable(cqspi->clk);
1348         if (ret) {
1349                 dev_err(dev, "Cannot enable QSPI clock.\n");
1350                 goto probe_clk_failed;
1351         }
1352
1353         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1354         data  = (unsigned long)of_device_get_match_data(dev);
1355         if (data & CQSPI_NEEDS_WR_DELAY)
1356                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1357                                                    cqspi->master_ref_clk_hz);
1358
1359         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1360                                pdev->name, cqspi);
1361         if (ret) {
1362                 dev_err(dev, "Cannot request IRQ.\n");
1363                 goto probe_irq_failed;
1364         }
1365
1366         cqspi_wait_idle(cqspi);
1367         cqspi_controller_init(cqspi);
1368         cqspi->current_cs = -1;
1369         cqspi->sclk = 0;
1370
1371         ret = cqspi_setup_flash(cqspi, np);
1372         if (ret) {
1373                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1374                 goto probe_setup_failed;
1375         }
1376
1377         return ret;
1378 probe_setup_failed:
1379         cqspi_controller_enable(cqspi, 0);
1380 probe_irq_failed:
1381         clk_disable_unprepare(cqspi->clk);
1382 probe_clk_failed:
1383         pm_runtime_put_sync(dev);
1384         pm_runtime_disable(dev);
1385         return ret;
1386 }
1387
1388 static int cqspi_remove(struct platform_device *pdev)
1389 {
1390         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1391         int i;
1392
1393         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1394                 if (cqspi->f_pdata[i].registered)
1395                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1396
1397         cqspi_controller_enable(cqspi, 0);
1398
1399         if (cqspi->rx_chan)
1400                 dma_release_channel(cqspi->rx_chan);
1401
1402         clk_disable_unprepare(cqspi->clk);
1403
1404         pm_runtime_put_sync(&pdev->dev);
1405         pm_runtime_disable(&pdev->dev);
1406
1407         return 0;
1408 }
1409
1410 #ifdef CONFIG_PM_SLEEP
1411 static int cqspi_suspend(struct device *dev)
1412 {
1413         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1414
1415         cqspi_controller_enable(cqspi, 0);
1416         return 0;
1417 }
1418
1419 static int cqspi_resume(struct device *dev)
1420 {
1421         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1422
1423         cqspi_controller_enable(cqspi, 1);
1424         return 0;
1425 }
1426
1427 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1428         .suspend = cqspi_suspend,
1429         .resume = cqspi_resume,
1430 };
1431
1432 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1433 #else
1434 #define CQSPI_DEV_PM_OPS        NULL
1435 #endif
1436
1437 static const struct of_device_id cqspi_dt_ids[] = {
1438         {
1439                 .compatible = "cdns,qspi-nor",
1440                 .data = (void *)0,
1441         },
1442         {
1443                 .compatible = "ti,k2g-qspi",
1444                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1445         },
1446         { /* end of table */ }
1447 };
1448
1449 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1450
1451 static struct platform_driver cqspi_platform_driver = {
1452         .probe = cqspi_probe,
1453         .remove = cqspi_remove,
1454         .driver = {
1455                 .name = CQSPI_NAME,
1456                 .pm = CQSPI_DEV_PM_OPS,
1457                 .of_match_table = cqspi_dt_ids,
1458         },
1459 };
1460
1461 module_platform_driver(cqspi_platform_driver);
1462
1463 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1464 MODULE_LICENSE("GPL v2");
1465 MODULE_ALIAS("platform:" CQSPI_NAME);
1466 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1467 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");