drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/err.h>
  24 #include <linux/errno.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/mtd/spi-nor.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/sched.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/timer.h>
  40
  41 #define CQSPI_NAME                      "cadence-qspi"
  42 #define CQSPI_MAX_CHIPSELECT            16
  43
  44 /* Quirks */
  45 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  46
  47 /* Capabilities mask */
  48 #define CQSPI_BASE_HWCAPS_MASK                                  \
  49         (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |             \
  50         SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 |       \
  51         SNOR_HWCAPS_PP)
  52
  53 struct cqspi_st;
  54
  55 struct cqspi_flash_pdata {
  56         struct spi_nor  nor;
  57         struct cqspi_st *cqspi;
  58         u32             clk_rate;
  59         u32             read_delay;
  60         u32             tshsl_ns;
  61         u32             tsd2d_ns;
  62         u32             tchsh_ns;
  63         u32             tslch_ns;
  64         u8              inst_width;
  65         u8              addr_width;
  66         u8              data_width;
  67         u8              cs;
  68         bool            registered;
  69         bool            use_direct_mode;
  70 };
  71
  72 struct cqspi_st {
  73         struct platform_device  *pdev;
  74
  75         struct clk              *clk;
  76         unsigned int            sclk;
  77
  78         void __iomem            *iobase;
  79         void __iomem            *ahb_base;
  80         resource_size_t         ahb_size;
  81         struct completion       transfer_complete;
  82         struct mutex            bus_mutex;
  83
  84         struct dma_chan         *rx_chan;
  85         struct completion       rx_dma_complete;
  86         dma_addr_t              mmap_phys_base;
  87
  88         int                     current_cs;
  89         int                     current_page_size;
  90         int                     current_erase_size;
  91         int                     current_addr_width;
  92         unsigned long           master_ref_clk_hz;
  93         bool                    is_decoded_cs;
  94         u32                     fifo_depth;
  95         u32                     fifo_width;
  96         bool                    rclk_en;
  97         u32                     trigger_address;
  98         u32                     wr_delay;
  99         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 100 };
 101
 102 struct cqspi_driver_platdata {
 103         u32 hwcaps_mask;
 104         u8 quirks;
 105 };
 106
 107 /* Operation timeout value */
 108 #define CQSPI_TIMEOUT_MS                        500
 109 #define CQSPI_READ_TIMEOUT_MS                   10
 110
 111 /* Instruction type */
 112 #define CQSPI_INST_TYPE_SINGLE                  0
 113 #define CQSPI_INST_TYPE_DUAL                    1
 114 #define CQSPI_INST_TYPE_QUAD                    2
 115 #define CQSPI_INST_TYPE_OCTAL                   3
 116
 117 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 118 #define CQSPI_DUMMY_BYTES_MAX                   4
 119 #define CQSPI_DUMMY_CLKS_MAX                    31
 120
 121 #define CQSPI_STIG_DATA_LEN_MAX                 8
 122
 123 /* Register map */
 124 #define CQSPI_REG_CONFIG                        0x00
 125 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 126 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 127 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 128 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 129 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 130 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 131 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 132 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 133 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 134
 135 #define CQSPI_REG_RD_INSTR                      0x04
 136 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 137 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 138 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 139 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 140 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 141 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 142 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 143 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 144 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 145 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 146
 147 #define CQSPI_REG_WR_INSTR                      0x08
 148 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 149 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 150 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 151
 152 #define CQSPI_REG_DELAY                         0x0C
 153 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 154 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 155 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 156 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 157 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 158 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 159 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 160 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 161
 162 #define CQSPI_REG_READCAPTURE                   0x10
 163 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 164 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 165 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 166
 167 #define CQSPI_REG_SIZE                          0x14
 168 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 169 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 170 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 171 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 172 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 173 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 174
 175 #define CQSPI_REG_SRAMPARTITION                 0x18
 176 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 177
 178 #define CQSPI_REG_DMA                           0x20
 179 #define CQSPI_REG_DMA_SINGLE_LSB                0
 180 #define CQSPI_REG_DMA_BURST_LSB                 8
 181 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 182 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 183
 184 #define CQSPI_REG_REMAP                         0x24
 185 #define CQSPI_REG_MODE_BIT                      0x28
 186
 187 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 188 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 189 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 190 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 191 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 192
 193 #define CQSPI_REG_IRQSTATUS                     0x40
 194 #define CQSPI_REG_IRQMASK                       0x44
 195
 196 #define CQSPI_REG_INDIRECTRD                    0x60
 197 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 198 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 199 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 200
 201 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 202 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 203 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 204
 205 #define CQSPI_REG_CMDCTRL                       0x90
 206 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 207 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 208 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 209 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 210 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 211 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 212 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 213 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 214 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 215 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 216 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 217 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 218
 219 #define CQSPI_REG_INDIRECTWR                    0x70
 220 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 221 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 222 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 223
 224 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 225 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 226 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 227
 228 #define CQSPI_REG_CMDADDRESS                    0x94
 229 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 230 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 231 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 232 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 233
 234 /* Interrupt status bits */
 235 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 236 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 237 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 238 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 239 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 240 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 241 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 242 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 243
 244 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 245                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 246                                          CQSPI_REG_IRQ_IND_COMP)
 247
 248 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 249                                          CQSPI_REG_IRQ_WATERMARK        | \
 250                                          CQSPI_REG_IRQ_UNDERFLOW)
 251
 252 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 253
 254 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 255 {
 256         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 257         u32 val;
 258
 259         while (1) {
 260                 val = readl(reg);
 261                 if (clear)
 262                         val = ~val;
 263                 val &= mask;
 264
 265                 if (val == mask)
 266                         return 0;
 267
 268                 if (time_after(jiffies, end))
 269                         return -ETIMEDOUT;
 270         }
 271 }
 272
 273 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 274 {
 275         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 276
 277         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 278 }
 279
 280 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 281 {
 282         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 283
 284         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 285         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 286 }
 287
 288 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 289 {
 290         struct cqspi_st *cqspi = dev;
 291         unsigned int irq_status;
 292
 293         /* Read interrupt status */
 294         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 295
 296         /* Clear interrupt */
 297         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 298
 299         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 300
 301         if (irq_status)
 302                 complete(&cqspi->transfer_complete);
 303
 304         return IRQ_HANDLED;
 305 }
 306
 307 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 308 {
 309         struct cqspi_flash_pdata *f_pdata = nor->priv;
 310         u32 rdreg = 0;
 311
 312         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 313         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 314         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 315
 316         return rdreg;
 317 }
 318
 319 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 320 {
 321         const unsigned int poll_idle_retry = 3;
 322         unsigned int count = 0;
 323         unsigned long timeout;
 324
 325         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 326         while (1) {
 327                 /*
 328                  * Read few times in succession to ensure the controller
 329                  * is indeed idle, that is, the bit does not transition
 330                  * low again.
 331                  */
 332                 if (cqspi_is_idle(cqspi))
 333                         count++;
 334                 else
 335                         count = 0;
 336
 337                 if (count >= poll_idle_retry)
 338                         return 0;
 339
 340                 if (time_after(jiffies, timeout)) {
 341                         /* Timeout, in busy mode. */
 342                         dev_err(&cqspi->pdev->dev,
 343                                 "QSPI is still busy after %dms timeout.\n",
 344                                 CQSPI_TIMEOUT_MS);
 345                         return -ETIMEDOUT;
 346                 }
 347
 348                 cpu_relax();
 349         }
 350 }
 351
 352 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 353 {
 354         void __iomem *reg_base = cqspi->iobase;
 355         int ret;
 356
 357         /* Write the CMDCTRL without start execution. */
 358         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 359         /* Start execute */
 360         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 361         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 362
 363         /* Polling for completion. */
 364         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 365                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 366         if (ret) {
 367                 dev_err(&cqspi->pdev->dev,
 368                         "Flash command execution timed out.\n");
 369                 return ret;
 370         }
 371
 372         /* Polling QSPI idle status. */
 373         return cqspi_wait_idle(cqspi);
 374 }
 375
 376 static int cqspi_command_read(struct spi_nor *nor,
 377                               const u8 *txbuf, const unsigned n_tx,
 378                               u8 *rxbuf, const unsigned n_rx)
 379 {
 380         struct cqspi_flash_pdata *f_pdata = nor->priv;
 381         struct cqspi_st *cqspi = f_pdata->cqspi;
 382         void __iomem *reg_base = cqspi->iobase;
 383         unsigned int rdreg;
 384         unsigned int reg;
 385         unsigned int read_len;
 386         int status;
 387
 388         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 389                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 390                         n_rx, rxbuf);
 391                 return -EINVAL;
 392         }
 393
 394         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 395
 396         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 397         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 398
 399         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 400
 401         /* 0 means 1 byte. */
 402         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 403                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 404         status = cqspi_exec_flash_cmd(cqspi, reg);
 405         if (status)
 406                 return status;
 407
 408         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 409
 410         /* Put the read value into rx_buf */
 411         read_len = (n_rx > 4) ? 4 : n_rx;
 412         memcpy(rxbuf, &reg, read_len);
 413         rxbuf += read_len;
 414
 415         if (n_rx > 4) {
 416                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 417
 418                 read_len = n_rx - read_len;
 419                 memcpy(rxbuf, &reg, read_len);
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 426                                const u8 *txbuf, const unsigned n_tx)
 427 {
 428         struct cqspi_flash_pdata *f_pdata = nor->priv;
 429         struct cqspi_st *cqspi = f_pdata->cqspi;
 430         void __iomem *reg_base = cqspi->iobase;
 431         unsigned int reg;
 432         unsigned int data;
 433         u32 write_len;
 434         int ret;
 435
 436         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 437                 dev_err(nor->dev,
 438                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 439                         n_tx, txbuf);
 440                 return -EINVAL;
 441         }
 442
 443         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 444         if (n_tx) {
 445                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 446                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 447                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 448                 data = 0;
 449                 write_len = (n_tx > 4) ? 4 : n_tx;
 450                 memcpy(&data, txbuf, write_len);
 451                 txbuf += write_len;
 452                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 453
 454                 if (n_tx > 4) {
 455                         data = 0;
 456                         write_len = n_tx - 4;
 457                         memcpy(&data, txbuf, write_len);
 458                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 459                 }
 460         }
 461         ret = cqspi_exec_flash_cmd(cqspi, reg);
 462         return ret;
 463 }
 464
 465 static int cqspi_command_write_addr(struct spi_nor *nor,
 466                                     const u8 opcode, const unsigned int addr)
 467 {
 468         struct cqspi_flash_pdata *f_pdata = nor->priv;
 469         struct cqspi_st *cqspi = f_pdata->cqspi;
 470         void __iomem *reg_base = cqspi->iobase;
 471         unsigned int reg;
 472
 473         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 474         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 475         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 476                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 477
 478         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 479
 480         return cqspi_exec_flash_cmd(cqspi, reg);
 481 }
 482
 483 static int cqspi_read_setup(struct spi_nor *nor)
 484 {
 485         struct cqspi_flash_pdata *f_pdata = nor->priv;
 486         struct cqspi_st *cqspi = f_pdata->cqspi;
 487         void __iomem *reg_base = cqspi->iobase;
 488         unsigned int dummy_clk = 0;
 489         unsigned int reg;
 490
 491         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 492         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 493
 494         /* Setup dummy clock cycles */
 495         dummy_clk = nor->read_dummy;
 496         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 497                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 498
 499         if (dummy_clk / 8) {
 500                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 501                 /* Set mode bits high to ensure chip doesn't enter XIP */
 502                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 503
 504                 /* Need to subtract the mode byte (8 clocks). */
 505                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 506                         dummy_clk -= 8;
 507
 508                 if (dummy_clk)
 509                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 510                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 511         }
 512
 513         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 514
 515         /* Set address width */
 516         reg = readl(reg_base + CQSPI_REG_SIZE);
 517         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 518         reg |= (nor->addr_width - 1);
 519         writel(reg, reg_base + CQSPI_REG_SIZE);
 520         return 0;
 521 }
 522
 523 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 524                                        loff_t from_addr, const size_t n_rx)
 525 {
 526         struct cqspi_flash_pdata *f_pdata = nor->priv;
 527         struct cqspi_st *cqspi = f_pdata->cqspi;
 528         void __iomem *reg_base = cqspi->iobase;
 529         void __iomem *ahb_base = cqspi->ahb_base;
 530         unsigned int remaining = n_rx;
 531         unsigned int mod_bytes = n_rx % 4;
 532         unsigned int bytes_to_read = 0;
 533         u8 *rxbuf_end = rxbuf + n_rx;
 534         int ret = 0;
 535
 536         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 537         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 538
 539         /* Clear all interrupts. */
 540         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 541
 542         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 543
 544         reinit_completion(&cqspi->transfer_complete);
 545         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 546                reg_base + CQSPI_REG_INDIRECTRD);
 547
 548         while (remaining > 0) {
 549                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 550                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 551                         ret = -ETIMEDOUT;
 552
 553                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 554
 555                 if (ret && bytes_to_read == 0) {
 556                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 557                         goto failrd;
 558                 }
 559
 560                 while (bytes_to_read != 0) {
 561                         unsigned int word_remain = round_down(remaining, 4);
 562
 563                         bytes_to_read *= cqspi->fifo_width;
 564                         bytes_to_read = bytes_to_read > remaining ?
 565                                         remaining : bytes_to_read;
 566                         bytes_to_read = round_down(bytes_to_read, 4);
 567                         /* Read 4 byte word chunks then single bytes */
 568                         if (bytes_to_read) {
 569                                 ioread32_rep(ahb_base, rxbuf,
 570                                              (bytes_to_read / 4));
 571                         } else if (!word_remain && mod_bytes) {
 572                                 unsigned int temp = ioread32(ahb_base);
 573
 574                                 bytes_to_read = mod_bytes;
 575                                 memcpy(rxbuf, &temp, min((unsigned int)
 576                                                          (rxbuf_end - rxbuf),
 577                                                          bytes_to_read));
 578                         }
 579                         rxbuf += bytes_to_read;
 580                         remaining -= bytes_to_read;
 581                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 582                 }
 583
 584                 if (remaining > 0)
 585                         reinit_completion(&cqspi->transfer_complete);
 586         }
 587
 588         /* Check indirect done status */
 589         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 590                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 591         if (ret) {
 592                 dev_err(nor->dev,
 593                         "Indirect read completion error (%i)\n", ret);
 594                 goto failrd;
 595         }
 596
 597         /* Disable interrupt */
 598         writel(0, reg_base + CQSPI_REG_IRQMASK);
 599
 600         /* Clear indirect completion status */
 601         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 602
 603         return 0;
 604
 605 failrd:
 606         /* Disable interrupt */
 607         writel(0, reg_base + CQSPI_REG_IRQMASK);
 608
 609         /* Cancel the indirect read */
 610         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 611                reg_base + CQSPI_REG_INDIRECTRD);
 612         return ret;
 613 }
 614
 615 static int cqspi_write_setup(struct spi_nor *nor)
 616 {
 617         unsigned int reg;
 618         struct cqspi_flash_pdata *f_pdata = nor->priv;
 619         struct cqspi_st *cqspi = f_pdata->cqspi;
 620         void __iomem *reg_base = cqspi->iobase;
 621
 622         /* Set opcode. */
 623         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 624         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 625         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 626         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 627
 628         reg = readl(reg_base + CQSPI_REG_SIZE);
 629         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 630         reg |= (nor->addr_width - 1);
 631         writel(reg, reg_base + CQSPI_REG_SIZE);
 632         return 0;
 633 }
 634
 635 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 636                                         const u8 *txbuf, const size_t n_tx)
 637 {
 638         const unsigned int page_size = nor->page_size;
 639         struct cqspi_flash_pdata *f_pdata = nor->priv;
 640         struct cqspi_st *cqspi = f_pdata->cqspi;
 641         void __iomem *reg_base = cqspi->iobase;
 642         unsigned int remaining = n_tx;
 643         unsigned int write_bytes;
 644         int ret;
 645
 646         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 647         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 648
 649         /* Clear all interrupts. */
 650         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 651
 652         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 653
 654         reinit_completion(&cqspi->transfer_complete);
 655         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 656                reg_base + CQSPI_REG_INDIRECTWR);
 657         /*
 658          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 659          * Controller programming sequence, couple of cycles of
 660          * QSPI_REF_CLK delay is required for the above bit to
 661          * be internally synchronized by the QSPI module. Provide 5
 662          * cycles of delay.
 663          */
 664         if (cqspi->wr_delay)
 665                 ndelay(cqspi->wr_delay);
 666
 667         while (remaining > 0) {
 668                 size_t write_words, mod_bytes;
 669
 670                 write_bytes = remaining > page_size ? page_size : remaining;
 671                 write_words = write_bytes / 4;
 672                 mod_bytes = write_bytes % 4;
 673                 /* Write 4 bytes at a time then single bytes. */
 674                 if (write_words) {
 675                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 676                         txbuf += (write_words * 4);
 677                 }
 678                 if (mod_bytes) {
 679                         unsigned int temp = 0xFFFFFFFF;
 680
 681                         memcpy(&temp, txbuf, mod_bytes);
 682                         iowrite32(temp, cqspi->ahb_base);
 683                         txbuf += mod_bytes;
 684                 }
 685
 686                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 687                                         msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 688                         dev_err(nor->dev, "Indirect write timeout\n");
 689                         ret = -ETIMEDOUT;
 690                         goto failwr;
 691                 }
 692
 693                 remaining -= write_bytes;
 694
 695                 if (remaining > 0)
 696                         reinit_completion(&cqspi->transfer_complete);
 697         }
 698
 699         /* Check indirect done status */
 700         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 701                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 702         if (ret) {
 703                 dev_err(nor->dev,
 704                         "Indirect write completion error (%i)\n", ret);
 705                 goto failwr;
 706         }
 707
 708         /* Disable interrupt. */
 709         writel(0, reg_base + CQSPI_REG_IRQMASK);
 710
 711         /* Clear indirect completion status */
 712         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 713
 714         cqspi_wait_idle(cqspi);
 715
 716         return 0;
 717
 718 failwr:
 719         /* Disable interrupt. */
 720         writel(0, reg_base + CQSPI_REG_IRQMASK);
 721
 722         /* Cancel the indirect write */
 723         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 724                reg_base + CQSPI_REG_INDIRECTWR);
 725         return ret;
 726 }
 727
 728 static void cqspi_chipselect(struct spi_nor *nor)
 729 {
 730         struct cqspi_flash_pdata *f_pdata = nor->priv;
 731         struct cqspi_st *cqspi = f_pdata->cqspi;
 732         void __iomem *reg_base = cqspi->iobase;
 733         unsigned int chip_select = f_pdata->cs;
 734         unsigned int reg;
 735
 736         reg = readl(reg_base + CQSPI_REG_CONFIG);
 737         if (cqspi->is_decoded_cs) {
 738                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 739         } else {
 740                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 741
 742                 /* Convert CS if without decoder.
 743                  * CS0 to 4b'1110
 744                  * CS1 to 4b'1101
 745                  * CS2 to 4b'1011
 746                  * CS3 to 4b'0111
 747                  */
 748                 chip_select = 0xF & ~(1 << chip_select);
 749         }
 750
 751         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 752                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 753         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 754             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 755         writel(reg, reg_base + CQSPI_REG_CONFIG);
 756 }
 757
 758 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 759 {
 760         struct cqspi_flash_pdata *f_pdata = nor->priv;
 761         struct cqspi_st *cqspi = f_pdata->cqspi;
 762         void __iomem *iobase = cqspi->iobase;
 763         unsigned int reg;
 764
 765         /* configure page size and block size. */
 766         reg = readl(iobase + CQSPI_REG_SIZE);
 767         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 768         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 769         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 770         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 771         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 772         reg |= (nor->addr_width - 1);
 773         writel(reg, iobase + CQSPI_REG_SIZE);
 774
 775         /* configure the chip select */
 776         cqspi_chipselect(nor);
 777
 778         /* Store the new configuration of the controller */
 779         cqspi->current_page_size = nor->page_size;
 780         cqspi->current_erase_size = nor->mtd.erasesize;
 781         cqspi->current_addr_width = nor->addr_width;
 782 }
 783
 784 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 785                                            const unsigned int ns_val)
 786 {
 787         unsigned int ticks;
 788
 789         ticks = ref_clk_hz / 1000;      /* kHz */
 790         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 791
 792         return ticks;
 793 }
 794
 795 static void cqspi_delay(struct spi_nor *nor)
 796 {
 797         struct cqspi_flash_pdata *f_pdata = nor->priv;
 798         struct cqspi_st *cqspi = f_pdata->cqspi;
 799         void __iomem *iobase = cqspi->iobase;
 800         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 801         unsigned int tshsl, tchsh, tslch, tsd2d;
 802         unsigned int reg;
 803         unsigned int tsclk;
 804
 805         /* calculate the number of ref ticks for one sclk tick */
 806         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 807
 808         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 809         /* this particular value must be at least one sclk */
 810         if (tshsl < tsclk)
 811                 tshsl = tsclk;
 812
 813         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 814         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 815         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 816
 817         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 818                << CQSPI_REG_DELAY_TSHSL_LSB;
 819         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 820                 << CQSPI_REG_DELAY_TCHSH_LSB;
 821         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 822                 << CQSPI_REG_DELAY_TSLCH_LSB;
 823         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 824                 << CQSPI_REG_DELAY_TSD2D_LSB;
 825         writel(reg, iobase + CQSPI_REG_DELAY);
 826 }
 827
 828 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 829 {
 830         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 831         void __iomem *reg_base = cqspi->iobase;
 832         u32 reg, div;
 833
 834         /* Recalculate the baudrate divisor based on QSPI specification. */
 835         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 836
 837         reg = readl(reg_base + CQSPI_REG_CONFIG);
 838         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 839         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 840         writel(reg, reg_base + CQSPI_REG_CONFIG);
 841 }
 842
 843 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 844                                    const bool bypass,
 845                                    const unsigned int delay)
 846 {
 847         void __iomem *reg_base = cqspi->iobase;
 848         unsigned int reg;
 849
 850         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 851
 852         if (bypass)
 853                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 854         else
 855                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 856
 857         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 858                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 859
 860         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 861                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 862
 863         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 864 }
 865
 866 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 867 {
 868         void __iomem *reg_base = cqspi->iobase;
 869         unsigned int reg;
 870
 871         reg = readl(reg_base + CQSPI_REG_CONFIG);
 872
 873         if (enable)
 874                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 875         else
 876                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 877
 878         writel(reg, reg_base + CQSPI_REG_CONFIG);
 879 }
 880
 881 static void cqspi_configure(struct spi_nor *nor)
 882 {
 883         struct cqspi_flash_pdata *f_pdata = nor->priv;
 884         struct cqspi_st *cqspi = f_pdata->cqspi;
 885         const unsigned int sclk = f_pdata->clk_rate;
 886         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 887         int switch_ck = (cqspi->sclk != sclk);
 888
 889         if ((cqspi->current_page_size != nor->page_size) ||
 890             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 891             (cqspi->current_addr_width != nor->addr_width))
 892                 switch_cs = 1;
 893
 894         if (switch_cs || switch_ck)
 895                 cqspi_controller_enable(cqspi, 0);
 896
 897         /* Switch chip select. */
 898         if (switch_cs) {
 899                 cqspi->current_cs = f_pdata->cs;
 900                 cqspi_configure_cs_and_sizes(nor);
 901         }
 902
 903         /* Setup baudrate divisor and delays */
 904         if (switch_ck) {
 905                 cqspi->sclk = sclk;
 906                 cqspi_config_baudrate_div(cqspi);
 907                 cqspi_delay(nor);
 908                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 909                                        f_pdata->read_delay);
 910         }
 911
 912         if (switch_cs || switch_ck)
 913                 cqspi_controller_enable(cqspi, 1);
 914 }
 915
 916 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 917 {
 918         struct cqspi_flash_pdata *f_pdata = nor->priv;
 919
 920         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 921         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 922         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 923
 924         if (read) {
 925                 switch (nor->read_proto) {
 926                 case SNOR_PROTO_1_1_1:
 927                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 928                         break;
 929                 case SNOR_PROTO_1_1_2:
 930                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 931                         break;
 932                 case SNOR_PROTO_1_1_4:
 933                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 934                         break;
 935                 case SNOR_PROTO_1_1_8:
 936                         f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
 937                         break;
 938                 default:
 939                         return -EINVAL;
 940                 }
 941         }
 942
 943         cqspi_configure(nor);
 944
 945         return 0;
 946 }
 947
 948 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 949                            size_t len, const u_char *buf)
 950 {
 951         struct cqspi_flash_pdata *f_pdata = nor->priv;
 952         struct cqspi_st *cqspi = f_pdata->cqspi;
 953         int ret;
 954
 955         ret = cqspi_set_protocol(nor, 0);
 956         if (ret)
 957                 return ret;
 958
 959         ret = cqspi_write_setup(nor);
 960         if (ret)
 961                 return ret;
 962
 963         if (f_pdata->use_direct_mode) {
 964                 memcpy_toio(cqspi->ahb_base + to, buf, len);
 965                 ret = cqspi_wait_idle(cqspi);
 966         } else {
 967                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
 968         }
 969         if (ret)
 970                 return ret;
 971
 972         return len;
 973 }
 974
 975 static void cqspi_rx_dma_callback(void *param)
 976 {
 977         struct cqspi_st *cqspi = param;
 978
 979         complete(&cqspi->rx_dma_complete);
 980 }
 981
 982 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
 983                                      loff_t from, size_t len)
 984 {
 985         struct cqspi_flash_pdata *f_pdata = nor->priv;
 986         struct cqspi_st *cqspi = f_pdata->cqspi;
 987         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 988         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
 989         int ret = 0;
 990         struct dma_async_tx_descriptor *tx;
 991         dma_cookie_t cookie;
 992         dma_addr_t dma_dst;
 993
 994         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
 995                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
 996                 return 0;
 997         }
 998
 999         dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
1000         if (dma_mapping_error(nor->dev, dma_dst)) {
1001                 dev_err(nor->dev, "dma mapping failed\n");
1002                 return -ENOMEM;
1003         }
1004         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1005                                        len, flags);
1006         if (!tx) {
1007                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
1008                 ret = -EIO;
1009                 goto err_unmap;
1010         }
1011
1012         tx->callback = cqspi_rx_dma_callback;
1013         tx->callback_param = cqspi;
1014         cookie = tx->tx_submit(tx);
1015         reinit_completion(&cqspi->rx_dma_complete);
1016
1017         ret = dma_submit_error(cookie);
1018         if (ret) {
1019                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
1020                 ret = -EIO;
1021                 goto err_unmap;
1022         }
1023
1024         dma_async_issue_pending(cqspi->rx_chan);
1025         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1026                                          msecs_to_jiffies(len))) {
1027                 dmaengine_terminate_sync(cqspi->rx_chan);
1028                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
1029                 ret = -ETIMEDOUT;
1030                 goto err_unmap;
1031         }
1032
1033 err_unmap:
1034         dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
1035
1036         return ret;
1037 }
1038
1039 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1040                           size_t len, u_char *buf)
1041 {
1042         struct cqspi_flash_pdata *f_pdata = nor->priv;
1043         int ret;
1044
1045         ret = cqspi_set_protocol(nor, 1);
1046         if (ret)
1047                 return ret;
1048
1049         ret = cqspi_read_setup(nor);
1050         if (ret)
1051                 return ret;
1052
1053         if (f_pdata->use_direct_mode)
1054                 ret = cqspi_direct_read_execute(nor, buf, from, len);
1055         else
1056                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1057         if (ret)
1058                 return ret;
1059
1060         return len;
1061 }
1062
1063 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1064 {
1065         int ret;
1066
1067         ret = cqspi_set_protocol(nor, 0);
1068         if (ret)
1069                 return ret;
1070
1071         /* Send write enable, then erase commands. */
1072         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1073         if (ret)
1074                 return ret;
1075
1076         /* Set up command buffer. */
1077         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1078         if (ret)
1079                 return ret;
1080
1081         return 0;
1082 }
1083
1084 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1085 {
1086         struct cqspi_flash_pdata *f_pdata = nor->priv;
1087         struct cqspi_st *cqspi = f_pdata->cqspi;
1088
1089         mutex_lock(&cqspi->bus_mutex);
1090
1091         return 0;
1092 }
1093
1094 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1095 {
1096         struct cqspi_flash_pdata *f_pdata = nor->priv;
1097         struct cqspi_st *cqspi = f_pdata->cqspi;
1098
1099         mutex_unlock(&cqspi->bus_mutex);
1100 }
1101
1102 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1103 {
1104         int ret;
1105
1106         ret = cqspi_set_protocol(nor, 0);
1107         if (!ret)
1108                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1109
1110         return ret;
1111 }
1112
1113 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1114 {
1115         int ret;
1116
1117         ret = cqspi_set_protocol(nor, 0);
1118         if (!ret)
1119                 ret = cqspi_command_write(nor, opcode, buf, len);
1120
1121         return ret;
1122 }
1123
1124 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1125                                     struct cqspi_flash_pdata *f_pdata,
1126                                     struct device_node *np)
1127 {
1128         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1129                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1130                 return -ENXIO;
1131         }
1132
1133         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1134                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1135                 return -ENXIO;
1136         }
1137
1138         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1139                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1140                 return -ENXIO;
1141         }
1142
1143         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1144                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1145                 return -ENXIO;
1146         }
1147
1148         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1149                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1150                 return -ENXIO;
1151         }
1152
1153         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1154                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1155                 return -ENXIO;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int cqspi_of_get_pdata(struct platform_device *pdev)
1162 {
1163         struct device_node *np = pdev->dev.of_node;
1164         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1165
1166         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1167
1168         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1169                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1170                 return -ENXIO;
1171         }
1172
1173         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1174                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1175                 return -ENXIO;
1176         }
1177
1178         if (of_property_read_u32(np, "cdns,trigger-address",
1179                                  &cqspi->trigger_address)) {
1180                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1181                 return -ENXIO;
1182         }
1183
1184         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1185
1186         return 0;
1187 }
1188
1189 static void cqspi_controller_init(struct cqspi_st *cqspi)
1190 {
1191         u32 reg;
1192
1193         cqspi_controller_enable(cqspi, 0);
1194
1195         /* Configure the remap address register, no remap */
1196         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1197
1198         /* Disable all interrupts. */
1199         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1200
1201         /* Configure the SRAM split to 1:1 . */
1202         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1203
1204         /* Load indirect trigger address. */
1205         writel(cqspi->trigger_address,
1206                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1207
1208         /* Program read watermark -- 1/2 of the FIFO. */
1209         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1210                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1211         /* Program write watermark -- 1/8 of the FIFO. */
1212         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1213                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1214
1215         /* Enable Direct Access Controller */
1216         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1217         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1218         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1219
1220         cqspi_controller_enable(cqspi, 1);
1221 }
1222
1223 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1224 {
1225         dma_cap_mask_t mask;
1226
1227         dma_cap_zero(mask);
1228         dma_cap_set(DMA_MEMCPY, mask);
1229
1230         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1231         if (IS_ERR(cqspi->rx_chan)) {
1232                 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1233                 cqspi->rx_chan = NULL;
1234         }
1235         init_completion(&cqspi->rx_dma_complete);
1236 }
1237
1238 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1239 {
1240         struct platform_device *pdev = cqspi->pdev;
1241         struct device *dev = &pdev->dev;
1242         const struct cqspi_driver_platdata *ddata;
1243         struct spi_nor_hwcaps hwcaps;
1244         struct cqspi_flash_pdata *f_pdata;
1245         struct spi_nor *nor;
1246         struct mtd_info *mtd;
1247         unsigned int cs;
1248         int i, ret;
1249
1250         ddata = of_device_get_match_data(dev);
1251         if (!ddata) {
1252                 dev_err(dev, "Couldn't find driver data\n");
1253                 return -EINVAL;
1254         }
1255         hwcaps.mask = ddata->hwcaps_mask;
1256
1257         /* Get flash device data */
1258         for_each_available_child_of_node(dev->of_node, np) {
1259                 ret = of_property_read_u32(np, "reg", &cs);
1260                 if (ret) {
1261                         dev_err(dev, "Couldn't determine chip select.\n");
1262                         goto err;
1263                 }
1264
1265                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1266                         ret = -EINVAL;
1267                         dev_err(dev, "Chip select %d out of range.\n", cs);
1268                         goto err;
1269                 }
1270
1271                 f_pdata = &cqspi->f_pdata[cs];
1272                 f_pdata->cqspi = cqspi;
1273                 f_pdata->cs = cs;
1274
1275                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1276                 if (ret)
1277                         goto err;
1278
1279                 nor = &f_pdata->nor;
1280                 mtd = &nor->mtd;
1281
1282                 mtd->priv = nor;
1283
1284                 nor->dev = dev;
1285                 spi_nor_set_flash_node(nor, np);
1286                 nor->priv = f_pdata;
1287
1288                 nor->read_reg = cqspi_read_reg;
1289                 nor->write_reg = cqspi_write_reg;
1290                 nor->read = cqspi_read;
1291                 nor->write = cqspi_write;
1292                 nor->erase = cqspi_erase;
1293                 nor->prepare = cqspi_prep;
1294                 nor->unprepare = cqspi_unprep;
1295
1296                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1297                                            dev_name(dev), cs);
1298                 if (!mtd->name) {
1299                         ret = -ENOMEM;
1300                         goto err;
1301                 }
1302
1303                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1304                 if (ret)
1305                         goto err;
1306
1307                 ret = mtd_device_register(mtd, NULL, 0);
1308                 if (ret)
1309                         goto err;
1310
1311                 f_pdata->registered = true;
1312
1313                 if (mtd->size <= cqspi->ahb_size) {
1314                         f_pdata->use_direct_mode = true;
1315                         dev_dbg(nor->dev, "using direct mode for %s\n",
1316                                 mtd->name);
1317
1318                         if (!cqspi->rx_chan)
1319                                 cqspi_request_mmap_dma(cqspi);
1320                 }
1321         }
1322
1323         return 0;
1324
1325 err:
1326         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1327                 if (cqspi->f_pdata[i].registered)
1328                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1329         return ret;
1330 }
1331
1332 static int cqspi_probe(struct platform_device *pdev)
1333 {
1334         struct device_node *np = pdev->dev.of_node;
1335         struct device *dev = &pdev->dev;
1336         struct cqspi_st *cqspi;
1337         struct resource *res;
1338         struct resource *res_ahb;
1339         const struct cqspi_driver_platdata *ddata;
1340         int ret;
1341         int irq;
1342
1343         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1344         if (!cqspi)
1345                 return -ENOMEM;
1346
1347         mutex_init(&cqspi->bus_mutex);
1348         cqspi->pdev = pdev;
1349         platform_set_drvdata(pdev, cqspi);
1350
1351         /* Obtain configuration from OF. */
1352         ret = cqspi_of_get_pdata(pdev);
1353         if (ret) {
1354                 dev_err(dev, "Cannot get mandatory OF data.\n");
1355                 return -ENODEV;
1356         }
1357
1358         /* Obtain QSPI clock. */
1359         cqspi->clk = devm_clk_get(dev, NULL);
1360         if (IS_ERR(cqspi->clk)) {
1361                 dev_err(dev, "Cannot claim QSPI clock.\n");
1362                 return PTR_ERR(cqspi->clk);
1363         }
1364
1365         /* Obtain and remap controller address. */
1366         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367         cqspi->iobase = devm_ioremap_resource(dev, res);
1368         if (IS_ERR(cqspi->iobase)) {
1369                 dev_err(dev, "Cannot remap controller address.\n");
1370                 return PTR_ERR(cqspi->iobase);
1371         }
1372
1373         /* Obtain and remap AHB address. */
1374         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1375         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1376         if (IS_ERR(cqspi->ahb_base)) {
1377                 dev_err(dev, "Cannot remap AHB address.\n");
1378                 return PTR_ERR(cqspi->ahb_base);
1379         }
1380         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1381         cqspi->ahb_size = resource_size(res_ahb);
1382
1383         init_completion(&cqspi->transfer_complete);
1384
1385         /* Obtain IRQ line. */
1386         irq = platform_get_irq(pdev, 0);
1387         if (irq < 0) {
1388                 dev_err(dev, "Cannot obtain IRQ.\n");
1389                 return -ENXIO;
1390         }
1391
1392         pm_runtime_enable(dev);
1393         ret = pm_runtime_get_sync(dev);
1394         if (ret < 0) {
1395                 pm_runtime_put_noidle(dev);
1396                 return ret;
1397         }
1398
1399         ret = clk_prepare_enable(cqspi->clk);
1400         if (ret) {
1401                 dev_err(dev, "Cannot enable QSPI clock.\n");
1402                 goto probe_clk_failed;
1403         }
1404
1405         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1406         ddata  = of_device_get_match_data(dev);
1407         if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
1408                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1409                                                    cqspi->master_ref_clk_hz);
1410
1411         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1412                                pdev->name, cqspi);
1413         if (ret) {
1414                 dev_err(dev, "Cannot request IRQ.\n");
1415                 goto probe_irq_failed;
1416         }
1417
1418         cqspi_wait_idle(cqspi);
1419         cqspi_controller_init(cqspi);
1420         cqspi->current_cs = -1;
1421         cqspi->sclk = 0;
1422
1423         ret = cqspi_setup_flash(cqspi, np);
1424         if (ret) {
1425                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1426                 goto probe_setup_failed;
1427         }
1428
1429         return ret;
1430 probe_setup_failed:
1431         cqspi_controller_enable(cqspi, 0);
1432 probe_irq_failed:
1433         clk_disable_unprepare(cqspi->clk);
1434 probe_clk_failed:
1435         pm_runtime_put_sync(dev);
1436         pm_runtime_disable(dev);
1437         return ret;
1438 }
1439
1440 static int cqspi_remove(struct platform_device *pdev)
1441 {
1442         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1443         int i;
1444
1445         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1446                 if (cqspi->f_pdata[i].registered)
1447                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1448
1449         cqspi_controller_enable(cqspi, 0);
1450
1451         if (cqspi->rx_chan)
1452                 dma_release_channel(cqspi->rx_chan);
1453
1454         clk_disable_unprepare(cqspi->clk);
1455
1456         pm_runtime_put_sync(&pdev->dev);
1457         pm_runtime_disable(&pdev->dev);
1458
1459         return 0;
1460 }
1461
1462 #ifdef CONFIG_PM_SLEEP
1463 static int cqspi_suspend(struct device *dev)
1464 {
1465         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1466
1467         cqspi_controller_enable(cqspi, 0);
1468         return 0;
1469 }
1470
1471 static int cqspi_resume(struct device *dev)
1472 {
1473         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1474
1475         cqspi_controller_enable(cqspi, 1);
1476         return 0;
1477 }
1478
1479 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1480         .suspend = cqspi_suspend,
1481         .resume = cqspi_resume,
1482 };
1483
1484 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1485 #else
1486 #define CQSPI_DEV_PM_OPS        NULL
1487 #endif
1488
1489 static const struct cqspi_driver_platdata cdns_qspi = {
1490         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1491 };
1492
1493 static const struct cqspi_driver_platdata k2g_qspi = {
1494         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1495         .quirks = CQSPI_NEEDS_WR_DELAY,
1496 };
1497
1498 static const struct cqspi_driver_platdata am654_ospi = {
1499         .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
1500         .quirks = CQSPI_NEEDS_WR_DELAY,
1501 };
1502
1503 static const struct of_device_id cqspi_dt_ids[] = {
1504         {
1505                 .compatible = "cdns,qspi-nor",
1506                 .data = &cdns_qspi,
1507         },
1508         {
1509                 .compatible = "ti,k2g-qspi",
1510                 .data = &k2g_qspi,
1511         },
1512         {
1513                 .compatible = "ti,am654-ospi",
1514                 .data = &am654_ospi,
1515         },
1516         { /* end of table */ }
1517 };
1518
1519 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1520
1521 static struct platform_driver cqspi_platform_driver = {
1522         .probe = cqspi_probe,
1523         .remove = cqspi_remove,
1524         .driver = {
1525                 .name = CQSPI_NAME,
1526                 .pm = CQSPI_DEV_PM_OPS,
1527                 .of_match_table = cqspi_dt_ids,
1528         },
1529 };
1530
1531 module_platform_driver(cqspi_platform_driver);
1532
1533 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1534 MODULE_LICENSE("GPL v2");
1535 MODULE_ALIAS("platform:" CQSPI_NAME);
1536 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1537 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");