drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright © 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/onenand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/gpio.h>
  38
  39 #include <asm/mach/flash.h>
  40 #include <linux/platform_data/mtd-onenand-omap2.h>
  41
  42 #include <linux/omap-dma.h>
  43
  44 #define DRIVER_NAME "omap2-onenand"
  45
  46 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  47
  48 struct omap2_onenand {
  49         struct platform_device *pdev;
  50         int gpmc_cs;
  51         unsigned long phys_base;
  52         unsigned int mem_size;
  53         int gpio_irq;
  54         struct mtd_info mtd;
  55         struct onenand_chip onenand;
  56         struct completion irq_done;
  57         struct completion dma_done;
  58         int dma_channel;
  59         int freq;
  60         int (*setup)(void __iomem *base, int *freq_ptr);
  61         u8 flags;
  62 };
  63
  64 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  65 {
  66         struct omap2_onenand *c = data;
  67
  68         complete(&c->dma_done);
  69 }
  70
  71 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  72 {
  73         struct omap2_onenand *c = dev_id;
  74
  75         complete(&c->irq_done);
  76
  77         return IRQ_HANDLED;
  78 }
  79
  80 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  81 {
  82         return readw(c->onenand.base + reg);
  83 }
  84
  85 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  86                              int reg)
  87 {
  88         writew(value, c->onenand.base + reg);
  89 }
  90
  91 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
  92 {
  93         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
  94                msg, state, ctrl, intr);
  95 }
  96
  97 static void wait_warn(char *msg, int state, unsigned int ctrl,
  98                       unsigned int intr)
  99 {
 100         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 101                "intr 0x%04x\n", msg, state, ctrl, intr);
 102 }
 103
 104 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 105 {
 106         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 107         struct onenand_chip *this = mtd->priv;
 108         unsigned int intr = 0;
 109         unsigned int ctrl, ctrl_mask;
 110         unsigned long timeout;
 111         u32 syscfg;
 112
 113         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 114             state == FL_VERIFYING_ERASE) {
 115                 int i = 21;
 116                 unsigned int intr_flags = ONENAND_INT_MASTER;
 117
 118                 switch (state) {
 119                 case FL_RESETING:
 120                         intr_flags |= ONENAND_INT_RESET;
 121                         break;
 122                 case FL_PREPARING_ERASE:
 123                         intr_flags |= ONENAND_INT_ERASE;
 124                         break;
 125                 case FL_VERIFYING_ERASE:
 126                         i = 101;
 127                         break;
 128                 }
 129
 130                 while (--i) {
 131                         udelay(1);
 132                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 133                         if (intr & ONENAND_INT_MASTER)
 134                                 break;
 135                 }
 136                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 137                 if (ctrl & ONENAND_CTRL_ERROR) {
 138                         wait_err("controller error", state, ctrl, intr);
 139                         return -EIO;
 140                 }
 141                 if ((intr & intr_flags) == intr_flags)
 142                         return 0;
 143                 /* Continue in wait for interrupt branch */
 144         }
 145
 146         if (state != FL_READING) {
 147                 int result;
 148
 149                 /* Turn interrupts on */
 150                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 151                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 152                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 153                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 154                         if (c->flags & ONENAND_IN_OMAP34XX)
 155                                 /* Add a delay to let GPIO settle */
 156                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 157                 }
 158
 159                 reinit_completion(&c->irq_done);
 160                 if (c->gpio_irq) {
 161                         result = gpio_get_value(c->gpio_irq);
 162                         if (result == -1) {
 163                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 164                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 165                                 wait_err("gpio error", state, ctrl, intr);
 166                                 return -EIO;
 167                         }
 168                 } else
 169                         result = 0;
 170                 if (result == 0) {
 171                         int retry_cnt = 0;
 172 retry:
 173                         if (!wait_for_completion_io_timeout(&c->irq_done,
 174                                                 msecs_to_jiffies(20))) {
 175                                 /* Timeout after 20ms */
 176                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 177                                 if (ctrl & ONENAND_CTRL_ONGO &&
 178                                     !this->ongoing) {
 179                                         /*
 180                                          * The operation seems to be still going
 181                                          * so give it some more time.
 182                                          */
 183                                         retry_cnt += 1;
 184                                         if (retry_cnt < 3)
 185                                                 goto retry;
 186                                         intr = read_reg(c,
 187                                                         ONENAND_REG_INTERRUPT);
 188                                         wait_err("timeout", state, ctrl, intr);
 189                                         return -EIO;
 190                                 }
 191                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 192                                 if ((intr & ONENAND_INT_MASTER) == 0)
 193                                         wait_warn("timeout", state, ctrl, intr);
 194                         }
 195                 }
 196         } else {
 197                 int retry_cnt = 0;
 198
 199                 /* Turn interrupts off */
 200                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 201                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 202                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 203
 204                 timeout = jiffies + msecs_to_jiffies(20);
 205                 while (1) {
 206                         if (time_before(jiffies, timeout)) {
 207                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 208                                 if (intr & ONENAND_INT_MASTER)
 209                                         break;
 210                         } else {
 211                                 /* Timeout after 20ms */
 212                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 213                                 if (ctrl & ONENAND_CTRL_ONGO) {
 214                                         /*
 215                                          * The operation seems to be still going
 216                                          * so give it some more time.
 217                                          */
 218                                         retry_cnt += 1;
 219                                         if (retry_cnt < 3) {
 220                                                 timeout = jiffies +
 221                                                           msecs_to_jiffies(20);
 222                                                 continue;
 223                                         }
 224                                 }
 225                                 break;
 226                         }
 227                 }
 228         }
 229
 230         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 231         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 232
 233         if (intr & ONENAND_INT_READ) {
 234                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 235
 236                 if (ecc) {
 237                         unsigned int addr1, addr8;
 238
 239                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 240                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 241                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 242                                 printk(KERN_ERR "onenand_wait: ECC error = "
 243                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 244                                        ecc, addr1, addr8);
 245                                 mtd->ecc_stats.failed++;
 246                                 return -EBADMSG;
 247                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 248                                 printk(KERN_NOTICE "onenand_wait: correctable "
 249                                        "ECC error = 0x%04x, addr1 %#x, "
 250                                        "addr8 %#x\n", ecc, addr1, addr8);
 251                                 mtd->ecc_stats.corrected++;
 252                         }
 253                 }
 254         } else if (state == FL_READING) {
 255                 wait_err("timeout", state, ctrl, intr);
 256                 return -EIO;
 257         }
 258
 259         if (ctrl & ONENAND_CTRL_ERROR) {
 260                 wait_err("controller error", state, ctrl, intr);
 261                 if (ctrl & ONENAND_CTRL_LOCK)
 262                         printk(KERN_ERR "onenand_wait: "
 263                                         "Device is write protected!!!\n");
 264                 return -EIO;
 265         }
 266
 267         ctrl_mask = 0xFE9F;
 268         if (this->ongoing)
 269                 ctrl_mask &= ~0x8000;
 270
 271         if (ctrl & ctrl_mask)
 272                 wait_warn("unexpected controller status", state, ctrl, intr);
 273
 274         return 0;
 275 }
 276
 277 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 278 {
 279         struct onenand_chip *this = mtd->priv;
 280
 281         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 282                 if (area == ONENAND_DATARAM)
 283                         return this->writesize;
 284                 if (area == ONENAND_SPARERAM)
 285                         return mtd->oobsize;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 292                                              dma_addr_t src, dma_addr_t dst,
 293                                              size_t count)
 294 {
 295         int data_type = __ffs((src | dst | count));
 296
 297         if (data_type > OMAP_DMA_DATA_TYPE_S32)
 298                 data_type = OMAP_DMA_DATA_TYPE_S32;
 299
 300         omap_set_dma_transfer_params(c->dma_channel, data_type,
 301                                      count / BIT(data_type), 1, 0, 0, 0);
 302         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 303                                 src, 0, 0);
 304         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 305                                  dst, 0, 0);
 306
 307         reinit_completion(&c->dma_done);
 308         omap_start_dma(c->dma_channel);
 309         if (!wait_for_completion_io_timeout(&c->dma_done,
 310                                             msecs_to_jiffies(20))) {
 311                 omap_stop_dma(c->dma_channel);
 312                 return -ETIMEDOUT;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 319                                         unsigned char *buffer, int offset,
 320                                         size_t count)
 321 {
 322         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 323         struct onenand_chip *this = mtd->priv;
 324         dma_addr_t dma_src, dma_dst;
 325         int bram_offset;
 326         void *buf = (void *)buffer;
 327         size_t xtra;
 328         int ret;
 329
 330         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 331         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 332                 goto out_copy;
 333
 334         /* panic_write() may be in an interrupt context */
 335         if (in_interrupt() || oops_in_progress)
 336                 goto out_copy;
 337
 338         if (buf >= high_memory) {
 339                 struct page *p1;
 340
 341                 if (((size_t)buf & PAGE_MASK) !=
 342                     ((size_t)(buf + count - 1) & PAGE_MASK))
 343                         goto out_copy;
 344                 p1 = vmalloc_to_page(buf);
 345                 if (!p1)
 346                         goto out_copy;
 347                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 348         }
 349
 350         xtra = count & 3;
 351         if (xtra) {
 352                 count -= xtra;
 353                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 354         }
 355
 356         dma_src = c->phys_base + bram_offset;
 357         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 358         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 359                 dev_err(&c->pdev->dev,
 360                         "Couldn't DMA map a %d byte buffer\n",
 361                         count);
 362                 goto out_copy;
 363         }
 364
 365         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 366         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 367
 368         if (ret) {
 369                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 370                 goto out_copy;
 371         }
 372
 373         return 0;
 374
 375 out_copy:
 376         memcpy(buf, this->base + bram_offset, count);
 377         return 0;
 378 }
 379
 380 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 381                                          const unsigned char *buffer,
 382                                          int offset, size_t count)
 383 {
 384         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 385         struct onenand_chip *this = mtd->priv;
 386         dma_addr_t dma_src, dma_dst;
 387         int bram_offset;
 388         void *buf = (void *)buffer;
 389         int ret;
 390
 391         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 392         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 393                 goto out_copy;
 394
 395         /* panic_write() may be in an interrupt context */
 396         if (in_interrupt() || oops_in_progress)
 397                 goto out_copy;
 398
 399         if (buf >= high_memory) {
 400                 struct page *p1;
 401
 402                 if (((size_t)buf & PAGE_MASK) !=
 403                     ((size_t)(buf + count - 1) & PAGE_MASK))
 404                         goto out_copy;
 405                 p1 = vmalloc_to_page(buf);
 406                 if (!p1)
 407                         goto out_copy;
 408                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 409         }
 410
 411         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 412         dma_dst = c->phys_base + bram_offset;
 413         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 414                 dev_err(&c->pdev->dev,
 415                         "Couldn't DMA map a %d byte buffer\n",
 416                         count);
 417                 return -1;
 418         }
 419
 420         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 421         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 422
 423         if (ret) {
 424                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 425                 goto out_copy;
 426         }
 427
 428         return 0;
 429
 430 out_copy:
 431         memcpy(this->base + bram_offset, buf, count);
 432         return 0;
 433 }
 434
 435 static struct platform_driver omap2_onenand_driver;
 436
 437 static void omap2_onenand_shutdown(struct platform_device *pdev)
 438 {
 439         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 440
 441         /* With certain content in the buffer RAM, the OMAP boot ROM code
 442          * can recognize the flash chip incorrectly. Zero it out before
 443          * soft reset.
 444          */
 445         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 446 }
 447
 448 static int omap2_onenand_probe(struct platform_device *pdev)
 449 {
 450         struct omap_onenand_platform_data *pdata;
 451         struct omap2_onenand *c;
 452         struct onenand_chip *this;
 453         int r;
 454         struct resource *res;
 455
 456         pdata = dev_get_platdata(&pdev->dev);
 457         if (pdata == NULL) {
 458                 dev_err(&pdev->dev, "platform data missing\n");
 459                 return -ENODEV;
 460         }
 461
 462         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 463         if (!c)
 464                 return -ENOMEM;
 465
 466         init_completion(&c->irq_done);
 467         init_completion(&c->dma_done);
 468         c->flags = pdata->flags;
 469         c->gpmc_cs = pdata->cs;
 470         c->gpio_irq = pdata->gpio_irq;
 471         c->dma_channel = pdata->dma_channel;
 472         if (c->dma_channel < 0) {
 473                 /* if -1, don't use DMA */
 474                 c->gpio_irq = 0;
 475         }
 476
 477         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 478         if (res == NULL) {
 479                 r = -EINVAL;
 480                 dev_err(&pdev->dev, "error getting memory resource\n");
 481                 goto err_kfree;
 482         }
 483
 484         c->phys_base = res->start;
 485         c->mem_size = resource_size(res);
 486
 487         if (request_mem_region(c->phys_base, c->mem_size,
 488                                pdev->dev.driver->name) == NULL) {
 489                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 490                                                 c->phys_base, c->mem_size);
 491                 r = -EBUSY;
 492                 goto err_kfree;
 493         }
 494         c->onenand.base = ioremap(c->phys_base, c->mem_size);
 495         if (c->onenand.base == NULL) {
 496                 r = -ENOMEM;
 497                 goto err_release_mem_region;
 498         }
 499
 500         if (pdata->onenand_setup != NULL) {
 501                 r = pdata->onenand_setup(c->onenand.base, &c->freq);
 502                 if (r < 0) {
 503                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 504                                 "%d\n", r);
 505                         goto err_iounmap;
 506                 }
 507                 c->setup = pdata->onenand_setup;
 508         }
 509
 510         if (c->gpio_irq) {
 511                 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
 512                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 513                                 "OneNAND\n", c->gpio_irq);
 514                         goto err_iounmap;
 515         }
 516         gpio_direction_input(c->gpio_irq);
 517
 518         if ((r = request_irq(gpio_to_irq(c->gpio_irq),
 519                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 520                              pdev->dev.driver->name, c)) < 0)
 521                 goto err_release_gpio;
 522         }
 523
 524         if (c->dma_channel >= 0) {
 525                 r = omap_request_dma(0, pdev->dev.driver->name,
 526                                      omap2_onenand_dma_cb, (void *) c,
 527                                      &c->dma_channel);
 528                 if (r == 0) {
 529                         omap_set_dma_write_mode(c->dma_channel,
 530                                                 OMAP_DMA_WRITE_NON_POSTED);
 531                         omap_set_dma_src_data_pack(c->dma_channel, 1);
 532                         omap_set_dma_src_burst_mode(c->dma_channel,
 533                                                     OMAP_DMA_DATA_BURST_8);
 534                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
 535                         omap_set_dma_dest_burst_mode(c->dma_channel,
 536                                                      OMAP_DMA_DATA_BURST_8);
 537                 } else {
 538                         dev_info(&pdev->dev,
 539                                  "failed to allocate DMA for OneNAND, "
 540                                  "using PIO instead\n");
 541                         c->dma_channel = -1;
 542                 }
 543         }
 544
 545         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 546                  "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
 547                  c->onenand.base, c->freq);
 548
 549         c->pdev = pdev;
 550         c->mtd.priv = &c->onenand;
 551
 552         c->mtd.dev.parent = &pdev->dev;
 553         mtd_set_of_node(&c->mtd, pdata->of_node);
 554
 555         this = &c->onenand;
 556         if (c->dma_channel >= 0) {
 557                 this->wait = omap2_onenand_wait;
 558                 this->read_bufferram = omap2_onenand_read_bufferram;
 559                 this->write_bufferram = omap2_onenand_write_bufferram;
 560         }
 561
 562         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 563                 goto err_release_dma;
 564
 565         r = mtd_device_register(&c->mtd, NULL, 0);
 566         if (r)
 567                 goto err_release_onenand;
 568
 569         platform_set_drvdata(pdev, c);
 570
 571         return 0;
 572
 573 err_release_onenand:
 574         onenand_release(&c->mtd);
 575 err_release_dma:
 576         if (c->dma_channel != -1)
 577                 omap_free_dma(c->dma_channel);
 578         if (c->gpio_irq)
 579                 free_irq(gpio_to_irq(c->gpio_irq), c);
 580 err_release_gpio:
 581         if (c->gpio_irq)
 582                 gpio_free(c->gpio_irq);
 583 err_iounmap:
 584         iounmap(c->onenand.base);
 585 err_release_mem_region:
 586         release_mem_region(c->phys_base, c->mem_size);
 587 err_kfree:
 588         kfree(c);
 589
 590         return r;
 591 }
 592
 593 static int omap2_onenand_remove(struct platform_device *pdev)
 594 {
 595         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 596
 597         onenand_release(&c->mtd);
 598         if (c->dma_channel != -1)
 599                 omap_free_dma(c->dma_channel);
 600         omap2_onenand_shutdown(pdev);
 601         if (c->gpio_irq) {
 602                 free_irq(gpio_to_irq(c->gpio_irq), c);
 603                 gpio_free(c->gpio_irq);
 604         }
 605         iounmap(c->onenand.base);
 606         release_mem_region(c->phys_base, c->mem_size);
 607         kfree(c);
 608
 609         return 0;
 610 }
 611
 612 static struct platform_driver omap2_onenand_driver = {
 613         .probe          = omap2_onenand_probe,
 614         .remove         = omap2_onenand_remove,
 615         .shutdown       = omap2_onenand_shutdown,
 616         .driver         = {
 617                 .name   = DRIVER_NAME,
 618         },
 619 };
 620
 621 module_platform_driver(omap2_onenand_driver);
 622
 623 MODULE_ALIAS("platform:" DRIVER_NAME);
 624 MODULE_LICENSE("GPL");
 625 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 626 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");