1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
6 * Peter Pan <peterpandong@micron.com>
7 * Boris Brezillon <boris.brezillon@bootlin.com>
10 #define pr_fmt(fmt) "spi-nand: " fmt
12 #include <linux/device.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/mtd/spinand.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
22 static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
23 const struct nand_page_io_req *req,
26 struct nand_device *nand = spinand_to_nand(spinand);
29 if (nand->memorg.planes_per_lun < 2)
32 /* The plane number is passed in MSB just above the column address */
33 shift = fls(nand->memorg.pagesize);
34 *column |= req->pos.plane << shift;
37 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
39 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
43 ret = spi_mem_exec_op(spinand->spimem, &op);
47 *val = *spinand->scratchbuf;
51 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
53 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
56 *spinand->scratchbuf = val;
57 return spi_mem_exec_op(spinand->spimem, &op);
60 static int spinand_read_status(struct spinand_device *spinand, u8 *status)
62 return spinand_read_reg_op(spinand, REG_STATUS, status);
65 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg)
67 struct nand_device *nand = spinand_to_nand(spinand);
69 if (WARN_ON(spinand->cur_target < 0 ||
70 spinand->cur_target >= nand->memorg.ntargets))
73 *cfg = spinand->cfg_cache[spinand->cur_target];
77 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg)
79 struct nand_device *nand = spinand_to_nand(spinand);
82 if (WARN_ON(spinand->cur_target < 0 ||
83 spinand->cur_target >= nand->memorg.ntargets))
86 if (spinand->cfg_cache[spinand->cur_target] == cfg)
89 ret = spinand_write_reg_op(spinand, REG_CFG, cfg);
93 spinand->cfg_cache[spinand->cur_target] = cfg;
98 * spinand_upd_cfg() - Update the configuration register
99 * @spinand: the spinand device
100 * @mask: the mask encoding the bits to update in the config reg
101 * @val: the new value to apply
103 * Update the configuration register.
105 * Return: 0 on success, a negative error code otherwise.
107 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val)
112 ret = spinand_get_cfg(spinand, &cfg);
119 return spinand_set_cfg(spinand, cfg);
123 * spinand_select_target() - Select a specific NAND target/die
124 * @spinand: the spinand device
125 * @target: the target/die to select
127 * Select a new target/die. If chip only has one die, this function is a NOOP.
129 * Return: 0 on success, a negative error code otherwise.
131 int spinand_select_target(struct spinand_device *spinand, unsigned int target)
133 struct nand_device *nand = spinand_to_nand(spinand);
136 if (WARN_ON(target >= nand->memorg.ntargets))
139 if (spinand->cur_target == target)
142 if (nand->memorg.ntargets == 1) {
143 spinand->cur_target = target;
147 ret = spinand->select_target(spinand, target);
151 spinand->cur_target = target;
155 static int spinand_init_cfg_cache(struct spinand_device *spinand)
157 struct nand_device *nand = spinand_to_nand(spinand);
158 struct device *dev = &spinand->spimem->spi->dev;
162 spinand->cfg_cache = devm_kcalloc(dev,
163 nand->memorg.ntargets,
164 sizeof(*spinand->cfg_cache),
166 if (!spinand->cfg_cache)
169 for (target = 0; target < nand->memorg.ntargets; target++) {
170 ret = spinand_select_target(spinand, target);
175 * We use spinand_read_reg_op() instead of spinand_get_cfg()
176 * here to bypass the config cache.
178 ret = spinand_read_reg_op(spinand, REG_CFG,
179 &spinand->cfg_cache[target]);
187 static int spinand_init_quad_enable(struct spinand_device *spinand)
191 if (!(spinand->flags & SPINAND_HAS_QE_BIT))
194 if (spinand->op_templates.read_cache->data.buswidth == 4 ||
195 spinand->op_templates.write_cache->data.buswidth == 4 ||
196 spinand->op_templates.update_cache->data.buswidth == 4)
199 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
200 enable ? CFG_QUAD_ENABLE : 0);
203 static int spinand_ecc_enable(struct spinand_device *spinand,
206 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE,
207 enable ? CFG_ECC_ENABLE : 0);
210 static int spinand_write_enable_op(struct spinand_device *spinand)
212 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
214 return spi_mem_exec_op(spinand->spimem, &op);
217 static int spinand_load_page_op(struct spinand_device *spinand,
218 const struct nand_page_io_req *req)
220 struct nand_device *nand = spinand_to_nand(spinand);
221 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
222 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
224 return spi_mem_exec_op(spinand->spimem, &op);
227 static int spinand_read_from_cache_op(struct spinand_device *spinand,
228 const struct nand_page_io_req *req)
230 struct spi_mem_op op = *spinand->op_templates.read_cache;
231 struct nand_device *nand = spinand_to_nand(spinand);
232 struct mtd_info *mtd = nanddev_to_mtd(nand);
233 struct nand_page_io_req adjreq = *req;
234 unsigned int nbytes = 0;
240 adjreq.datalen = nanddev_page_size(nand);
242 adjreq.databuf.in = spinand->databuf;
243 buf = spinand->databuf;
244 nbytes = adjreq.datalen;
248 adjreq.ooblen = nanddev_per_page_oobsize(nand);
250 adjreq.oobbuf.in = spinand->oobbuf;
251 nbytes += nanddev_per_page_oobsize(nand);
253 buf = spinand->oobbuf;
254 column = nanddev_page_size(nand);
258 spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
259 op.addr.val = column;
262 * Some controllers are limited in term of max RX data size. In this
263 * case, just repeat the READ_CACHE operation after updating the
267 op.data.buf.in = buf;
268 op.data.nbytes = nbytes;
269 ret = spi_mem_adjust_op_size(spinand->spimem, &op);
273 ret = spi_mem_exec_op(spinand->spimem, &op);
277 buf += op.data.nbytes;
278 nbytes -= op.data.nbytes;
279 op.addr.val += op.data.nbytes;
283 memcpy(req->databuf.in, spinand->databuf + req->dataoffs,
287 if (req->mode == MTD_OPS_AUTO_OOB)
288 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in,
293 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs,
300 static int spinand_write_to_cache_op(struct spinand_device *spinand,
301 const struct nand_page_io_req *req)
303 struct spi_mem_op op = *spinand->op_templates.write_cache;
304 struct nand_device *nand = spinand_to_nand(spinand);
305 struct mtd_info *mtd = nanddev_to_mtd(nand);
306 struct nand_page_io_req adjreq = *req;
307 unsigned int nbytes = 0;
312 memset(spinand->databuf, 0xff,
313 nanddev_page_size(nand) +
314 nanddev_per_page_oobsize(nand));
317 memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
320 adjreq.datalen = nanddev_page_size(nand);
321 adjreq.databuf.out = spinand->databuf;
322 nbytes = adjreq.datalen;
323 buf = spinand->databuf;
327 if (req->mode == MTD_OPS_AUTO_OOB)
328 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out,
333 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
336 adjreq.ooblen = nanddev_per_page_oobsize(nand);
338 nbytes += nanddev_per_page_oobsize(nand);
340 buf = spinand->oobbuf;
341 column = nanddev_page_size(nand);
345 spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
347 op = *spinand->op_templates.write_cache;
348 op.addr.val = column;
351 * Some controllers are limited in term of max TX data size. In this
352 * case, split the operation into one LOAD CACHE and one or more
356 op.data.buf.out = buf;
357 op.data.nbytes = nbytes;
359 ret = spi_mem_adjust_op_size(spinand->spimem, &op);
363 ret = spi_mem_exec_op(spinand->spimem, &op);
367 buf += op.data.nbytes;
368 nbytes -= op.data.nbytes;
369 op.addr.val += op.data.nbytes;
372 * We need to use the RANDOM LOAD CACHE operation if there's
373 * more than one iteration, because the LOAD operation resets
377 column = op.addr.val;
378 op = *spinand->op_templates.update_cache;
379 op.addr.val = column;
386 static int spinand_program_op(struct spinand_device *spinand,
387 const struct nand_page_io_req *req)
389 struct nand_device *nand = spinand_to_nand(spinand);
390 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
391 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
393 return spi_mem_exec_op(spinand->spimem, &op);
396 static int spinand_erase_op(struct spinand_device *spinand,
397 const struct nand_pos *pos)
399 struct nand_device *nand = spinand_to_nand(spinand);
400 unsigned int row = nanddev_pos_to_row(nand, pos);
401 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
403 return spi_mem_exec_op(spinand->spimem, &op);
406 static int spinand_wait(struct spinand_device *spinand, u8 *s)
408 unsigned long timeo = jiffies + msecs_to_jiffies(400);
413 ret = spinand_read_status(spinand, &status);
417 if (!(status & STATUS_BUSY))
419 } while (time_before(jiffies, timeo));
422 * Extra read, just in case the STATUS_READY bit has changed
423 * since our last check
425 ret = spinand_read_status(spinand, &status);
433 return status & STATUS_BUSY ? -ETIMEDOUT : 0;
436 static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
438 struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
442 ret = spi_mem_exec_op(spinand->spimem, &op);
444 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
449 static int spinand_reset_op(struct spinand_device *spinand)
451 struct spi_mem_op op = SPINAND_RESET_OP;
454 ret = spi_mem_exec_op(spinand->spimem, &op);
458 return spinand_wait(spinand, NULL);
461 static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
463 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
466 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
468 struct nand_device *nand = spinand_to_nand(spinand);
470 if (spinand->eccinfo.get_status)
471 return spinand->eccinfo.get_status(spinand, status);
473 switch (status & STATUS_ECC_MASK) {
474 case STATUS_ECC_NO_BITFLIPS:
477 case STATUS_ECC_HAS_BITFLIPS:
479 * We have no way to know exactly how many bitflips have been
480 * fixed, so let's return the maximum possible value so that
481 * wear-leveling layers move the data immediately.
483 return nand->eccreq.strength;
485 case STATUS_ECC_UNCOR_ERROR:
495 static int spinand_read_page(struct spinand_device *spinand,
496 const struct nand_page_io_req *req,
502 ret = spinand_load_page_op(spinand, req);
506 ret = spinand_wait(spinand, &status);
510 ret = spinand_read_from_cache_op(spinand, req);
517 return spinand_check_ecc_status(spinand, status);
520 static int spinand_write_page(struct spinand_device *spinand,
521 const struct nand_page_io_req *req)
526 ret = spinand_write_enable_op(spinand);
530 ret = spinand_write_to_cache_op(spinand, req);
534 ret = spinand_program_op(spinand, req);
538 ret = spinand_wait(spinand, &status);
539 if (!ret && (status & STATUS_PROG_FAILED))
545 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
546 struct mtd_oob_ops *ops)
548 struct spinand_device *spinand = mtd_to_spinand(mtd);
549 struct nand_device *nand = mtd_to_nanddev(mtd);
550 unsigned int max_bitflips = 0;
551 struct nand_io_iter iter;
552 bool enable_ecc = false;
553 bool ecc_failed = false;
556 if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
559 mutex_lock(&spinand->lock);
561 nanddev_io_for_each_page(nand, from, ops, &iter) {
562 ret = spinand_select_target(spinand, iter.req.pos.target);
566 ret = spinand_ecc_enable(spinand, enable_ecc);
570 ret = spinand_read_page(spinand, &iter.req, enable_ecc);
571 if (ret < 0 && ret != -EBADMSG)
574 if (ret == -EBADMSG) {
576 mtd->ecc_stats.failed++;
579 mtd->ecc_stats.corrected += ret;
580 max_bitflips = max_t(unsigned int, max_bitflips, ret);
583 ops->retlen += iter.req.datalen;
584 ops->oobretlen += iter.req.ooblen;
587 mutex_unlock(&spinand->lock);
589 if (ecc_failed && !ret)
592 return ret ? ret : max_bitflips;
595 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
596 struct mtd_oob_ops *ops)
598 struct spinand_device *spinand = mtd_to_spinand(mtd);
599 struct nand_device *nand = mtd_to_nanddev(mtd);
600 struct nand_io_iter iter;
601 bool enable_ecc = false;
604 if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
607 mutex_lock(&spinand->lock);
609 nanddev_io_for_each_page(nand, to, ops, &iter) {
610 ret = spinand_select_target(spinand, iter.req.pos.target);
614 ret = spinand_ecc_enable(spinand, enable_ecc);
618 ret = spinand_write_page(spinand, &iter.req);
622 ops->retlen += iter.req.datalen;
623 ops->oobretlen += iter.req.ooblen;
626 mutex_unlock(&spinand->lock);
631 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
633 struct spinand_device *spinand = nand_to_spinand(nand);
634 struct nand_page_io_req req = {
638 .oobbuf.in = spinand->oobbuf,
642 memset(spinand->oobbuf, 0, 2);
643 spinand_select_target(spinand, pos->target);
644 spinand_read_page(spinand, &req, false);
645 if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
651 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
653 struct nand_device *nand = mtd_to_nanddev(mtd);
654 struct spinand_device *spinand = nand_to_spinand(nand);
658 nanddev_offs_to_pos(nand, offs, &pos);
659 mutex_lock(&spinand->lock);
660 ret = nanddev_isbad(nand, &pos);
661 mutex_unlock(&spinand->lock);
666 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
668 struct spinand_device *spinand = nand_to_spinand(nand);
669 struct nand_page_io_req req = {
673 .oobbuf.out = spinand->oobbuf,
677 /* Erase block before marking it bad. */
678 ret = spinand_select_target(spinand, pos->target);
682 ret = spinand_write_enable_op(spinand);
686 spinand_erase_op(spinand, pos);
688 memset(spinand->oobbuf, 0, 2);
689 return spinand_write_page(spinand, &req);
692 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
694 struct nand_device *nand = mtd_to_nanddev(mtd);
695 struct spinand_device *spinand = nand_to_spinand(nand);
699 nanddev_offs_to_pos(nand, offs, &pos);
700 mutex_lock(&spinand->lock);
701 ret = nanddev_markbad(nand, &pos);
702 mutex_unlock(&spinand->lock);
707 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos)
709 struct spinand_device *spinand = nand_to_spinand(nand);
713 ret = spinand_select_target(spinand, pos->target);
717 ret = spinand_write_enable_op(spinand);
721 ret = spinand_erase_op(spinand, pos);
725 ret = spinand_wait(spinand, &status);
726 if (!ret && (status & STATUS_ERASE_FAILED))
732 static int spinand_mtd_erase(struct mtd_info *mtd,
733 struct erase_info *einfo)
735 struct spinand_device *spinand = mtd_to_spinand(mtd);
738 mutex_lock(&spinand->lock);
739 ret = nanddev_mtd_erase(mtd, einfo);
740 mutex_unlock(&spinand->lock);
745 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
747 struct spinand_device *spinand = mtd_to_spinand(mtd);
748 struct nand_device *nand = mtd_to_nanddev(mtd);
752 nanddev_offs_to_pos(nand, offs, &pos);
753 mutex_lock(&spinand->lock);
754 ret = nanddev_isreserved(nand, &pos);
755 mutex_unlock(&spinand->lock);
760 static const struct nand_ops spinand_ops = {
761 .erase = spinand_erase,
762 .markbad = spinand_markbad,
763 .isbad = spinand_isbad,
766 static const struct spinand_manufacturer *spinand_manufacturers[] = {
767 &gigadevice_spinand_manufacturer,
768 ¯onix_spinand_manufacturer,
769 µn_spinand_manufacturer,
770 &toshiba_spinand_manufacturer,
771 &winbond_spinand_manufacturer,
774 static int spinand_manufacturer_detect(struct spinand_device *spinand)
779 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
780 ret = spinand_manufacturers[i]->ops->detect(spinand);
782 spinand->manufacturer = spinand_manufacturers[i];
784 } else if (ret < 0) {
792 static int spinand_manufacturer_init(struct spinand_device *spinand)
794 if (spinand->manufacturer->ops->init)
795 return spinand->manufacturer->ops->init(spinand);
800 static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
802 /* Release manufacturer private data */
803 if (spinand->manufacturer->ops->cleanup)
804 return spinand->manufacturer->ops->cleanup(spinand);
807 static const struct spi_mem_op *
808 spinand_select_op_variant(struct spinand_device *spinand,
809 const struct spinand_op_variants *variants)
811 struct nand_device *nand = spinand_to_nand(spinand);
814 for (i = 0; i < variants->nops; i++) {
815 struct spi_mem_op op = variants->ops[i];
819 nbytes = nanddev_per_page_oobsize(nand) +
820 nanddev_page_size(nand);
823 op.data.nbytes = nbytes;
824 ret = spi_mem_adjust_op_size(spinand->spimem, &op);
828 if (!spi_mem_supports_op(spinand->spimem, &op))
831 nbytes -= op.data.nbytes;
835 return &variants->ops[i];
842 * spinand_match_and_init() - Try to find a match between a device ID and an
843 * entry in a spinand_info table
844 * @spinand: SPI NAND object
845 * @table: SPI NAND device description table
846 * @table_size: size of the device description table
848 * Should be used by SPI NAND manufacturer drivers when they want to find a
849 * match between a device ID retrieved through the READ_ID command and an
850 * entry in the SPI NAND description table. If a match is found, the spinand
851 * object will be initialized with information provided by the matching
852 * spinand_info entry.
854 * Return: 0 on success, a negative error code otherwise.
856 int spinand_match_and_init(struct spinand_device *spinand,
857 const struct spinand_info *table,
858 unsigned int table_size, u8 devid)
860 struct nand_device *nand = spinand_to_nand(spinand);
863 for (i = 0; i < table_size; i++) {
864 const struct spinand_info *info = &table[i];
865 const struct spi_mem_op *op;
867 if (devid != info->devid)
870 nand->memorg = table[i].memorg;
871 nand->eccreq = table[i].eccreq;
872 spinand->eccinfo = table[i].eccinfo;
873 spinand->flags = table[i].flags;
874 spinand->select_target = table[i].select_target;
876 op = spinand_select_op_variant(spinand,
877 info->op_variants.read_cache);
881 spinand->op_templates.read_cache = op;
883 op = spinand_select_op_variant(spinand,
884 info->op_variants.write_cache);
888 spinand->op_templates.write_cache = op;
890 op = spinand_select_op_variant(spinand,
891 info->op_variants.update_cache);
892 spinand->op_templates.update_cache = op;
900 static int spinand_detect(struct spinand_device *spinand)
902 struct device *dev = &spinand->spimem->spi->dev;
903 struct nand_device *nand = spinand_to_nand(spinand);
906 ret = spinand_reset_op(spinand);
910 ret = spinand_read_id_op(spinand, spinand->id.data);
914 spinand->id.len = SPINAND_MAX_ID_LEN;
916 ret = spinand_manufacturer_detect(spinand);
918 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
923 if (nand->memorg.ntargets > 1 && !spinand->select_target) {
925 "SPI NANDs with more than one die must implement ->select_target()\n");
929 dev_info(&spinand->spimem->spi->dev,
930 "%s SPI NAND was found.\n", spinand->manufacturer->name);
931 dev_info(&spinand->spimem->spi->dev,
932 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
933 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
934 nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
939 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
940 struct mtd_oob_region *region)
945 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
946 struct mtd_oob_region *region)
951 /* Reserve 2 bytes for the BBM. */
958 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
959 .ecc = spinand_noecc_ooblayout_ecc,
960 .free = spinand_noecc_ooblayout_free,
963 static int spinand_init(struct spinand_device *spinand)
965 struct device *dev = &spinand->spimem->spi->dev;
966 struct mtd_info *mtd = spinand_to_mtd(spinand);
967 struct nand_device *nand = mtd_to_nanddev(mtd);
971 * We need a scratch buffer because the spi_mem interface requires that
972 * buf passed in spi_mem_op->data.buf be DMA-able.
974 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
975 if (!spinand->scratchbuf)
978 ret = spinand_detect(spinand);
983 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
984 * may use this buffer for DMA access.
985 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
987 spinand->databuf = kzalloc(nanddev_page_size(nand) +
988 nanddev_per_page_oobsize(nand),
990 if (!spinand->databuf) {
995 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
997 ret = spinand_init_cfg_cache(spinand);
1001 ret = spinand_init_quad_enable(spinand);
1005 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0);
1009 ret = spinand_manufacturer_init(spinand);
1012 "Failed to initialize the SPI NAND chip (err = %d)\n",
1017 /* After power up, all blocks are locked, so unlock them here. */
1018 for (i = 0; i < nand->memorg.ntargets; i++) {
1019 ret = spinand_select_target(spinand, i);
1023 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
1028 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
1030 goto err_manuf_cleanup;
1033 * Right now, we don't support ECC, so let the whole oob
1034 * area is available for user.
1036 mtd->_read_oob = spinand_mtd_read;
1037 mtd->_write_oob = spinand_mtd_write;
1038 mtd->_block_isbad = spinand_mtd_block_isbad;
1039 mtd->_block_markbad = spinand_mtd_block_markbad;
1040 mtd->_block_isreserved = spinand_mtd_block_isreserved;
1041 mtd->_erase = spinand_mtd_erase;
1043 if (spinand->eccinfo.ooblayout)
1044 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
1046 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
1048 ret = mtd_ooblayout_count_freebytes(mtd);
1050 goto err_cleanup_nanddev;
1052 mtd->oobavail = ret;
1056 err_cleanup_nanddev:
1057 nanddev_cleanup(nand);
1060 spinand_manufacturer_cleanup(spinand);
1063 kfree(spinand->databuf);
1064 kfree(spinand->scratchbuf);
1068 static void spinand_cleanup(struct spinand_device *spinand)
1070 struct nand_device *nand = spinand_to_nand(spinand);
1072 nanddev_cleanup(nand);
1073 spinand_manufacturer_cleanup(spinand);
1074 kfree(spinand->databuf);
1075 kfree(spinand->scratchbuf);
1078 static int spinand_probe(struct spi_mem *mem)
1080 struct spinand_device *spinand;
1081 struct mtd_info *mtd;
1084 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
1089 spinand->spimem = mem;
1090 spi_mem_set_drvdata(mem, spinand);
1091 spinand_set_of_node(spinand, mem->spi->dev.of_node);
1092 mutex_init(&spinand->lock);
1093 mtd = spinand_to_mtd(spinand);
1094 mtd->dev.parent = &mem->spi->dev;
1096 ret = spinand_init(spinand);
1100 ret = mtd_device_register(mtd, NULL, 0);
1102 goto err_spinand_cleanup;
1106 err_spinand_cleanup:
1107 spinand_cleanup(spinand);
1112 static int spinand_remove(struct spi_mem *mem)
1114 struct spinand_device *spinand;
1115 struct mtd_info *mtd;
1118 spinand = spi_mem_get_drvdata(mem);
1119 mtd = spinand_to_mtd(spinand);
1121 ret = mtd_device_unregister(mtd);
1125 spinand_cleanup(spinand);
1130 static const struct spi_device_id spinand_ids[] = {
1131 { .name = "spi-nand" },
1136 static const struct of_device_id spinand_of_ids[] = {
1137 { .compatible = "spi-nand" },
1142 static struct spi_mem_driver spinand_drv = {
1144 .id_table = spinand_ids,
1147 .of_match_table = of_match_ptr(spinand_of_ids),
1150 .probe = spinand_probe,
1151 .remove = spinand_remove,
1153 module_spi_mem_driver(spinand_drv);
1155 MODULE_DESCRIPTION("SPI NAND framework");
1156 MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>");
1157 MODULE_LICENSE("GPL v2");