drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/errno.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/module.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/of_address.h>
  19 #include <linux/pinctrl/consumer.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 /* Bad block marker length */
  25 #define FMC2_BBM_LEN                    2
  26
  27 /* ECC step size */
  28 #define FMC2_ECC_STEP_SIZE              512
  29
  30 /* BCHDSRx registers length */
  31 #define FMC2_BCHDSRS_LEN                20
  32
  33 /* HECCR length */
  34 #define FMC2_HECCR_LEN                  4
  35
  36 /* Max requests done for a 8k nand page size */
  37 #define FMC2_MAX_SG                     16
  38
  39 /* Max chip enable */
  40 #define FMC2_MAX_CE                     2
  41
  42 /* Max ECC buffer length */
  43 #define FMC2_MAX_ECC_BUF_LEN            (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
  44
  45 #define FMC2_TIMEOUT_MS                 5000
  46
  47 /* Timings */
  48 #define FMC2_THIZ                       1
  49 #define FMC2_TIO                        8000
  50 #define FMC2_TSYNC                      3000
  51 #define FMC2_PCR_TIMING_MASK            0xf
  52 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  53
  54 /* FMC2 Controller Registers */
  55 #define FMC2_BCR1                       0x0
  56 #define FMC2_PCR                        0x80
  57 #define FMC2_SR                         0x84
  58 #define FMC2_PMEM                       0x88
  59 #define FMC2_PATT                       0x8c
  60 #define FMC2_HECCR                      0x94
  61 #define FMC2_ISR                        0x184
  62 #define FMC2_ICR                        0x188
  63 #define FMC2_CSQCR                      0x200
  64 #define FMC2_CSQCFGR1                   0x204
  65 #define FMC2_CSQCFGR2                   0x208
  66 #define FMC2_CSQCFGR3                   0x20c
  67 #define FMC2_CSQAR1                     0x210
  68 #define FMC2_CSQAR2                     0x214
  69 #define FMC2_CSQIER                     0x220
  70 #define FMC2_CSQISR                     0x224
  71 #define FMC2_CSQICR                     0x228
  72 #define FMC2_CSQEMSR                    0x230
  73 #define FMC2_BCHIER                     0x250
  74 #define FMC2_BCHISR                     0x254
  75 #define FMC2_BCHICR                     0x258
  76 #define FMC2_BCHPBR1                    0x260
  77 #define FMC2_BCHPBR2                    0x264
  78 #define FMC2_BCHPBR3                    0x268
  79 #define FMC2_BCHPBR4                    0x26c
  80 #define FMC2_BCHDSR0                    0x27c
  81 #define FMC2_BCHDSR1                    0x280
  82 #define FMC2_BCHDSR2                    0x284
  83 #define FMC2_BCHDSR3                    0x288
  84 #define FMC2_BCHDSR4                    0x28c
  85
  86 /* Register: FMC2_BCR1 */
  87 #define FMC2_BCR1_FMC2EN                BIT(31)
  88
  89 /* Register: FMC2_PCR */
  90 #define FMC2_PCR_PWAITEN                BIT(1)
  91 #define FMC2_PCR_PBKEN                  BIT(2)
  92 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  93 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  94 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  95 #define FMC2_PCR_ECCEN                  BIT(6)
  96 #define FMC2_PCR_ECCALG                 BIT(8)
  97 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  98 #define FMC2_PCR_TCLR_DEFAULT           0xf
  99 #define FMC2_PCR_TAR                    GENMASK(16, 13)
 100 #define FMC2_PCR_TAR_DEFAULT            0xf
 101 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
 102 #define FMC2_PCR_ECCSS_512              1
 103 #define FMC2_PCR_ECCSS_2048             3
 104 #define FMC2_PCR_BCHECC                 BIT(24)
 105 #define FMC2_PCR_WEN                    BIT(25)
 106
 107 /* Register: FMC2_SR */
 108 #define FMC2_SR_NWRF                    BIT(6)
 109
 110 /* Register: FMC2_PMEM */
 111 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
 112 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
 113 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
 114 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
 115 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
 116
 117 /* Register: FMC2_PATT */
 118 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
 119 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
 120 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
 121 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
 122 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
 123
 124 /* Register: FMC2_ISR */
 125 #define FMC2_ISR_IHLF                   BIT(1)
 126
 127 /* Register: FMC2_ICR */
 128 #define FMC2_ICR_CIHLF                  BIT(1)
 129
 130 /* Register: FMC2_CSQCR */
 131 #define FMC2_CSQCR_CSQSTART             BIT(0)
 132
 133 /* Register: FMC2_CSQCFGR1 */
 134 #define FMC2_CSQCFGR1_CMD2EN            BIT(1)
 135 #define FMC2_CSQCFGR1_DMADEN            BIT(2)
 136 #define FMC2_CSQCFGR1_ACYNBR            GENMASK(6, 4)
 137 #define FMC2_CSQCFGR1_CMD1              GENMASK(15, 8)
 138 #define FMC2_CSQCFGR1_CMD2              GENMASK(23, 16)
 139 #define FMC2_CSQCFGR1_CMD1T             BIT(24)
 140 #define FMC2_CSQCFGR1_CMD2T             BIT(25)
 141
 142 /* Register: FMC2_CSQCFGR2 */
 143 #define FMC2_CSQCFGR2_SQSDTEN           BIT(0)
 144 #define FMC2_CSQCFGR2_RCMD2EN           BIT(1)
 145 #define FMC2_CSQCFGR2_DMASEN            BIT(2)
 146 #define FMC2_CSQCFGR2_RCMD1             GENMASK(15, 8)
 147 #define FMC2_CSQCFGR2_RCMD2             GENMASK(23, 16)
 148 #define FMC2_CSQCFGR2_RCMD1T            BIT(24)
 149 #define FMC2_CSQCFGR2_RCMD2T            BIT(25)
 150
 151 /* Register: FMC2_CSQCFGR3 */
 152 #define FMC2_CSQCFGR3_SNBR              GENMASK(13, 8)
 153 #define FMC2_CSQCFGR3_AC1T              BIT(16)
 154 #define FMC2_CSQCFGR3_AC2T              BIT(17)
 155 #define FMC2_CSQCFGR3_AC3T              BIT(18)
 156 #define FMC2_CSQCFGR3_AC4T              BIT(19)
 157 #define FMC2_CSQCFGR3_AC5T              BIT(20)
 158 #define FMC2_CSQCFGR3_SDT               BIT(21)
 159 #define FMC2_CSQCFGR3_RAC1T             BIT(22)
 160 #define FMC2_CSQCFGR3_RAC2T             BIT(23)
 161
 162 /* Register: FMC2_CSQCAR1 */
 163 #define FMC2_CSQCAR1_ADDC1              GENMASK(7, 0)
 164 #define FMC2_CSQCAR1_ADDC2              GENMASK(15, 8)
 165 #define FMC2_CSQCAR1_ADDC3              GENMASK(23, 16)
 166 #define FMC2_CSQCAR1_ADDC4              GENMASK(31, 24)
 167
 168 /* Register: FMC2_CSQCAR2 */
 169 #define FMC2_CSQCAR2_ADDC5              GENMASK(7, 0)
 170 #define FMC2_CSQCAR2_NANDCEN            GENMASK(11, 10)
 171 #define FMC2_CSQCAR2_SAO                GENMASK(31, 16)
 172
 173 /* Register: FMC2_CSQIER */
 174 #define FMC2_CSQIER_TCIE                BIT(0)
 175
 176 /* Register: FMC2_CSQICR */
 177 #define FMC2_CSQICR_CLEAR_IRQ           GENMASK(4, 0)
 178
 179 /* Register: FMC2_CSQEMSR */
 180 #define FMC2_CSQEMSR_SEM                GENMASK(15, 0)
 181
 182 /* Register: FMC2_BCHIER */
 183 #define FMC2_BCHIER_DERIE               BIT(1)
 184 #define FMC2_BCHIER_EPBRIE              BIT(4)
 185
 186 /* Register: FMC2_BCHICR */
 187 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 188
 189 /* Register: FMC2_BCHDSR0 */
 190 #define FMC2_BCHDSR0_DUE                BIT(0)
 191 #define FMC2_BCHDSR0_DEF                BIT(1)
 192 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 193
 194 /* Register: FMC2_BCHDSR1 */
 195 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 196 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 197
 198 /* Register: FMC2_BCHDSR2 */
 199 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 200 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 201
 202 /* Register: FMC2_BCHDSR3 */
 203 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 204 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 205
 206 /* Register: FMC2_BCHDSR4 */
 207 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 208 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 209
 210 enum stm32_fmc2_ecc {
 211         FMC2_ECC_HAM = 1,
 212         FMC2_ECC_BCH4 = 4,
 213         FMC2_ECC_BCH8 = 8
 214 };
 215
 216 enum stm32_fmc2_irq_state {
 217         FMC2_IRQ_UNKNOWN = 0,
 218         FMC2_IRQ_BCH,
 219         FMC2_IRQ_SEQ
 220 };
 221
 222 struct stm32_fmc2_timings {
 223         u8 tclr;
 224         u8 tar;
 225         u8 thiz;
 226         u8 twait;
 227         u8 thold_mem;
 228         u8 tset_mem;
 229         u8 thold_att;
 230         u8 tset_att;
 231 };
 232
 233 struct stm32_fmc2_nand {
 234         struct nand_chip chip;
 235         struct gpio_desc *wp_gpio;
 236         struct stm32_fmc2_timings timings;
 237         int ncs;
 238         int cs_used[FMC2_MAX_CE];
 239 };
 240
 241 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 242 {
 243         return container_of(chip, struct stm32_fmc2_nand, chip);
 244 }
 245
 246 struct stm32_fmc2_nfc {
 247         struct nand_controller base;
 248         struct stm32_fmc2_nand nand;
 249         struct device *dev;
 250         struct device *cdev;
 251         struct regmap *regmap;
 252         void __iomem *data_base[FMC2_MAX_CE];
 253         void __iomem *cmd_base[FMC2_MAX_CE];
 254         void __iomem *addr_base[FMC2_MAX_CE];
 255         phys_addr_t io_phys_addr;
 256         phys_addr_t data_phys_addr[FMC2_MAX_CE];
 257         struct clk *clk;
 258         u8 irq_state;
 259
 260         struct dma_chan *dma_tx_ch;
 261         struct dma_chan *dma_rx_ch;
 262         struct dma_chan *dma_ecc_ch;
 263         struct sg_table dma_data_sg;
 264         struct sg_table dma_ecc_sg;
 265         u8 *ecc_buf;
 266         int dma_ecc_len;
 267         u32 tx_dma_max_burst;
 268         u32 rx_dma_max_burst;
 269
 270         struct completion complete;
 271         struct completion dma_data_complete;
 272         struct completion dma_ecc_complete;
 273
 274         u8 cs_assigned;
 275         int cs_sel;
 276 };
 277
 278 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
 279 {
 280         return container_of(base, struct stm32_fmc2_nfc, base);
 281 }
 282
 283 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 284 {
 285         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 286         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 287         struct stm32_fmc2_timings *timings = &nand->timings;
 288         u32 pmem, patt;
 289
 290         /* Set tclr/tar timings */
 291         regmap_update_bits(nfc->regmap, FMC2_PCR,
 292                            FMC2_PCR_TCLR | FMC2_PCR_TAR,
 293                            FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
 294                            FIELD_PREP(FMC2_PCR_TAR, timings->tar));
 295
 296         /* Set tset/twait/thold/thiz timings in common bank */
 297         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 298         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 299         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 300         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 301         regmap_write(nfc->regmap, FMC2_PMEM, pmem);
 302
 303         /* Set tset/twait/thold/thiz timings in attribut bank */
 304         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 305         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 306         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 307         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 308         regmap_write(nfc->regmap, FMC2_PATT, patt);
 309 }
 310
 311 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 312 {
 313         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 314         u32 pcr = 0, pcr_mask;
 315
 316         /* Configure ECC algorithm (default configuration is Hamming) */
 317         pcr_mask = FMC2_PCR_ECCALG;
 318         pcr_mask |= FMC2_PCR_BCHECC;
 319         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 320                 pcr |= FMC2_PCR_ECCALG;
 321                 pcr |= FMC2_PCR_BCHECC;
 322         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 323                 pcr |= FMC2_PCR_ECCALG;
 324         }
 325
 326         /* Set buswidth */
 327         pcr_mask |= FMC2_PCR_PWID;
 328         if (chip->options & NAND_BUSWIDTH_16)
 329                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 330
 331         /* Set ECC sector size */
 332         pcr_mask |= FMC2_PCR_ECCSS;
 333         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 334
 335         regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
 336 }
 337
 338 static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
 339 {
 340         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 341         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 342         struct dma_slave_config dma_cfg;
 343         int ret;
 344
 345         if (nand->cs_used[chipnr] == nfc->cs_sel)
 346                 return 0;
 347
 348         nfc->cs_sel = nand->cs_used[chipnr];
 349         stm32_fmc2_nfc_setup(chip);
 350         stm32_fmc2_nfc_timings_init(chip);
 351
 352         if (nfc->dma_tx_ch) {
 353                 memset(&dma_cfg, 0, sizeof(dma_cfg));
 354                 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
 355                 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 356                 dma_cfg.dst_maxburst = nfc->tx_dma_max_burst /
 357                                        dma_cfg.dst_addr_width;
 358
 359                 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
 360                 if (ret) {
 361                         dev_err(nfc->dev, "tx DMA engine slave config failed\n");
 362                         return ret;
 363                 }
 364         }
 365
 366         if (nfc->dma_rx_ch) {
 367                 memset(&dma_cfg, 0, sizeof(dma_cfg));
 368                 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];
 369                 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 370                 dma_cfg.src_maxburst = nfc->rx_dma_max_burst /
 371                                        dma_cfg.src_addr_width;
 372
 373                 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);
 374                 if (ret) {
 375                         dev_err(nfc->dev, "rx DMA engine slave config failed\n");
 376                         return ret;
 377                 }
 378         }
 379
 380         if (nfc->dma_ecc_ch) {
 381                 /*
 382                  * Hamming: we read HECCR register
 383                  * BCH4/BCH8: we read BCHDSRSx registers
 384                  */
 385                 memset(&dma_cfg, 0, sizeof(dma_cfg));
 386                 dma_cfg.src_addr = nfc->io_phys_addr;
 387                 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
 388                                     FMC2_HECCR : FMC2_BCHDSR0;
 389                 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 390
 391                 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg);
 392                 if (ret) {
 393                         dev_err(nfc->dev, "ECC DMA engine slave config failed\n");
 394                         return ret;
 395                 }
 396
 397                 /* Calculate ECC length needed for one sector */
 398                 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
 399                                    FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
 406 {
 407         u32 pcr;
 408
 409         pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
 410                     FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
 411
 412         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
 413 }
 414
 415 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 416 {
 417         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
 418                            enable ? FMC2_PCR_ECCEN : 0);
 419 }
 420
 421 static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
 422 {
 423         nfc->irq_state = FMC2_IRQ_SEQ;
 424
 425         regmap_update_bits(nfc->regmap, FMC2_CSQIER,
 426                            FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
 427 }
 428
 429 static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
 430 {
 431         regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
 432
 433         nfc->irq_state = FMC2_IRQ_UNKNOWN;
 434 }
 435
 436 static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
 437 {
 438         regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
 439 }
 440
 441 static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
 442 {
 443         nfc->irq_state = FMC2_IRQ_BCH;
 444
 445         if (mode == NAND_ECC_WRITE)
 446                 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 447                                    FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
 448         else
 449                 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 450                                    FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
 451 }
 452
 453 static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
 454 {
 455         regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 456                            FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
 457
 458         nfc->irq_state = FMC2_IRQ_UNKNOWN;
 459 }
 460
 461 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 462 {
 463         regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
 464 }
 465
 466 /*
 467  * Enable ECC logic and reset syndrome/parity bits previously calculated
 468  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 469  */
 470 static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
 471 {
 472         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 473
 474         stm32_fmc2_nfc_set_ecc(nfc, false);
 475
 476         if (chip->ecc.strength != FMC2_ECC_HAM) {
 477                 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
 478                                    mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
 479
 480                 reinit_completion(&nfc->complete);
 481                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 482                 stm32_fmc2_nfc_enable_bch_irq(nfc, mode);
 483         }
 484
 485         stm32_fmc2_nfc_set_ecc(nfc, true);
 486 }
 487
 488 /*
 489  * ECC Hamming calculation
 490  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 491  * max of 1-bit)
 492  */
 493 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
 494 {
 495         ecc[0] = ecc_sta;
 496         ecc[1] = ecc_sta >> 8;
 497         ecc[2] = ecc_sta >> 16;
 498 }
 499
 500 static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
 501                                         u8 *ecc)
 502 {
 503         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 504         u32 sr, heccr;
 505         int ret;
 506
 507         ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
 508                                        sr & FMC2_SR_NWRF, 1,
 509                                        1000 * FMC2_TIMEOUT_MS);
 510         if (ret) {
 511                 dev_err(nfc->dev, "ham timeout\n");
 512                 return ret;
 513         }
 514
 515         regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
 516         stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
 517         stm32_fmc2_nfc_set_ecc(nfc, false);
 518
 519         return 0;
 520 }
 521
 522 static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat,
 523                                       u8 *read_ecc, u8 *calc_ecc)
 524 {
 525         u8 bit_position = 0, b0, b1, b2;
 526         u32 byte_addr = 0, b;
 527         u32 i, shifting = 1;
 528
 529         /* Indicate which bit and byte is faulty (if any) */
 530         b0 = read_ecc[0] ^ calc_ecc[0];
 531         b1 = read_ecc[1] ^ calc_ecc[1];
 532         b2 = read_ecc[2] ^ calc_ecc[2];
 533         b = b0 | (b1 << 8) | (b2 << 16);
 534
 535         /* No errors */
 536         if (likely(!b))
 537                 return 0;
 538
 539         /* Calculate bit position */
 540         for (i = 0; i < 3; i++) {
 541                 switch (b % 4) {
 542                 case 2:
 543                         bit_position += shifting;
 544                         break;
 545                 case 1:
 546                         break;
 547                 default:
 548                         return -EBADMSG;
 549                 }
 550                 shifting <<= 1;
 551                 b >>= 2;
 552         }
 553
 554         /* Calculate byte position */
 555         shifting = 1;
 556         for (i = 0; i < 9; i++) {
 557                 switch (b % 4) {
 558                 case 2:
 559                         byte_addr += shifting;
 560                         break;
 561                 case 1:
 562                         break;
 563                 default:
 564                         return -EBADMSG;
 565                 }
 566                 shifting <<= 1;
 567                 b >>= 2;
 568         }
 569
 570         /* Flip the bit */
 571         dat[byte_addr] ^= (1 << bit_position);
 572
 573         return 1;
 574 }
 575
 576 /*
 577  * ECC BCH calculation and correction
 578  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 579  * max of 4-bit/8-bit)
 580  */
 581 static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
 582                                         u8 *ecc)
 583 {
 584         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 585         u32 bchpbr;
 586
 587         /* Wait until the BCH code is ready */
 588         if (!wait_for_completion_timeout(&nfc->complete,
 589                                          msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
 590                 dev_err(nfc->dev, "bch timeout\n");
 591                 stm32_fmc2_nfc_disable_bch_irq(nfc);
 592                 return -ETIMEDOUT;
 593         }
 594
 595         /* Read parity bits */
 596         regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
 597         ecc[0] = bchpbr;
 598         ecc[1] = bchpbr >> 8;
 599         ecc[2] = bchpbr >> 16;
 600         ecc[3] = bchpbr >> 24;
 601
 602         regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
 603         ecc[4] = bchpbr;
 604         ecc[5] = bchpbr >> 8;
 605         ecc[6] = bchpbr >> 16;
 606
 607         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 608                 ecc[7] = bchpbr >> 24;
 609
 610                 regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
 611                 ecc[8] = bchpbr;
 612                 ecc[9] = bchpbr >> 8;
 613                 ecc[10] = bchpbr >> 16;
 614                 ecc[11] = bchpbr >> 24;
 615
 616                 regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
 617                 ecc[12] = bchpbr;
 618         }
 619
 620         stm32_fmc2_nfc_set_ecc(nfc, false);
 621
 622         return 0;
 623 }
 624
 625 static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
 626 {
 627         u32 bchdsr0 = ecc_sta[0];
 628         u32 bchdsr1 = ecc_sta[1];
 629         u32 bchdsr2 = ecc_sta[2];
 630         u32 bchdsr3 = ecc_sta[3];
 631         u32 bchdsr4 = ecc_sta[4];
 632         u16 pos[8];
 633         int i, den;
 634         unsigned int nb_errs = 0;
 635
 636         /* No errors found */
 637         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 638                 return 0;
 639
 640         /* Too many errors detected */
 641         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 642                 return -EBADMSG;
 643
 644         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 645         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 646         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 647         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 648         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 649         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 650         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 651         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 652
 653         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 654         for (i = 0; i < den; i++) {
 655                 if (pos[i] < eccsize * 8) {
 656                         change_bit(pos[i], (unsigned long *)dat);
 657                         nb_errs++;
 658                 }
 659         }
 660
 661         return nb_errs;
 662 }
 663
 664 static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
 665                                       u8 *read_ecc, u8 *calc_ecc)
 666 {
 667         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 668         u32 ecc_sta[5];
 669
 670         /* Wait until the decoding error is ready */
 671         if (!wait_for_completion_timeout(&nfc->complete,
 672                                          msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
 673                 dev_err(nfc->dev, "bch timeout\n");
 674                 stm32_fmc2_nfc_disable_bch_irq(nfc);
 675                 return -ETIMEDOUT;
 676         }
 677
 678         regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
 679
 680         stm32_fmc2_nfc_set_ecc(nfc, false);
 681
 682         return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta);
 683 }
 684
 685 static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf,
 686                                     int oob_required, int page)
 687 {
 688         struct mtd_info *mtd = nand_to_mtd(chip);
 689         int ret, i, s, stat, eccsize = chip->ecc.size;
 690         int eccbytes = chip->ecc.bytes;
 691         int eccsteps = chip->ecc.steps;
 692         int eccstrength = chip->ecc.strength;
 693         u8 *p = buf;
 694         u8 *ecc_calc = chip->ecc.calc_buf;
 695         u8 *ecc_code = chip->ecc.code_buf;
 696         unsigned int max_bitflips = 0;
 697
 698         ret = nand_read_page_op(chip, page, 0, NULL, 0);
 699         if (ret)
 700                 return ret;
 701
 702         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 703              s++, i += eccbytes, p += eccsize) {
 704                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 705
 706                 /* Read the nand page sector (512 bytes) */
 707                 ret = nand_change_read_column_op(chip, s * eccsize, p,
 708                                                  eccsize, false);
 709                 if (ret)
 710                         return ret;
 711
 712                 /* Read the corresponding ECC bytes */
 713                 ret = nand_change_read_column_op(chip, i, ecc_code,
 714                                                  eccbytes, false);
 715                 if (ret)
 716                         return ret;
 717
 718                 /* Correct the data */
 719                 stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
 720                 if (stat == -EBADMSG)
 721                         /* Check for empty pages with bitflips */
 722                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 723                                                            ecc_code, eccbytes,
 724                                                            NULL, 0,
 725                                                            eccstrength);
 726
 727                 if (stat < 0) {
 728                         mtd->ecc_stats.failed++;
 729                 } else {
 730                         mtd->ecc_stats.corrected += stat;
 731                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 732                 }
 733         }
 734
 735         /* Read oob */
 736         if (oob_required) {
 737                 ret = nand_change_read_column_op(chip, mtd->writesize,
 738                                                  chip->oob_poi, mtd->oobsize,
 739                                                  false);
 740                 if (ret)
 741                         return ret;
 742         }
 743
 744         return max_bitflips;
 745 }
 746
 747 /* Sequencer read/write configuration */
 748 static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
 749                                         int raw, bool write_data)
 750 {
 751         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 752         struct mtd_info *mtd = nand_to_mtd(chip);
 753         u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
 754         /*
 755          * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
 756          * cfg[3] => csqar1, cfg[4] => csqar2
 757          */
 758         u32 cfg[5];
 759
 760         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
 761                            write_data ? FMC2_PCR_WEN : 0);
 762
 763         /*
 764          * - Set Program Page/Page Read command
 765          * - Enable DMA request data
 766          * - Set timings
 767          */
 768         cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
 769         if (write_data)
 770                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
 771         else
 772                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
 773                           FMC2_CSQCFGR1_CMD2EN |
 774                           FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
 775                           FMC2_CSQCFGR1_CMD2T;
 776
 777         /*
 778          * - Set Random Data Input/Random Data Read command
 779          * - Enable the sequencer to access the Spare data area
 780          * - Enable  DMA request status decoding for read
 781          * - Set timings
 782          */
 783         if (write_data)
 784                 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
 785         else
 786                 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
 787                          FMC2_CSQCFGR2_RCMD2EN |
 788                          FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
 789                          FMC2_CSQCFGR2_RCMD1T |
 790                          FMC2_CSQCFGR2_RCMD2T;
 791         if (!raw) {
 792                 cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
 793                 cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
 794         }
 795
 796         /*
 797          * - Set the number of sectors to be written
 798          * - Set timings
 799          */
 800         cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
 801         if (write_data) {
 802                 cfg[2] |= FMC2_CSQCFGR3_RAC2T;
 803                 if (chip->options & NAND_ROW_ADDR_3)
 804                         cfg[2] |= FMC2_CSQCFGR3_AC5T;
 805                 else
 806                         cfg[2] |= FMC2_CSQCFGR3_AC4T;
 807         }
 808
 809         /*
 810          * Set the fourth first address cycles
 811          * Byte 1 and byte 2 => column, we start at 0x0
 812          * Byte 3 and byte 4 => page
 813          */
 814         cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
 815         cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
 816
 817         /*
 818          * - Set chip enable number
 819          * - Set ECC byte offset in the spare area
 820          * - Calculate the number of address cycles to be issued
 821          * - Set byte 5 of address cycle if needed
 822          */
 823         cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
 824         if (chip->options & NAND_BUSWIDTH_16)
 825                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
 826         else
 827                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
 828         if (chip->options & NAND_ROW_ADDR_3) {
 829                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
 830                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
 831         } else {
 832                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
 833         }
 834
 835         regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
 836 }
 837
 838 static void stm32_fmc2_nfc_dma_callback(void *arg)
 839 {
 840         complete((struct completion *)arg);
 841 }
 842
 843 /* Read/write data from/to a page */
 844 static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
 845                                int raw, bool write_data)
 846 {
 847         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 848         struct dma_async_tx_descriptor *desc_data, *desc_ecc;
 849         struct scatterlist *sg;
 850         struct dma_chan *dma_ch = nfc->dma_rx_ch;
 851         enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
 852         enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
 853         int eccsteps = chip->ecc.steps;
 854         int eccsize = chip->ecc.size;
 855         unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
 856         const u8 *p = buf;
 857         int s, ret;
 858
 859         /* Configure DMA data */
 860         if (write_data) {
 861                 dma_data_dir = DMA_TO_DEVICE;
 862                 dma_transfer_dir = DMA_MEM_TO_DEV;
 863                 dma_ch = nfc->dma_tx_ch;
 864         }
 865
 866         for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) {
 867                 sg_set_buf(sg, p, eccsize);
 868                 p += eccsize;
 869         }
 870
 871         ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl,
 872                          eccsteps, dma_data_dir);
 873         if (!ret)
 874                 return -EIO;
 875
 876         desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl,
 877                                             eccsteps, dma_transfer_dir,
 878                                             DMA_PREP_INTERRUPT);
 879         if (!desc_data) {
 880                 ret = -ENOMEM;
 881                 goto err_unmap_data;
 882         }
 883
 884         reinit_completion(&nfc->dma_data_complete);
 885         reinit_completion(&nfc->complete);
 886         desc_data->callback = stm32_fmc2_nfc_dma_callback;
 887         desc_data->callback_param = &nfc->dma_data_complete;
 888         ret = dma_submit_error(dmaengine_submit(desc_data));
 889         if (ret)
 890                 goto err_unmap_data;
 891
 892         dma_async_issue_pending(dma_ch);
 893
 894         if (!write_data && !raw) {
 895                 /* Configure DMA ECC status */
 896                 p = nfc->ecc_buf;
 897                 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
 898                         sg_set_buf(sg, p, nfc->dma_ecc_len);
 899                         p += nfc->dma_ecc_len;
 900                 }
 901
 902                 ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
 903                                  eccsteps, dma_data_dir);
 904                 if (!ret) {
 905                         ret = -EIO;
 906                         goto err_unmap_data;
 907                 }
 908
 909                 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
 910                                                    nfc->dma_ecc_sg.sgl,
 911                                                    eccsteps, dma_transfer_dir,
 912                                                    DMA_PREP_INTERRUPT);
 913                 if (!desc_ecc) {
 914                         ret = -ENOMEM;
 915                         goto err_unmap_ecc;
 916                 }
 917
 918                 reinit_completion(&nfc->dma_ecc_complete);
 919                 desc_ecc->callback = stm32_fmc2_nfc_dma_callback;
 920                 desc_ecc->callback_param = &nfc->dma_ecc_complete;
 921                 ret = dma_submit_error(dmaengine_submit(desc_ecc));
 922                 if (ret)
 923                         goto err_unmap_ecc;
 924
 925                 dma_async_issue_pending(nfc->dma_ecc_ch);
 926         }
 927
 928         stm32_fmc2_nfc_clear_seq_irq(nfc);
 929         stm32_fmc2_nfc_enable_seq_irq(nfc);
 930
 931         /* Start the transfer */
 932         regmap_update_bits(nfc->regmap, FMC2_CSQCR,
 933                            FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
 934
 935         /* Wait end of sequencer transfer */
 936         if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
 937                 dev_err(nfc->dev, "seq timeout\n");
 938                 stm32_fmc2_nfc_disable_seq_irq(nfc);
 939                 dmaengine_terminate_all(dma_ch);
 940                 if (!write_data && !raw)
 941                         dmaengine_terminate_all(nfc->dma_ecc_ch);
 942                 ret = -ETIMEDOUT;
 943                 goto err_unmap_ecc;
 944         }
 945
 946         /* Wait DMA data transfer completion */
 947         if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) {
 948                 dev_err(nfc->dev, "data DMA timeout\n");
 949                 dmaengine_terminate_all(dma_ch);
 950                 ret = -ETIMEDOUT;
 951         }
 952
 953         /* Wait DMA ECC transfer completion */
 954         if (!write_data && !raw) {
 955                 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete,
 956                                                  timeout)) {
 957                         dev_err(nfc->dev, "ECC DMA timeout\n");
 958                         dmaengine_terminate_all(nfc->dma_ecc_ch);
 959                         ret = -ETIMEDOUT;
 960                 }
 961         }
 962
 963 err_unmap_ecc:
 964         if (!write_data && !raw)
 965                 dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
 966                              eccsteps, dma_data_dir);
 967
 968 err_unmap_data:
 969         dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
 970
 971         return ret;
 972 }
 973
 974 static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf,
 975                                     int oob_required, int page, int raw)
 976 {
 977         struct mtd_info *mtd = nand_to_mtd(chip);
 978         int ret;
 979
 980         /* Configure the sequencer */
 981         stm32_fmc2_nfc_rw_page_init(chip, page, raw, true);
 982
 983         /* Write the page */
 984         ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true);
 985         if (ret)
 986                 return ret;
 987
 988         /* Write oob */
 989         if (oob_required) {
 990                 ret = nand_change_write_column_op(chip, mtd->writesize,
 991                                                   chip->oob_poi, mtd->oobsize,
 992                                                   false);
 993                 if (ret)
 994                         return ret;
 995         }
 996
 997         return nand_prog_page_end_op(chip);
 998 }
 999
1000 static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf,
1001                                          int oob_required, int page)
1002 {
1003         int ret;
1004
1005         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1006         if (ret)
1007                 return ret;
1008
1009         return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false);
1010 }
1011
1012 static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip,
1013                                              const u8 *buf, int oob_required,
1014                                              int page)
1015 {
1016         int ret;
1017
1018         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1019         if (ret)
1020                 return ret;
1021
1022         return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true);
1023 }
1024
1025 /* Get a status indicating which sectors have errors */
1026 static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1027 {
1028         u32 csqemsr;
1029
1030         regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1031
1032         return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
1033 }
1034
1035 static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
1036                                       u8 *read_ecc, u8 *calc_ecc)
1037 {
1038         struct mtd_info *mtd = nand_to_mtd(chip);
1039         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1040         int eccbytes = chip->ecc.bytes;
1041         int eccsteps = chip->ecc.steps;
1042         int eccstrength = chip->ecc.strength;
1043         int i, s, eccsize = chip->ecc.size;
1044         u32 *ecc_sta = (u32 *)nfc->ecc_buf;
1045         u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1046         unsigned int max_bitflips = 0;
1047
1048         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
1049                 int stat = 0;
1050
1051                 if (eccstrength == FMC2_ECC_HAM) {
1052                         /* Ecc_sta = FMC2_HECCR */
1053                         if (sta_map & BIT(s)) {
1054                                 stm32_fmc2_nfc_ham_set_ecc(*ecc_sta,
1055                                                            &calc_ecc[i]);
1056                                 stat = stm32_fmc2_nfc_ham_correct(chip, dat,
1057                                                                   &read_ecc[i],
1058                                                                   &calc_ecc[i]);
1059                         }
1060                         ecc_sta++;
1061                 } else {
1062                         /*
1063                          * Ecc_sta[0] = FMC2_BCHDSR0
1064                          * Ecc_sta[1] = FMC2_BCHDSR1
1065                          * Ecc_sta[2] = FMC2_BCHDSR2
1066                          * Ecc_sta[3] = FMC2_BCHDSR3
1067                          * Ecc_sta[4] = FMC2_BCHDSR4
1068                          */
1069                         if (sta_map & BIT(s))
1070                                 stat = stm32_fmc2_nfc_bch_decode(eccsize, dat,
1071                                                                  ecc_sta);
1072                         ecc_sta += 5;
1073                 }
1074
1075                 if (stat == -EBADMSG)
1076                         /* Check for empty pages with bitflips */
1077                         stat = nand_check_erased_ecc_chunk(dat, eccsize,
1078                                                            &read_ecc[i],
1079                                                            eccbytes,
1080                                                            NULL, 0,
1081                                                            eccstrength);
1082
1083                 if (stat < 0) {
1084                         mtd->ecc_stats.failed++;
1085                 } else {
1086                         mtd->ecc_stats.corrected += stat;
1087                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1088                 }
1089         }
1090
1091         return max_bitflips;
1092 }
1093
1094 static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf,
1095                                         int oob_required, int page)
1096 {
1097         struct mtd_info *mtd = nand_to_mtd(chip);
1098         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1099         u8 *ecc_calc = chip->ecc.calc_buf;
1100         u8 *ecc_code = chip->ecc.code_buf;
1101         u16 sta_map;
1102         int ret;
1103
1104         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1105         if (ret)
1106                 return ret;
1107
1108         /* Configure the sequencer */
1109         stm32_fmc2_nfc_rw_page_init(chip, page, 0, false);
1110
1111         /* Read the page */
1112         ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false);
1113         if (ret)
1114                 return ret;
1115
1116         sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1117
1118         /* Check if errors happen */
1119         if (likely(!sta_map)) {
1120                 if (oob_required)
1121                         return nand_change_read_column_op(chip, mtd->writesize,
1122                                                           chip->oob_poi,
1123                                                           mtd->oobsize, false);
1124
1125                 return 0;
1126         }
1127
1128         /* Read oob */
1129         ret = nand_change_read_column_op(chip, mtd->writesize,
1130                                          chip->oob_poi, mtd->oobsize, false);
1131         if (ret)
1132                 return ret;
1133
1134         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1135                                          chip->ecc.total);
1136         if (ret)
1137                 return ret;
1138
1139         /* Correct data */
1140         return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1141 }
1142
1143 static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf,
1144                                             int oob_required, int page)
1145 {
1146         struct mtd_info *mtd = nand_to_mtd(chip);
1147         int ret;
1148
1149         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1150         if (ret)
1151                 return ret;
1152
1153         /* Configure the sequencer */
1154         stm32_fmc2_nfc_rw_page_init(chip, page, 1, false);
1155
1156         /* Read the page */
1157         ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false);
1158         if (ret)
1159                 return ret;
1160
1161         /* Read oob */
1162         if (oob_required)
1163                 return nand_change_read_column_op(chip, mtd->writesize,
1164                                                   chip->oob_poi, mtd->oobsize,
1165                                                   false);
1166
1167         return 0;
1168 }
1169
1170 static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id)
1171 {
1172         struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id;
1173
1174         if (nfc->irq_state == FMC2_IRQ_SEQ)
1175                 /* Sequencer is used */
1176                 stm32_fmc2_nfc_disable_seq_irq(nfc);
1177         else if (nfc->irq_state == FMC2_IRQ_BCH)
1178                 /* BCH is used */
1179                 stm32_fmc2_nfc_disable_bch_irq(nfc);
1180
1181         complete(&nfc->complete);
1182
1183         return IRQ_HANDLED;
1184 }
1185
1186 static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf,
1187                                      unsigned int len, bool force_8bit)
1188 {
1189         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1190         void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
1191
1192         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1193                 /* Reconfigure bus width to 8-bit */
1194                 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1195
1196         if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1197                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1198                         *(u8 *)buf = readb_relaxed(io_addr_r);
1199                         buf += sizeof(u8);
1200                         len -= sizeof(u8);
1201                 }
1202
1203                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1204                     len >= sizeof(u16)) {
1205                         *(u16 *)buf = readw_relaxed(io_addr_r);
1206                         buf += sizeof(u16);
1207                         len -= sizeof(u16);
1208                 }
1209         }
1210
1211         /* Buf is aligned */
1212         while (len >= sizeof(u32)) {
1213                 *(u32 *)buf = readl_relaxed(io_addr_r);
1214                 buf += sizeof(u32);
1215                 len -= sizeof(u32);
1216         }
1217
1218         /* Read remaining bytes */
1219         if (len >= sizeof(u16)) {
1220                 *(u16 *)buf = readw_relaxed(io_addr_r);
1221                 buf += sizeof(u16);
1222                 len -= sizeof(u16);
1223         }
1224
1225         if (len)
1226                 *(u8 *)buf = readb_relaxed(io_addr_r);
1227
1228         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1229                 /* Reconfigure bus width to 16-bit */
1230                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1231 }
1232
1233 static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf,
1234                                       unsigned int len, bool force_8bit)
1235 {
1236         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1237         void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
1238
1239         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1240                 /* Reconfigure bus width to 8-bit */
1241                 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1242
1243         if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1244                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1245                         writeb_relaxed(*(u8 *)buf, io_addr_w);
1246                         buf += sizeof(u8);
1247                         len -= sizeof(u8);
1248                 }
1249
1250                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1251                     len >= sizeof(u16)) {
1252                         writew_relaxed(*(u16 *)buf, io_addr_w);
1253                         buf += sizeof(u16);
1254                         len -= sizeof(u16);
1255                 }
1256         }
1257
1258         /* Buf is aligned */
1259         while (len >= sizeof(u32)) {
1260                 writel_relaxed(*(u32 *)buf, io_addr_w);
1261                 buf += sizeof(u32);
1262                 len -= sizeof(u32);
1263         }
1264
1265         /* Write remaining bytes */
1266         if (len >= sizeof(u16)) {
1267                 writew_relaxed(*(u16 *)buf, io_addr_w);
1268                 buf += sizeof(u16);
1269                 len -= sizeof(u16);
1270         }
1271
1272         if (len)
1273                 writeb_relaxed(*(u8 *)buf, io_addr_w);
1274
1275         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1276                 /* Reconfigure bus width to 16-bit */
1277                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1278 }
1279
1280 static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
1281                                   unsigned long timeout_ms)
1282 {
1283         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1284         const struct nand_sdr_timings *timings;
1285         u32 isr, sr;
1286
1287         /* Check if there is no pending requests to the NAND flash */
1288         if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1289                                      sr & FMC2_SR_NWRF, 1,
1290                                      1000 * FMC2_TIMEOUT_MS))
1291                 dev_warn(nfc->dev, "Waitrdy timeout\n");
1292
1293         /* Wait tWB before R/B# signal is low */
1294         timings = nand_get_sdr_timings(nand_get_interface_config(chip));
1295         ndelay(PSEC_TO_NSEC(timings->tWB_max));
1296
1297         /* R/B# signal is low, clear high level flag */
1298         regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1299
1300         /* Wait R/B# signal is high */
1301         return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1302                                         isr & FMC2_ISR_IHLF, 5,
1303                                         1000 * FMC2_TIMEOUT_MS);
1304 }
1305
1306 static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
1307                                   const struct nand_operation *op,
1308                                   bool check_only)
1309 {
1310         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1311         const struct nand_op_instr *instr = NULL;
1312         unsigned int op_id, i, timeout;
1313         int ret;
1314
1315         if (check_only)
1316                 return 0;
1317
1318         ret = stm32_fmc2_nfc_select_chip(chip, op->cs);
1319         if (ret)
1320                 return ret;
1321
1322         for (op_id = 0; op_id < op->ninstrs; op_id++) {
1323                 instr = &op->instrs[op_id];
1324
1325                 switch (instr->type) {
1326                 case NAND_OP_CMD_INSTR:
1327                         writeb_relaxed(instr->ctx.cmd.opcode,
1328                                        nfc->cmd_base[nfc->cs_sel]);
1329                         break;
1330
1331                 case NAND_OP_ADDR_INSTR:
1332                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
1333                                 writeb_relaxed(instr->ctx.addr.addrs[i],
1334                                                nfc->addr_base[nfc->cs_sel]);
1335                         break;
1336
1337                 case NAND_OP_DATA_IN_INSTR:
1338                         stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in,
1339                                                  instr->ctx.data.len,
1340                                                  instr->ctx.data.force_8bit);
1341                         break;
1342
1343                 case NAND_OP_DATA_OUT_INSTR:
1344                         stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out,
1345                                                   instr->ctx.data.len,
1346                                                   instr->ctx.data.force_8bit);
1347                         break;
1348
1349                 case NAND_OP_WAITRDY_INSTR:
1350                         timeout = instr->ctx.waitrdy.timeout_ms;
1351                         ret = stm32_fmc2_nfc_waitrdy(chip, timeout);
1352                         break;
1353                 }
1354         }
1355
1356         return ret;
1357 }
1358
1359 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1360 {
1361         u32 pcr;
1362
1363         regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1364
1365         /* Set CS used to undefined */
1366         nfc->cs_sel = -1;
1367
1368         /* Enable wait feature and nand flash memory bank */
1369         pcr |= FMC2_PCR_PWAITEN;
1370         pcr |= FMC2_PCR_PBKEN;
1371
1372         /* Set buswidth to 8 bits mode for identification */
1373         pcr &= ~FMC2_PCR_PWID;
1374
1375         /* ECC logic is disabled */
1376         pcr &= ~FMC2_PCR_ECCEN;
1377
1378         /* Default mode */
1379         pcr &= ~FMC2_PCR_ECCALG;
1380         pcr &= ~FMC2_PCR_BCHECC;
1381         pcr &= ~FMC2_PCR_WEN;
1382
1383         /* Set default ECC sector size */
1384         pcr &= ~FMC2_PCR_ECCSS;
1385         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
1386
1387         /* Set default tclr/tar timings */
1388         pcr &= ~FMC2_PCR_TCLR;
1389         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
1390         pcr &= ~FMC2_PCR_TAR;
1391         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
1392
1393         /* Enable FMC2 controller */
1394         if (nfc->dev == nfc->cdev)
1395                 regmap_update_bits(nfc->regmap, FMC2_BCR1,
1396                                    FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1397
1398         regmap_write(nfc->regmap, FMC2_PCR, pcr);
1399         regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1400         regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1401 }
1402
1403 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
1404                                         const struct nand_sdr_timings *sdrt)
1405 {
1406         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1407         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
1408         struct stm32_fmc2_timings *tims = &nand->timings;
1409         unsigned long hclk = clk_get_rate(nfc->clk);
1410         unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
1411         unsigned long timing, tar, tclr, thiz, twait;
1412         unsigned long tset_mem, tset_att, thold_mem, thold_att;
1413
1414         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
1415         timing = DIV_ROUND_UP(tar, hclkp) - 1;
1416         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1417
1418         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
1419         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
1420         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1421
1422         tims->thiz = FMC2_THIZ;
1423         thiz = (tims->thiz + 1) * hclkp;
1424
1425         /*
1426          * tWAIT > tRP
1427          * tWAIT > tWP
1428          * tWAIT > tREA + tIO
1429          */
1430         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
1431         twait = max_t(unsigned long, twait, sdrt->tWP_min);
1432         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
1433         timing = DIV_ROUND_UP(twait, hclkp);
1434         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1435
1436         /*
1437          * tSETUP_MEM > tCS - tWAIT
1438          * tSETUP_MEM > tALS - tWAIT
1439          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
1440          */
1441         tset_mem = hclkp;
1442         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
1443                 tset_mem = sdrt->tCS_min - twait;
1444         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
1445                 tset_mem = sdrt->tALS_min - twait;
1446         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1447             (tset_mem < sdrt->tDS_min - (twait - thiz)))
1448                 tset_mem = sdrt->tDS_min - (twait - thiz);
1449         timing = DIV_ROUND_UP(tset_mem, hclkp);
1450         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1451
1452         /*
1453          * tHOLD_MEM > tCH
1454          * tHOLD_MEM > tREH - tSETUP_MEM
1455          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
1456          */
1457         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
1458         if (sdrt->tREH_min > tset_mem &&
1459             (thold_mem < sdrt->tREH_min - tset_mem))
1460                 thold_mem = sdrt->tREH_min - tset_mem;
1461         if ((sdrt->tRC_min > tset_mem + twait) &&
1462             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
1463                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
1464         if ((sdrt->tWC_min > tset_mem + twait) &&
1465             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
1466                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
1467         timing = DIV_ROUND_UP(thold_mem, hclkp);
1468         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1469
1470         /*
1471          * tSETUP_ATT > tCS - tWAIT
1472          * tSETUP_ATT > tCLS - tWAIT
1473          * tSETUP_ATT > tALS - tWAIT
1474          * tSETUP_ATT > tRHW - tHOLD_MEM
1475          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
1476          */
1477         tset_att = hclkp;
1478         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
1479                 tset_att = sdrt->tCS_min - twait;
1480         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
1481                 tset_att = sdrt->tCLS_min - twait;
1482         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
1483                 tset_att = sdrt->tALS_min - twait;
1484         if (sdrt->tRHW_min > thold_mem &&
1485             (tset_att < sdrt->tRHW_min - thold_mem))
1486                 tset_att = sdrt->tRHW_min - thold_mem;
1487         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1488             (tset_att < sdrt->tDS_min - (twait - thiz)))
1489                 tset_att = sdrt->tDS_min - (twait - thiz);
1490         timing = DIV_ROUND_UP(tset_att, hclkp);
1491         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1492
1493         /*
1494          * tHOLD_ATT > tALH
1495          * tHOLD_ATT > tCH
1496          * tHOLD_ATT > tCLH
1497          * tHOLD_ATT > tCOH
1498          * tHOLD_ATT > tDH
1499          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
1500          * tHOLD_ATT > tADL - tSETUP_MEM
1501          * tHOLD_ATT > tWH - tSETUP_MEM
1502          * tHOLD_ATT > tWHR - tSETUP_MEM
1503          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
1504          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
1505          */
1506         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
1507         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
1508         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
1509         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
1510         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
1511         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
1512             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
1513                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
1514         if (sdrt->tADL_min > tset_mem &&
1515             (thold_att < sdrt->tADL_min - tset_mem))
1516                 thold_att = sdrt->tADL_min - tset_mem;
1517         if (sdrt->tWH_min > tset_mem &&
1518             (thold_att < sdrt->tWH_min - tset_mem))
1519                 thold_att = sdrt->tWH_min - tset_mem;
1520         if (sdrt->tWHR_min > tset_mem &&
1521             (thold_att < sdrt->tWHR_min - tset_mem))
1522                 thold_att = sdrt->tWHR_min - tset_mem;
1523         if ((sdrt->tRC_min > tset_att + twait) &&
1524             (thold_att < sdrt->tRC_min - (tset_att + twait)))
1525                 thold_att = sdrt->tRC_min - (tset_att + twait);
1526         if ((sdrt->tWC_min > tset_att + twait) &&
1527             (thold_att < sdrt->tWC_min - (tset_att + twait)))
1528                 thold_att = sdrt->tWC_min - (tset_att + twait);
1529         timing = DIV_ROUND_UP(thold_att, hclkp);
1530         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1531 }
1532
1533 static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
1534                                           const struct nand_interface_config *conf)
1535 {
1536         const struct nand_sdr_timings *sdrt;
1537
1538         sdrt = nand_get_sdr_timings(conf);
1539         if (IS_ERR(sdrt))
1540                 return PTR_ERR(sdrt);
1541
1542         if (conf->timings.mode > 3)
1543                 return -EOPNOTSUPP;
1544
1545         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
1546                 return 0;
1547
1548         stm32_fmc2_nfc_calc_timings(chip, sdrt);
1549         stm32_fmc2_nfc_timings_init(chip);
1550
1551         return 0;
1552 }
1553
1554 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
1555 {
1556         struct dma_slave_caps caps;
1557         int ret = 0;
1558
1559         nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
1560         if (IS_ERR(nfc->dma_tx_ch)) {
1561                 ret = PTR_ERR(nfc->dma_tx_ch);
1562                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1563                         dev_err(nfc->dev,
1564                                 "failed to request tx DMA channel: %d\n", ret);
1565                 nfc->dma_tx_ch = NULL;
1566                 goto err_dma;
1567         }
1568
1569         ret = dma_get_slave_caps(nfc->dma_tx_ch, &caps);
1570         if (ret)
1571                 return ret;
1572         nfc->tx_dma_max_burst = caps.max_burst;
1573
1574         nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
1575         if (IS_ERR(nfc->dma_rx_ch)) {
1576                 ret = PTR_ERR(nfc->dma_rx_ch);
1577                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1578                         dev_err(nfc->dev,
1579                                 "failed to request rx DMA channel: %d\n", ret);
1580                 nfc->dma_rx_ch = NULL;
1581                 goto err_dma;
1582         }
1583
1584         ret = dma_get_slave_caps(nfc->dma_rx_ch, &caps);
1585         if (ret)
1586                 return ret;
1587         nfc->rx_dma_max_burst = caps.max_burst;
1588
1589         nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
1590         if (IS_ERR(nfc->dma_ecc_ch)) {
1591                 ret = PTR_ERR(nfc->dma_ecc_ch);
1592                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1593                         dev_err(nfc->dev,
1594                                 "failed to request ecc DMA channel: %d\n", ret);
1595                 nfc->dma_ecc_ch = NULL;
1596                 goto err_dma;
1597         }
1598
1599         ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
1600         if (ret)
1601                 return ret;
1602
1603         /* Allocate a buffer to store ECC status registers */
1604         nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1605         if (!nfc->ecc_buf)
1606                 return -ENOMEM;
1607
1608         ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
1609         if (ret)
1610                 return ret;
1611
1612         init_completion(&nfc->dma_data_complete);
1613         init_completion(&nfc->dma_ecc_complete);
1614
1615         return 0;
1616
1617 err_dma:
1618         if (ret == -ENODEV) {
1619                 dev_warn(nfc->dev,
1620                          "DMAs not defined in the DT, polling mode is used\n");
1621                 ret = 0;
1622         }
1623
1624         return ret;
1625 }
1626
1627 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
1628 {
1629         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1630
1631         /*
1632          * Specific callbacks to read/write a page depending on
1633          * the mode (polling/sequencer) and the algo used (Hamming, BCH).
1634          */
1635         if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) {
1636                 /* DMA => use sequencer mode callbacks */
1637                 chip->ecc.correct = stm32_fmc2_nfc_seq_correct;
1638                 chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page;
1639                 chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page;
1640                 chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw;
1641                 chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw;
1642         } else {
1643                 /* No DMA => use polling mode callbacks */
1644                 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
1645                 if (chip->ecc.strength == FMC2_ECC_HAM) {
1646                         /* Hamming is used */
1647                         chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
1648                         chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
1649                         chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
1650                 } else {
1651                         /* BCH is used */
1652                         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
1653                         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
1654                         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
1655                 }
1656         }
1657
1658         /* Specific configurations depending on the algo used */
1659         if (chip->ecc.strength == FMC2_ECC_HAM)
1660                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
1661         else if (chip->ecc.strength == FMC2_ECC_BCH8)
1662                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
1663         else
1664                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
1665 }
1666
1667 static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1668                                         struct mtd_oob_region *oobregion)
1669 {
1670         struct nand_chip *chip = mtd_to_nand(mtd);
1671         struct nand_ecc_ctrl *ecc = &chip->ecc;
1672
1673         if (section)
1674                 return -ERANGE;
1675
1676         oobregion->length = ecc->total;
1677         oobregion->offset = FMC2_BBM_LEN;
1678
1679         return 0;
1680 }
1681
1682 static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1683                                          struct mtd_oob_region *oobregion)
1684 {
1685         struct nand_chip *chip = mtd_to_nand(mtd);
1686         struct nand_ecc_ctrl *ecc = &chip->ecc;
1687
1688         if (section)
1689                 return -ERANGE;
1690
1691         oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
1692         oobregion->offset = ecc->total + FMC2_BBM_LEN;
1693
1694         return 0;
1695 }
1696
1697 static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = {
1698         .ecc = stm32_fmc2_nfc_ooblayout_ecc,
1699         .free = stm32_fmc2_nfc_ooblayout_free,
1700 };
1701
1702 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
1703 {
1704         /* Hamming */
1705         if (strength == FMC2_ECC_HAM)
1706                 return 4;
1707
1708         /* BCH8 */
1709         if (strength == FMC2_ECC_BCH8)
1710                 return 14;
1711
1712         /* BCH4 */
1713         return 8;
1714 }
1715
1716 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
1717                      FMC2_ECC_STEP_SIZE,
1718                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
1719
1720 static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
1721 {
1722         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1723         struct mtd_info *mtd = nand_to_mtd(chip);
1724         int ret;
1725
1726         /*
1727          * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported
1728          * Hamming => ecc.strength = 1
1729          * BCH4 => ecc.strength = 4
1730          * BCH8 => ecc.strength = 8
1731          * ECC sector size = 512
1732          */
1733         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
1734                 dev_err(nfc->dev,
1735                         "nand_ecc_engine_type is not well defined in the DT\n");
1736                 return -EINVAL;
1737         }
1738
1739         /* Default ECC settings in case they are not set in the device tree */
1740         if (!chip->ecc.size)
1741                 chip->ecc.size = FMC2_ECC_STEP_SIZE;
1742
1743         if (!chip->ecc.strength)
1744                 chip->ecc.strength = FMC2_ECC_BCH8;
1745
1746         ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1747                                    mtd->oobsize - FMC2_BBM_LEN);
1748         if (ret) {
1749                 dev_err(nfc->dev, "no valid ECC settings set\n");
1750                 return ret;
1751         }
1752
1753         if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
1754                 dev_err(nfc->dev, "nand page size is not supported\n");
1755                 return -EINVAL;
1756         }
1757
1758         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1759                 chip->bbt_options |= NAND_BBT_NO_OOB;
1760
1761         stm32_fmc2_nfc_nand_callbacks_setup(chip);
1762
1763         mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1764
1765         stm32_fmc2_nfc_setup(chip);
1766
1767         return 0;
1768 }
1769
1770 static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
1771         .attach_chip = stm32_fmc2_nfc_attach_chip,
1772         .exec_op = stm32_fmc2_nfc_exec_op,
1773         .setup_interface = stm32_fmc2_nfc_setup_interface,
1774 };
1775
1776 static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
1777 {
1778         if (nand->wp_gpio)
1779                 gpiod_set_value(nand->wp_gpio, 1);
1780 }
1781
1782 static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
1783 {
1784         if (nand->wp_gpio)
1785                 gpiod_set_value(nand->wp_gpio, 0);
1786 }
1787
1788 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1789                                       struct device_node *dn)
1790 {
1791         struct stm32_fmc2_nand *nand = &nfc->nand;
1792         u32 cs;
1793         int ret, i;
1794
1795         if (!of_get_property(dn, "reg", &nand->ncs))
1796                 return -EINVAL;
1797
1798         nand->ncs /= sizeof(u32);
1799         if (!nand->ncs) {
1800                 dev_err(nfc->dev, "invalid reg property size\n");
1801                 return -EINVAL;
1802         }
1803
1804         for (i = 0; i < nand->ncs; i++) {
1805                 ret = of_property_read_u32_index(dn, "reg", i, &cs);
1806                 if (ret) {
1807                         dev_err(nfc->dev, "could not retrieve reg property: %d\n",
1808                                 ret);
1809                         return ret;
1810                 }
1811
1812                 if (cs >= FMC2_MAX_CE) {
1813                         dev_err(nfc->dev, "invalid reg value: %d\n", cs);
1814                         return -EINVAL;
1815                 }
1816
1817                 if (nfc->cs_assigned & BIT(cs)) {
1818                         dev_err(nfc->dev, "cs already assigned: %d\n", cs);
1819                         return -EINVAL;
1820                 }
1821
1822                 nfc->cs_assigned |= BIT(cs);
1823                 nand->cs_used[i] = cs;
1824         }
1825
1826         nand->wp_gpio = devm_fwnode_gpiod_get(nfc->dev, of_fwnode_handle(dn),
1827                                               "wp", GPIOD_OUT_HIGH, "wp");
1828         if (IS_ERR(nand->wp_gpio)) {
1829                 ret = PTR_ERR(nand->wp_gpio);
1830                 if (ret != -ENOENT)
1831                         return dev_err_probe(nfc->dev, ret,
1832                                              "failed to request WP GPIO\n");
1833
1834                 nand->wp_gpio = NULL;
1835         }
1836
1837         nand_set_flash_node(&nand->chip, dn);
1838
1839         return 0;
1840 }
1841
1842 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1843 {
1844         struct device_node *dn = nfc->dev->of_node;
1845         struct device_node *child;
1846         int nchips = of_get_child_count(dn);
1847         int ret = 0;
1848
1849         if (!nchips) {
1850                 dev_err(nfc->dev, "NAND chip not defined\n");
1851                 return -EINVAL;
1852         }
1853
1854         if (nchips > 1) {
1855                 dev_err(nfc->dev, "too many NAND chips defined\n");
1856                 return -EINVAL;
1857         }
1858
1859         for_each_child_of_node(dn, child) {
1860                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
1861                 if (ret < 0) {
1862                         of_node_put(child);
1863                         return ret;
1864                 }
1865         }
1866
1867         return ret;
1868 }
1869
1870 static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
1871 {
1872         struct device *dev = nfc->dev;
1873         bool ebi_found = false;
1874
1875         if (dev->parent && of_device_is_compatible(dev->parent->of_node,
1876                                                    "st,stm32mp1-fmc2-ebi"))
1877                 ebi_found = true;
1878
1879         if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
1880                 if (ebi_found) {
1881                         nfc->cdev = dev->parent;
1882
1883                         return 0;
1884                 }
1885
1886                 return -EINVAL;
1887         }
1888
1889         if (ebi_found)
1890                 return -EINVAL;
1891
1892         nfc->cdev = dev;
1893
1894         return 0;
1895 }
1896
1897 static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
1898 {
1899         struct device *dev = &pdev->dev;
1900         struct reset_control *rstc;
1901         struct stm32_fmc2_nfc *nfc;
1902         struct stm32_fmc2_nand *nand;
1903         struct resource *res;
1904         struct mtd_info *mtd;
1905         struct nand_chip *chip;
1906         struct resource cres;
1907         int chip_cs, mem_region, ret, irq;
1908         int start_region = 0;
1909
1910         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1911         if (!nfc)
1912                 return -ENOMEM;
1913
1914         nfc->dev = dev;
1915         nand_controller_init(&nfc->base);
1916         nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
1917
1918         ret = stm32_fmc2_nfc_set_cdev(nfc);
1919         if (ret)
1920                 return ret;
1921
1922         ret = stm32_fmc2_nfc_parse_dt(nfc);
1923         if (ret)
1924                 return ret;
1925
1926         ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
1927         if (ret)
1928                 return ret;
1929
1930         nfc->io_phys_addr = cres.start;
1931
1932         nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
1933         if (IS_ERR(nfc->regmap))
1934                 return PTR_ERR(nfc->regmap);
1935
1936         if (nfc->dev == nfc->cdev)
1937                 start_region = 1;
1938
1939         for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
1940              chip_cs++, mem_region += 3) {
1941                 if (!(nfc->cs_assigned & BIT(chip_cs)))
1942                         continue;
1943
1944                 nfc->data_base[chip_cs] = devm_platform_get_and_ioremap_resource(pdev,
1945                                                 mem_region, &res);
1946                 if (IS_ERR(nfc->data_base[chip_cs]))
1947                         return PTR_ERR(nfc->data_base[chip_cs]);
1948
1949                 nfc->data_phys_addr[chip_cs] = res->start;
1950
1951                 nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 1);
1952                 if (IS_ERR(nfc->cmd_base[chip_cs]))
1953                         return PTR_ERR(nfc->cmd_base[chip_cs]);
1954
1955                 nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 2);
1956                 if (IS_ERR(nfc->addr_base[chip_cs]))
1957                         return PTR_ERR(nfc->addr_base[chip_cs]);
1958         }
1959
1960         irq = platform_get_irq(pdev, 0);
1961         if (irq < 0)
1962                 return irq;
1963
1964         ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0,
1965                                dev_name(dev), nfc);
1966         if (ret) {
1967                 dev_err(dev, "failed to request irq\n");
1968                 return ret;
1969         }
1970
1971         init_completion(&nfc->complete);
1972
1973         nfc->clk = devm_clk_get_enabled(nfc->cdev, NULL);
1974         if (IS_ERR(nfc->clk)) {
1975                 dev_err(dev, "can not get and enable the clock\n");
1976                 return PTR_ERR(nfc->clk);
1977         }
1978
1979         rstc = devm_reset_control_get(dev, NULL);
1980         if (IS_ERR(rstc)) {
1981                 ret = PTR_ERR(rstc);
1982                 if (ret == -EPROBE_DEFER)
1983                         return ret;
1984         } else {
1985                 reset_control_assert(rstc);
1986                 reset_control_deassert(rstc);
1987         }
1988
1989         ret = stm32_fmc2_nfc_dma_setup(nfc);
1990         if (ret)
1991                 goto err_release_dma;
1992
1993         stm32_fmc2_nfc_init(nfc);
1994
1995         nand = &nfc->nand;
1996         chip = &nand->chip;
1997         mtd = nand_to_mtd(chip);
1998         mtd->dev.parent = dev;
1999
2000         chip->controller = &nfc->base;
2001         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
2002                          NAND_USES_DMA;
2003
2004         stm32_fmc2_nfc_wp_disable(nand);
2005
2006         /* Scan to find existence of the device */
2007         ret = nand_scan(chip, nand->ncs);
2008         if (ret)
2009                 goto err_wp_enable;
2010
2011         ret = mtd_device_register(mtd, NULL, 0);
2012         if (ret)
2013                 goto err_nand_cleanup;
2014
2015         platform_set_drvdata(pdev, nfc);
2016
2017         return 0;
2018
2019 err_nand_cleanup:
2020         nand_cleanup(chip);
2021
2022 err_wp_enable:
2023         stm32_fmc2_nfc_wp_enable(nand);
2024
2025 err_release_dma:
2026         if (nfc->dma_ecc_ch)
2027                 dma_release_channel(nfc->dma_ecc_ch);
2028         if (nfc->dma_tx_ch)
2029                 dma_release_channel(nfc->dma_tx_ch);
2030         if (nfc->dma_rx_ch)
2031                 dma_release_channel(nfc->dma_rx_ch);
2032
2033         sg_free_table(&nfc->dma_data_sg);
2034         sg_free_table(&nfc->dma_ecc_sg);
2035
2036         return ret;
2037 }
2038
2039 static void stm32_fmc2_nfc_remove(struct platform_device *pdev)
2040 {
2041         struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev);
2042         struct stm32_fmc2_nand *nand = &nfc->nand;
2043         struct nand_chip *chip = &nand->chip;
2044         int ret;
2045
2046         ret = mtd_device_unregister(nand_to_mtd(chip));
2047         WARN_ON(ret);
2048         nand_cleanup(chip);
2049
2050         if (nfc->dma_ecc_ch)
2051                 dma_release_channel(nfc->dma_ecc_ch);
2052         if (nfc->dma_tx_ch)
2053                 dma_release_channel(nfc->dma_tx_ch);
2054         if (nfc->dma_rx_ch)
2055                 dma_release_channel(nfc->dma_rx_ch);
2056
2057         sg_free_table(&nfc->dma_data_sg);
2058         sg_free_table(&nfc->dma_ecc_sg);
2059
2060         stm32_fmc2_nfc_wp_enable(nand);
2061 }
2062
2063 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
2064 {
2065         struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2066         struct stm32_fmc2_nand *nand = &nfc->nand;
2067
2068         clk_disable_unprepare(nfc->clk);
2069
2070         stm32_fmc2_nfc_wp_enable(nand);
2071
2072         pinctrl_pm_select_sleep_state(dev);
2073
2074         return 0;
2075 }
2076
2077 static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
2078 {
2079         struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2080         struct stm32_fmc2_nand *nand = &nfc->nand;
2081         int chip_cs, ret;
2082
2083         pinctrl_pm_select_default_state(dev);
2084
2085         ret = clk_prepare_enable(nfc->clk);
2086         if (ret) {
2087                 dev_err(dev, "can not enable the clock\n");
2088                 return ret;
2089         }
2090
2091         stm32_fmc2_nfc_init(nfc);
2092
2093         stm32_fmc2_nfc_wp_disable(nand);
2094
2095         for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
2096                 if (!(nfc->cs_assigned & BIT(chip_cs)))
2097                         continue;
2098
2099                 nand_reset(&nand->chip, chip_cs);
2100         }
2101
2102         return 0;
2103 }
2104
2105 static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend,
2106                          stm32_fmc2_nfc_resume);
2107
2108 static const struct of_device_id stm32_fmc2_nfc_match[] = {
2109         {.compatible = "st,stm32mp15-fmc2"},
2110         {.compatible = "st,stm32mp1-fmc2-nfc"},
2111         {}
2112 };
2113 MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
2114
2115 static struct platform_driver stm32_fmc2_nfc_driver = {
2116         .probe  = stm32_fmc2_nfc_probe,
2117         .remove_new = stm32_fmc2_nfc_remove,
2118         .driver = {
2119                 .name = "stm32_fmc2_nfc",
2120                 .of_match_table = stm32_fmc2_nfc_match,
2121                 .pm = &stm32_fmc2_nfc_pm_ops,
2122         },
2123 };
2124 module_platform_driver(stm32_fmc2_nfc_driver);
2125
2126 MODULE_ALIAS("platform:stm32_fmc2_nfc");
2127 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
2128 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver");
2129 MODULE_LICENSE("GPL v2");