1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright © 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
10 #define pr_fmt(fmt) "nand-s3c2410: " fmt
12 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/cpufreq.h>
29 #include <linux/of_device.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/rawnand.h>
33 #include <linux/mtd/partitions.h>
35 #include <linux/platform_data/mtd-nand-s3c2410.h>
37 #define S3C2410_NFREG(x) (x)
39 #define S3C2410_NFCONF S3C2410_NFREG(0x00)
40 #define S3C2410_NFCMD S3C2410_NFREG(0x04)
41 #define S3C2410_NFADDR S3C2410_NFREG(0x08)
42 #define S3C2410_NFDATA S3C2410_NFREG(0x0C)
43 #define S3C2410_NFSTAT S3C2410_NFREG(0x10)
44 #define S3C2410_NFECC S3C2410_NFREG(0x14)
45 #define S3C2440_NFCONT S3C2410_NFREG(0x04)
46 #define S3C2440_NFCMD S3C2410_NFREG(0x08)
47 #define S3C2440_NFADDR S3C2410_NFREG(0x0C)
48 #define S3C2440_NFDATA S3C2410_NFREG(0x10)
49 #define S3C2440_NFSTAT S3C2410_NFREG(0x20)
50 #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
51 #define S3C2412_NFSTAT S3C2410_NFREG(0x28)
52 #define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
53 #define S3C2410_NFCONF_EN (1<<15)
54 #define S3C2410_NFCONF_INITECC (1<<12)
55 #define S3C2410_NFCONF_nFCE (1<<11)
56 #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
57 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
58 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
59 #define S3C2410_NFSTAT_BUSY (1<<0)
60 #define S3C2440_NFCONF_TACLS(x) ((x)<<12)
61 #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
62 #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
63 #define S3C2440_NFCONT_INITECC (1<<4)
64 #define S3C2440_NFCONT_nFCE (1<<1)
65 #define S3C2440_NFCONT_ENABLE (1<<0)
66 #define S3C2440_NFSTAT_READY (1<<0)
67 #define S3C2412_NFCONF_NANDBOOT (1<<31)
68 #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
69 #define S3C2412_NFCONT_nFCE0 (1<<1)
70 #define S3C2412_NFSTAT_READY (1<<0)
72 /* new oob placement block for use with hardware ecc generation
74 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
75 struct mtd_oob_region *oobregion)
80 oobregion->offset = 0;
81 oobregion->length = 3;
86 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
87 struct mtd_oob_region *oobregion)
92 oobregion->offset = 8;
93 oobregion->length = 8;
98 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
99 .ecc = s3c2410_ooblayout_ecc,
100 .free = s3c2410_ooblayout_free,
103 /* controller and mtd information */
105 struct s3c2410_nand_info;
108 * struct s3c2410_nand_mtd - driver MTD structure
109 * @mtd: The MTD instance to pass to the MTD layer.
110 * @chip: The NAND chip information.
111 * @set: The platform information supplied for this set of NAND chips.
112 * @info: Link back to the hardware information.
114 struct s3c2410_nand_mtd {
115 struct nand_chip chip;
116 struct s3c2410_nand_set *set;
117 struct s3c2410_nand_info *info;
126 enum s3c_nand_clk_state {
132 /* overview of the s3c2410 nand state */
135 * struct s3c2410_nand_info - NAND controller state.
136 * @controller: Base controller structure.
137 * @mtds: An array of MTD instances on this controller.
138 * @platform: The platform data for this board.
139 * @device: The platform device we bound to.
140 * @clk: The clock resource for this controller.
141 * @regs: The area mapped for the hardware registers.
142 * @sel_reg: Pointer to the register controlling the NAND selection.
143 * @sel_bit: The bit in @sel_reg to select the NAND chip.
144 * @mtd_count: The number of MTDs created from this controller.
145 * @save_sel: The contents of @sel_reg to be saved over suspend.
146 * @clk_rate: The clock rate from @clk.
147 * @clk_state: The current clock state.
148 * @cpu_type: The exact type of this controller.
149 * @freq_transition: CPUFreq notifier block
151 struct s3c2410_nand_info {
153 struct nand_controller controller;
154 struct s3c2410_nand_mtd *mtds;
155 struct s3c2410_platform_nand *platform;
158 struct device *device;
161 void __iomem *sel_reg;
164 unsigned long save_sel;
165 unsigned long clk_rate;
166 enum s3c_nand_clk_state clk_state;
168 enum s3c_cpu_type cpu_type;
170 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
171 struct notifier_block freq_transition;
175 struct s3c24XX_nand_devtype_data {
176 enum s3c_cpu_type type;
179 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
180 .type = TYPE_S3C2410,
183 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
184 .type = TYPE_S3C2412,
187 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
188 .type = TYPE_S3C2440,
191 /* conversion functions */
193 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
195 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
199 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
201 return s3c2410_nand_mtd_toours(mtd)->info;
204 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
206 return platform_get_drvdata(dev);
209 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
211 return dev_get_platdata(&dev->dev);
214 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
216 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
224 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
225 * @info: The controller instance.
226 * @new_state: State to which clock should be set.
228 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
229 enum s3c_nand_clk_state new_state)
231 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
234 if (info->clk_state == CLOCK_ENABLE) {
235 if (new_state != CLOCK_ENABLE)
236 clk_disable_unprepare(info->clk);
238 if (new_state == CLOCK_ENABLE)
239 clk_prepare_enable(info->clk);
242 info->clk_state = new_state;
245 /* timing calculations */
247 #define NS_IN_KHZ 1000000
250 * s3c_nand_calc_rate - calculate timing data.
251 * @wanted: The cycle time in nanoseconds.
252 * @clk: The clock rate in kHz.
253 * @max: The maximum divider value.
255 * Calculate the timing value from the given parameters.
257 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
261 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
263 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
266 pr_err("%d ns is too big for current clock rate %ld\n",
277 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
279 /* controller setup */
282 * s3c2410_nand_setrate - setup controller timing information.
283 * @info: The controller instance.
285 * Given the information supplied by the platform, calculate and set
286 * the necessary timing registers in the hardware to generate the
287 * necessary timing cycles to the hardware.
289 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
291 struct s3c2410_platform_nand *plat = info->platform;
292 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
293 int tacls, twrph0, twrph1;
294 unsigned long clkrate = clk_get_rate(info->clk);
295 unsigned long set, cfg, mask;
298 /* calculate the timing information for the controller */
300 info->clk_rate = clkrate;
301 clkrate /= 1000; /* turn clock into kHz for ease of use */
304 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
305 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
306 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
308 /* default timings */
314 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
315 dev_err(info->device, "cannot get suitable timings\n");
319 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
320 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
321 twrph1, to_ns(twrph1, clkrate));
323 switch (info->cpu_type) {
325 mask = (S3C2410_NFCONF_TACLS(3) |
326 S3C2410_NFCONF_TWRPH0(7) |
327 S3C2410_NFCONF_TWRPH1(7));
328 set = S3C2410_NFCONF_EN;
329 set |= S3C2410_NFCONF_TACLS(tacls - 1);
330 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
331 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
336 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
337 S3C2440_NFCONF_TWRPH0(7) |
338 S3C2440_NFCONF_TWRPH1(7));
340 set = S3C2440_NFCONF_TACLS(tacls - 1);
341 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
342 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
349 local_irq_save(flags);
351 cfg = readl(info->regs + S3C2410_NFCONF);
354 writel(cfg, info->regs + S3C2410_NFCONF);
356 local_irq_restore(flags);
358 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
364 * s3c2410_nand_inithw - basic hardware initialisation
365 * @info: The hardware state.
367 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
368 * to setup the hardware access speeds and set the controller to be enabled.
370 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
374 ret = s3c2410_nand_setrate(info);
378 switch (info->cpu_type) {
385 /* enable the controller and de-assert nFCE */
387 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
394 * s3c2410_nand_select_chip - select the given nand chip
395 * @this: NAND chip object.
396 * @chip: The chip number.
398 * This is called by the MTD layer to either select a given chip for the
399 * @mtd instance, or to indicate that the access has finished and the
400 * chip can be de-selected.
402 * The routine ensures that the nFCE line is correctly setup, and any
403 * platform specific selection code is called to route nFCE to the specific
406 static void s3c2410_nand_select_chip(struct nand_chip *this, int chip)
408 struct s3c2410_nand_info *info;
409 struct s3c2410_nand_mtd *nmtd;
412 nmtd = nand_get_controller_data(this);
416 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
418 cur = readl(info->sel_reg);
421 cur |= info->sel_bit;
423 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
424 dev_err(info->device, "invalid chip %d\n", chip);
428 if (info->platform != NULL) {
429 if (info->platform->select_chip != NULL)
430 (info->platform->select_chip) (nmtd->set, chip);
433 cur &= ~info->sel_bit;
436 writel(cur, info->sel_reg);
439 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
442 /* s3c2410_nand_hwcontrol
444 * Issue command and address cycles to the chip
447 static void s3c2410_nand_hwcontrol(struct nand_chip *chip, int cmd,
450 struct mtd_info *mtd = nand_to_mtd(chip);
451 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
453 if (cmd == NAND_CMD_NONE)
457 writeb(cmd, info->regs + S3C2410_NFCMD);
459 writeb(cmd, info->regs + S3C2410_NFADDR);
462 /* command and control functions */
464 static void s3c2440_nand_hwcontrol(struct nand_chip *chip, int cmd,
467 struct mtd_info *mtd = nand_to_mtd(chip);
468 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
470 if (cmd == NAND_CMD_NONE)
474 writeb(cmd, info->regs + S3C2440_NFCMD);
476 writeb(cmd, info->regs + S3C2440_NFADDR);
479 /* s3c2410_nand_devready()
481 * returns 0 if the nand is busy, 1 if it is ready
484 static int s3c2410_nand_devready(struct nand_chip *chip)
486 struct mtd_info *mtd = nand_to_mtd(chip);
487 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
488 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
491 static int s3c2440_nand_devready(struct nand_chip *chip)
493 struct mtd_info *mtd = nand_to_mtd(chip);
494 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
495 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
498 static int s3c2412_nand_devready(struct nand_chip *chip)
500 struct mtd_info *mtd = nand_to_mtd(chip);
501 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
502 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
505 /* ECC handling functions */
507 static int s3c2410_nand_correct_data(struct nand_chip *chip, u_char *dat,
508 u_char *read_ecc, u_char *calc_ecc)
510 struct mtd_info *mtd = nand_to_mtd(chip);
511 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
512 unsigned int diff0, diff1, diff2;
513 unsigned int bit, byte;
515 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
517 diff0 = read_ecc[0] ^ calc_ecc[0];
518 diff1 = read_ecc[1] ^ calc_ecc[1];
519 diff2 = read_ecc[2] ^ calc_ecc[2];
521 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
522 __func__, 3, read_ecc, 3, calc_ecc,
523 diff0, diff1, diff2);
525 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
526 return 0; /* ECC is ok */
528 /* sometimes people do not think about using the ECC, so check
529 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
530 * the error, on the assumption that this is an un-eccd page.
532 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
533 && info->platform->ignore_unset_ecc)
536 /* Can we correct this ECC (ie, one row and column change).
537 * Note, this is similar to the 256 error code on smartmedia */
539 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
540 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
541 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
542 /* calculate the bit position of the error */
544 bit = ((diff2 >> 3) & 1) |
548 /* calculate the byte position of the error */
550 byte = ((diff2 << 7) & 0x100) |
551 ((diff1 << 0) & 0x80) |
552 ((diff1 << 1) & 0x40) |
553 ((diff1 << 2) & 0x20) |
554 ((diff1 << 3) & 0x10) |
555 ((diff0 >> 4) & 0x08) |
556 ((diff0 >> 3) & 0x04) |
557 ((diff0 >> 2) & 0x02) |
558 ((diff0 >> 1) & 0x01);
560 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
563 dat[byte] ^= (1 << bit);
567 /* if there is only one bit difference in the ECC, then
568 * one of only a row or column parity has changed, which
569 * means the error is most probably in the ECC itself */
571 diff0 |= (diff1 << 8);
572 diff0 |= (diff2 << 16);
574 /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
575 if ((diff0 & (diff0 - 1)) == 0)
583 * These allow the s3c2410 and s3c2440 to use the controller's ECC
584 * generator block to ECC the data as it passes through]
587 static void s3c2410_nand_enable_hwecc(struct nand_chip *chip, int mode)
589 struct s3c2410_nand_info *info;
592 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
593 ctrl = readl(info->regs + S3C2410_NFCONF);
594 ctrl |= S3C2410_NFCONF_INITECC;
595 writel(ctrl, info->regs + S3C2410_NFCONF);
598 static void s3c2412_nand_enable_hwecc(struct nand_chip *chip, int mode)
600 struct s3c2410_nand_info *info;
603 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
604 ctrl = readl(info->regs + S3C2440_NFCONT);
605 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
606 info->regs + S3C2440_NFCONT);
609 static void s3c2440_nand_enable_hwecc(struct nand_chip *chip, int mode)
611 struct s3c2410_nand_info *info;
614 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
615 ctrl = readl(info->regs + S3C2440_NFCONT);
616 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
619 static int s3c2410_nand_calculate_ecc(struct nand_chip *chip,
620 const u_char *dat, u_char *ecc_code)
622 struct mtd_info *mtd = nand_to_mtd(chip);
623 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
625 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
626 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
627 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
629 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
634 static int s3c2412_nand_calculate_ecc(struct nand_chip *chip,
635 const u_char *dat, u_char *ecc_code)
637 struct mtd_info *mtd = nand_to_mtd(chip);
638 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
639 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
642 ecc_code[1] = ecc >> 8;
643 ecc_code[2] = ecc >> 16;
645 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
650 static int s3c2440_nand_calculate_ecc(struct nand_chip *chip,
651 const u_char *dat, u_char *ecc_code)
653 struct mtd_info *mtd = nand_to_mtd(chip);
654 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
655 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
658 ecc_code[1] = ecc >> 8;
659 ecc_code[2] = ecc >> 16;
661 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
666 /* over-ride the standard functions for a little more speed. We can
667 * use read/write block to move the data buffers to/from the controller
670 static void s3c2410_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
672 readsb(this->legacy.IO_ADDR_R, buf, len);
675 static void s3c2440_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
677 struct mtd_info *mtd = nand_to_mtd(this);
678 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
680 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
682 /* cleanup if we've got less than a word to do */
686 for (; len & 3; len--)
687 *buf++ = readb(info->regs + S3C2440_NFDATA);
691 static void s3c2410_nand_write_buf(struct nand_chip *this, const u_char *buf,
694 writesb(this->legacy.IO_ADDR_W, buf, len);
697 static void s3c2440_nand_write_buf(struct nand_chip *this, const u_char *buf,
700 struct mtd_info *mtd = nand_to_mtd(this);
701 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
703 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
705 /* cleanup any fractional write */
709 for (; len & 3; len--, buf++)
710 writeb(*buf, info->regs + S3C2440_NFDATA);
714 /* cpufreq driver support */
716 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
718 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
719 unsigned long val, void *data)
721 struct s3c2410_nand_info *info;
722 unsigned long newclk;
724 info = container_of(nb, struct s3c2410_nand_info, freq_transition);
725 newclk = clk_get_rate(info->clk);
727 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
728 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
729 s3c2410_nand_setrate(info);
735 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
737 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
739 return cpufreq_register_notifier(&info->freq_transition,
740 CPUFREQ_TRANSITION_NOTIFIER);
744 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
746 cpufreq_unregister_notifier(&info->freq_transition,
747 CPUFREQ_TRANSITION_NOTIFIER);
751 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
757 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
762 /* device management functions */
764 static int s3c24xx_nand_remove(struct platform_device *pdev)
766 struct s3c2410_nand_info *info = to_nand_info(pdev);
771 s3c2410_nand_cpufreq_deregister(info);
773 /* Release all our mtds and their partitions, then go through
774 * freeing the resources used
777 if (info->mtds != NULL) {
778 struct s3c2410_nand_mtd *ptr = info->mtds;
781 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
782 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
783 WARN_ON(mtd_device_unregister(nand_to_mtd(&ptr->chip)));
784 nand_cleanup(&ptr->chip);
788 /* free the common resources */
790 if (!IS_ERR(info->clk))
791 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
796 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
797 struct s3c2410_nand_mtd *mtd,
798 struct s3c2410_nand_set *set)
801 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
803 mtdinfo->name = set->name;
805 return mtd_device_register(mtdinfo, set->partitions,
812 static int s3c2410_nand_setup_interface(struct nand_chip *chip, int csline,
813 const struct nand_interface_config *conf)
815 struct mtd_info *mtd = nand_to_mtd(chip);
816 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
817 struct s3c2410_platform_nand *pdata = info->platform;
818 const struct nand_sdr_timings *timings;
821 timings = nand_get_sdr_timings(conf);
825 tacls = timings->tCLS_min - timings->tWP_min;
829 pdata->tacls = DIV_ROUND_UP(tacls, 1000);
830 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
831 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
833 return s3c2410_nand_setrate(info);
837 * s3c2410_nand_init_chip - initialise a single instance of an chip
838 * @info: The base NAND controller the chip is on.
839 * @nmtd: The new controller MTD instance to fill in.
840 * @set: The information passed from the board specific platform data.
842 * Initialise the given @nmtd from the information in @info and @set. This
843 * readies the structure for use with the MTD layer functions by ensuring
844 * all pointers are setup and the necessary control routines selected.
846 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
847 struct s3c2410_nand_mtd *nmtd,
848 struct s3c2410_nand_set *set)
850 struct device_node *np = info->device->of_node;
851 struct nand_chip *chip = &nmtd->chip;
852 void __iomem *regs = info->regs;
854 nand_set_flash_node(chip, set->of_node);
856 chip->legacy.write_buf = s3c2410_nand_write_buf;
857 chip->legacy.read_buf = s3c2410_nand_read_buf;
858 chip->legacy.select_chip = s3c2410_nand_select_chip;
859 chip->legacy.chip_delay = 50;
860 nand_set_controller_data(chip, nmtd);
861 chip->options = set->options;
862 chip->controller = &info->controller;
865 * let's keep behavior unchanged for legacy boards booting via pdata and
866 * auto-detect timings only when booting with a device tree.
869 chip->options |= NAND_KEEP_TIMINGS;
871 switch (info->cpu_type) {
873 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
874 info->sel_reg = regs + S3C2410_NFCONF;
875 info->sel_bit = S3C2410_NFCONF_nFCE;
876 chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol;
877 chip->legacy.dev_ready = s3c2410_nand_devready;
881 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
882 info->sel_reg = regs + S3C2440_NFCONT;
883 info->sel_bit = S3C2440_NFCONT_nFCE;
884 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
885 chip->legacy.dev_ready = s3c2440_nand_devready;
886 chip->legacy.read_buf = s3c2440_nand_read_buf;
887 chip->legacy.write_buf = s3c2440_nand_write_buf;
891 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
892 info->sel_reg = regs + S3C2440_NFCONT;
893 info->sel_bit = S3C2412_NFCONT_nFCE0;
894 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
895 chip->legacy.dev_ready = s3c2412_nand_devready;
897 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
898 dev_info(info->device, "System booted from NAND\n");
903 chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
908 chip->ecc.engine_type = info->platform->engine_type;
911 * If you use u-boot BBT creation code, specifying this flag will
912 * let the kernel fish out the BBT from the NAND.
915 chip->bbt_options |= NAND_BBT_USE_FLASH;
919 * s3c2410_nand_attach_chip - Init the ECC engine after NAND scan
920 * @chip: The NAND chip
922 * This hook is called by the core after the identification of the NAND chip,
923 * once the relevant per-chip information is up to date.. This call ensure that
924 * we update the internal state accordingly.
926 * The internal state is currently limited to the ECC state information.
928 static int s3c2410_nand_attach_chip(struct nand_chip *chip)
930 struct mtd_info *mtd = nand_to_mtd(chip);
931 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
933 switch (chip->ecc.engine_type) {
935 case NAND_ECC_ENGINE_TYPE_NONE:
936 dev_info(info->device, "ECC disabled\n");
939 case NAND_ECC_ENGINE_TYPE_SOFT:
941 * This driver expects Hamming based ECC when engine_type is set
942 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to
943 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ecc_algo field
944 * to s3c2410_platform_nand.
946 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
947 dev_info(info->device, "soft ECC\n");
950 case NAND_ECC_ENGINE_TYPE_ON_HOST:
951 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
952 chip->ecc.correct = s3c2410_nand_correct_data;
953 chip->ecc.strength = 1;
955 switch (info->cpu_type) {
957 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
958 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
962 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
963 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
967 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
968 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
972 dev_dbg(info->device, "chip %p => page shift %d\n",
973 chip, chip->page_shift);
975 /* change the behaviour depending on whether we are using
976 * the large or small page nand device */
977 if (chip->page_shift > 10) {
978 chip->ecc.size = 256;
981 chip->ecc.size = 512;
983 mtd_set_ooblayout(nand_to_mtd(chip),
984 &s3c2410_ooblayout_ops);
987 dev_info(info->device, "hardware ECC\n");
991 dev_err(info->device, "invalid ECC mode!\n");
995 if (chip->bbt_options & NAND_BBT_USE_FLASH)
996 chip->options |= NAND_SKIP_BBTSCAN;
1001 static const struct nand_controller_ops s3c24xx_nand_controller_ops = {
1002 .attach_chip = s3c2410_nand_attach_chip,
1003 .setup_interface = s3c2410_nand_setup_interface,
1006 static const struct of_device_id s3c24xx_nand_dt_ids[] = {
1008 .compatible = "samsung,s3c2410-nand",
1009 .data = &s3c2410_nand_devtype_data,
1011 /* also compatible with s3c6400 */
1012 .compatible = "samsung,s3c2412-nand",
1013 .data = &s3c2412_nand_devtype_data,
1015 .compatible = "samsung,s3c2440-nand",
1016 .data = &s3c2440_nand_devtype_data,
1020 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
1022 static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
1024 const struct s3c24XX_nand_devtype_data *devtype_data;
1025 struct s3c2410_platform_nand *pdata;
1026 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1027 struct device_node *np = pdev->dev.of_node, *child;
1028 struct s3c2410_nand_set *sets;
1030 devtype_data = of_device_get_match_data(&pdev->dev);
1034 info->cpu_type = devtype_data->type;
1036 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1040 pdev->dev.platform_data = pdata;
1042 pdata->nr_sets = of_get_child_count(np);
1043 if (!pdata->nr_sets)
1046 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets),
1053 for_each_available_child_of_node(np, child) {
1054 sets->name = (char *)child->name;
1055 sets->of_node = child;
1066 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
1068 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1070 info->cpu_type = platform_get_device_id(pdev)->driver_data;
1075 /* s3c24xx_nand_probe
1077 * called by device layer when it finds a device matching
1078 * one our driver can handled. This code checks to see if
1079 * it can allocate all necessary resources then calls the
1080 * nand layer to look for devices
1082 static int s3c24xx_nand_probe(struct platform_device *pdev)
1084 struct s3c2410_platform_nand *plat;
1085 struct s3c2410_nand_info *info;
1086 struct s3c2410_nand_mtd *nmtd;
1087 struct s3c2410_nand_set *sets;
1088 struct resource *res;
1094 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1100 platform_set_drvdata(pdev, info);
1102 nand_controller_init(&info->controller);
1103 info->controller.ops = &s3c24xx_nand_controller_ops;
1105 /* get the clock source and enable it */
1107 info->clk = devm_clk_get(&pdev->dev, "nand");
1108 if (IS_ERR(info->clk)) {
1109 dev_err(&pdev->dev, "failed to get clock\n");
1114 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1116 if (pdev->dev.of_node)
1117 err = s3c24xx_nand_probe_dt(pdev);
1119 err = s3c24xx_nand_probe_pdata(pdev);
1124 plat = to_nand_plat(pdev);
1126 /* allocate and map the resource */
1128 /* currently we assume we have the one resource */
1129 res = pdev->resource;
1130 size = resource_size(res);
1132 info->device = &pdev->dev;
1133 info->platform = plat;
1135 info->regs = devm_ioremap_resource(&pdev->dev, res);
1136 if (IS_ERR(info->regs)) {
1137 err = PTR_ERR(info->regs);
1141 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1143 if (!plat->sets || plat->nr_sets < 1) {
1149 nr_sets = plat->nr_sets;
1151 info->mtd_count = nr_sets;
1153 /* allocate our information */
1155 size = nr_sets * sizeof(*info->mtds);
1156 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1157 if (info->mtds == NULL) {
1162 /* initialise all possible chips */
1166 for (setno = 0; setno < nr_sets; setno++, nmtd++, sets++) {
1167 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1169 pr_debug("initialising set %d (%p, info %p)\n",
1172 mtd->dev.parent = &pdev->dev;
1173 s3c2410_nand_init_chip(info, nmtd, sets);
1175 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1);
1179 s3c2410_nand_add_partition(info, nmtd, sets);
1182 /* initialise the hardware */
1183 err = s3c2410_nand_inithw(info);
1187 err = s3c2410_nand_cpufreq_register(info);
1189 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1193 if (allow_clk_suspend(info)) {
1194 dev_info(&pdev->dev, "clock idle support enabled\n");
1195 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1201 s3c24xx_nand_remove(pdev);
1211 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1213 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1216 info->save_sel = readl(info->sel_reg);
1218 /* For the moment, we must ensure nFCE is high during
1219 * the time we are suspended. This really should be
1220 * handled by suspending the MTDs we are using, but
1221 * that is currently not the case. */
1223 writel(info->save_sel | info->sel_bit, info->sel_reg);
1225 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1231 static int s3c24xx_nand_resume(struct platform_device *dev)
1233 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1237 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1238 s3c2410_nand_inithw(info);
1240 /* Restore the state of the nFCE line. */
1242 sel = readl(info->sel_reg);
1243 sel &= ~info->sel_bit;
1244 sel |= info->save_sel & info->sel_bit;
1245 writel(sel, info->sel_reg);
1247 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1254 #define s3c24xx_nand_suspend NULL
1255 #define s3c24xx_nand_resume NULL
1258 /* driver device registration */
1260 static const struct platform_device_id s3c24xx_driver_ids[] = {
1262 .name = "s3c2410-nand",
1263 .driver_data = TYPE_S3C2410,
1265 .name = "s3c2440-nand",
1266 .driver_data = TYPE_S3C2440,
1268 .name = "s3c2412-nand",
1269 .driver_data = TYPE_S3C2412,
1271 .name = "s3c6400-nand",
1272 .driver_data = TYPE_S3C2412, /* compatible with 2412 */
1277 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1279 static struct platform_driver s3c24xx_nand_driver = {
1280 .probe = s3c24xx_nand_probe,
1281 .remove = s3c24xx_nand_remove,
1282 .suspend = s3c24xx_nand_suspend,
1283 .resume = s3c24xx_nand_resume,
1284 .id_table = s3c24xx_driver_ids,
1286 .name = "s3c24xx-nand",
1287 .of_match_table = s3c24xx_nand_dt_ids,
1291 module_platform_driver(s3c24xx_nand_driver);
1293 MODULE_LICENSE("GPL");
1294 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1295 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");