drivers/mtd/nand/raw/qcom_nandc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/slab.h>
   8 #include <linux/bitops.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/dmaengine.h>
  11 #include <linux/module.h>
  12 #include <linux/mtd/rawnand.h>
  13 #include <linux/mtd/partitions.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma/qcom_bam_dma.h>
  18
  19 /* NANDc reg offsets */
  20 #define NAND_FLASH_CMD                  0x00
  21 #define NAND_ADDR0                      0x04
  22 #define NAND_ADDR1                      0x08
  23 #define NAND_FLASH_CHIP_SELECT          0x0c
  24 #define NAND_EXEC_CMD                   0x10
  25 #define NAND_FLASH_STATUS               0x14
  26 #define NAND_BUFFER_STATUS              0x18
  27 #define NAND_DEV0_CFG0                  0x20
  28 #define NAND_DEV0_CFG1                  0x24
  29 #define NAND_DEV0_ECC_CFG               0x28
  30 #define NAND_AUTO_STATUS_EN             0x2c
  31 #define NAND_DEV1_CFG0                  0x30
  32 #define NAND_DEV1_CFG1                  0x34
  33 #define NAND_READ_ID                    0x40
  34 #define NAND_READ_STATUS                0x44
  35 #define NAND_DEV_CMD0                   0xa0
  36 #define NAND_DEV_CMD1                   0xa4
  37 #define NAND_DEV_CMD2                   0xa8
  38 #define NAND_DEV_CMD_VLD                0xac
  39 #define SFLASHC_BURST_CFG               0xe0
  40 #define NAND_ERASED_CW_DETECT_CFG       0xe8
  41 #define NAND_ERASED_CW_DETECT_STATUS    0xec
  42 #define NAND_EBI2_ECC_BUF_CFG           0xf0
  43 #define FLASH_BUF_ACC                   0x100
  44
  45 #define NAND_CTRL                       0xf00
  46 #define NAND_VERSION                    0xf08
  47 #define NAND_READ_LOCATION_0            0xf20
  48 #define NAND_READ_LOCATION_1            0xf24
  49 #define NAND_READ_LOCATION_2            0xf28
  50 #define NAND_READ_LOCATION_3            0xf2c
  51 #define NAND_READ_LOCATION_LAST_CW_0    0xf40
  52 #define NAND_READ_LOCATION_LAST_CW_1    0xf44
  53 #define NAND_READ_LOCATION_LAST_CW_2    0xf48
  54 #define NAND_READ_LOCATION_LAST_CW_3    0xf4c
  55
  56 /* dummy register offsets, used by write_reg_dma */
  57 #define NAND_DEV_CMD1_RESTORE           0xdead
  58 #define NAND_DEV_CMD_VLD_RESTORE        0xbeef
  59
  60 /* NAND_FLASH_CMD bits */
  61 #define PAGE_ACC                        BIT(4)
  62 #define LAST_PAGE                       BIT(5)
  63
  64 /* NAND_FLASH_CHIP_SELECT bits */
  65 #define NAND_DEV_SEL                    0
  66 #define DM_EN                           BIT(2)
  67
  68 /* NAND_FLASH_STATUS bits */
  69 #define FS_OP_ERR                       BIT(4)
  70 #define FS_READY_BSY_N                  BIT(5)
  71 #define FS_MPU_ERR                      BIT(8)
  72 #define FS_DEVICE_STS_ERR               BIT(16)
  73 #define FS_DEVICE_WP                    BIT(23)
  74
  75 /* NAND_BUFFER_STATUS bits */
  76 #define BS_UNCORRECTABLE_BIT            BIT(8)
  77 #define BS_CORRECTABLE_ERR_MSK          0x1f
  78
  79 /* NAND_DEVn_CFG0 bits */
  80 #define DISABLE_STATUS_AFTER_WRITE      4
  81 #define CW_PER_PAGE                     6
  82 #define UD_SIZE_BYTES                   9
  83 #define ECC_PARITY_SIZE_BYTES_RS        19
  84 #define SPARE_SIZE_BYTES                23
  85 #define NUM_ADDR_CYCLES                 27
  86 #define STATUS_BFR_READ                 30
  87 #define SET_RD_MODE_AFTER_STATUS        31
  88
  89 /* NAND_DEVn_CFG0 bits */
  90 #define DEV0_CFG1_ECC_DISABLE           0
  91 #define WIDE_FLASH                      1
  92 #define NAND_RECOVERY_CYCLES            2
  93 #define CS_ACTIVE_BSY                   5
  94 #define BAD_BLOCK_BYTE_NUM              6
  95 #define BAD_BLOCK_IN_SPARE_AREA         16
  96 #define WR_RD_BSY_GAP                   17
  97 #define ENABLE_BCH_ECC                  27
  98
  99 /* NAND_DEV0_ECC_CFG bits */
 100 #define ECC_CFG_ECC_DISABLE             0
 101 #define ECC_SW_RESET                    1
 102 #define ECC_MODE                        4
 103 #define ECC_PARITY_SIZE_BYTES_BCH       8
 104 #define ECC_NUM_DATA_BYTES              16
 105 #define ECC_FORCE_CLK_OPEN              30
 106
 107 /* NAND_DEV_CMD1 bits */
 108 #define READ_ADDR                       0
 109
 110 /* NAND_DEV_CMD_VLD bits */
 111 #define READ_START_VLD                  BIT(0)
 112 #define READ_STOP_VLD                   BIT(1)
 113 #define WRITE_START_VLD                 BIT(2)
 114 #define ERASE_START_VLD                 BIT(3)
 115 #define SEQ_READ_START_VLD              BIT(4)
 116
 117 /* NAND_EBI2_ECC_BUF_CFG bits */
 118 #define NUM_STEPS                       0
 119
 120 /* NAND_ERASED_CW_DETECT_CFG bits */
 121 #define ERASED_CW_ECC_MASK              1
 122 #define AUTO_DETECT_RES                 0
 123 #define MASK_ECC                        (1 << ERASED_CW_ECC_MASK)
 124 #define RESET_ERASED_DET                (1 << AUTO_DETECT_RES)
 125 #define ACTIVE_ERASED_DET               (0 << AUTO_DETECT_RES)
 126 #define CLR_ERASED_PAGE_DET             (RESET_ERASED_DET | MASK_ECC)
 127 #define SET_ERASED_PAGE_DET             (ACTIVE_ERASED_DET | MASK_ECC)
 128
 129 /* NAND_ERASED_CW_DETECT_STATUS bits */
 130 #define PAGE_ALL_ERASED                 BIT(7)
 131 #define CODEWORD_ALL_ERASED             BIT(6)
 132 #define PAGE_ERASED                     BIT(5)
 133 #define CODEWORD_ERASED                 BIT(4)
 134 #define ERASED_PAGE                     (PAGE_ALL_ERASED | PAGE_ERASED)
 135 #define ERASED_CW                       (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
 136
 137 /* NAND_READ_LOCATION_n bits */
 138 #define READ_LOCATION_OFFSET            0
 139 #define READ_LOCATION_SIZE              16
 140 #define READ_LOCATION_LAST              31
 141
 142 /* Version Mask */
 143 #define NAND_VERSION_MAJOR_MASK         0xf0000000
 144 #define NAND_VERSION_MAJOR_SHIFT        28
 145 #define NAND_VERSION_MINOR_MASK         0x0fff0000
 146 #define NAND_VERSION_MINOR_SHIFT        16
 147
 148 /* NAND OP_CMDs */
 149 #define OP_PAGE_READ                    0x2
 150 #define OP_PAGE_READ_WITH_ECC           0x3
 151 #define OP_PAGE_READ_WITH_ECC_SPARE     0x4
 152 #define OP_PAGE_READ_ONFI_READ          0x5
 153 #define OP_PROGRAM_PAGE                 0x6
 154 #define OP_PAGE_PROGRAM_WITH_ECC        0x7
 155 #define OP_PROGRAM_PAGE_SPARE           0x9
 156 #define OP_BLOCK_ERASE                  0xa
 157 #define OP_FETCH_ID                     0xb
 158 #define OP_RESET_DEVICE                 0xd
 159
 160 /* Default Value for NAND_DEV_CMD_VLD */
 161 #define NAND_DEV_CMD_VLD_VAL            (READ_START_VLD | WRITE_START_VLD | \
 162                                          ERASE_START_VLD | SEQ_READ_START_VLD)
 163
 164 /* NAND_CTRL bits */
 165 #define BAM_MODE_EN                     BIT(0)
 166
 167 /*
 168  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
 169  * the driver calls the chunks 'step' or 'codeword' interchangeably
 170  */
 171 #define NANDC_STEP_SIZE                 512
 172
 173 /*
 174  * the largest page size we support is 8K, this will have 16 steps/codewords
 175  * of 512 bytes each
 176  */
 177 #define MAX_NUM_STEPS                   (SZ_8K / NANDC_STEP_SIZE)
 178
 179 /* we read at most 3 registers per codeword scan */
 180 #define MAX_REG_RD                      (3 * MAX_NUM_STEPS)
 181
 182 /* ECC modes supported by the controller */
 183 #define ECC_NONE        BIT(0)
 184 #define ECC_RS_4BIT     BIT(1)
 185 #define ECC_BCH_4BIT    BIT(2)
 186 #define ECC_BCH_8BIT    BIT(3)
 187
 188 #define nandc_set_read_loc_first(chip, reg, cw_offset, read_size, is_last_read_loc)     \
 189 nandc_set_reg(chip, reg,                        \
 190               ((cw_offset) << READ_LOCATION_OFFSET) |           \
 191               ((read_size) << READ_LOCATION_SIZE) |                     \
 192               ((is_last_read_loc) << READ_LOCATION_LAST))
 193
 194 #define nandc_set_read_loc_last(chip, reg, cw_offset, read_size, is_last_read_loc)      \
 195 nandc_set_reg(chip, reg,                        \
 196               ((cw_offset) << READ_LOCATION_OFFSET) |           \
 197               ((read_size) << READ_LOCATION_SIZE) |                     \
 198               ((is_last_read_loc) << READ_LOCATION_LAST))
 199 /*
 200  * Returns the actual register address for all NAND_DEV_ registers
 201  * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
 202  */
 203 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
 204
 205 /* Returns the NAND register physical address */
 206 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
 207
 208 /* Returns the dma address for reg read buffer */
 209 #define reg_buf_dma_addr(chip, vaddr) \
 210         ((chip)->reg_read_dma + \
 211         ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
 212
 213 #define QPIC_PER_CW_CMD_ELEMENTS        32
 214 #define QPIC_PER_CW_CMD_SGL             32
 215 #define QPIC_PER_CW_DATA_SGL            8
 216
 217 #define QPIC_NAND_COMPLETION_TIMEOUT    msecs_to_jiffies(2000)
 218
 219 /*
 220  * Flags used in DMA descriptor preparation helper functions
 221  * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
 222  */
 223 /* Don't set the EOT in current tx BAM sgl */
 224 #define NAND_BAM_NO_EOT                 BIT(0)
 225 /* Set the NWD flag in current BAM sgl */
 226 #define NAND_BAM_NWD                    BIT(1)
 227 /* Finish writing in the current BAM sgl and start writing in another BAM sgl */
 228 #define NAND_BAM_NEXT_SGL               BIT(2)
 229 /*
 230  * Erased codeword status is being used two times in single transfer so this
 231  * flag will determine the current value of erased codeword status register
 232  */
 233 #define NAND_ERASED_CW_SET              BIT(4)
 234
 235 /*
 236  * This data type corresponds to the BAM transaction which will be used for all
 237  * NAND transfers.
 238  * @bam_ce - the array of BAM command elements
 239  * @cmd_sgl - sgl for NAND BAM command pipe
 240  * @data_sgl - sgl for NAND BAM consumer/producer pipe
 241  * @bam_ce_pos - the index in bam_ce which is available for next sgl
 242  * @bam_ce_start - the index in bam_ce which marks the start position ce
 243  *                 for current sgl. It will be used for size calculation
 244  *                 for current sgl
 245  * @cmd_sgl_pos - current index in command sgl.
 246  * @cmd_sgl_start - start index in command sgl.
 247  * @tx_sgl_pos - current index in data sgl for tx.
 248  * @tx_sgl_start - start index in data sgl for tx.
 249  * @rx_sgl_pos - current index in data sgl for rx.
 250  * @rx_sgl_start - start index in data sgl for rx.
 251  * @wait_second_completion - wait for second DMA desc completion before making
 252  *                           the NAND transfer completion.
 253  * @txn_done - completion for NAND transfer.
 254  * @last_data_desc - last DMA desc in data channel (tx/rx).
 255  * @last_cmd_desc - last DMA desc in command channel.
 256  */
 257 struct bam_transaction {
 258         struct bam_cmd_element *bam_ce;
 259         struct scatterlist *cmd_sgl;
 260         struct scatterlist *data_sgl;
 261         u32 bam_ce_pos;
 262         u32 bam_ce_start;
 263         u32 cmd_sgl_pos;
 264         u32 cmd_sgl_start;
 265         u32 tx_sgl_pos;
 266         u32 tx_sgl_start;
 267         u32 rx_sgl_pos;
 268         u32 rx_sgl_start;
 269         bool wait_second_completion;
 270         struct completion txn_done;
 271         struct dma_async_tx_descriptor *last_data_desc;
 272         struct dma_async_tx_descriptor *last_cmd_desc;
 273 };
 274
 275 /*
 276  * This data type corresponds to the nand dma descriptor
 277  * @list - list for desc_info
 278  * @dir - DMA transfer direction
 279  * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
 280  *            ADM
 281  * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
 282  * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
 283  * @dma_desc - low level DMA engine descriptor
 284  */
 285 struct desc_info {
 286         struct list_head node;
 287
 288         enum dma_data_direction dir;
 289         union {
 290                 struct scatterlist adm_sgl;
 291                 struct {
 292                         struct scatterlist *bam_sgl;
 293                         int sgl_cnt;
 294                 };
 295         };
 296         struct dma_async_tx_descriptor *dma_desc;
 297 };
 298
 299 /*
 300  * holds the current register values that we want to write. acts as a contiguous
 301  * chunk of memory which we use to write the controller registers through DMA.
 302  */
 303 struct nandc_regs {
 304         __le32 cmd;
 305         __le32 addr0;
 306         __le32 addr1;
 307         __le32 chip_sel;
 308         __le32 exec;
 309
 310         __le32 cfg0;
 311         __le32 cfg1;
 312         __le32 ecc_bch_cfg;
 313
 314         __le32 clrflashstatus;
 315         __le32 clrreadstatus;
 316
 317         __le32 cmd1;
 318         __le32 vld;
 319
 320         __le32 orig_cmd1;
 321         __le32 orig_vld;
 322
 323         __le32 ecc_buf_cfg;
 324         __le32 read_location0;
 325         __le32 read_location1;
 326         __le32 read_location2;
 327         __le32 read_location3;
 328         __le32 read_location_last0;
 329         __le32 read_location_last1;
 330         __le32 read_location_last2;
 331         __le32 read_location_last3;
 332
 333         __le32 erased_cw_detect_cfg_clr;
 334         __le32 erased_cw_detect_cfg_set;
 335 };
 336
 337 /*
 338  * NAND controller data struct
 339  *
 340  * @controller:                 base controller structure
 341  * @host_list:                  list containing all the chips attached to the
 342  *                              controller
 343  * @dev:                        parent device
 344  * @base:                       MMIO base
 345  * @base_phys:                  physical base address of controller registers
 346  * @base_dma:                   dma base address of controller registers
 347  * @core_clk:                   controller clock
 348  * @aon_clk:                    another controller clock
 349  *
 350  * @chan:                       dma channel
 351  * @cmd_crci:                   ADM DMA CRCI for command flow control
 352  * @data_crci:                  ADM DMA CRCI for data flow control
 353  * @desc_list:                  DMA descriptor list (list of desc_infos)
 354  *
 355  * @data_buffer:                our local DMA buffer for page read/writes,
 356  *                              used when we can't use the buffer provided
 357  *                              by upper layers directly
 358  * @buf_size/count/start:       markers for chip->legacy.read_buf/write_buf
 359  *                              functions
 360  * @reg_read_buf:               local buffer for reading back registers via DMA
 361  * @reg_read_dma:               contains dma address for register read buffer
 362  * @reg_read_pos:               marker for data read in reg_read_buf
 363  *
 364  * @regs:                       a contiguous chunk of memory for DMA register
 365  *                              writes. contains the register values to be
 366  *                              written to controller
 367  * @cmd1/vld:                   some fixed controller register values
 368  * @props:                      properties of current NAND controller,
 369  *                              initialized via DT match data
 370  * @max_cwperpage:              maximum QPIC codewords required. calculated
 371  *                              from all connected NAND devices pagesize
 372  */
 373 struct qcom_nand_controller {
 374         struct nand_controller controller;
 375         struct list_head host_list;
 376
 377         struct device *dev;
 378
 379         void __iomem *base;
 380         phys_addr_t base_phys;
 381         dma_addr_t base_dma;
 382
 383         struct clk *core_clk;
 384         struct clk *aon_clk;
 385
 386         union {
 387                 /* will be used only by QPIC for BAM DMA */
 388                 struct {
 389                         struct dma_chan *tx_chan;
 390                         struct dma_chan *rx_chan;
 391                         struct dma_chan *cmd_chan;
 392                 };
 393
 394                 /* will be used only by EBI2 for ADM DMA */
 395                 struct {
 396                         struct dma_chan *chan;
 397                         unsigned int cmd_crci;
 398                         unsigned int data_crci;
 399                 };
 400         };
 401
 402         struct list_head desc_list;
 403         struct bam_transaction *bam_txn;
 404
 405         u8              *data_buffer;
 406         int             buf_size;
 407         int             buf_count;
 408         int             buf_start;
 409         unsigned int    max_cwperpage;
 410
 411         __le32 *reg_read_buf;
 412         dma_addr_t reg_read_dma;
 413         int reg_read_pos;
 414
 415         struct nandc_regs *regs;
 416
 417         u32 cmd1, vld;
 418         const struct qcom_nandc_props *props;
 419 };
 420
 421 /*
 422  * NAND chip structure
 423  *
 424  * @chip:                       base NAND chip structure
 425  * @node:                       list node to add itself to host_list in
 426  *                              qcom_nand_controller
 427  *
 428  * @cs:                         chip select value for this chip
 429  * @cw_size:                    the number of bytes in a single step/codeword
 430  *                              of a page, consisting of all data, ecc, spare
 431  *                              and reserved bytes
 432  * @cw_data:                    the number of bytes within a codeword protected
 433  *                              by ECC
 434  * @use_ecc:                    request the controller to use ECC for the
 435  *                              upcoming read/write
 436  * @bch_enabled:                flag to tell whether BCH ECC mode is used
 437  * @ecc_bytes_hw:               ECC bytes used by controller hardware for this
 438  *                              chip
 439  * @status:                     value to be returned if NAND_CMD_STATUS command
 440  *                              is executed
 441  * @last_command:               keeps track of last command on this chip. used
 442  *                              for reading correct status
 443  *
 444  * @cfg0, cfg1, cfg0_raw..:     NANDc register configurations needed for
 445  *                              ecc/non-ecc mode for the current nand flash
 446  *                              device
 447  */
 448 struct qcom_nand_host {
 449         struct nand_chip chip;
 450         struct list_head node;
 451
 452         int cs;
 453         int cw_size;
 454         int cw_data;
 455         bool use_ecc;
 456         bool bch_enabled;
 457         int ecc_bytes_hw;
 458         int spare_bytes;
 459         int bbm_size;
 460         u8 status;
 461         int last_command;
 462
 463         u32 cfg0, cfg1;
 464         u32 cfg0_raw, cfg1_raw;
 465         u32 ecc_buf_cfg;
 466         u32 ecc_bch_cfg;
 467         u32 clrflashstatus;
 468         u32 clrreadstatus;
 469 };
 470
 471 /*
 472  * This data type corresponds to the NAND controller properties which varies
 473  * among different NAND controllers.
 474  * @ecc_modes - ecc mode for NAND
 475  * @is_bam - whether NAND controller is using BAM
 476  * @is_qpic - whether NAND CTRL is part of qpic IP
 477  * @qpic_v2 - flag to indicate QPIC IP version 2
 478  * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
 479  */
 480 struct qcom_nandc_props {
 481         u32 ecc_modes;
 482         bool is_bam;
 483         bool is_qpic;
 484         bool qpic_v2;
 485         u32 dev_cmd_reg_start;
 486 };
 487
 488 /* Frees the BAM transaction memory */
 489 static void free_bam_transaction(struct qcom_nand_controller *nandc)
 490 {
 491         struct bam_transaction *bam_txn = nandc->bam_txn;
 492
 493         devm_kfree(nandc->dev, bam_txn);
 494 }
 495
 496 /* Allocates and Initializes the BAM transaction */
 497 static struct bam_transaction *
 498 alloc_bam_transaction(struct qcom_nand_controller *nandc)
 499 {
 500         struct bam_transaction *bam_txn;
 501         size_t bam_txn_size;
 502         unsigned int num_cw = nandc->max_cwperpage;
 503         void *bam_txn_buf;
 504
 505         bam_txn_size =
 506                 sizeof(*bam_txn) + num_cw *
 507                 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
 508                 (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
 509                 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
 510
 511         bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
 512         if (!bam_txn_buf)
 513                 return NULL;
 514
 515         bam_txn = bam_txn_buf;
 516         bam_txn_buf += sizeof(*bam_txn);
 517
 518         bam_txn->bam_ce = bam_txn_buf;
 519         bam_txn_buf +=
 520                 sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
 521
 522         bam_txn->cmd_sgl = bam_txn_buf;
 523         bam_txn_buf +=
 524                 sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
 525
 526         bam_txn->data_sgl = bam_txn_buf;
 527
 528         init_completion(&bam_txn->txn_done);
 529
 530         return bam_txn;
 531 }
 532
 533 /* Clears the BAM transaction indexes */
 534 static void clear_bam_transaction(struct qcom_nand_controller *nandc)
 535 {
 536         struct bam_transaction *bam_txn = nandc->bam_txn;
 537
 538         if (!nandc->props->is_bam)
 539                 return;
 540
 541         bam_txn->bam_ce_pos = 0;
 542         bam_txn->bam_ce_start = 0;
 543         bam_txn->cmd_sgl_pos = 0;
 544         bam_txn->cmd_sgl_start = 0;
 545         bam_txn->tx_sgl_pos = 0;
 546         bam_txn->tx_sgl_start = 0;
 547         bam_txn->rx_sgl_pos = 0;
 548         bam_txn->rx_sgl_start = 0;
 549         bam_txn->last_data_desc = NULL;
 550         bam_txn->wait_second_completion = false;
 551
 552         sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
 553                       QPIC_PER_CW_CMD_SGL);
 554         sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
 555                       QPIC_PER_CW_DATA_SGL);
 556
 557         reinit_completion(&bam_txn->txn_done);
 558 }
 559
 560 /* Callback for DMA descriptor completion */
 561 static void qpic_bam_dma_done(void *data)
 562 {
 563         struct bam_transaction *bam_txn = data;
 564
 565         /*
 566          * In case of data transfer with NAND, 2 callbacks will be generated.
 567          * One for command channel and another one for data channel.
 568          * If current transaction has data descriptors
 569          * (i.e. wait_second_completion is true), then set this to false
 570          * and wait for second DMA descriptor completion.
 571          */
 572         if (bam_txn->wait_second_completion)
 573                 bam_txn->wait_second_completion = false;
 574         else
 575                 complete(&bam_txn->txn_done);
 576 }
 577
 578 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 579 {
 580         return container_of(chip, struct qcom_nand_host, chip);
 581 }
 582
 583 static inline struct qcom_nand_controller *
 584 get_qcom_nand_controller(struct nand_chip *chip)
 585 {
 586         return container_of(chip->controller, struct qcom_nand_controller,
 587                             controller);
 588 }
 589
 590 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
 591 {
 592         return ioread32(nandc->base + offset);
 593 }
 594
 595 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
 596                                u32 val)
 597 {
 598         iowrite32(val, nandc->base + offset);
 599 }
 600
 601 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
 602                                           bool is_cpu)
 603 {
 604         if (!nandc->props->is_bam)
 605                 return;
 606
 607         if (is_cpu)
 608                 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
 609                                         MAX_REG_RD *
 610                                         sizeof(*nandc->reg_read_buf),
 611                                         DMA_FROM_DEVICE);
 612         else
 613                 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
 614                                            MAX_REG_RD *
 615                                            sizeof(*nandc->reg_read_buf),
 616                                            DMA_FROM_DEVICE);
 617 }
 618
 619 static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 620 {
 621         switch (offset) {
 622         case NAND_FLASH_CMD:
 623                 return &regs->cmd;
 624         case NAND_ADDR0:
 625                 return &regs->addr0;
 626         case NAND_ADDR1:
 627                 return &regs->addr1;
 628         case NAND_FLASH_CHIP_SELECT:
 629                 return &regs->chip_sel;
 630         case NAND_EXEC_CMD:
 631                 return &regs->exec;
 632         case NAND_FLASH_STATUS:
 633                 return &regs->clrflashstatus;
 634         case NAND_DEV0_CFG0:
 635                 return &regs->cfg0;
 636         case NAND_DEV0_CFG1:
 637                 return &regs->cfg1;
 638         case NAND_DEV0_ECC_CFG:
 639                 return &regs->ecc_bch_cfg;
 640         case NAND_READ_STATUS:
 641                 return &regs->clrreadstatus;
 642         case NAND_DEV_CMD1:
 643                 return &regs->cmd1;
 644         case NAND_DEV_CMD1_RESTORE:
 645                 return &regs->orig_cmd1;
 646         case NAND_DEV_CMD_VLD:
 647                 return &regs->vld;
 648         case NAND_DEV_CMD_VLD_RESTORE:
 649                 return &regs->orig_vld;
 650         case NAND_EBI2_ECC_BUF_CFG:
 651                 return &regs->ecc_buf_cfg;
 652         case NAND_READ_LOCATION_0:
 653                 return &regs->read_location0;
 654         case NAND_READ_LOCATION_1:
 655                 return &regs->read_location1;
 656         case NAND_READ_LOCATION_2:
 657                 return &regs->read_location2;
 658         case NAND_READ_LOCATION_3:
 659                 return &regs->read_location3;
 660         case NAND_READ_LOCATION_LAST_CW_0:
 661                 return &regs->read_location_last0;
 662         case NAND_READ_LOCATION_LAST_CW_1:
 663                 return &regs->read_location_last1;
 664         case NAND_READ_LOCATION_LAST_CW_2:
 665                 return &regs->read_location_last2;
 666         case NAND_READ_LOCATION_LAST_CW_3:
 667                 return &regs->read_location_last3;
 668         default:
 669                 return NULL;
 670         }
 671 }
 672
 673 static void nandc_set_reg(struct nand_chip *chip, int offset,
 674                           u32 val)
 675 {
 676         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 677         struct nandc_regs *regs = nandc->regs;
 678         __le32 *reg;
 679
 680         reg = offset_to_nandc_reg(regs, offset);
 681
 682         if (reg)
 683                 *reg = cpu_to_le32(val);
 684 }
 685
 686 /* Helper to check the code word, whether it is last cw or not */
 687 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
 688 {
 689         return cw == (ecc->steps - 1);
 690 }
 691
 692 /* helper to configure location register values */
 693 static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
 694                                int cw_offset, int read_size, int is_last_read_loc)
 695 {
 696         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 697         struct nand_ecc_ctrl *ecc = &chip->ecc;
 698         int reg_base = NAND_READ_LOCATION_0;
 699
 700         if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
 701                 reg_base = NAND_READ_LOCATION_LAST_CW_0;
 702
 703         reg_base += reg * 4;
 704
 705         if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
 706                 return nandc_set_read_loc_last(chip, reg_base, cw_offset,
 707                                 read_size, is_last_read_loc);
 708         else
 709                 return nandc_set_read_loc_first(chip, reg_base, cw_offset,
 710                                 read_size, is_last_read_loc);
 711 }
 712
 713 /* helper to configure address register values */
 714 static void set_address(struct qcom_nand_host *host, u16 column, int page)
 715 {
 716         struct nand_chip *chip = &host->chip;
 717
 718         if (chip->options & NAND_BUSWIDTH_16)
 719                 column >>= 1;
 720
 721         nandc_set_reg(chip, NAND_ADDR0, page << 16 | column);
 722         nandc_set_reg(chip, NAND_ADDR1, page >> 16 & 0xff);
 723 }
 724
 725 /*
 726  * update_rw_regs:      set up read/write register values, these will be
 727  *                      written to the NAND controller registers via DMA
 728  *
 729  * @num_cw:             number of steps for the read/write operation
 730  * @read:               read or write operation
 731  * @cw  :               which code word
 732  */
 733 static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
 734 {
 735         struct nand_chip *chip = &host->chip;
 736         u32 cmd, cfg0, cfg1, ecc_bch_cfg;
 737
 738         if (read) {
 739                 if (host->use_ecc)
 740                         cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
 741                 else
 742                         cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
 743         } else {
 744                 cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
 745         }
 746
 747         if (host->use_ecc) {
 748                 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) |
 749                                 (num_cw - 1) << CW_PER_PAGE;
 750
 751                 cfg1 = host->cfg1;
 752                 ecc_bch_cfg = host->ecc_bch_cfg;
 753         } else {
 754                 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
 755                                 (num_cw - 1) << CW_PER_PAGE;
 756
 757                 cfg1 = host->cfg1_raw;
 758                 ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
 759         }
 760
 761         nandc_set_reg(chip, NAND_FLASH_CMD, cmd);
 762         nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
 763         nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
 764         nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
 765         nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
 766         nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
 767         nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
 768         nandc_set_reg(chip, NAND_EXEC_CMD, 1);
 769
 770         if (read)
 771                 nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
 772                                    host->cw_data : host->cw_size, 1);
 773 }
 774
 775 /*
 776  * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
 777  * for BAM. This descriptor will be added in the NAND DMA descriptor queue
 778  * which will be submitted to DMA engine.
 779  */
 780 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
 781                                   struct dma_chan *chan,
 782                                   unsigned long flags)
 783 {
 784         struct desc_info *desc;
 785         struct scatterlist *sgl;
 786         unsigned int sgl_cnt;
 787         int ret;
 788         struct bam_transaction *bam_txn = nandc->bam_txn;
 789         enum dma_transfer_direction dir_eng;
 790         struct dma_async_tx_descriptor *dma_desc;
 791
 792         desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 793         if (!desc)
 794                 return -ENOMEM;
 795
 796         if (chan == nandc->cmd_chan) {
 797                 sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
 798                 sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
 799                 bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
 800                 dir_eng = DMA_MEM_TO_DEV;
 801                 desc->dir = DMA_TO_DEVICE;
 802         } else if (chan == nandc->tx_chan) {
 803                 sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
 804                 sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
 805                 bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
 806                 dir_eng = DMA_MEM_TO_DEV;
 807                 desc->dir = DMA_TO_DEVICE;
 808         } else {
 809                 sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
 810                 sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
 811                 bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
 812                 dir_eng = DMA_DEV_TO_MEM;
 813                 desc->dir = DMA_FROM_DEVICE;
 814         }
 815
 816         sg_mark_end(sgl + sgl_cnt - 1);
 817         ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
 818         if (ret == 0) {
 819                 dev_err(nandc->dev, "failure in mapping desc\n");
 820                 kfree(desc);
 821                 return -ENOMEM;
 822         }
 823
 824         desc->sgl_cnt = sgl_cnt;
 825         desc->bam_sgl = sgl;
 826
 827         dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
 828                                            flags);
 829
 830         if (!dma_desc) {
 831                 dev_err(nandc->dev, "failure in prep desc\n");
 832                 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
 833                 kfree(desc);
 834                 return -EINVAL;
 835         }
 836
 837         desc->dma_desc = dma_desc;
 838
 839         /* update last data/command descriptor */
 840         if (chan == nandc->cmd_chan)
 841                 bam_txn->last_cmd_desc = dma_desc;
 842         else
 843                 bam_txn->last_data_desc = dma_desc;
 844
 845         list_add_tail(&desc->node, &nandc->desc_list);
 846
 847         return 0;
 848 }
 849
 850 /*
 851  * Prepares the command descriptor for BAM DMA which will be used for NAND
 852  * register reads and writes. The command descriptor requires the command
 853  * to be formed in command element type so this function uses the command
 854  * element from bam transaction ce array and fills the same with required
 855  * data. A single SGL can contain multiple command elements so
 856  * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
 857  * after the current command element.
 858  */
 859 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
 860                                  int reg_off, const void *vaddr,
 861                                  int size, unsigned int flags)
 862 {
 863         int bam_ce_size;
 864         int i, ret;
 865         struct bam_cmd_element *bam_ce_buffer;
 866         struct bam_transaction *bam_txn = nandc->bam_txn;
 867
 868         bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
 869
 870         /* fill the command desc */
 871         for (i = 0; i < size; i++) {
 872                 if (read)
 873                         bam_prep_ce(&bam_ce_buffer[i],
 874                                     nandc_reg_phys(nandc, reg_off + 4 * i),
 875                                     BAM_READ_COMMAND,
 876                                     reg_buf_dma_addr(nandc,
 877                                                      (__le32 *)vaddr + i));
 878                 else
 879                         bam_prep_ce_le32(&bam_ce_buffer[i],
 880                                          nandc_reg_phys(nandc, reg_off + 4 * i),
 881                                          BAM_WRITE_COMMAND,
 882                                          *((__le32 *)vaddr + i));
 883         }
 884
 885         bam_txn->bam_ce_pos += size;
 886
 887         /* use the separate sgl after this command */
 888         if (flags & NAND_BAM_NEXT_SGL) {
 889                 bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
 890                 bam_ce_size = (bam_txn->bam_ce_pos -
 891                                 bam_txn->bam_ce_start) *
 892                                 sizeof(struct bam_cmd_element);
 893                 sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
 894                            bam_ce_buffer, bam_ce_size);
 895                 bam_txn->cmd_sgl_pos++;
 896                 bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
 897
 898                 if (flags & NAND_BAM_NWD) {
 899                         ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
 900                                                      DMA_PREP_FENCE |
 901                                                      DMA_PREP_CMD);
 902                         if (ret)
 903                                 return ret;
 904                 }
 905         }
 906
 907         return 0;
 908 }
 909
 910 /*
 911  * Prepares the data descriptor for BAM DMA which will be used for NAND
 912  * data reads and writes.
 913  */
 914 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
 915                                   const void *vaddr,
 916                                   int size, unsigned int flags)
 917 {
 918         int ret;
 919         struct bam_transaction *bam_txn = nandc->bam_txn;
 920
 921         if (read) {
 922                 sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
 923                            vaddr, size);
 924                 bam_txn->rx_sgl_pos++;
 925         } else {
 926                 sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
 927                            vaddr, size);
 928                 bam_txn->tx_sgl_pos++;
 929
 930                 /*
 931                  * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
 932                  * is not set, form the DMA descriptor
 933                  */
 934                 if (!(flags & NAND_BAM_NO_EOT)) {
 935                         ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
 936                                                      DMA_PREP_INTERRUPT);
 937                         if (ret)
 938                                 return ret;
 939                 }
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
 946                              int reg_off, const void *vaddr, int size,
 947                              bool flow_control)
 948 {
 949         struct desc_info *desc;
 950         struct dma_async_tx_descriptor *dma_desc;
 951         struct scatterlist *sgl;
 952         struct dma_slave_config slave_conf;
 953         enum dma_transfer_direction dir_eng;
 954         int ret;
 955
 956         desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 957         if (!desc)
 958                 return -ENOMEM;
 959
 960         sgl = &desc->adm_sgl;
 961
 962         sg_init_one(sgl, vaddr, size);
 963
 964         if (read) {
 965                 dir_eng = DMA_DEV_TO_MEM;
 966                 desc->dir = DMA_FROM_DEVICE;
 967         } else {
 968                 dir_eng = DMA_MEM_TO_DEV;
 969                 desc->dir = DMA_TO_DEVICE;
 970         }
 971
 972         ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
 973         if (ret == 0) {
 974                 ret = -ENOMEM;
 975                 goto err;
 976         }
 977
 978         memset(&slave_conf, 0x00, sizeof(slave_conf));
 979
 980         slave_conf.device_fc = flow_control;
 981         if (read) {
 982                 slave_conf.src_maxburst = 16;
 983                 slave_conf.src_addr = nandc->base_dma + reg_off;
 984                 slave_conf.slave_id = nandc->data_crci;
 985         } else {
 986                 slave_conf.dst_maxburst = 16;
 987                 slave_conf.dst_addr = nandc->base_dma + reg_off;
 988                 slave_conf.slave_id = nandc->cmd_crci;
 989         }
 990
 991         ret = dmaengine_slave_config(nandc->chan, &slave_conf);
 992         if (ret) {
 993                 dev_err(nandc->dev, "failed to configure dma channel\n");
 994                 goto err;
 995         }
 996
 997         dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
 998         if (!dma_desc) {
 999                 dev_err(nandc->dev, "failed to prepare desc\n");
1000                 ret = -EINVAL;
1001                 goto err;
1002         }
1003
1004         desc->dma_desc = dma_desc;
1005
1006         list_add_tail(&desc->node, &nandc->desc_list);
1007
1008         return 0;
1009 err:
1010         kfree(desc);
1011
1012         return ret;
1013 }
1014
1015 /*
1016  * read_reg_dma:        prepares a descriptor to read a given number of
1017  *                      contiguous registers to the reg_read_buf pointer
1018  *
1019  * @first:              offset of the first register in the contiguous block
1020  * @num_regs:           number of registers to read
1021  * @flags:              flags to control DMA descriptor preparation
1022  */
1023 static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
1024                         int num_regs, unsigned int flags)
1025 {
1026         bool flow_control = false;
1027         void *vaddr;
1028
1029         vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
1030         nandc->reg_read_pos += num_regs;
1031
1032         if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
1033                 first = dev_cmd_reg_addr(nandc, first);
1034
1035         if (nandc->props->is_bam)
1036                 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
1037                                              num_regs, flags);
1038
1039         if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
1040                 flow_control = true;
1041
1042         return prep_adm_dma_desc(nandc, true, first, vaddr,
1043                                  num_regs * sizeof(u32), flow_control);
1044 }
1045
1046 /*
1047  * write_reg_dma:       prepares a descriptor to write a given number of
1048  *                      contiguous registers
1049  *
1050  * @first:              offset of the first register in the contiguous block
1051  * @num_regs:           number of registers to write
1052  * @flags:              flags to control DMA descriptor preparation
1053  */
1054 static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
1055                          int num_regs, unsigned int flags)
1056 {
1057         bool flow_control = false;
1058         struct nandc_regs *regs = nandc->regs;
1059         void *vaddr;
1060
1061         vaddr = offset_to_nandc_reg(regs, first);
1062
1063         if (first == NAND_ERASED_CW_DETECT_CFG) {
1064                 if (flags & NAND_ERASED_CW_SET)
1065                         vaddr = &regs->erased_cw_detect_cfg_set;
1066                 else
1067                         vaddr = &regs->erased_cw_detect_cfg_clr;
1068         }
1069
1070         if (first == NAND_EXEC_CMD)
1071                 flags |= NAND_BAM_NWD;
1072
1073         if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
1074                 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
1075
1076         if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
1077                 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
1078
1079         if (nandc->props->is_bam)
1080                 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
1081                                              num_regs, flags);
1082
1083         if (first == NAND_FLASH_CMD)
1084                 flow_control = true;
1085
1086         return prep_adm_dma_desc(nandc, false, first, vaddr,
1087                                  num_regs * sizeof(u32), flow_control);
1088 }
1089
1090 /*
1091  * read_data_dma:       prepares a DMA descriptor to transfer data from the
1092  *                      controller's internal buffer to the buffer 'vaddr'
1093  *
1094  * @reg_off:            offset within the controller's data buffer
1095  * @vaddr:              virtual address of the buffer we want to write to
1096  * @size:               DMA transaction size in bytes
1097  * @flags:              flags to control DMA descriptor preparation
1098  */
1099 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
1100                          const u8 *vaddr, int size, unsigned int flags)
1101 {
1102         if (nandc->props->is_bam)
1103                 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
1104
1105         return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
1106 }
1107
1108 /*
1109  * write_data_dma:      prepares a DMA descriptor to transfer data from
1110  *                      'vaddr' to the controller's internal buffer
1111  *
1112  * @reg_off:            offset within the controller's data buffer
1113  * @vaddr:              virtual address of the buffer we want to read from
1114  * @size:               DMA transaction size in bytes
1115  * @flags:              flags to control DMA descriptor preparation
1116  */
1117 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
1118                           const u8 *vaddr, int size, unsigned int flags)
1119 {
1120         if (nandc->props->is_bam)
1121                 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
1122
1123         return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
1124 }
1125
1126 /*
1127  * Helper to prepare DMA descriptors for configuring registers
1128  * before reading a NAND page.
1129  */
1130 static void config_nand_page_read(struct nand_chip *chip)
1131 {
1132         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1133
1134         write_reg_dma(nandc, NAND_ADDR0, 2, 0);
1135         write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
1136         write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
1137         write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
1138         write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
1139                       NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
1140 }
1141
1142 /*
1143  * Helper to prepare DMA descriptors for configuring registers
1144  * before reading each codeword in NAND page.
1145  */
1146 static void
1147 config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
1148 {
1149         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1150         struct nand_ecc_ctrl *ecc = &chip->ecc;
1151
1152         int reg = NAND_READ_LOCATION_0;
1153
1154         if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
1155                 reg = NAND_READ_LOCATION_LAST_CW_0;
1156
1157         if (nandc->props->is_bam)
1158                 write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
1159
1160         write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1161         write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1162
1163         if (use_ecc) {
1164                 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
1165                 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
1166                              NAND_BAM_NEXT_SGL);
1167         } else {
1168                 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1169         }
1170 }
1171
1172 /*
1173  * Helper to prepare dma descriptors to configure registers needed for reading a
1174  * single codeword in page
1175  */
1176 static void
1177 config_nand_single_cw_page_read(struct nand_chip *chip,
1178                                 bool use_ecc, int cw)
1179 {
1180         config_nand_page_read(chip);
1181         config_nand_cw_read(chip, use_ecc, cw);
1182 }
1183
1184 /*
1185  * Helper to prepare DMA descriptors used to configure registers needed for
1186  * before writing a NAND page.
1187  */
1188 static void config_nand_page_write(struct nand_chip *chip)
1189 {
1190         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1191
1192         write_reg_dma(nandc, NAND_ADDR0, 2, 0);
1193         write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
1194         write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
1195                       NAND_BAM_NEXT_SGL);
1196 }
1197
1198 /*
1199  * Helper to prepare DMA descriptors for configuring registers
1200  * before writing each codeword in NAND page.
1201  */
1202 static void config_nand_cw_write(struct nand_chip *chip)
1203 {
1204         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1205
1206         write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1207         write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1208
1209         read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1210
1211         write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
1212         write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
1213 }
1214
1215 /*
1216  * the following functions are used within chip->legacy.cmdfunc() to
1217  * perform different NAND_CMD_* commands
1218  */
1219
1220 /* sets up descriptors for NAND_CMD_PARAM */
1221 static int nandc_param(struct qcom_nand_host *host)
1222 {
1223         struct nand_chip *chip = &host->chip;
1224         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1225
1226         /*
1227          * NAND_CMD_PARAM is called before we know much about the FLASH chip
1228          * in use. we configure the controller to perform a raw read of 512
1229          * bytes to read onfi params
1230          */
1231         if (nandc->props->qpic_v2)
1232                 nandc_set_reg(chip, NAND_FLASH_CMD, OP_PAGE_READ_ONFI_READ |
1233                               PAGE_ACC | LAST_PAGE);
1234         else
1235                 nandc_set_reg(chip, NAND_FLASH_CMD, OP_PAGE_READ |
1236                               PAGE_ACC | LAST_PAGE);
1237
1238         nandc_set_reg(chip, NAND_ADDR0, 0);
1239         nandc_set_reg(chip, NAND_ADDR1, 0);
1240         nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
1241                                         | 512 << UD_SIZE_BYTES
1242                                         | 5 << NUM_ADDR_CYCLES
1243                                         | 0 << SPARE_SIZE_BYTES);
1244         nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
1245                                         | 0 << CS_ACTIVE_BSY
1246                                         | 17 << BAD_BLOCK_BYTE_NUM
1247                                         | 1 << BAD_BLOCK_IN_SPARE_AREA
1248                                         | 2 << WR_RD_BSY_GAP
1249                                         | 0 << WIDE_FLASH
1250                                         | 1 << DEV0_CFG1_ECC_DISABLE);
1251         nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
1252
1253         /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
1254         if (!nandc->props->qpic_v2) {
1255                 nandc_set_reg(chip, NAND_DEV_CMD_VLD,
1256                               (nandc->vld & ~READ_START_VLD));
1257                 nandc_set_reg(chip, NAND_DEV_CMD1,
1258                               (nandc->cmd1 & ~(0xFF << READ_ADDR))
1259                               | NAND_CMD_PARAM << READ_ADDR);
1260         }
1261
1262         nandc_set_reg(chip, NAND_EXEC_CMD, 1);
1263
1264         if (!nandc->props->qpic_v2) {
1265                 nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
1266                 nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
1267         }
1268
1269         nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
1270
1271         if (!nandc->props->qpic_v2) {
1272                 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
1273                 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
1274         }
1275
1276         nandc->buf_count = 512;
1277         memset(nandc->data_buffer, 0xff, nandc->buf_count);
1278
1279         config_nand_single_cw_page_read(chip, false, 0);
1280
1281         read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
1282                       nandc->buf_count, 0);
1283
1284         /* restore CMD1 and VLD regs */
1285         if (!nandc->props->qpic_v2) {
1286                 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
1287                 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
1288         }
1289
1290         return 0;
1291 }
1292
1293 /* sets up descriptors for NAND_CMD_ERASE1 */
1294 static int erase_block(struct qcom_nand_host *host, int page_addr)
1295 {
1296         struct nand_chip *chip = &host->chip;
1297         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1298
1299         nandc_set_reg(chip, NAND_FLASH_CMD,
1300                       OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
1301         nandc_set_reg(chip, NAND_ADDR0, page_addr);
1302         nandc_set_reg(chip, NAND_ADDR1, 0);
1303         nandc_set_reg(chip, NAND_DEV0_CFG0,
1304                       host->cfg0_raw & ~(7 << CW_PER_PAGE));
1305         nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
1306         nandc_set_reg(chip, NAND_EXEC_CMD, 1);
1307         nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
1308         nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
1309
1310         write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1311         write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
1312         write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1313
1314         read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1315
1316         write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
1317         write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
1318
1319         return 0;
1320 }
1321
1322 /* sets up descriptors for NAND_CMD_READID */
1323 static int read_id(struct qcom_nand_host *host, int column)
1324 {
1325         struct nand_chip *chip = &host->chip;
1326         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1327
1328         if (column == -1)
1329                 return 0;
1330
1331         nandc_set_reg(chip, NAND_FLASH_CMD, OP_FETCH_ID);
1332         nandc_set_reg(chip, NAND_ADDR0, column);
1333         nandc_set_reg(chip, NAND_ADDR1, 0);
1334         nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT,
1335                       nandc->props->is_bam ? 0 : DM_EN);
1336         nandc_set_reg(chip, NAND_EXEC_CMD, 1);
1337
1338         write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
1339         write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1340
1341         read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1342
1343         return 0;
1344 }
1345
1346 /* sets up descriptors for NAND_CMD_RESET */
1347 static int reset(struct qcom_nand_host *host)
1348 {
1349         struct nand_chip *chip = &host->chip;
1350         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1351
1352         nandc_set_reg(chip, NAND_FLASH_CMD, OP_RESET_DEVICE);
1353         nandc_set_reg(chip, NAND_EXEC_CMD, 1);
1354
1355         write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1356         write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1357
1358         read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1359
1360         return 0;
1361 }
1362
1363 /* helpers to submit/free our list of dma descriptors */
1364 static int submit_descs(struct qcom_nand_controller *nandc)
1365 {
1366         struct desc_info *desc;
1367         dma_cookie_t cookie = 0;
1368         struct bam_transaction *bam_txn = nandc->bam_txn;
1369         int r;
1370
1371         if (nandc->props->is_bam) {
1372                 if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
1373                         r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
1374                         if (r)
1375                                 return r;
1376                 }
1377
1378                 if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
1379                         r = prepare_bam_async_desc(nandc, nandc->tx_chan,
1380                                                    DMA_PREP_INTERRUPT);
1381                         if (r)
1382                                 return r;
1383                 }
1384
1385                 if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
1386                         r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
1387                                                    DMA_PREP_CMD);
1388                         if (r)
1389                                 return r;
1390                 }
1391         }
1392
1393         list_for_each_entry(desc, &nandc->desc_list, node)
1394                 cookie = dmaengine_submit(desc->dma_desc);
1395
1396         if (nandc->props->is_bam) {
1397                 bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
1398                 bam_txn->last_cmd_desc->callback_param = bam_txn;
1399                 if (bam_txn->last_data_desc) {
1400                         bam_txn->last_data_desc->callback = qpic_bam_dma_done;
1401                         bam_txn->last_data_desc->callback_param = bam_txn;
1402                         bam_txn->wait_second_completion = true;
1403                 }
1404
1405                 dma_async_issue_pending(nandc->tx_chan);
1406                 dma_async_issue_pending(nandc->rx_chan);
1407                 dma_async_issue_pending(nandc->cmd_chan);
1408
1409                 if (!wait_for_completion_timeout(&bam_txn->txn_done,
1410                                                  QPIC_NAND_COMPLETION_TIMEOUT))
1411                         return -ETIMEDOUT;
1412         } else {
1413                 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
1414                         return -ETIMEDOUT;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static void free_descs(struct qcom_nand_controller *nandc)
1421 {
1422         struct desc_info *desc, *n;
1423
1424         list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
1425                 list_del(&desc->node);
1426
1427                 if (nandc->props->is_bam)
1428                         dma_unmap_sg(nandc->dev, desc->bam_sgl,
1429                                      desc->sgl_cnt, desc->dir);
1430                 else
1431                         dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
1432                                      desc->dir);
1433
1434                 kfree(desc);
1435         }
1436 }
1437
1438 /* reset the register read buffer for next NAND operation */
1439 static void clear_read_regs(struct qcom_nand_controller *nandc)
1440 {
1441         nandc->reg_read_pos = 0;
1442         nandc_read_buffer_sync(nandc, false);
1443 }
1444
1445 static void pre_command(struct qcom_nand_host *host, int command)
1446 {
1447         struct nand_chip *chip = &host->chip;
1448         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1449
1450         nandc->buf_count = 0;
1451         nandc->buf_start = 0;
1452         host->use_ecc = false;
1453         host->last_command = command;
1454
1455         clear_read_regs(nandc);
1456
1457         if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
1458             command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
1459                 clear_bam_transaction(nandc);
1460 }
1461
1462 /*
1463  * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our
1464  * privately maintained status byte, this status byte can be read after
1465  * NAND_CMD_STATUS is called
1466  */
1467 static void parse_erase_write_errors(struct qcom_nand_host *host, int command)
1468 {
1469         struct nand_chip *chip = &host->chip;
1470         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1471         struct nand_ecc_ctrl *ecc = &chip->ecc;
1472         int num_cw;
1473         int i;
1474
1475         num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
1476         nandc_read_buffer_sync(nandc, true);
1477
1478         for (i = 0; i < num_cw; i++) {
1479                 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
1480
1481                 if (flash_status & FS_MPU_ERR)
1482                         host->status &= ~NAND_STATUS_WP;
1483
1484                 if (flash_status & FS_OP_ERR || (i == (num_cw - 1) &&
1485                                                  (flash_status &
1486                                                   FS_DEVICE_STS_ERR)))
1487                         host->status |= NAND_STATUS_FAIL;
1488         }
1489 }
1490
1491 static void post_command(struct qcom_nand_host *host, int command)
1492 {
1493         struct nand_chip *chip = &host->chip;
1494         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1495
1496         switch (command) {
1497         case NAND_CMD_READID:
1498                 nandc_read_buffer_sync(nandc, true);
1499                 memcpy(nandc->data_buffer, nandc->reg_read_buf,
1500                        nandc->buf_count);
1501                 break;
1502         case NAND_CMD_PAGEPROG:
1503         case NAND_CMD_ERASE1:
1504                 parse_erase_write_errors(host, command);
1505                 break;
1506         default:
1507                 break;
1508         }
1509 }
1510
1511 /*
1512  * Implements chip->legacy.cmdfunc. It's  only used for a limited set of
1513  * commands. The rest of the commands wouldn't be called by upper layers.
1514  * For example, NAND_CMD_READOOB would never be called because we have our own
1515  * versions of read_oob ops for nand_ecc_ctrl.
1516  */
1517 static void qcom_nandc_command(struct nand_chip *chip, unsigned int command,
1518                                int column, int page_addr)
1519 {
1520         struct qcom_nand_host *host = to_qcom_nand_host(chip);
1521         struct nand_ecc_ctrl *ecc = &chip->ecc;
1522         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1523         bool wait = false;
1524         int ret = 0;
1525
1526         pre_command(host, command);
1527
1528         switch (command) {
1529         case NAND_CMD_RESET:
1530                 ret = reset(host);
1531                 wait = true;
1532                 break;
1533
1534         case NAND_CMD_READID:
1535                 nandc->buf_count = 4;
1536                 ret = read_id(host, column);
1537                 wait = true;
1538                 break;
1539
1540         case NAND_CMD_PARAM:
1541                 ret = nandc_param(host);
1542                 wait = true;
1543                 break;
1544
1545         case NAND_CMD_ERASE1:
1546                 ret = erase_block(host, page_addr);
1547                 wait = true;
1548                 break;
1549
1550         case NAND_CMD_READ0:
1551                 /* we read the entire page for now */
1552                 WARN_ON(column != 0);
1553
1554                 host->use_ecc = true;
1555                 set_address(host, 0, page_addr);
1556                 update_rw_regs(host, ecc->steps, true, 0);
1557                 break;
1558
1559         case NAND_CMD_SEQIN:
1560                 WARN_ON(column != 0);
1561                 set_address(host, 0, page_addr);
1562                 break;
1563
1564         case NAND_CMD_PAGEPROG:
1565         case NAND_CMD_STATUS:
1566         case NAND_CMD_NONE:
1567         default:
1568                 break;
1569         }
1570
1571         if (ret) {
1572                 dev_err(nandc->dev, "failure executing command %d\n",
1573                         command);
1574                 free_descs(nandc);
1575                 return;
1576         }
1577
1578         if (wait) {
1579                 ret = submit_descs(nandc);
1580                 if (ret)
1581                         dev_err(nandc->dev,
1582                                 "failure submitting descs for command %d\n",
1583                                 command);
1584         }
1585
1586         free_descs(nandc);
1587
1588         post_command(host, command);
1589 }
1590
1591 /*
1592  * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1593  * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
1594  *
1595  * when using RS ECC, the HW reports the same erros when reading an erased CW,
1596  * but it notifies that it is an erased CW by placing special characters at
1597  * certain offsets in the buffer.
1598  *
1599  * verify if the page is erased or not, and fix up the page for RS ECC by
1600  * replacing the special characters with 0xff.
1601  */
1602 static bool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)
1603 {
1604         u8 empty1, empty2;
1605
1606         /*
1607          * an erased page flags an error in NAND_FLASH_STATUS, check if the page
1608          * is erased by looking for 0x54s at offsets 3 and 175 from the
1609          * beginning of each codeword
1610          */
1611
1612         empty1 = data_buf[3];
1613         empty2 = data_buf[175];
1614
1615         /*
1616          * if the erased codework markers, if they exist override them with
1617          * 0xffs
1618          */
1619         if ((empty1 == 0x54 && empty2 == 0xff) ||
1620             (empty1 == 0xff && empty2 == 0x54)) {
1621                 data_buf[3] = 0xff;
1622                 data_buf[175] = 0xff;
1623         }
1624
1625         /*
1626          * check if the entire chunk contains 0xffs or not. if it doesn't, then
1627          * restore the original values at the special offsets
1628          */
1629         if (memchr_inv(data_buf, 0xff, data_len)) {
1630                 data_buf[3] = empty1;
1631                 data_buf[175] = empty2;
1632
1633                 return false;
1634         }
1635
1636         return true;
1637 }
1638
1639 struct read_stats {
1640         __le32 flash;
1641         __le32 buffer;
1642         __le32 erased_cw;
1643 };
1644
1645 /* reads back FLASH_STATUS register set by the controller */
1646 static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
1647 {
1648         struct nand_chip *chip = &host->chip;
1649         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1650         int i;
1651
1652         nandc_read_buffer_sync(nandc, true);
1653
1654         for (i = 0; i < cw_cnt; i++) {
1655                 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
1656
1657                 if (flash & (FS_OP_ERR | FS_MPU_ERR))
1658                         return -EIO;
1659         }
1660
1661         return 0;
1662 }
1663
1664 /* performs raw read for one codeword */
1665 static int
1666 qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
1667                        u8 *data_buf, u8 *oob_buf, int page, int cw)
1668 {
1669         struct qcom_nand_host *host = to_qcom_nand_host(chip);
1670         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1671         struct nand_ecc_ctrl *ecc = &chip->ecc;
1672         int data_size1, data_size2, oob_size1, oob_size2;
1673         int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
1674
1675         nand_read_page_op(chip, page, 0, NULL, 0);
1676         host->use_ecc = false;
1677
1678         clear_bam_transaction(nandc);
1679         set_address(host, host->cw_size * cw, page);
1680         update_rw_regs(host, 1, true, cw);
1681         config_nand_page_read(chip);
1682
1683         data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
1684         oob_size1 = host->bbm_size;
1685
1686         if (qcom_nandc_is_last_cw(ecc, cw)) {
1687                 data_size2 = ecc->size - data_size1 -
1688                              ((ecc->steps - 1) * 4);
1689                 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +
1690                             host->spare_bytes;
1691         } else {
1692                 data_size2 = host->cw_data - data_size1;
1693                 oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1694         }
1695
1696         if (nandc->props->is_bam) {
1697                 nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
1698                 read_loc += data_size1;
1699
1700                 nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
1701                 read_loc += oob_size1;
1702
1703                 nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
1704                 read_loc += data_size2;
1705
1706                 nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
1707         }
1708
1709         config_nand_cw_read(chip, false, cw);
1710
1711         read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
1712         reg_off += data_size1;
1713
1714         read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
1715         reg_off += oob_size1;
1716
1717         read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
1718         reg_off += data_size2;
1719
1720         read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
1721
1722         ret = submit_descs(nandc);
1723         free_descs(nandc);
1724         if (ret) {
1725                 dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
1726                 return ret;
1727         }
1728
1729         return check_flash_errors(host, 1);
1730 }
1731
1732 /*
1733  * Bitflips can happen in erased codewords also so this function counts the
1734  * number of 0 in each CW for which ECC engine returns the uncorrectable
1735  * error. The page will be assumed as erased if this count is less than or
1736  * equal to the ecc->strength for each CW.
1737  *
1738  * 1. Both DATA and OOB need to be checked for number of 0. The
1739  *    top-level API can be called with only data buf or OOB buf so use
1740  *    chip->data_buf if data buf is null and chip->oob_poi if oob buf
1741  *    is null for copying the raw bytes.
1742  * 2. Perform raw read for all the CW which has uncorrectable errors.
1743  * 3. For each CW, check the number of 0 in cw_data and usable OOB bytes.
1744  *    The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1745  *    the number of bitflips in this area.
1746  */
1747 static int
1748 check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf,
1749                       u8 *oob_buf, unsigned long uncorrectable_cws,
1750                       int page, unsigned int max_bitflips)
1751 {
1752         struct nand_chip *chip = &host->chip;
1753         struct mtd_info *mtd = nand_to_mtd(chip);
1754         struct nand_ecc_ctrl *ecc = &chip->ecc;
1755         u8 *cw_data_buf, *cw_oob_buf;
1756         int cw, data_size, oob_size, ret = 0;
1757
1758         if (!data_buf)
1759                 data_buf = nand_get_data_buf(chip);
1760
1761         if (!oob_buf) {
1762                 nand_get_data_buf(chip);
1763                 oob_buf = chip->oob_poi;
1764         }
1765
1766         for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {
1767                 if (qcom_nandc_is_last_cw(ecc, cw)) {
1768                         data_size = ecc->size - ((ecc->steps - 1) * 4);
1769                         oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;
1770                 } else {
1771                         data_size = host->cw_data;
1772                         oob_size = host->ecc_bytes_hw;
1773                 }
1774
1775                 /* determine starting buffer address for current CW */
1776                 cw_data_buf = data_buf + (cw * host->cw_data);
1777                 cw_oob_buf = oob_buf + (cw * ecc->bytes);
1778
1779                 ret = qcom_nandc_read_cw_raw(mtd, chip, cw_data_buf,
1780                                              cw_oob_buf, page, cw);
1781                 if (ret)
1782                         return ret;
1783
1784                 /*
1785                  * make sure it isn't an erased page reported
1786                  * as not-erased by HW because of a few bitflips
1787                  */
1788                 ret = nand_check_erased_ecc_chunk(cw_data_buf, data_size,
1789                                                   cw_oob_buf + host->bbm_size,
1790                                                   oob_size, NULL,
1791                                                   0, ecc->strength);
1792                 if (ret < 0) {
1793                         mtd->ecc_stats.failed++;
1794                 } else {
1795                         mtd->ecc_stats.corrected += ret;
1796                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1797                 }
1798         }
1799
1800         return max_bitflips;
1801 }
1802
1803 /*
1804  * reads back status registers set by the controller to notify page read
1805  * errors. this is equivalent to what 'ecc->correct()' would do.
1806  */
1807 static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
1808                              u8 *oob_buf, int page)
1809 {
1810         struct nand_chip *chip = &host->chip;
1811         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1812         struct mtd_info *mtd = nand_to_mtd(chip);
1813         struct nand_ecc_ctrl *ecc = &chip->ecc;
1814         unsigned int max_bitflips = 0, uncorrectable_cws = 0;
1815         struct read_stats *buf;
1816         bool flash_op_err = false, erased;
1817         int i;
1818         u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
1819
1820         buf = (struct read_stats *)nandc->reg_read_buf;
1821         nandc_read_buffer_sync(nandc, true);
1822
1823         for (i = 0; i < ecc->steps; i++, buf++) {
1824                 u32 flash, buffer, erased_cw;
1825                 int data_len, oob_len;
1826
1827                 if (qcom_nandc_is_last_cw(ecc, i)) {
1828                         data_len = ecc->size - ((ecc->steps - 1) << 2);
1829                         oob_len = ecc->steps << 2;
1830                 } else {
1831                         data_len = host->cw_data;
1832                         oob_len = 0;
1833                 }
1834
1835                 flash = le32_to_cpu(buf->flash);
1836                 buffer = le32_to_cpu(buf->buffer);
1837                 erased_cw = le32_to_cpu(buf->erased_cw);
1838
1839                 /*
1840                  * Check ECC failure for each codeword. ECC failure can
1841                  * happen in either of the following conditions
1842                  * 1. If number of bitflips are greater than ECC engine
1843                  *    capability.
1844                  * 2. If this codeword contains all 0xff for which erased
1845                  *    codeword detection check will be done.
1846                  */
1847                 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
1848                         /*
1849                          * For BCH ECC, ignore erased codeword errors, if
1850                          * ERASED_CW bits are set.
1851                          */
1852                         if (host->bch_enabled) {
1853                                 erased = (erased_cw & ERASED_CW) == ERASED_CW ?
1854                                          true : false;
1855                         /*
1856                          * For RS ECC, HW reports the erased CW by placing
1857                          * special characters at certain offsets in the buffer.
1858                          * These special characters will be valid only if
1859                          * complete page is read i.e. data_buf is not NULL.
1860                          */
1861                         } else if (data_buf) {
1862                                 erased = erased_chunk_check_and_fixup(data_buf,
1863                                                                       data_len);
1864                         } else {
1865                                 erased = false;
1866                         }
1867
1868                         if (!erased)
1869                                 uncorrectable_cws |= BIT(i);
1870                 /*
1871                  * Check if MPU or any other operational error (timeout,
1872                  * device failure, etc.) happened for this codeword and
1873                  * make flash_op_err true. If flash_op_err is set, then
1874                  * EIO will be returned for page read.
1875                  */
1876                 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
1877                         flash_op_err = true;
1878                 /*
1879                  * No ECC or operational errors happened. Check the number of
1880                  * bits corrected and update the ecc_stats.corrected.
1881                  */
1882                 } else {
1883                         unsigned int stat;
1884
1885                         stat = buffer & BS_CORRECTABLE_ERR_MSK;
1886                         mtd->ecc_stats.corrected += stat;
1887                         max_bitflips = max(max_bitflips, stat);
1888                 }
1889
1890                 if (data_buf)
1891                         data_buf += data_len;
1892                 if (oob_buf)
1893                         oob_buf += oob_len + ecc->bytes;
1894         }
1895
1896         if (flash_op_err)
1897                 return -EIO;
1898
1899         if (!uncorrectable_cws)
1900                 return max_bitflips;
1901
1902         return check_for_erased_page(host, data_buf_start, oob_buf_start,
1903                                      uncorrectable_cws, page,
1904                                      max_bitflips);
1905 }
1906
1907 /*
1908  * helper to perform the actual page read operation, used by ecc->read_page(),
1909  * ecc->read_oob()
1910  */
1911 static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
1912                          u8 *oob_buf, int page)
1913 {
1914         struct nand_chip *chip = &host->chip;
1915         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1916         struct nand_ecc_ctrl *ecc = &chip->ecc;
1917         u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
1918         int i, ret;
1919
1920         config_nand_page_read(chip);
1921
1922         /* queue cmd descs for each codeword */
1923         for (i = 0; i < ecc->steps; i++) {
1924                 int data_size, oob_size;
1925
1926                 if (qcom_nandc_is_last_cw(ecc, i)) {
1927                         data_size = ecc->size - ((ecc->steps - 1) << 2);
1928                         oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
1929                                    host->spare_bytes;
1930                 } else {
1931                         data_size = host->cw_data;
1932                         oob_size = host->ecc_bytes_hw + host->spare_bytes;
1933                 }
1934
1935                 if (nandc->props->is_bam) {
1936                         if (data_buf && oob_buf) {
1937                                 nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
1938                                 nandc_set_read_loc(chip, i, 1, data_size,
1939                                                    oob_size, 1);
1940                         } else if (data_buf) {
1941                                 nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
1942                         } else {
1943                                 nandc_set_read_loc(chip, i, 0, data_size,
1944                                                    oob_size, 1);
1945                         }
1946                 }
1947
1948                 config_nand_cw_read(chip, true, i);
1949
1950                 if (data_buf)
1951                         read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
1952                                       data_size, 0);
1953
1954                 /*
1955                  * when ecc is enabled, the controller doesn't read the real
1956                  * or dummy bad block markers in each chunk. To maintain a
1957                  * consistent layout across RAW and ECC reads, we just
1958                  * leave the real/dummy BBM offsets empty (i.e, filled with
1959                  * 0xffs)
1960                  */
1961                 if (oob_buf) {
1962                         int j;
1963
1964                         for (j = 0; j < host->bbm_size; j++)
1965                                 *oob_buf++ = 0xff;
1966
1967                         read_data_dma(nandc, FLASH_BUF_ACC + data_size,
1968                                       oob_buf, oob_size, 0);
1969                 }
1970
1971                 if (data_buf)
1972                         data_buf += data_size;
1973                 if (oob_buf)
1974                         oob_buf += oob_size;
1975         }
1976
1977         ret = submit_descs(nandc);
1978         free_descs(nandc);
1979
1980         if (ret) {
1981                 dev_err(nandc->dev, "failure to read page/oob\n");
1982                 return ret;
1983         }
1984
1985         return parse_read_errors(host, data_buf_start, oob_buf_start, page);
1986 }
1987
1988 /*
1989  * a helper that copies the last step/codeword of a page (containing free oob)
1990  * into our local buffer
1991  */
1992 static int copy_last_cw(struct qcom_nand_host *host, int page)
1993 {
1994         struct nand_chip *chip = &host->chip;
1995         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1996         struct nand_ecc_ctrl *ecc = &chip->ecc;
1997         int size;
1998         int ret;
1999
2000         clear_read_regs(nandc);
2001
2002         size = host->use_ecc ? host->cw_data : host->cw_size;
2003
2004         /* prepare a clean read buffer */
2005         memset(nandc->data_buffer, 0xff, size);
2006
2007         set_address(host, host->cw_size * (ecc->steps - 1), page);
2008         update_rw_regs(host, 1, true, ecc->steps - 1);
2009
2010         config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
2011
2012         read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
2013
2014         ret = submit_descs(nandc);
2015         if (ret)
2016                 dev_err(nandc->dev, "failed to copy last codeword\n");
2017
2018         free_descs(nandc);
2019
2020         return ret;
2021 }
2022
2023 /* implements ecc->read_page() */
2024 static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,
2025                                 int oob_required, int page)
2026 {
2027         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2028         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2029         u8 *data_buf, *oob_buf = NULL;
2030
2031         nand_read_page_op(chip, page, 0, NULL, 0);
2032         data_buf = buf;
2033         oob_buf = oob_required ? chip->oob_poi : NULL;
2034
2035         clear_bam_transaction(nandc);
2036
2037         return read_page_ecc(host, data_buf, oob_buf, page);
2038 }
2039
2040 /* implements ecc->read_page_raw() */
2041 static int qcom_nandc_read_page_raw(struct nand_chip *chip, uint8_t *buf,
2042                                     int oob_required, int page)
2043 {
2044         struct mtd_info *mtd = nand_to_mtd(chip);
2045         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2046         struct nand_ecc_ctrl *ecc = &chip->ecc;
2047         int cw, ret;
2048         u8 *data_buf = buf, *oob_buf = chip->oob_poi;
2049
2050         for (cw = 0; cw < ecc->steps; cw++) {
2051                 ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,
2052                                              page, cw);
2053                 if (ret)
2054                         return ret;
2055
2056                 data_buf += host->cw_data;
2057                 oob_buf += ecc->bytes;
2058         }
2059
2060         return 0;
2061 }
2062
2063 /* implements ecc->read_oob() */
2064 static int qcom_nandc_read_oob(struct nand_chip *chip, int page)
2065 {
2066         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2067         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2068         struct nand_ecc_ctrl *ecc = &chip->ecc;
2069
2070         clear_read_regs(nandc);
2071         clear_bam_transaction(nandc);
2072
2073         host->use_ecc = true;
2074         set_address(host, 0, page);
2075         update_rw_regs(host, ecc->steps, true, 0);
2076
2077         return read_page_ecc(host, NULL, chip->oob_poi, page);
2078 }
2079
2080 /* implements ecc->write_page() */
2081 static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf,
2082                                  int oob_required, int page)
2083 {
2084         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2085         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2086         struct nand_ecc_ctrl *ecc = &chip->ecc;
2087         u8 *data_buf, *oob_buf;
2088         int i, ret;
2089
2090         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
2091
2092         clear_read_regs(nandc);
2093         clear_bam_transaction(nandc);
2094
2095         data_buf = (u8 *)buf;
2096         oob_buf = chip->oob_poi;
2097
2098         host->use_ecc = true;
2099         update_rw_regs(host, ecc->steps, false, 0);
2100         config_nand_page_write(chip);
2101
2102         for (i = 0; i < ecc->steps; i++) {
2103                 int data_size, oob_size;
2104
2105                 if (qcom_nandc_is_last_cw(ecc, i)) {
2106                         data_size = ecc->size - ((ecc->steps - 1) << 2);
2107                         oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
2108                                    host->spare_bytes;
2109                 } else {
2110                         data_size = host->cw_data;
2111                         oob_size = ecc->bytes;
2112                 }
2113
2114
2115                 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
2116                                i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
2117
2118                 /*
2119                  * when ECC is enabled, we don't really need to write anything
2120                  * to oob for the first n - 1 codewords since these oob regions
2121                  * just contain ECC bytes that's written by the controller
2122                  * itself. For the last codeword, we skip the bbm positions and
2123                  * write to the free oob area.
2124                  */
2125                 if (qcom_nandc_is_last_cw(ecc, i)) {
2126                         oob_buf += host->bbm_size;
2127
2128                         write_data_dma(nandc, FLASH_BUF_ACC + data_size,
2129                                        oob_buf, oob_size, 0);
2130                 }
2131
2132                 config_nand_cw_write(chip);
2133
2134                 data_buf += data_size;
2135                 oob_buf += oob_size;
2136         }
2137
2138         ret = submit_descs(nandc);
2139         if (ret)
2140                 dev_err(nandc->dev, "failure to write page\n");
2141
2142         free_descs(nandc);
2143
2144         if (!ret)
2145                 ret = nand_prog_page_end_op(chip);
2146
2147         return ret;
2148 }
2149
2150 /* implements ecc->write_page_raw() */
2151 static int qcom_nandc_write_page_raw(struct nand_chip *chip,
2152                                      const uint8_t *buf, int oob_required,
2153                                      int page)
2154 {
2155         struct mtd_info *mtd = nand_to_mtd(chip);
2156         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2157         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2158         struct nand_ecc_ctrl *ecc = &chip->ecc;
2159         u8 *data_buf, *oob_buf;
2160         int i, ret;
2161
2162         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
2163         clear_read_regs(nandc);
2164         clear_bam_transaction(nandc);
2165
2166         data_buf = (u8 *)buf;
2167         oob_buf = chip->oob_poi;
2168
2169         host->use_ecc = false;
2170         update_rw_regs(host, ecc->steps, false, 0);
2171         config_nand_page_write(chip);
2172
2173         for (i = 0; i < ecc->steps; i++) {
2174                 int data_size1, data_size2, oob_size1, oob_size2;
2175                 int reg_off = FLASH_BUF_ACC;
2176
2177                 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
2178                 oob_size1 = host->bbm_size;
2179
2180                 if (qcom_nandc_is_last_cw(ecc, i)) {
2181                         data_size2 = ecc->size - data_size1 -
2182                                      ((ecc->steps - 1) << 2);
2183                         oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
2184                                     host->spare_bytes;
2185                 } else {
2186                         data_size2 = host->cw_data - data_size1;
2187                         oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
2188                 }
2189
2190                 write_data_dma(nandc, reg_off, data_buf, data_size1,
2191                                NAND_BAM_NO_EOT);
2192                 reg_off += data_size1;
2193                 data_buf += data_size1;
2194
2195                 write_data_dma(nandc, reg_off, oob_buf, oob_size1,
2196                                NAND_BAM_NO_EOT);
2197                 reg_off += oob_size1;
2198                 oob_buf += oob_size1;
2199
2200                 write_data_dma(nandc, reg_off, data_buf, data_size2,
2201                                NAND_BAM_NO_EOT);
2202                 reg_off += data_size2;
2203                 data_buf += data_size2;
2204
2205                 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
2206                 oob_buf += oob_size2;
2207
2208                 config_nand_cw_write(chip);
2209         }
2210
2211         ret = submit_descs(nandc);
2212         if (ret)
2213                 dev_err(nandc->dev, "failure to write raw page\n");
2214
2215         free_descs(nandc);
2216
2217         if (!ret)
2218                 ret = nand_prog_page_end_op(chip);
2219
2220         return ret;
2221 }
2222
2223 /*
2224  * implements ecc->write_oob()
2225  *
2226  * the NAND controller cannot write only data or only OOB within a codeword
2227  * since ECC is calculated for the combined codeword. So update the OOB from
2228  * chip->oob_poi, and pad the data area with OxFF before writing.
2229  */
2230 static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
2231 {
2232         struct mtd_info *mtd = nand_to_mtd(chip);
2233         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2234         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2235         struct nand_ecc_ctrl *ecc = &chip->ecc;
2236         u8 *oob = chip->oob_poi;
2237         int data_size, oob_size;
2238         int ret;
2239
2240         host->use_ecc = true;
2241         clear_bam_transaction(nandc);
2242
2243         /* calculate the data and oob size for the last codeword/step */
2244         data_size = ecc->size - ((ecc->steps - 1) << 2);
2245         oob_size = mtd->oobavail;
2246
2247         memset(nandc->data_buffer, 0xff, host->cw_data);
2248         /* override new oob content to last codeword */
2249         mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob,
2250                                     0, mtd->oobavail);
2251
2252         set_address(host, host->cw_size * (ecc->steps - 1), page);
2253         update_rw_regs(host, 1, false, 0);
2254
2255         config_nand_page_write(chip);
2256         write_data_dma(nandc, FLASH_BUF_ACC,
2257                        nandc->data_buffer, data_size + oob_size, 0);
2258         config_nand_cw_write(chip);
2259
2260         ret = submit_descs(nandc);
2261
2262         free_descs(nandc);
2263
2264         if (ret) {
2265                 dev_err(nandc->dev, "failure to write oob\n");
2266                 return -EIO;
2267         }
2268
2269         return nand_prog_page_end_op(chip);
2270 }
2271
2272 static int qcom_nandc_block_bad(struct nand_chip *chip, loff_t ofs)
2273 {
2274         struct mtd_info *mtd = nand_to_mtd(chip);
2275         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2276         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2277         struct nand_ecc_ctrl *ecc = &chip->ecc;
2278         int page, ret, bbpos, bad = 0;
2279
2280         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
2281
2282         /*
2283          * configure registers for a raw sub page read, the address is set to
2284          * the beginning of the last codeword, we don't care about reading ecc
2285          * portion of oob. we just want the first few bytes from this codeword
2286          * that contains the BBM
2287          */
2288         host->use_ecc = false;
2289
2290         clear_bam_transaction(nandc);
2291         ret = copy_last_cw(host, page);
2292         if (ret)
2293                 goto err;
2294
2295         if (check_flash_errors(host, 1)) {
2296                 dev_warn(nandc->dev, "error when trying to read BBM\n");
2297                 goto err;
2298         }
2299
2300         bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);
2301
2302         bad = nandc->data_buffer[bbpos] != 0xff;
2303
2304         if (chip->options & NAND_BUSWIDTH_16)
2305                 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff);
2306 err:
2307         return bad;
2308 }
2309
2310 static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
2311 {
2312         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2313         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2314         struct nand_ecc_ctrl *ecc = &chip->ecc;
2315         int page, ret;
2316
2317         clear_read_regs(nandc);
2318         clear_bam_transaction(nandc);
2319
2320         /*
2321          * to mark the BBM as bad, we flash the entire last codeword with 0s.
2322          * we don't care about the rest of the content in the codeword since
2323          * we aren't going to use this block again
2324          */
2325         memset(nandc->data_buffer, 0x00, host->cw_size);
2326
2327         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
2328
2329         /* prepare write */
2330         host->use_ecc = false;
2331         set_address(host, host->cw_size * (ecc->steps - 1), page);
2332         update_rw_regs(host, 1, false, ecc->steps - 1);
2333
2334         config_nand_page_write(chip);
2335         write_data_dma(nandc, FLASH_BUF_ACC,
2336                        nandc->data_buffer, host->cw_size, 0);
2337         config_nand_cw_write(chip);
2338
2339         ret = submit_descs(nandc);
2340
2341         free_descs(nandc);
2342
2343         if (ret) {
2344                 dev_err(nandc->dev, "failure to update BBM\n");
2345                 return -EIO;
2346         }
2347
2348         return nand_prog_page_end_op(chip);
2349 }
2350
2351 /*
2352  * the three functions below implement chip->legacy.read_byte(),
2353  * chip->legacy.read_buf() and chip->legacy.write_buf() respectively. these
2354  * aren't used for reading/writing page data, they are used for smaller data
2355  * like reading id, status etc
2356  */
2357 static uint8_t qcom_nandc_read_byte(struct nand_chip *chip)
2358 {
2359         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2360         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2361         u8 *buf = nandc->data_buffer;
2362         u8 ret = 0x0;
2363
2364         if (host->last_command == NAND_CMD_STATUS) {
2365                 ret = host->status;
2366
2367                 host->status = NAND_STATUS_READY | NAND_STATUS_WP;
2368
2369                 return ret;
2370         }
2371
2372         if (nandc->buf_start < nandc->buf_count)
2373                 ret = buf[nandc->buf_start++];
2374
2375         return ret;
2376 }
2377
2378 static void qcom_nandc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
2379 {
2380         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2381         int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
2382
2383         memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len);
2384         nandc->buf_start += real_len;
2385 }
2386
2387 static void qcom_nandc_write_buf(struct nand_chip *chip, const uint8_t *buf,
2388                                  int len)
2389 {
2390         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2391         int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
2392
2393         memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len);
2394
2395         nandc->buf_start += real_len;
2396 }
2397
2398 /* we support only one external chip for now */
2399 static void qcom_nandc_select_chip(struct nand_chip *chip, int chipnr)
2400 {
2401         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2402
2403         if (chipnr <= 0)
2404                 return;
2405
2406         dev_warn(nandc->dev, "invalid chip select\n");
2407 }
2408
2409 /*
2410  * NAND controller page layout info
2411  *
2412  * Layout with ECC enabled:
2413  *
2414  * |----------------------|  |---------------------------------|
2415  * |           xx.......yy|  |             *********xx.......yy|
2416  * |    DATA   xx..ECC..yy|  |    DATA     **SPARE**xx..ECC..yy|
2417  * |   (516)   xx.......yy|  |  (516-n*4)  **(n*4)**xx.......yy|
2418  * |           xx.......yy|  |             *********xx.......yy|
2419  * |----------------------|  |---------------------------------|
2420  *     codeword 1,2..n-1                  codeword n
2421  *  <---(528/532 Bytes)-->    <-------(528/532 Bytes)--------->
2422  *
2423  * n = Number of codewords in the page
2424  * . = ECC bytes
2425  * * = Spare/free bytes
2426  * x = Unused byte(s)
2427  * y = Reserved byte(s)
2428  *
2429  * 2K page: n = 4, spare = 16 bytes
2430  * 4K page: n = 8, spare = 32 bytes
2431  * 8K page: n = 16, spare = 64 bytes
2432  *
2433  * the qcom nand controller operates at a sub page/codeword level. each
2434  * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2435  * the number of ECC bytes vary based on the ECC strength and the bus width.
2436  *
2437  * the first n - 1 codewords contains 516 bytes of user data, the remaining
2438  * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2439  * both user data and spare(oobavail) bytes that sum up to 516 bytes.
2440  *
2441  * When we access a page with ECC enabled, the reserved bytes(s) are not
2442  * accessible at all. When reading, we fill up these unreadable positions
2443  * with 0xffs. When writing, the controller skips writing the inaccessible
2444  * bytes.
2445  *
2446  * Layout with ECC disabled:
2447  *
2448  * |------------------------------|  |---------------------------------------|
2449  * |         yy          xx.......|  |         bb          *********xx.......|
2450  * |  DATA1  yy  DATA2   xx..ECC..|  |  DATA1  bb  DATA2   **SPARE**xx..ECC..|
2451  * | (size1) yy (size2)  xx.......|  | (size1) bb (size2)  **(n*4)**xx.......|
2452  * |         yy          xx.......|  |         bb          *********xx.......|
2453  * |------------------------------|  |---------------------------------------|
2454  *         codeword 1,2..n-1                        codeword n
2455  *  <-------(528/532 Bytes)------>    <-----------(528/532 Bytes)----------->
2456  *
2457  * n = Number of codewords in the page
2458  * . = ECC bytes
2459  * * = Spare/free bytes
2460  * x = Unused byte(s)
2461  * y = Dummy Bad Bock byte(s)
2462  * b = Real Bad Block byte(s)
2463  * size1/size2 = function of codeword size and 'n'
2464  *
2465  * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2466  * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
2467  * Block Markers. In the last codeword, this position contains the real BBM
2468  *
2469  * In order to have a consistent layout between RAW and ECC modes, we assume
2470  * the following OOB layout arrangement:
2471  *
2472  * |-----------|  |--------------------|
2473  * |yyxx.......|  |bb*********xx.......|
2474  * |yyxx..ECC..|  |bb*FREEOOB*xx..ECC..|
2475  * |yyxx.......|  |bb*********xx.......|
2476  * |yyxx.......|  |bb*********xx.......|
2477  * |-----------|  |--------------------|
2478  *  first n - 1       nth OOB region
2479  *  OOB regions
2480  *
2481  * n = Number of codewords in the page
2482  * . = ECC bytes
2483  * * = FREE OOB bytes
2484  * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2485  * x = Unused byte(s)
2486  * b = Real bad block byte(s) (inaccessible when ECC enabled)
2487  *
2488  * This layout is read as is when ECC is disabled. When ECC is enabled, the
2489  * inaccessible Bad Block byte(s) are ignored when we write to a page/oob,
2490  * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2491  * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2492  * the sum of the three).
2493  */
2494 static int qcom_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2495                                    struct mtd_oob_region *oobregion)
2496 {
2497         struct nand_chip *chip = mtd_to_nand(mtd);
2498         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2499         struct nand_ecc_ctrl *ecc = &chip->ecc;
2500
2501         if (section > 1)
2502                 return -ERANGE;
2503
2504         if (!section) {
2505                 oobregion->length = (ecc->bytes * (ecc->steps - 1)) +
2506                                     host->bbm_size;
2507                 oobregion->offset = 0;
2508         } else {
2509                 oobregion->length = host->ecc_bytes_hw + host->spare_bytes;
2510                 oobregion->offset = mtd->oobsize - oobregion->length;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int qcom_nand_ooblayout_free(struct mtd_info *mtd, int section,
2517                                      struct mtd_oob_region *oobregion)
2518 {
2519         struct nand_chip *chip = mtd_to_nand(mtd);
2520         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2521         struct nand_ecc_ctrl *ecc = &chip->ecc;
2522
2523         if (section)
2524                 return -ERANGE;
2525
2526         oobregion->length = ecc->steps * 4;
2527         oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;
2528
2529         return 0;
2530 }
2531
2532 static const struct mtd_ooblayout_ops qcom_nand_ooblayout_ops = {
2533         .ecc = qcom_nand_ooblayout_ecc,
2534         .free = qcom_nand_ooblayout_free,
2535 };
2536
2537 static int
2538 qcom_nandc_calc_ecc_bytes(int step_size, int strength)
2539 {
2540         return strength == 4 ? 12 : 16;
2541 }
2542 NAND_ECC_CAPS_SINGLE(qcom_nandc_ecc_caps, qcom_nandc_calc_ecc_bytes,
2543                      NANDC_STEP_SIZE, 4, 8);
2544
2545 static int qcom_nand_attach_chip(struct nand_chip *chip)
2546 {
2547         struct mtd_info *mtd = nand_to_mtd(chip);
2548         struct qcom_nand_host *host = to_qcom_nand_host(chip);
2549         struct nand_ecc_ctrl *ecc = &chip->ecc;
2550         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2551         int cwperpage, bad_block_byte, ret;
2552         bool wide_bus;
2553         int ecc_mode = 1;
2554
2555         /* controller only supports 512 bytes data steps */
2556         ecc->size = NANDC_STEP_SIZE;
2557         wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
2558         cwperpage = mtd->writesize / NANDC_STEP_SIZE;
2559
2560         /*
2561          * Each CW has 4 available OOB bytes which will be protected with ECC
2562          * so remaining bytes can be used for ECC.
2563          */
2564         ret = nand_ecc_choose_conf(chip, &qcom_nandc_ecc_caps,
2565                                    mtd->oobsize - (cwperpage * 4));
2566         if (ret) {
2567                 dev_err(nandc->dev, "No valid ECC settings possible\n");
2568                 return ret;
2569         }
2570
2571         if (ecc->strength >= 8) {
2572                 /* 8 bit ECC defaults to BCH ECC on all platforms */
2573                 host->bch_enabled = true;
2574                 ecc_mode = 1;
2575
2576                 if (wide_bus) {
2577                         host->ecc_bytes_hw = 14;
2578                         host->spare_bytes = 0;
2579                         host->bbm_size = 2;
2580                 } else {
2581                         host->ecc_bytes_hw = 13;
2582                         host->spare_bytes = 2;
2583                         host->bbm_size = 1;
2584                 }
2585         } else {
2586                 /*
2587                  * if the controller supports BCH for 4 bit ECC, the controller
2588                  * uses lesser bytes for ECC. If RS is used, the ECC bytes is
2589                  * always 10 bytes
2590                  */
2591                 if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
2592                         /* BCH */
2593                         host->bch_enabled = true;
2594                         ecc_mode = 0;
2595
2596                         if (wide_bus) {
2597                                 host->ecc_bytes_hw = 8;
2598                                 host->spare_bytes = 2;
2599                                 host->bbm_size = 2;
2600                         } else {
2601                                 host->ecc_bytes_hw = 7;
2602                                 host->spare_bytes = 4;
2603                                 host->bbm_size = 1;
2604                         }
2605                 } else {
2606                         /* RS */
2607                         host->ecc_bytes_hw = 10;
2608
2609                         if (wide_bus) {
2610                                 host->spare_bytes = 0;
2611                                 host->bbm_size = 2;
2612                         } else {
2613                                 host->spare_bytes = 1;
2614                                 host->bbm_size = 1;
2615                         }
2616                 }
2617         }
2618
2619         /*
2620          * we consider ecc->bytes as the sum of all the non-data content in a
2621          * step. It gives us a clean representation of the oob area (even if
2622          * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit
2623          * ECC and 12 bytes for 4 bit ECC
2624          */
2625         ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;
2626
2627         ecc->read_page          = qcom_nandc_read_page;
2628         ecc->read_page_raw      = qcom_nandc_read_page_raw;
2629         ecc->read_oob           = qcom_nandc_read_oob;
2630         ecc->write_page         = qcom_nandc_write_page;
2631         ecc->write_page_raw     = qcom_nandc_write_page_raw;
2632         ecc->write_oob          = qcom_nandc_write_oob;
2633
2634         ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2635
2636         mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
2637
2638         nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
2639                                      cwperpage);
2640
2641         /*
2642          * DATA_UD_BYTES varies based on whether the read/write command protects
2643          * spare data with ECC too. We protect spare data by default, so we set
2644          * it to main + spare data, which are 512 and 4 bytes respectively.
2645          */
2646         host->cw_data = 516;
2647
2648         /*
2649          * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes
2650          * for 8 bit ECC
2651          */
2652         host->cw_size = host->cw_data + ecc->bytes;
2653         bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
2654
2655         host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
2656                                 | host->cw_data << UD_SIZE_BYTES
2657                                 | 0 << DISABLE_STATUS_AFTER_WRITE
2658                                 | 5 << NUM_ADDR_CYCLES
2659                                 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
2660                                 | 0 << STATUS_BFR_READ
2661                                 | 1 << SET_RD_MODE_AFTER_STATUS
2662                                 | host->spare_bytes << SPARE_SIZE_BYTES;
2663
2664         host->cfg1 = 7 << NAND_RECOVERY_CYCLES
2665                                 | 0 <<  CS_ACTIVE_BSY
2666                                 | bad_block_byte << BAD_BLOCK_BYTE_NUM
2667                                 | 0 << BAD_BLOCK_IN_SPARE_AREA
2668                                 | 2 << WR_RD_BSY_GAP
2669                                 | wide_bus << WIDE_FLASH
2670                                 | host->bch_enabled << ENABLE_BCH_ECC;
2671
2672         host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
2673                                 | host->cw_size << UD_SIZE_BYTES
2674                                 | 5 << NUM_ADDR_CYCLES
2675                                 | 0 << SPARE_SIZE_BYTES;
2676
2677         host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
2678                                 | 0 << CS_ACTIVE_BSY
2679                                 | 17 << BAD_BLOCK_BYTE_NUM
2680                                 | 1 << BAD_BLOCK_IN_SPARE_AREA
2681                                 | 2 << WR_RD_BSY_GAP
2682                                 | wide_bus << WIDE_FLASH
2683                                 | 1 << DEV0_CFG1_ECC_DISABLE;
2684
2685         host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
2686                                 | 0 << ECC_SW_RESET
2687                                 | host->cw_data << ECC_NUM_DATA_BYTES
2688                                 | 1 << ECC_FORCE_CLK_OPEN
2689                                 | ecc_mode << ECC_MODE
2690                                 | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
2691
2692         host->ecc_buf_cfg = 0x203 << NUM_STEPS;
2693
2694         host->clrflashstatus = FS_READY_BSY_N;
2695         host->clrreadstatus = 0xc0;
2696         nandc->regs->erased_cw_detect_cfg_clr =
2697                 cpu_to_le32(CLR_ERASED_PAGE_DET);
2698         nandc->regs->erased_cw_detect_cfg_set =
2699                 cpu_to_le32(SET_ERASED_PAGE_DET);
2700
2701         dev_dbg(nandc->dev,
2702                 "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
2703                 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg,
2704                 host->cw_size, host->cw_data, ecc->strength, ecc->bytes,
2705                 cwperpage);
2706
2707         return 0;
2708 }
2709
2710 static const struct nand_controller_ops qcom_nandc_ops = {
2711         .attach_chip = qcom_nand_attach_chip,
2712 };
2713
2714 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2715 {
2716         if (nandc->props->is_bam) {
2717                 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2718                         dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2719                                          MAX_REG_RD *
2720                                          sizeof(*nandc->reg_read_buf),
2721                                          DMA_FROM_DEVICE);
2722
2723                 if (nandc->tx_chan)
2724                         dma_release_channel(nandc->tx_chan);
2725
2726                 if (nandc->rx_chan)
2727                         dma_release_channel(nandc->rx_chan);
2728
2729                 if (nandc->cmd_chan)
2730                         dma_release_channel(nandc->cmd_chan);
2731         } else {
2732                 if (nandc->chan)
2733                         dma_release_channel(nandc->chan);
2734         }
2735 }
2736
2737 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
2738 {
2739         int ret;
2740
2741         ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
2742         if (ret) {
2743                 dev_err(nandc->dev, "failed to set DMA mask\n");
2744                 return ret;
2745         }
2746
2747         /*
2748          * we use the internal buffer for reading ONFI params, reading small
2749          * data like ID and status, and preforming read-copy-write operations
2750          * when writing to a codeword partially. 532 is the maximum possible
2751          * size of a codeword for our nand controller
2752          */
2753         nandc->buf_size = 532;
2754
2755         nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size,
2756                                         GFP_KERNEL);
2757         if (!nandc->data_buffer)
2758                 return -ENOMEM;
2759
2760         nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs),
2761                                         GFP_KERNEL);
2762         if (!nandc->regs)
2763                 return -ENOMEM;
2764
2765         nandc->reg_read_buf = devm_kcalloc(nandc->dev,
2766                                 MAX_REG_RD, sizeof(*nandc->reg_read_buf),
2767                                 GFP_KERNEL);
2768         if (!nandc->reg_read_buf)
2769                 return -ENOMEM;
2770
2771         if (nandc->props->is_bam) {
2772                 nandc->reg_read_dma =
2773                         dma_map_single(nandc->dev, nandc->reg_read_buf,
2774                                        MAX_REG_RD *
2775                                        sizeof(*nandc->reg_read_buf),
2776                                        DMA_FROM_DEVICE);
2777                 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
2778                         dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
2779                         return -EIO;
2780                 }
2781
2782                 nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
2783                 if (IS_ERR(nandc->tx_chan)) {
2784                         ret = PTR_ERR(nandc->tx_chan);
2785                         nandc->tx_chan = NULL;
2786                         dev_err_probe(nandc->dev, ret,
2787                                       "tx DMA channel request failed\n");
2788                         goto unalloc;
2789                 }
2790
2791                 nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
2792                 if (IS_ERR(nandc->rx_chan)) {
2793                         ret = PTR_ERR(nandc->rx_chan);
2794                         nandc->rx_chan = NULL;
2795                         dev_err_probe(nandc->dev, ret,
2796                                       "rx DMA channel request failed\n");
2797                         goto unalloc;
2798                 }
2799
2800                 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
2801                 if (IS_ERR(nandc->cmd_chan)) {
2802                         ret = PTR_ERR(nandc->cmd_chan);
2803                         nandc->cmd_chan = NULL;
2804                         dev_err_probe(nandc->dev, ret,
2805                                       "cmd DMA channel request failed\n");
2806                         goto unalloc;
2807                 }
2808
2809                 /*
2810                  * Initially allocate BAM transaction to read ONFI param page.
2811                  * After detecting all the devices, this BAM transaction will
2812                  * be freed and the next BAM tranasction will be allocated with
2813                  * maximum codeword size
2814                  */
2815                 nandc->max_cwperpage = 1;
2816                 nandc->bam_txn = alloc_bam_transaction(nandc);
2817                 if (!nandc->bam_txn) {
2818                         dev_err(nandc->dev,
2819                                 "failed to allocate bam transaction\n");
2820                         ret = -ENOMEM;
2821                         goto unalloc;
2822                 }
2823         } else {
2824                 nandc->chan = dma_request_chan(nandc->dev, "rxtx");
2825                 if (IS_ERR(nandc->chan)) {
2826                         ret = PTR_ERR(nandc->chan);
2827                         nandc->chan = NULL;
2828                         dev_err_probe(nandc->dev, ret,
2829                                       "rxtx DMA channel request failed\n");
2830                         return ret;
2831                 }
2832         }
2833
2834         INIT_LIST_HEAD(&nandc->desc_list);
2835         INIT_LIST_HEAD(&nandc->host_list);
2836
2837         nand_controller_init(&nandc->controller);
2838         nandc->controller.ops = &qcom_nandc_ops;
2839
2840         return 0;
2841 unalloc:
2842         qcom_nandc_unalloc(nandc);
2843         return ret;
2844 }
2845
2846 /* one time setup of a few nand controller registers */
2847 static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
2848 {
2849         u32 nand_ctrl;
2850
2851         /* kill onenand */
2852         if (!nandc->props->is_qpic)
2853                 nandc_write(nandc, SFLASHC_BURST_CFG, 0);
2854
2855         if (!nandc->props->qpic_v2)
2856                 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
2857                             NAND_DEV_CMD_VLD_VAL);
2858
2859         /* enable ADM or BAM DMA */
2860         if (nandc->props->is_bam) {
2861                 nand_ctrl = nandc_read(nandc, NAND_CTRL);
2862
2863                 /*
2864                  *NAND_CTRL is an operational registers, and CPU
2865                  * access to operational registers are read only
2866                  * in BAM mode. So update the NAND_CTRL register
2867                  * only if it is not in BAM mode. In most cases BAM
2868                  * mode will be enabled in bootloader
2869                  */
2870                 if (!(nand_ctrl & BAM_MODE_EN))
2871                         nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
2872         } else {
2873                 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
2874         }
2875
2876         /* save the original values of these registers */
2877         if (!nandc->props->qpic_v2) {
2878                 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
2879                 nandc->vld = NAND_DEV_CMD_VLD_VAL;
2880         }
2881
2882         return 0;
2883 }
2884
2885 static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL };
2886
2887 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
2888                                             struct qcom_nand_host *host,
2889                                             struct device_node *dn)
2890 {
2891         struct nand_chip *chip = &host->chip;
2892         struct mtd_info *mtd = nand_to_mtd(chip);
2893         struct device *dev = nandc->dev;
2894         int ret;
2895
2896         ret = of_property_read_u32(dn, "reg", &host->cs);
2897         if (ret) {
2898                 dev_err(dev, "can't get chip-select\n");
2899                 return -ENXIO;
2900         }
2901
2902         nand_set_flash_node(chip, dn);
2903         mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
2904         if (!mtd->name)
2905                 return -ENOMEM;
2906
2907         mtd->owner = THIS_MODULE;
2908         mtd->dev.parent = dev;
2909
2910         chip->legacy.cmdfunc    = qcom_nandc_command;
2911         chip->legacy.select_chip        = qcom_nandc_select_chip;
2912         chip->legacy.read_byte  = qcom_nandc_read_byte;
2913         chip->legacy.read_buf   = qcom_nandc_read_buf;
2914         chip->legacy.write_buf  = qcom_nandc_write_buf;
2915         chip->legacy.set_features       = nand_get_set_features_notsupp;
2916         chip->legacy.get_features       = nand_get_set_features_notsupp;
2917
2918         /*
2919          * the bad block marker is readable only when we read the last codeword
2920          * of a page with ECC disabled. currently, the nand_base and nand_bbt
2921          * helpers don't allow us to read BB from a nand chip with ECC
2922          * disabled (MTD_OPS_PLACE_OOB is set by default). use the block_bad
2923          * and block_markbad helpers until we permanently switch to using
2924          * MTD_OPS_RAW for all drivers (with the help of badblockbits)
2925          */
2926         chip->legacy.block_bad          = qcom_nandc_block_bad;
2927         chip->legacy.block_markbad      = qcom_nandc_block_markbad;
2928
2929         chip->controller = &nandc->controller;
2930         chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA |
2931                          NAND_SKIP_BBTSCAN;
2932
2933         /* set up initial status value */
2934         host->status = NAND_STATUS_READY | NAND_STATUS_WP;
2935
2936         ret = nand_scan(chip, 1);
2937         if (ret)
2938                 return ret;
2939
2940         if (nandc->props->is_bam) {
2941                 free_bam_transaction(nandc);
2942                 nandc->bam_txn = alloc_bam_transaction(nandc);
2943                 if (!nandc->bam_txn) {
2944                         dev_err(nandc->dev,
2945                                 "failed to allocate bam transaction\n");
2946                         nand_cleanup(chip);
2947                         return -ENOMEM;
2948                 }
2949         }
2950
2951         ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
2952         if (ret)
2953                 nand_cleanup(chip);
2954
2955         return ret;
2956 }
2957
2958 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
2959 {
2960         struct device *dev = nandc->dev;
2961         struct device_node *dn = dev->of_node, *child;
2962         struct qcom_nand_host *host;
2963         int ret = -ENODEV;
2964
2965         for_each_available_child_of_node(dn, child) {
2966                 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2967                 if (!host) {
2968                         of_node_put(child);
2969                         return -ENOMEM;
2970                 }
2971
2972                 ret = qcom_nand_host_init_and_register(nandc, host, child);
2973                 if (ret) {
2974                         devm_kfree(dev, host);
2975                         continue;
2976                 }
2977
2978                 list_add_tail(&host->node, &nandc->host_list);
2979         }
2980
2981         return ret;
2982 }
2983
2984 /* parse custom DT properties here */
2985 static int qcom_nandc_parse_dt(struct platform_device *pdev)
2986 {
2987         struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
2988         struct device_node *np = nandc->dev->of_node;
2989         int ret;
2990
2991         if (!nandc->props->is_bam) {
2992                 ret = of_property_read_u32(np, "qcom,cmd-crci",
2993                                            &nandc->cmd_crci);
2994                 if (ret) {
2995                         dev_err(nandc->dev, "command CRCI unspecified\n");
2996                         return ret;
2997                 }
2998
2999                 ret = of_property_read_u32(np, "qcom,data-crci",
3000                                            &nandc->data_crci);
3001                 if (ret) {
3002                         dev_err(nandc->dev, "data CRCI unspecified\n");
3003                         return ret;
3004                 }
3005         }
3006
3007         return 0;
3008 }
3009
3010 static int qcom_nandc_probe(struct platform_device *pdev)
3011 {
3012         struct qcom_nand_controller *nandc;
3013         const void *dev_data;
3014         struct device *dev = &pdev->dev;
3015         struct resource *res;
3016         int ret;
3017
3018         nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
3019         if (!nandc)
3020                 return -ENOMEM;
3021
3022         platform_set_drvdata(pdev, nandc);
3023         nandc->dev = dev;
3024
3025         dev_data = of_device_get_match_data(dev);
3026         if (!dev_data) {
3027                 dev_err(&pdev->dev, "failed to get device data\n");
3028                 return -ENODEV;
3029         }
3030
3031         nandc->props = dev_data;
3032
3033         nandc->core_clk = devm_clk_get(dev, "core");
3034         if (IS_ERR(nandc->core_clk))
3035                 return PTR_ERR(nandc->core_clk);
3036
3037         nandc->aon_clk = devm_clk_get(dev, "aon");
3038         if (IS_ERR(nandc->aon_clk))
3039                 return PTR_ERR(nandc->aon_clk);
3040
3041         ret = qcom_nandc_parse_dt(pdev);
3042         if (ret)
3043                 return ret;
3044
3045         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3046         nandc->base = devm_ioremap_resource(dev, res);
3047         if (IS_ERR(nandc->base))
3048                 return PTR_ERR(nandc->base);
3049
3050         nandc->base_phys = res->start;
3051         nandc->base_dma = dma_map_resource(dev, res->start,
3052                                            resource_size(res),
3053                                            DMA_BIDIRECTIONAL, 0);
3054         if (dma_mapping_error(dev, nandc->base_dma))
3055                 return -ENXIO;
3056
3057         ret = qcom_nandc_alloc(nandc);
3058         if (ret)
3059                 goto err_nandc_alloc;
3060
3061         ret = clk_prepare_enable(nandc->core_clk);
3062         if (ret)
3063                 goto err_core_clk;
3064
3065         ret = clk_prepare_enable(nandc->aon_clk);
3066         if (ret)
3067                 goto err_aon_clk;
3068
3069         ret = qcom_nandc_setup(nandc);
3070         if (ret)
3071                 goto err_setup;
3072
3073         ret = qcom_probe_nand_devices(nandc);
3074         if (ret)
3075                 goto err_setup;
3076
3077         return 0;
3078
3079 err_setup:
3080         clk_disable_unprepare(nandc->aon_clk);
3081 err_aon_clk:
3082         clk_disable_unprepare(nandc->core_clk);
3083 err_core_clk:
3084         qcom_nandc_unalloc(nandc);
3085 err_nandc_alloc:
3086         dma_unmap_resource(dev, res->start, resource_size(res),
3087                            DMA_BIDIRECTIONAL, 0);
3088
3089         return ret;
3090 }
3091
3092 static int qcom_nandc_remove(struct platform_device *pdev)
3093 {
3094         struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
3095         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3096         struct qcom_nand_host *host;
3097         struct nand_chip *chip;
3098         int ret;
3099
3100         list_for_each_entry(host, &nandc->host_list, node) {
3101                 chip = &host->chip;
3102                 ret = mtd_device_unregister(nand_to_mtd(chip));
3103                 WARN_ON(ret);
3104                 nand_cleanup(chip);
3105         }
3106
3107         qcom_nandc_unalloc(nandc);
3108
3109         clk_disable_unprepare(nandc->aon_clk);
3110         clk_disable_unprepare(nandc->core_clk);
3111
3112         dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res),
3113                            DMA_BIDIRECTIONAL, 0);
3114
3115         return 0;
3116 }
3117
3118 static const struct qcom_nandc_props ipq806x_nandc_props = {
3119         .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
3120         .is_bam = false,
3121         .dev_cmd_reg_start = 0x0,
3122 };
3123
3124 static const struct qcom_nandc_props ipq4019_nandc_props = {
3125         .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
3126         .is_bam = true,
3127         .is_qpic = true,
3128         .dev_cmd_reg_start = 0x0,
3129 };
3130
3131 static const struct qcom_nandc_props ipq8074_nandc_props = {
3132         .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
3133         .is_bam = true,
3134         .is_qpic = true,
3135         .dev_cmd_reg_start = 0x7000,
3136 };
3137
3138 static const struct qcom_nandc_props sdx55_nandc_props = {
3139         .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
3140         .is_bam = true,
3141         .is_qpic = true,
3142         .qpic_v2 = true,
3143         .dev_cmd_reg_start = 0x7000,
3144 };
3145
3146 /*
3147  * data will hold a struct pointer containing more differences once we support
3148  * more controller variants
3149  */
3150 static const struct of_device_id qcom_nandc_of_match[] = {
3151         {
3152                 .compatible = "qcom,ipq806x-nand",
3153                 .data = &ipq806x_nandc_props,
3154         },
3155         {
3156                 .compatible = "qcom,ipq4019-nand",
3157                 .data = &ipq4019_nandc_props,
3158         },
3159         {
3160                 .compatible = "qcom,ipq6018-nand",
3161                 .data = &ipq8074_nandc_props,
3162         },
3163         {
3164                 .compatible = "qcom,ipq8074-nand",
3165                 .data = &ipq8074_nandc_props,
3166         },
3167         {
3168                 .compatible = "qcom,sdx55-nand",
3169                 .data = &sdx55_nandc_props,
3170         },
3171         {}
3172 };
3173 MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
3174
3175 static struct platform_driver qcom_nandc_driver = {
3176         .driver = {
3177                 .name = "qcom-nandc",
3178                 .of_match_table = qcom_nandc_of_match,
3179         },
3180         .probe   = qcom_nandc_probe,
3181         .remove  = qcom_nandc_remove,
3182 };
3183 module_platform_driver(qcom_nandc_driver);
3184
3185 MODULE_AUTHOR("Archit Taneja <architt@codeaurora.org>");
3186 MODULE_DESCRIPTION("Qualcomm NAND Controller driver");
3187 MODULE_LICENSE("GPL v2");