1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
4 * Copyright © 2004 Micron Technology Inc.
5 * Copyright © 2004 David Brownell
8 #include <linux/platform_device.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/sched.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
19 #include <linux/mtd/rawnand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/omap-dma.h>
23 #include <linux/slab.h>
25 #include <linux/of_device.h>
27 #include <linux/platform_data/elm.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
33 #define OMAP_NAND_TIMEOUT_MS 5000
35 #define NAND_Ecc_P1e (1 << 0)
36 #define NAND_Ecc_P2e (1 << 1)
37 #define NAND_Ecc_P4e (1 << 2)
38 #define NAND_Ecc_P8e (1 << 3)
39 #define NAND_Ecc_P16e (1 << 4)
40 #define NAND_Ecc_P32e (1 << 5)
41 #define NAND_Ecc_P64e (1 << 6)
42 #define NAND_Ecc_P128e (1 << 7)
43 #define NAND_Ecc_P256e (1 << 8)
44 #define NAND_Ecc_P512e (1 << 9)
45 #define NAND_Ecc_P1024e (1 << 10)
46 #define NAND_Ecc_P2048e (1 << 11)
48 #define NAND_Ecc_P1o (1 << 16)
49 #define NAND_Ecc_P2o (1 << 17)
50 #define NAND_Ecc_P4o (1 << 18)
51 #define NAND_Ecc_P8o (1 << 19)
52 #define NAND_Ecc_P16o (1 << 20)
53 #define NAND_Ecc_P32o (1 << 21)
54 #define NAND_Ecc_P64o (1 << 22)
55 #define NAND_Ecc_P128o (1 << 23)
56 #define NAND_Ecc_P256o (1 << 24)
57 #define NAND_Ecc_P512o (1 << 25)
58 #define NAND_Ecc_P1024o (1 << 26)
59 #define NAND_Ecc_P2048o (1 << 27)
61 #define TF(value) (value ? 1 : 0)
63 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
64 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
65 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
66 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
67 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
68 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
69 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
70 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
73 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
74 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
75 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
76 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
77 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
78 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
79 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
82 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
83 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
84 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
85 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
86 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
87 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
88 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
91 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
92 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
93 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
94 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
95 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
96 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
97 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
100 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102 #define PREFETCH_CONFIG1_CS_SHIFT 24
103 #define ECC_CONFIG_CS_SHIFT 1
105 #define ENABLE_PREFETCH (0x1 << 7)
106 #define DMA_MPU_MODE_SHIFT 2
107 #define ECCSIZE0_SHIFT 12
108 #define ECCSIZE1_SHIFT 22
109 #define ECC1RESULTSIZE 0x1
110 #define ECCCLEAR 0x100
112 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
113 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
114 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
115 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
116 #define STATUS_BUFF_EMPTY 0x00000001
118 #define SECTOR_BYTES 512
119 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
120 #define BCH4_BIT_PAD 4
122 /* GPMC ecc engine settings for read */
123 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
124 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
125 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
126 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
127 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
129 /* GPMC ecc engine settings for write */
130 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
132 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
137 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
138 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
140 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
141 0xac, 0x6b, 0xff, 0x99, 0x7b};
142 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
144 struct omap_nand_info {
145 struct nand_chip nand;
146 struct platform_device *pdev;
150 enum nand_io xfer_type;
152 enum omap_ecc ecc_opt;
153 struct device_node *elm_of_node;
155 unsigned long phys_base;
156 struct completion comp;
157 struct dma_chan *dma;
161 OMAP_NAND_IO_READ = 0, /* read */
162 OMAP_NAND_IO_WRITE, /* write */
166 /* Interface to GPMC */
167 struct gpmc_nand_regs reg;
168 struct gpmc_nand_ops *ops;
170 /* fields specific for BCHx_HW ECC scheme */
171 struct device *elm_dev;
172 /* NAND ready gpio */
173 struct gpio_desc *ready_gpiod;
175 unsigned int nsteps_per_eccpg;
176 unsigned int eccpg_size;
177 unsigned int eccpg_bytes;
180 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
182 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
186 * omap_prefetch_enable - configures and starts prefetch transfer
187 * @cs: cs (chip select) number
188 * @fifo_th: fifo threshold to be used for read/ write
189 * @dma_mode: dma mode enable (1) or disable (0)
190 * @u32_count: number of bytes to be transferred
191 * @is_write: prefetch read(0) or write post(1) mode
192 * @info: NAND device structure containing platform data
194 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
195 unsigned int u32_count, int is_write, struct omap_nand_info *info)
199 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
202 if (readl(info->reg.gpmc_prefetch_control))
205 /* Set the amount of bytes to be prefetched */
206 writel(u32_count, info->reg.gpmc_prefetch_config2);
208 /* Set dma/mpu mode, the prefetch read / post write and
209 * enable the engine. Set which cs is has requested for.
211 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
212 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
213 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1));
214 writel(val, info->reg.gpmc_prefetch_config1);
216 /* Start the prefetch engine */
217 writel(0x1, info->reg.gpmc_prefetch_control);
223 * omap_prefetch_reset - disables and stops the prefetch engine
225 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
229 /* check if the same module/cs is trying to reset */
230 config1 = readl(info->reg.gpmc_prefetch_config1);
231 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
234 /* Stop the PFPW engine */
235 writel(0x0, info->reg.gpmc_prefetch_control);
237 /* Reset/disable the PFPW engine */
238 writel(0x0, info->reg.gpmc_prefetch_config1);
244 * omap_hwcontrol - hardware specific access to control-lines
245 * @chip: NAND chip object
246 * @cmd: command to device
248 * NAND_NCE: bit 0 -> don't care
249 * NAND_CLE: bit 1 -> Command Latch
250 * NAND_ALE: bit 2 -> Address Latch
252 * NOTE: boards may use different bits for these!!
254 static void omap_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
256 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
258 if (cmd != NAND_CMD_NONE) {
260 writeb(cmd, info->reg.gpmc_nand_command);
262 else if (ctrl & NAND_ALE)
263 writeb(cmd, info->reg.gpmc_nand_address);
266 writeb(cmd, info->reg.gpmc_nand_data);
271 * omap_read_buf8 - read data from NAND controller into buffer
272 * @mtd: MTD device structure
273 * @buf: buffer to store date
274 * @len: number of bytes to read
276 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
278 struct nand_chip *nand = mtd_to_nand(mtd);
280 ioread8_rep(nand->legacy.IO_ADDR_R, buf, len);
284 * omap_write_buf8 - write buffer to NAND controller
285 * @mtd: MTD device structure
287 * @len: number of bytes to write
289 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
291 struct omap_nand_info *info = mtd_to_omap(mtd);
292 u_char *p = (u_char *)buf;
296 iowrite8(*p++, info->nand.legacy.IO_ADDR_W);
297 /* wait until buffer is available for write */
299 status = info->ops->nand_writebuffer_empty();
305 * omap_read_buf16 - read data from NAND controller into buffer
306 * @mtd: MTD device structure
307 * @buf: buffer to store date
308 * @len: number of bytes to read
310 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
312 struct nand_chip *nand = mtd_to_nand(mtd);
314 ioread16_rep(nand->legacy.IO_ADDR_R, buf, len / 2);
318 * omap_write_buf16 - write buffer to NAND controller
319 * @mtd: MTD device structure
321 * @len: number of bytes to write
323 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
325 struct omap_nand_info *info = mtd_to_omap(mtd);
326 u16 *p = (u16 *) buf;
328 /* FIXME try bursts of writesw() or DMA ... */
332 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
333 /* wait until buffer is available for write */
335 status = info->ops->nand_writebuffer_empty();
341 * omap_read_buf_pref - read data from NAND controller into buffer
342 * @chip: NAND chip object
343 * @buf: buffer to store date
344 * @len: number of bytes to read
346 static void omap_read_buf_pref(struct nand_chip *chip, u_char *buf, int len)
348 struct mtd_info *mtd = nand_to_mtd(chip);
349 struct omap_nand_info *info = mtd_to_omap(mtd);
350 uint32_t r_count = 0;
354 /* take care of subpage reads */
356 if (info->nand.options & NAND_BUSWIDTH_16)
357 omap_read_buf16(mtd, buf, len % 4);
359 omap_read_buf8(mtd, buf, len % 4);
360 p = (u32 *) (buf + len % 4);
364 /* configure and start prefetch transfer */
365 ret = omap_prefetch_enable(info->gpmc_cs,
366 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
368 /* PFPW engine is busy, use cpu copy method */
369 if (info->nand.options & NAND_BUSWIDTH_16)
370 omap_read_buf16(mtd, (u_char *)p, len);
372 omap_read_buf8(mtd, (u_char *)p, len);
375 r_count = readl(info->reg.gpmc_prefetch_status);
376 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
377 r_count = r_count >> 2;
378 ioread32_rep(info->nand.legacy.IO_ADDR_R, p, r_count);
382 /* disable and stop the PFPW engine */
383 omap_prefetch_reset(info->gpmc_cs, info);
388 * omap_write_buf_pref - write buffer to NAND controller
389 * @chip: NAND chip object
391 * @len: number of bytes to write
393 static void omap_write_buf_pref(struct nand_chip *chip, const u_char *buf,
396 struct mtd_info *mtd = nand_to_mtd(chip);
397 struct omap_nand_info *info = mtd_to_omap(mtd);
398 uint32_t w_count = 0;
401 unsigned long tim, limit;
404 /* take care of subpage writes */
406 writeb(*buf, info->nand.legacy.IO_ADDR_W);
407 p = (u16 *)(buf + 1);
411 /* configure and start prefetch transfer */
412 ret = omap_prefetch_enable(info->gpmc_cs,
413 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
415 /* PFPW engine is busy, use cpu copy method */
416 if (info->nand.options & NAND_BUSWIDTH_16)
417 omap_write_buf16(mtd, (u_char *)p, len);
419 omap_write_buf8(mtd, (u_char *)p, len);
422 w_count = readl(info->reg.gpmc_prefetch_status);
423 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
424 w_count = w_count >> 1;
425 for (i = 0; (i < w_count) && len; i++, len -= 2)
426 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
428 /* wait for data to flushed-out before reset the prefetch */
430 limit = (loops_per_jiffy *
431 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
434 val = readl(info->reg.gpmc_prefetch_status);
435 val = PREFETCH_STATUS_COUNT(val);
436 } while (val && (tim++ < limit));
438 /* disable and stop the PFPW engine */
439 omap_prefetch_reset(info->gpmc_cs, info);
444 * omap_nand_dma_callback: callback on the completion of dma transfer
445 * @data: pointer to completion data structure
447 static void omap_nand_dma_callback(void *data)
449 complete((struct completion *) data);
453 * omap_nand_dma_transfer: configure and start dma transfer
454 * @mtd: MTD device structure
455 * @addr: virtual address in RAM of source/destination
456 * @len: number of data bytes to be transferred
457 * @is_write: flag for read/write operation
459 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
460 unsigned int len, int is_write)
462 struct omap_nand_info *info = mtd_to_omap(mtd);
463 struct dma_async_tx_descriptor *tx;
464 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
466 struct scatterlist sg;
467 unsigned long tim, limit;
472 if (!virt_addr_valid(addr))
475 sg_init_one(&sg, addr, len);
476 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
478 dev_err(&info->pdev->dev,
479 "Couldn't DMA map a %d byte buffer\n", len);
483 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
484 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
485 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 tx->callback = omap_nand_dma_callback;
490 tx->callback_param = &info->comp;
491 dmaengine_submit(tx);
493 init_completion(&info->comp);
495 /* setup and start DMA using dma_addr */
496 dma_async_issue_pending(info->dma);
498 /* configure and start prefetch transfer */
499 ret = omap_prefetch_enable(info->gpmc_cs,
500 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
502 /* PFPW engine is busy, use cpu copy method */
505 wait_for_completion(&info->comp);
507 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
511 val = readl(info->reg.gpmc_prefetch_status);
512 val = PREFETCH_STATUS_COUNT(val);
513 } while (val && (tim++ < limit));
515 /* disable and stop the PFPW engine */
516 omap_prefetch_reset(info->gpmc_cs, info);
518 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
522 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
524 if (info->nand.options & NAND_BUSWIDTH_16)
525 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
526 : omap_write_buf16(mtd, (u_char *) addr, len);
528 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
529 : omap_write_buf8(mtd, (u_char *) addr, len);
534 * omap_read_buf_dma_pref - read data from NAND controller into buffer
535 * @chip: NAND chip object
536 * @buf: buffer to store date
537 * @len: number of bytes to read
539 static void omap_read_buf_dma_pref(struct nand_chip *chip, u_char *buf,
542 struct mtd_info *mtd = nand_to_mtd(chip);
544 if (len <= mtd->oobsize)
545 omap_read_buf_pref(chip, buf, len);
547 /* start transfer in DMA mode */
548 omap_nand_dma_transfer(mtd, buf, len, 0x0);
552 * omap_write_buf_dma_pref - write buffer to NAND controller
553 * @chip: NAND chip object
555 * @len: number of bytes to write
557 static void omap_write_buf_dma_pref(struct nand_chip *chip, const u_char *buf,
560 struct mtd_info *mtd = nand_to_mtd(chip);
562 if (len <= mtd->oobsize)
563 omap_write_buf_pref(chip, buf, len);
565 /* start transfer in DMA mode */
566 omap_nand_dma_transfer(mtd, (u_char *)buf, len, 0x1);
570 * omap_nand_irq - GPMC irq handler
571 * @this_irq: gpmc irq number
572 * @dev: omap_nand_info structure pointer is passed here
574 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
576 struct omap_nand_info *info = (struct omap_nand_info *) dev;
579 bytes = readl(info->reg.gpmc_prefetch_status);
580 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
581 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
582 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
583 if (this_irq == info->gpmc_irq_count)
586 if (info->buf_len && (info->buf_len < bytes))
587 bytes = info->buf_len;
588 else if (!info->buf_len)
590 iowrite32_rep(info->nand.legacy.IO_ADDR_W, (u32 *)info->buf,
592 info->buf = info->buf + bytes;
593 info->buf_len -= bytes;
596 ioread32_rep(info->nand.legacy.IO_ADDR_R, (u32 *)info->buf,
598 info->buf = info->buf + bytes;
600 if (this_irq == info->gpmc_irq_count)
607 complete(&info->comp);
609 disable_irq_nosync(info->gpmc_irq_fifo);
610 disable_irq_nosync(info->gpmc_irq_count);
616 * omap_read_buf_irq_pref - read data from NAND controller into buffer
617 * @chip: NAND chip object
618 * @buf: buffer to store date
619 * @len: number of bytes to read
621 static void omap_read_buf_irq_pref(struct nand_chip *chip, u_char *buf,
624 struct mtd_info *mtd = nand_to_mtd(chip);
625 struct omap_nand_info *info = mtd_to_omap(mtd);
628 if (len <= mtd->oobsize) {
629 omap_read_buf_pref(chip, buf, len);
633 info->iomode = OMAP_NAND_IO_READ;
635 init_completion(&info->comp);
637 /* configure and start prefetch transfer */
638 ret = omap_prefetch_enable(info->gpmc_cs,
639 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
641 /* PFPW engine is busy, use cpu copy method */
646 enable_irq(info->gpmc_irq_count);
647 enable_irq(info->gpmc_irq_fifo);
649 /* waiting for read to complete */
650 wait_for_completion(&info->comp);
652 /* disable and stop the PFPW engine */
653 omap_prefetch_reset(info->gpmc_cs, info);
657 if (info->nand.options & NAND_BUSWIDTH_16)
658 omap_read_buf16(mtd, buf, len);
660 omap_read_buf8(mtd, buf, len);
664 * omap_write_buf_irq_pref - write buffer to NAND controller
665 * @chip: NAND chip object
667 * @len: number of bytes to write
669 static void omap_write_buf_irq_pref(struct nand_chip *chip, const u_char *buf,
672 struct mtd_info *mtd = nand_to_mtd(chip);
673 struct omap_nand_info *info = mtd_to_omap(mtd);
675 unsigned long tim, limit;
678 if (len <= mtd->oobsize) {
679 omap_write_buf_pref(chip, buf, len);
683 info->iomode = OMAP_NAND_IO_WRITE;
684 info->buf = (u_char *) buf;
685 init_completion(&info->comp);
687 /* configure and start prefetch transfer : size=24 */
688 ret = omap_prefetch_enable(info->gpmc_cs,
689 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
691 /* PFPW engine is busy, use cpu copy method */
696 enable_irq(info->gpmc_irq_count);
697 enable_irq(info->gpmc_irq_fifo);
699 /* waiting for write to complete */
700 wait_for_completion(&info->comp);
702 /* wait for data to flushed-out before reset the prefetch */
704 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
706 val = readl(info->reg.gpmc_prefetch_status);
707 val = PREFETCH_STATUS_COUNT(val);
709 } while (val && (tim++ < limit));
711 /* disable and stop the PFPW engine */
712 omap_prefetch_reset(info->gpmc_cs, info);
716 if (info->nand.options & NAND_BUSWIDTH_16)
717 omap_write_buf16(mtd, buf, len);
719 omap_write_buf8(mtd, buf, len);
723 * gen_true_ecc - This function will generate true ECC value
724 * @ecc_buf: buffer to store ecc code
726 * This generated true ECC value can be used when correcting
727 * data read from NAND flash memory core
729 static void gen_true_ecc(u8 *ecc_buf)
731 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
732 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
734 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
735 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
736 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
737 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
738 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
739 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
743 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
744 * @ecc_data1: ecc code from nand spare area
745 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
746 * @page_data: page data
748 * This function compares two ECC's and indicates if there is an error.
749 * If the error can be corrected it will be corrected to the buffer.
750 * If there is no error, %0 is returned. If there is an error but it
751 * was corrected, %1 is returned. Otherwise, %-1 is returned.
753 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
754 u8 *ecc_data2, /* read from register */
758 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
759 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
766 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
768 gen_true_ecc(ecc_data1);
769 gen_true_ecc(ecc_data2);
771 for (i = 0; i <= 2; i++) {
772 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
773 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
776 for (i = 0; i < 8; i++) {
777 tmp0_bit[i] = *ecc_data1 % 2;
778 *ecc_data1 = *ecc_data1 / 2;
781 for (i = 0; i < 8; i++) {
782 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
783 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
786 for (i = 0; i < 8; i++) {
787 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
788 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
791 for (i = 0; i < 8; i++) {
792 comp0_bit[i] = *ecc_data2 % 2;
793 *ecc_data2 = *ecc_data2 / 2;
796 for (i = 0; i < 8; i++) {
797 comp1_bit[i] = *(ecc_data2 + 1) % 2;
798 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
801 for (i = 0; i < 8; i++) {
802 comp2_bit[i] = *(ecc_data2 + 2) % 2;
803 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
806 for (i = 0; i < 6; i++)
807 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
809 for (i = 0; i < 8; i++)
810 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
812 for (i = 0; i < 8; i++)
813 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
815 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
816 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
818 for (i = 0; i < 24; i++)
819 ecc_sum += ecc_bit[i];
823 /* Not reached because this function is not called if
824 * ECC values are equal
829 /* Uncorrectable error */
830 pr_debug("ECC UNCORRECTED_ERROR 1\n");
834 /* UN-Correctable error */
835 pr_debug("ECC UNCORRECTED_ERROR B\n");
839 /* Correctable error */
840 find_byte = (ecc_bit[23] << 8) +
850 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
852 pr_debug("Correcting single bit ECC error at offset: "
853 "%d, bit: %d\n", find_byte, find_bit);
855 page_data[find_byte] ^= (1 << find_bit);
860 if (ecc_data2[0] == 0 &&
865 pr_debug("UNCORRECTED_ERROR default\n");
871 * omap_correct_data - Compares the ECC read with HW generated ECC
872 * @chip: NAND chip object
874 * @read_ecc: ecc read from nand flash
875 * @calc_ecc: ecc read from HW ECC registers
877 * Compares the ecc read from nand spare area with ECC registers values
878 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
879 * detection and correction. If there are no errors, %0 is returned. If
880 * there were errors and all of the errors were corrected, the number of
881 * corrected errors is returned. If uncorrectable errors exist, %-1 is
884 static int omap_correct_data(struct nand_chip *chip, u_char *dat,
885 u_char *read_ecc, u_char *calc_ecc)
887 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
888 int blockCnt = 0, i = 0, ret = 0;
891 /* Ex NAND_ECC_HW12_2048 */
892 if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
893 info->nand.ecc.size == 2048)
898 for (i = 0; i < blockCnt; i++) {
899 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
900 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
903 /* keep track of the number of corrected errors */
914 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
915 * @chip: NAND chip object
916 * @dat: The pointer to data on which ecc is computed
917 * @ecc_code: The ecc_code buffer
919 * Using noninverted ECC can be considered ugly since writing a blank
920 * page ie. padding will clear the ECC bytes. This is no problem as long
921 * nobody is trying to write data on the seemingly unused page. Reading
922 * an erased page will produce an ECC mismatch between generated and read
923 * ECC bytes that has to be dealt with separately.
925 static int omap_calculate_ecc(struct nand_chip *chip, const u_char *dat,
928 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
931 val = readl(info->reg.gpmc_ecc_config);
932 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
935 /* read ecc result */
936 val = readl(info->reg.gpmc_ecc1_result);
937 *ecc_code++ = val; /* P128e, ..., P1e */
938 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
939 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
940 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
946 * omap_enable_hwecc - This function enables the hardware ecc functionality
947 * @chip: NAND chip object
948 * @mode: Read/Write mode
950 static void omap_enable_hwecc(struct nand_chip *chip, int mode)
952 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
953 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
956 /* clear ecc and enable bits */
957 val = ECCCLEAR | ECC1;
958 writel(val, info->reg.gpmc_ecc_control);
960 /* program ecc and result sizes */
961 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
963 writel(val, info->reg.gpmc_ecc_size_config);
968 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
970 case NAND_ECC_READSYN:
971 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
974 dev_info(&info->pdev->dev,
975 "error: unrecognized Mode[%d]!\n", mode);
979 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
980 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
981 writel(val, info->reg.gpmc_ecc_config);
985 * omap_wait - wait until the command is done
986 * @this: NAND Chip structure
988 * Wait function is called during Program and erase operations and
989 * the way it is called from MTD layer, we should wait till the NAND
990 * chip is ready after the programming/erase operation has completed.
992 * Erase can take up to 400ms and program up to 20ms according to
993 * general NAND and SmartMedia specs
995 static int omap_wait(struct nand_chip *this)
997 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
998 unsigned long timeo = jiffies;
1001 timeo += msecs_to_jiffies(400);
1003 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1004 while (time_before(jiffies, timeo)) {
1005 status = readb(info->reg.gpmc_nand_data);
1006 if (status & NAND_STATUS_READY)
1011 status = readb(info->reg.gpmc_nand_data);
1016 * omap_dev_ready - checks the NAND Ready GPIO line
1017 * @chip: NAND chip object
1019 * Returns true if ready and false if busy.
1021 static int omap_dev_ready(struct nand_chip *chip)
1023 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1025 return gpiod_get_value(info->ready_gpiod);
1029 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1030 * @chip: NAND chip object
1031 * @mode: Read/Write mode
1033 * When using BCH with SW correction (i.e. no ELM), sector size is set
1034 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1035 * for both reading and writing with:
1036 * eccsize0 = 0 (no additional protected byte in spare area)
1037 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1039 static void __maybe_unused omap_enable_hwecc_bch(struct nand_chip *chip,
1042 unsigned int bch_type;
1043 unsigned int dev_width, nsectors;
1044 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1045 enum omap_ecc ecc_opt = info->ecc_opt;
1047 unsigned int ecc_size1, ecc_size0;
1049 /* GPMC configurations for calculating ECC */
1051 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1054 wr_mode = BCH_WRAPMODE_6;
1055 ecc_size0 = BCH_ECC_SIZE0;
1056 ecc_size1 = BCH_ECC_SIZE1;
1058 case OMAP_ECC_BCH4_CODE_HW:
1060 nsectors = chip->ecc.steps;
1061 if (mode == NAND_ECC_READ) {
1062 wr_mode = BCH_WRAPMODE_1;
1063 ecc_size0 = BCH4R_ECC_SIZE0;
1064 ecc_size1 = BCH4R_ECC_SIZE1;
1066 wr_mode = BCH_WRAPMODE_6;
1067 ecc_size0 = BCH_ECC_SIZE0;
1068 ecc_size1 = BCH_ECC_SIZE1;
1071 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1074 wr_mode = BCH_WRAPMODE_6;
1075 ecc_size0 = BCH_ECC_SIZE0;
1076 ecc_size1 = BCH_ECC_SIZE1;
1078 case OMAP_ECC_BCH8_CODE_HW:
1080 nsectors = chip->ecc.steps;
1081 if (mode == NAND_ECC_READ) {
1082 wr_mode = BCH_WRAPMODE_1;
1083 ecc_size0 = BCH8R_ECC_SIZE0;
1084 ecc_size1 = BCH8R_ECC_SIZE1;
1086 wr_mode = BCH_WRAPMODE_6;
1087 ecc_size0 = BCH_ECC_SIZE0;
1088 ecc_size1 = BCH_ECC_SIZE1;
1091 case OMAP_ECC_BCH16_CODE_HW:
1093 nsectors = chip->ecc.steps;
1094 if (mode == NAND_ECC_READ) {
1096 ecc_size0 = 52; /* ECC bits in nibbles per sector */
1097 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
1100 ecc_size0 = 0; /* extra bits in nibbles per sector */
1101 ecc_size1 = 52; /* OOB bits in nibbles per sector */
1108 writel(ECC1, info->reg.gpmc_ecc_control);
1110 /* Configure ecc size for BCH */
1111 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1112 writel(val, info->reg.gpmc_ecc_size_config);
1114 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1116 /* BCH configuration */
1117 val = ((1 << 16) | /* enable BCH */
1118 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
1119 (wr_mode << 8) | /* wrap mode */
1120 (dev_width << 7) | /* bus width */
1121 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1122 (info->gpmc_cs << 1) | /* ECC CS */
1123 (0x1)); /* enable ECC */
1125 writel(val, info->reg.gpmc_ecc_config);
1127 /* Clear ecc and enable bits */
1128 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1131 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1132 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1133 0x97, 0x79, 0xe5, 0x24, 0xb5};
1136 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1137 * @mtd: MTD device structure
1138 * @dat: The pointer to data on which ecc is computed
1139 * @ecc_calc: The ecc_code buffer
1140 * @i: The sector number (for a multi sector page)
1142 * Support calculating of BCH4/8/16 ECC vectors for one sector
1143 * within a page. Sector number is in @i.
1145 static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
1146 const u_char *dat, u_char *ecc_calc, int i)
1148 struct omap_nand_info *info = mtd_to_omap(mtd);
1149 int eccbytes = info->nand.ecc.bytes;
1150 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1152 unsigned long bch_val1, bch_val2, bch_val3, bch_val4;
1156 ecc_code = ecc_calc;
1157 switch (info->ecc_opt) {
1158 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1159 case OMAP_ECC_BCH8_CODE_HW:
1160 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1161 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1162 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1163 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1164 *ecc_code++ = (bch_val4 & 0xFF);
1165 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1166 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1167 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1168 *ecc_code++ = (bch_val3 & 0xFF);
1169 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1170 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1171 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1172 *ecc_code++ = (bch_val2 & 0xFF);
1173 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1174 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1175 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1176 *ecc_code++ = (bch_val1 & 0xFF);
1178 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1179 case OMAP_ECC_BCH4_CODE_HW:
1180 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1181 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1182 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1183 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1184 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1185 ((bch_val1 >> 28) & 0xF);
1186 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1187 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1188 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1189 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1191 case OMAP_ECC_BCH16_CODE_HW:
1192 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1193 ecc_code[0] = ((val >> 8) & 0xFF);
1194 ecc_code[1] = ((val >> 0) & 0xFF);
1195 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1196 ecc_code[2] = ((val >> 24) & 0xFF);
1197 ecc_code[3] = ((val >> 16) & 0xFF);
1198 ecc_code[4] = ((val >> 8) & 0xFF);
1199 ecc_code[5] = ((val >> 0) & 0xFF);
1200 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1201 ecc_code[6] = ((val >> 24) & 0xFF);
1202 ecc_code[7] = ((val >> 16) & 0xFF);
1203 ecc_code[8] = ((val >> 8) & 0xFF);
1204 ecc_code[9] = ((val >> 0) & 0xFF);
1205 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1206 ecc_code[10] = ((val >> 24) & 0xFF);
1207 ecc_code[11] = ((val >> 16) & 0xFF);
1208 ecc_code[12] = ((val >> 8) & 0xFF);
1209 ecc_code[13] = ((val >> 0) & 0xFF);
1210 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1211 ecc_code[14] = ((val >> 24) & 0xFF);
1212 ecc_code[15] = ((val >> 16) & 0xFF);
1213 ecc_code[16] = ((val >> 8) & 0xFF);
1214 ecc_code[17] = ((val >> 0) & 0xFF);
1215 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1216 ecc_code[18] = ((val >> 24) & 0xFF);
1217 ecc_code[19] = ((val >> 16) & 0xFF);
1218 ecc_code[20] = ((val >> 8) & 0xFF);
1219 ecc_code[21] = ((val >> 0) & 0xFF);
1220 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1221 ecc_code[22] = ((val >> 24) & 0xFF);
1222 ecc_code[23] = ((val >> 16) & 0xFF);
1223 ecc_code[24] = ((val >> 8) & 0xFF);
1224 ecc_code[25] = ((val >> 0) & 0xFF);
1230 /* ECC scheme specific syndrome customizations */
1231 switch (info->ecc_opt) {
1232 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1233 /* Add constant polynomial to remainder, so that
1234 * ECC of blank pages results in 0x0 on reading back
1236 for (j = 0; j < eccbytes; j++)
1237 ecc_calc[j] ^= bch4_polynomial[j];
1239 case OMAP_ECC_BCH4_CODE_HW:
1240 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1241 ecc_calc[eccbytes - 1] = 0x0;
1243 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1244 /* Add constant polynomial to remainder, so that
1245 * ECC of blank pages results in 0x0 on reading back
1247 for (j = 0; j < eccbytes; j++)
1248 ecc_calc[j] ^= bch8_polynomial[j];
1250 case OMAP_ECC_BCH8_CODE_HW:
1251 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1252 ecc_calc[eccbytes - 1] = 0x0;
1254 case OMAP_ECC_BCH16_CODE_HW:
1264 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1265 * @chip: NAND chip object
1266 * @dat: The pointer to data on which ecc is computed
1267 * @ecc_calc: Buffer storing the calculated ECC bytes
1269 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1270 * when SW based correction is required as ECC is required for one sector
1273 static int omap_calculate_ecc_bch_sw(struct nand_chip *chip,
1274 const u_char *dat, u_char *ecc_calc)
1276 return _omap_calculate_ecc_bch(nand_to_mtd(chip), dat, ecc_calc, 0);
1280 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1281 * @mtd: MTD device structure
1282 * @dat: The pointer to data on which ecc is computed
1283 * @ecc_calc: Buffer storing the calculated ECC bytes
1285 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1287 static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
1288 const u_char *dat, u_char *ecc_calc)
1290 struct omap_nand_info *info = mtd_to_omap(mtd);
1291 int eccbytes = info->nand.ecc.bytes;
1292 unsigned long nsectors;
1295 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1296 for (i = 0; i < nsectors; i++) {
1297 ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
1301 ecc_calc += eccbytes;
1308 * erased_sector_bitflips - count bit flips
1309 * @data: data sector buffer
1311 * @info: omap_nand_info
1313 * Check the bit flips in erased page falls below correctable level.
1314 * If falls below, report the page as erased with correctable bit
1315 * flip, else report as uncorrectable page.
1317 static int erased_sector_bitflips(u_char *data, u_char *oob,
1318 struct omap_nand_info *info)
1320 int flip_bits = 0, i;
1322 for (i = 0; i < info->nand.ecc.size; i++) {
1323 flip_bits += hweight8(~data[i]);
1324 if (flip_bits > info->nand.ecc.strength)
1328 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1329 flip_bits += hweight8(~oob[i]);
1330 if (flip_bits > info->nand.ecc.strength)
1335 * Bit flips falls in correctable level.
1336 * Fill data area with 0xFF
1339 memset(data, 0xFF, info->nand.ecc.size);
1340 memset(oob, 0xFF, info->nand.ecc.bytes);
1347 * omap_elm_correct_data - corrects page data area in case error reported
1348 * @chip: NAND chip object
1350 * @read_ecc: ecc read from nand flash
1351 * @calc_ecc: ecc read from HW ECC registers
1353 * Calculated ecc vector reported as zero in case of non-error pages.
1354 * In case of non-zero ecc vector, first filter out erased-pages, and
1355 * then process data via ELM to detect bit-flips.
1357 static int omap_elm_correct_data(struct nand_chip *chip, u_char *data,
1358 u_char *read_ecc, u_char *calc_ecc)
1360 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1361 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1362 int eccsteps = info->nsteps_per_eccpg;
1363 int i , j, stat = 0;
1364 int eccflag, actual_eccbytes;
1365 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1366 u_char *ecc_vec = calc_ecc;
1367 u_char *spare_ecc = read_ecc;
1368 u_char *erased_ecc_vec;
1371 bool is_error_reported = false;
1372 u32 bit_pos, byte_pos, error_max, pos;
1375 switch (info->ecc_opt) {
1376 case OMAP_ECC_BCH4_CODE_HW:
1377 /* omit 7th ECC byte reserved for ROM code compatibility */
1378 actual_eccbytes = ecc->bytes - 1;
1379 erased_ecc_vec = bch4_vector;
1381 case OMAP_ECC_BCH8_CODE_HW:
1382 /* omit 14th ECC byte reserved for ROM code compatibility */
1383 actual_eccbytes = ecc->bytes - 1;
1384 erased_ecc_vec = bch8_vector;
1386 case OMAP_ECC_BCH16_CODE_HW:
1387 actual_eccbytes = ecc->bytes;
1388 erased_ecc_vec = bch16_vector;
1391 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1395 /* Initialize elm error vector to zero */
1396 memset(err_vec, 0, sizeof(err_vec));
1398 for (i = 0; i < eccsteps ; i++) {
1399 eccflag = 0; /* initialize eccflag */
1402 * Check any error reported,
1403 * In case of error, non zero ecc reported.
1405 for (j = 0; j < actual_eccbytes; j++) {
1406 if (calc_ecc[j] != 0) {
1407 eccflag = 1; /* non zero ecc, error present */
1413 if (memcmp(calc_ecc, erased_ecc_vec,
1414 actual_eccbytes) == 0) {
1416 * calc_ecc[] matches pattern for ECC(all 0xff)
1417 * so this is definitely an erased-page
1420 buf = &data[info->nand.ecc.size * i];
1422 * count number of 0-bits in read_buf.
1423 * This check can be removed once a similar
1424 * check is introduced in generic NAND driver
1426 bitflip_count = erased_sector_bitflips(
1427 buf, read_ecc, info);
1428 if (bitflip_count) {
1430 * number of 0-bits within ECC limits
1431 * So this may be an erased-page
1433 stat += bitflip_count;
1436 * Too many 0-bits. It may be a
1437 * - programmed-page, OR
1438 * - erased-page with many bit-flips
1439 * So this page requires check by ELM
1441 err_vec[i].error_reported = true;
1442 is_error_reported = true;
1447 /* Update the ecc vector */
1448 calc_ecc += ecc->bytes;
1449 read_ecc += ecc->bytes;
1452 /* Check if any error reported */
1453 if (!is_error_reported)
1456 /* Decode BCH error using ELM module */
1457 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1460 for (i = 0; i < eccsteps; i++) {
1461 if (err_vec[i].error_uncorrectable) {
1462 dev_err(&info->pdev->dev,
1463 "uncorrectable bit-flips found\n");
1465 } else if (err_vec[i].error_reported) {
1466 for (j = 0; j < err_vec[i].error_count; j++) {
1467 switch (info->ecc_opt) {
1468 case OMAP_ECC_BCH4_CODE_HW:
1469 /* Add 4 bits to take care of padding */
1470 pos = err_vec[i].error_loc[j] +
1473 case OMAP_ECC_BCH8_CODE_HW:
1474 case OMAP_ECC_BCH16_CODE_HW:
1475 pos = err_vec[i].error_loc[j];
1480 error_max = (ecc->size + actual_eccbytes) * 8;
1481 /* Calculate bit position of error */
1484 /* Calculate byte position of error */
1485 byte_pos = (error_max - pos - 1) / 8;
1487 if (pos < error_max) {
1488 if (byte_pos < 512) {
1489 pr_debug("bitflip@dat[%d]=%x\n",
1490 byte_pos, data[byte_pos]);
1491 data[byte_pos] ^= 1 << bit_pos;
1493 pr_debug("bitflip@oob[%d]=%x\n",
1495 spare_ecc[byte_pos - 512]);
1496 spare_ecc[byte_pos - 512] ^=
1500 dev_err(&info->pdev->dev,
1501 "invalid bit-flip @ %d:%d\n",
1508 /* Update number of correctable errors */
1509 stat = max_t(unsigned int, stat, err_vec[i].error_count);
1511 /* Update page data with sector size */
1513 spare_ecc += ecc->bytes;
1516 return (err) ? err : stat;
1520 * omap_write_page_bch - BCH ecc based write page function for entire page
1521 * @chip: nand chip info structure
1523 * @oob_required: must write chip->oob_poi to OOB
1526 * Custom write page method evolved to support multi sector writing in one shot
1528 static int omap_write_page_bch(struct nand_chip *chip, const uint8_t *buf,
1529 int oob_required, int page)
1531 struct mtd_info *mtd = nand_to_mtd(chip);
1532 struct omap_nand_info *info = mtd_to_omap(mtd);
1533 uint8_t *ecc_calc = chip->ecc.calc_buf;
1537 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1541 for (eccpg = 0; eccpg < info->neccpg; eccpg++) {
1542 /* Enable GPMC ecc engine */
1543 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1546 chip->legacy.write_buf(chip, buf + (eccpg * info->eccpg_size),
1549 /* Update ecc vector from GPMC result registers */
1550 ret = omap_calculate_ecc_bch_multi(mtd,
1551 buf + (eccpg * info->eccpg_size),
1556 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc,
1558 eccpg * info->eccpg_bytes,
1564 /* Write ecc vector to OOB area */
1565 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1567 return nand_prog_page_end_op(chip);
1571 * omap_write_subpage_bch - BCH hardware ECC based subpage write
1572 * @chip: nand chip info structure
1573 * @offset: column address of subpage within the page
1574 * @data_len: data length
1576 * @oob_required: must write chip->oob_poi to OOB
1577 * @page: page number to write
1579 * OMAP optimized subpage write method.
1581 static int omap_write_subpage_bch(struct nand_chip *chip, u32 offset,
1582 u32 data_len, const u8 *buf,
1583 int oob_required, int page)
1585 struct mtd_info *mtd = nand_to_mtd(chip);
1586 struct omap_nand_info *info = mtd_to_omap(mtd);
1587 u8 *ecc_calc = chip->ecc.calc_buf;
1588 int ecc_size = chip->ecc.size;
1589 int ecc_bytes = chip->ecc.bytes;
1590 u32 start_step = offset / ecc_size;
1591 u32 end_step = (offset + data_len - 1) / ecc_size;
1596 * Write entire page at one go as it would be optimal
1597 * as ECC is calculated by hardware.
1598 * ECC is calculated for all subpages but we choose
1599 * only what we want.
1601 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1605 for (eccpg = 0; eccpg < info->neccpg; eccpg++) {
1606 /* Enable GPMC ECC engine */
1607 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1610 chip->legacy.write_buf(chip, buf + (eccpg * info->eccpg_size),
1613 for (step = 0; step < info->nsteps_per_eccpg; step++) {
1614 unsigned int base_step = eccpg * info->nsteps_per_eccpg;
1615 const u8 *bufoffs = buf + (eccpg * info->eccpg_size);
1617 /* Mask ECC of un-touched subpages with 0xFFs */
1618 if ((step + base_step) < start_step ||
1619 (step + base_step) > end_step)
1620 memset(ecc_calc + (step * ecc_bytes), 0xff,
1623 ret = _omap_calculate_ecc_bch(mtd,
1624 bufoffs + (step * ecc_size),
1625 ecc_calc + (step * ecc_bytes),
1633 * Copy the calculated ECC for the whole page including the
1634 * masked values (0xFF) corresponding to unwritten subpages.
1636 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi,
1637 eccpg * info->eccpg_bytes,
1643 /* write OOB buffer to NAND device */
1644 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1646 return nand_prog_page_end_op(chip);
1650 * omap_read_page_bch - BCH ecc based page read function for entire page
1651 * @chip: nand chip info structure
1652 * @buf: buffer to store read data
1653 * @oob_required: caller requires OOB data read to chip->oob_poi
1654 * @page: page number to read
1656 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1657 * used for error correction.
1658 * Custom method evolved to support ELM error correction & multi sector
1659 * reading. On reading page data area is read along with OOB data with
1660 * ecc engine enabled. ecc vector updated after read of OOB data.
1661 * For non error pages ecc vector reported as zero.
1663 static int omap_read_page_bch(struct nand_chip *chip, uint8_t *buf,
1664 int oob_required, int page)
1666 struct mtd_info *mtd = nand_to_mtd(chip);
1667 struct omap_nand_info *info = mtd_to_omap(mtd);
1668 uint8_t *ecc_calc = chip->ecc.calc_buf;
1669 uint8_t *ecc_code = chip->ecc.code_buf;
1670 unsigned int max_bitflips = 0, eccpg;
1673 ret = nand_read_page_op(chip, page, 0, NULL, 0);
1677 for (eccpg = 0; eccpg < info->neccpg; eccpg++) {
1678 /* Enable GPMC ecc engine */
1679 chip->ecc.hwctl(chip, NAND_ECC_READ);
1682 ret = nand_change_read_column_op(chip, eccpg * info->eccpg_size,
1683 buf + (eccpg * info->eccpg_size),
1684 info->eccpg_size, false);
1688 /* Read oob bytes */
1689 ret = nand_change_read_column_op(chip,
1690 mtd->writesize + BBM_LEN +
1691 (eccpg * info->eccpg_bytes),
1692 chip->oob_poi + BBM_LEN +
1693 (eccpg * info->eccpg_bytes),
1694 info->eccpg_bytes, false);
1698 /* Calculate ecc bytes */
1699 ret = omap_calculate_ecc_bch_multi(mtd,
1700 buf + (eccpg * info->eccpg_size),
1705 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code,
1707 eccpg * info->eccpg_bytes,
1712 stat = chip->ecc.correct(chip,
1713 buf + (eccpg * info->eccpg_size),
1714 ecc_code, ecc_calc);
1716 mtd->ecc_stats.failed++;
1718 mtd->ecc_stats.corrected += stat;
1719 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1723 return max_bitflips;
1727 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1728 * @info: NAND device structure containing platform data
1729 * @elm_node: ELM's DT node
1731 static bool is_elm_present(struct omap_nand_info *info,
1732 struct device_node *elm_node)
1734 struct platform_device *pdev;
1736 /* check whether elm-id is passed via DT */
1738 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1741 pdev = of_find_device_by_node(elm_node);
1742 /* check whether ELM device is registered */
1744 dev_err(&info->pdev->dev, "ELM device not found\n");
1747 /* ELM module available, now configure it */
1748 info->elm_dev = &pdev->dev;
1752 static bool omap2_nand_ecc_check(struct omap_nand_info *info)
1754 bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1756 switch (info->ecc_opt) {
1757 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1758 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1759 ecc_needs_omap_bch = false;
1760 ecc_needs_bch = true;
1761 ecc_needs_elm = false;
1763 case OMAP_ECC_BCH4_CODE_HW:
1764 case OMAP_ECC_BCH8_CODE_HW:
1765 case OMAP_ECC_BCH16_CODE_HW:
1766 ecc_needs_omap_bch = true;
1767 ecc_needs_bch = false;
1768 ecc_needs_elm = true;
1771 ecc_needs_omap_bch = false;
1772 ecc_needs_bch = false;
1773 ecc_needs_elm = false;
1777 if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
1778 dev_err(&info->pdev->dev,
1779 "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
1782 if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1783 dev_err(&info->pdev->dev,
1784 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1787 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1788 dev_err(&info->pdev->dev, "ELM not available\n");
1795 static const char * const nand_xfer_types[] = {
1796 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1797 [NAND_OMAP_POLLED] = "polled",
1798 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1799 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1802 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1804 struct device_node *child = dev->of_node;
1809 if (of_property_read_u32(child, "reg", &cs) < 0) {
1810 dev_err(dev, "reg not found in DT\n");
1816 /* detect availability of ELM module. Won't be present pre-OMAP4 */
1817 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1818 if (!info->elm_of_node) {
1819 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1820 if (!info->elm_of_node)
1821 dev_dbg(dev, "ti,elm-id not in DT\n");
1824 /* select ecc-scheme for NAND */
1825 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1826 dev_err(dev, "ti,nand-ecc-opt not found\n");
1830 if (!strcmp(s, "sw")) {
1831 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1832 } else if (!strcmp(s, "ham1") ||
1833 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1834 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1835 } else if (!strcmp(s, "bch4")) {
1836 if (info->elm_of_node)
1837 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1839 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1840 } else if (!strcmp(s, "bch8")) {
1841 if (info->elm_of_node)
1842 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1844 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1845 } else if (!strcmp(s, "bch16")) {
1846 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1848 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1852 /* select data transfer mode */
1853 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1854 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1855 if (!strcasecmp(s, nand_xfer_types[i])) {
1856 info->xfer_type = i;
1861 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1868 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section,
1869 struct mtd_oob_region *oobregion)
1871 struct omap_nand_info *info = mtd_to_omap(mtd);
1872 struct nand_chip *chip = &info->nand;
1875 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1876 !(chip->options & NAND_BUSWIDTH_16))
1882 oobregion->offset = off;
1883 oobregion->length = chip->ecc.total;
1888 static int omap_ooblayout_free(struct mtd_info *mtd, int section,
1889 struct mtd_oob_region *oobregion)
1891 struct omap_nand_info *info = mtd_to_omap(mtd);
1892 struct nand_chip *chip = &info->nand;
1895 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1896 !(chip->options & NAND_BUSWIDTH_16))
1902 off += chip->ecc.total;
1903 if (off >= mtd->oobsize)
1906 oobregion->offset = off;
1907 oobregion->length = mtd->oobsize - off;
1912 static const struct mtd_ooblayout_ops omap_ooblayout_ops = {
1913 .ecc = omap_ooblayout_ecc,
1914 .free = omap_ooblayout_free,
1917 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section,
1918 struct mtd_oob_region *oobregion)
1920 struct nand_device *nand = mtd_to_nanddev(mtd);
1921 unsigned int nsteps = nanddev_get_ecc_nsteps(nand);
1922 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand);
1925 if (section >= nsteps)
1929 * When SW correction is employed, one OMAP specific marker byte is
1930 * reserved after each ECC step.
1932 oobregion->offset = off + (section * (ecc_bytes + 1));
1933 oobregion->length = ecc_bytes;
1938 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section,
1939 struct mtd_oob_region *oobregion)
1941 struct nand_device *nand = mtd_to_nanddev(mtd);
1942 unsigned int nsteps = nanddev_get_ecc_nsteps(nand);
1943 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand);
1950 * When SW correction is employed, one OMAP specific marker byte is
1951 * reserved after each ECC step.
1953 off += ((ecc_bytes + 1) * nsteps);
1954 if (off >= mtd->oobsize)
1957 oobregion->offset = off;
1958 oobregion->length = mtd->oobsize - off;
1963 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
1964 .ecc = omap_sw_ooblayout_ecc,
1965 .free = omap_sw_ooblayout_free,
1968 static int omap_nand_attach_chip(struct nand_chip *chip)
1970 struct mtd_info *mtd = nand_to_mtd(chip);
1971 struct omap_nand_info *info = mtd_to_omap(mtd);
1972 struct device *dev = &info->pdev->dev;
1973 int min_oobbytes = BBM_LEN;
1974 int elm_bch_strength = -1;
1975 int oobbytes_per_step;
1976 dma_cap_mask_t mask;
1979 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1980 chip->bbt_options |= NAND_BBT_NO_OOB;
1982 chip->options |= NAND_SKIP_BBTSCAN;
1984 /* Re-populate low-level callbacks based on xfer modes */
1985 switch (info->xfer_type) {
1986 case NAND_OMAP_PREFETCH_POLLED:
1987 chip->legacy.read_buf = omap_read_buf_pref;
1988 chip->legacy.write_buf = omap_write_buf_pref;
1991 case NAND_OMAP_POLLED:
1992 /* Use nand_base defaults for {read,write}_buf */
1995 case NAND_OMAP_PREFETCH_DMA:
1997 dma_cap_set(DMA_SLAVE, mask);
1998 info->dma = dma_request_chan(dev->parent, "rxtx");
2000 if (IS_ERR(info->dma)) {
2001 dev_err(dev, "DMA engine request failed\n");
2002 return PTR_ERR(info->dma);
2004 struct dma_slave_config cfg;
2006 memset(&cfg, 0, sizeof(cfg));
2007 cfg.src_addr = info->phys_base;
2008 cfg.dst_addr = info->phys_base;
2009 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2010 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2011 cfg.src_maxburst = 16;
2012 cfg.dst_maxburst = 16;
2013 err = dmaengine_slave_config(info->dma, &cfg);
2016 "DMA engine slave config failed: %d\n",
2020 chip->legacy.read_buf = omap_read_buf_dma_pref;
2021 chip->legacy.write_buf = omap_write_buf_dma_pref;
2025 case NAND_OMAP_PREFETCH_IRQ:
2026 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);
2027 if (info->gpmc_irq_fifo <= 0)
2029 err = devm_request_irq(dev, info->gpmc_irq_fifo,
2030 omap_nand_irq, IRQF_SHARED,
2031 "gpmc-nand-fifo", info);
2033 dev_err(dev, "Requesting IRQ %d, error %d\n",
2034 info->gpmc_irq_fifo, err);
2035 info->gpmc_irq_fifo = 0;
2039 info->gpmc_irq_count = platform_get_irq(info->pdev, 1);
2040 if (info->gpmc_irq_count <= 0)
2042 err = devm_request_irq(dev, info->gpmc_irq_count,
2043 omap_nand_irq, IRQF_SHARED,
2044 "gpmc-nand-count", info);
2046 dev_err(dev, "Requesting IRQ %d, error %d\n",
2047 info->gpmc_irq_count, err);
2048 info->gpmc_irq_count = 0;
2052 chip->legacy.read_buf = omap_read_buf_irq_pref;
2053 chip->legacy.write_buf = omap_write_buf_irq_pref;
2058 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type);
2062 if (!omap2_nand_ecc_check(info))
2066 * Bail out earlier to let NAND_ECC_ENGINE_TYPE_SOFT code create its own
2067 * ooblayout instead of using ours.
2069 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2070 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
2071 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2075 /* Populate MTD interface based on ECC scheme */
2076 switch (info->ecc_opt) {
2077 case OMAP_ECC_HAM1_CODE_HW:
2078 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
2079 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2080 chip->ecc.bytes = 3;
2081 chip->ecc.size = 512;
2082 chip->ecc.strength = 1;
2083 chip->ecc.calculate = omap_calculate_ecc;
2084 chip->ecc.hwctl = omap_enable_hwecc;
2085 chip->ecc.correct = omap_correct_data;
2086 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2087 oobbytes_per_step = chip->ecc.bytes;
2089 if (!(chip->options & NAND_BUSWIDTH_16))
2094 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
2095 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2096 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2097 chip->ecc.size = 512;
2098 chip->ecc.bytes = 7;
2099 chip->ecc.strength = 4;
2100 chip->ecc.hwctl = omap_enable_hwecc_bch;
2101 chip->ecc.correct = rawnand_sw_bch_correct;
2102 chip->ecc.calculate = omap_calculate_ecc_bch_sw;
2103 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2104 /* Reserve one byte for the OMAP marker */
2105 oobbytes_per_step = chip->ecc.bytes + 1;
2106 /* Software BCH library is used for locating errors */
2107 err = rawnand_sw_bch_init(chip);
2109 dev_err(dev, "Unable to use BCH library\n");
2114 case OMAP_ECC_BCH4_CODE_HW:
2115 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2116 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2117 chip->ecc.size = 512;
2118 /* 14th bit is kept reserved for ROM-code compatibility */
2119 chip->ecc.bytes = 7 + 1;
2120 chip->ecc.strength = 4;
2121 chip->ecc.hwctl = omap_enable_hwecc_bch;
2122 chip->ecc.correct = omap_elm_correct_data;
2123 chip->ecc.read_page = omap_read_page_bch;
2124 chip->ecc.write_page = omap_write_page_bch;
2125 chip->ecc.write_subpage = omap_write_subpage_bch;
2126 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2127 oobbytes_per_step = chip->ecc.bytes;
2128 elm_bch_strength = BCH4_ECC;
2131 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2132 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2133 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2134 chip->ecc.size = 512;
2135 chip->ecc.bytes = 13;
2136 chip->ecc.strength = 8;
2137 chip->ecc.hwctl = omap_enable_hwecc_bch;
2138 chip->ecc.correct = rawnand_sw_bch_correct;
2139 chip->ecc.calculate = omap_calculate_ecc_bch_sw;
2140 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2141 /* Reserve one byte for the OMAP marker */
2142 oobbytes_per_step = chip->ecc.bytes + 1;
2143 /* Software BCH library is used for locating errors */
2144 err = rawnand_sw_bch_init(chip);
2146 dev_err(dev, "unable to use BCH library\n");
2151 case OMAP_ECC_BCH8_CODE_HW:
2152 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2153 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2154 chip->ecc.size = 512;
2155 /* 14th bit is kept reserved for ROM-code compatibility */
2156 chip->ecc.bytes = 13 + 1;
2157 chip->ecc.strength = 8;
2158 chip->ecc.hwctl = omap_enable_hwecc_bch;
2159 chip->ecc.correct = omap_elm_correct_data;
2160 chip->ecc.read_page = omap_read_page_bch;
2161 chip->ecc.write_page = omap_write_page_bch;
2162 chip->ecc.write_subpage = omap_write_subpage_bch;
2163 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2164 oobbytes_per_step = chip->ecc.bytes;
2165 elm_bch_strength = BCH8_ECC;
2168 case OMAP_ECC_BCH16_CODE_HW:
2169 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2170 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2171 chip->ecc.size = 512;
2172 chip->ecc.bytes = 26;
2173 chip->ecc.strength = 16;
2174 chip->ecc.hwctl = omap_enable_hwecc_bch;
2175 chip->ecc.correct = omap_elm_correct_data;
2176 chip->ecc.read_page = omap_read_page_bch;
2177 chip->ecc.write_page = omap_write_page_bch;
2178 chip->ecc.write_subpage = omap_write_subpage_bch;
2179 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2180 oobbytes_per_step = chip->ecc.bytes;
2181 elm_bch_strength = BCH16_ECC;
2184 dev_err(dev, "Invalid or unsupported ECC scheme\n");
2188 if (elm_bch_strength >= 0) {
2189 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2190 info->neccpg = chip->ecc.steps / ERROR_VECTOR_MAX;
2192 info->nsteps_per_eccpg = ERROR_VECTOR_MAX;
2195 info->nsteps_per_eccpg = chip->ecc.steps;
2197 info->eccpg_size = info->nsteps_per_eccpg * chip->ecc.size;
2198 info->eccpg_bytes = info->nsteps_per_eccpg * chip->ecc.bytes;
2200 err = elm_config(info->elm_dev, elm_bch_strength,
2201 info->nsteps_per_eccpg, chip->ecc.size,
2207 /* Check if NAND device's OOB is enough to store ECC signatures */
2208 min_oobbytes += (oobbytes_per_step *
2209 (mtd->writesize / chip->ecc.size));
2210 if (mtd->oobsize < min_oobbytes) {
2212 "Not enough OOB bytes: required = %d, available=%d\n",
2213 min_oobbytes, mtd->oobsize);
2220 static const struct nand_controller_ops omap_nand_controller_ops = {
2221 .attach_chip = omap_nand_attach_chip,
2224 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2225 static struct nand_controller omap_gpmc_controller;
2226 static bool omap_gpmc_controller_initialized;
2228 static int omap_nand_probe(struct platform_device *pdev)
2230 struct omap_nand_info *info;
2231 struct mtd_info *mtd;
2232 struct nand_chip *nand_chip;
2234 struct resource *res;
2235 struct device *dev = &pdev->dev;
2237 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
2244 err = omap_get_dt_info(dev, info);
2248 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
2250 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
2254 nand_chip = &info->nand;
2255 mtd = nand_to_mtd(nand_chip);
2256 mtd->dev.parent = &pdev->dev;
2257 nand_set_flash_node(nand_chip, dev->of_node);
2260 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
2261 "omap2-nand.%d", info->gpmc_cs);
2263 dev_err(&pdev->dev, "Failed to set MTD name\n");
2268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2269 nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
2270 if (IS_ERR(nand_chip->legacy.IO_ADDR_R))
2271 return PTR_ERR(nand_chip->legacy.IO_ADDR_R);
2273 info->phys_base = res->start;
2275 if (!omap_gpmc_controller_initialized) {
2276 omap_gpmc_controller.ops = &omap_nand_controller_ops;
2277 nand_controller_init(&omap_gpmc_controller);
2278 omap_gpmc_controller_initialized = true;
2281 nand_chip->controller = &omap_gpmc_controller;
2283 nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
2284 nand_chip->legacy.cmd_ctrl = omap_hwcontrol;
2286 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
2288 if (IS_ERR(info->ready_gpiod)) {
2289 dev_err(dev, "failed to get ready gpio\n");
2290 return PTR_ERR(info->ready_gpiod);
2294 * If RDY/BSY line is connected to OMAP then use the omap ready
2295 * function and the generic nand_wait function which reads the status
2296 * register after monitoring the RDY/BSY line. Otherwise use a standard
2297 * chip delay which is slightly more than tR (AC Timing) of the NAND
2298 * device and read status register until you get a failure or success
2300 if (info->ready_gpiod) {
2301 nand_chip->legacy.dev_ready = omap_dev_ready;
2302 nand_chip->legacy.chip_delay = 0;
2304 nand_chip->legacy.waitfunc = omap_wait;
2305 nand_chip->legacy.chip_delay = 50;
2308 if (info->flash_bbt)
2309 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2311 /* scan NAND device connected to chip controller */
2312 nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
2314 err = nand_scan(nand_chip, 1);
2318 err = mtd_device_register(mtd, NULL, 0);
2322 platform_set_drvdata(pdev, mtd);
2327 nand_cleanup(nand_chip);
2330 if (!IS_ERR_OR_NULL(info->dma))
2331 dma_release_channel(info->dma);
2333 rawnand_sw_bch_cleanup(nand_chip);
2338 static int omap_nand_remove(struct platform_device *pdev)
2340 struct mtd_info *mtd = platform_get_drvdata(pdev);
2341 struct nand_chip *nand_chip = mtd_to_nand(mtd);
2342 struct omap_nand_info *info = mtd_to_omap(mtd);
2345 rawnand_sw_bch_cleanup(nand_chip);
2348 dma_release_channel(info->dma);
2349 ret = mtd_device_unregister(mtd);
2351 nand_cleanup(nand_chip);
2355 static const struct of_device_id omap_nand_ids[] = {
2356 { .compatible = "ti,omap2-nand", },
2359 MODULE_DEVICE_TABLE(of, omap_nand_ids);
2361 static struct platform_driver omap_nand_driver = {
2362 .probe = omap_nand_probe,
2363 .remove = omap_nand_remove,
2365 .name = DRIVER_NAME,
2366 .of_match_table = of_match_ptr(omap_nand_ids),
2370 module_platform_driver(omap_nand_driver);
2372 MODULE_ALIAS("platform:" DRIVER_NAME);
2373 MODULE_LICENSE("GPL");
2374 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");