1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
4 * Copyright © 2004 Micron Technology Inc.
5 * Copyright © 2004 David Brownell
8 #include <linux/platform_device.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/sched.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
19 #include <linux/mtd/rawnand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/omap-dma.h>
23 #include <linux/slab.h>
25 #include <linux/of_device.h>
27 #include <linux/platform_data/elm.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
33 #define OMAP_NAND_TIMEOUT_MS 5000
35 #define NAND_Ecc_P1e (1 << 0)
36 #define NAND_Ecc_P2e (1 << 1)
37 #define NAND_Ecc_P4e (1 << 2)
38 #define NAND_Ecc_P8e (1 << 3)
39 #define NAND_Ecc_P16e (1 << 4)
40 #define NAND_Ecc_P32e (1 << 5)
41 #define NAND_Ecc_P64e (1 << 6)
42 #define NAND_Ecc_P128e (1 << 7)
43 #define NAND_Ecc_P256e (1 << 8)
44 #define NAND_Ecc_P512e (1 << 9)
45 #define NAND_Ecc_P1024e (1 << 10)
46 #define NAND_Ecc_P2048e (1 << 11)
48 #define NAND_Ecc_P1o (1 << 16)
49 #define NAND_Ecc_P2o (1 << 17)
50 #define NAND_Ecc_P4o (1 << 18)
51 #define NAND_Ecc_P8o (1 << 19)
52 #define NAND_Ecc_P16o (1 << 20)
53 #define NAND_Ecc_P32o (1 << 21)
54 #define NAND_Ecc_P64o (1 << 22)
55 #define NAND_Ecc_P128o (1 << 23)
56 #define NAND_Ecc_P256o (1 << 24)
57 #define NAND_Ecc_P512o (1 << 25)
58 #define NAND_Ecc_P1024o (1 << 26)
59 #define NAND_Ecc_P2048o (1 << 27)
61 #define TF(value) (value ? 1 : 0)
63 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
64 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
65 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
66 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
67 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
68 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
69 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
70 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
73 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
74 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
75 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
76 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
77 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
78 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
79 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
82 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
83 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
84 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
85 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
86 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
87 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
88 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
91 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
92 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
93 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
94 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
95 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
96 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
97 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
100 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102 #define PREFETCH_CONFIG1_CS_SHIFT 24
103 #define ECC_CONFIG_CS_SHIFT 1
105 #define ENABLE_PREFETCH (0x1 << 7)
106 #define DMA_MPU_MODE_SHIFT 2
107 #define ECCSIZE0_SHIFT 12
108 #define ECCSIZE1_SHIFT 22
109 #define ECC1RESULTSIZE 0x1
110 #define ECCCLEAR 0x100
112 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
113 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
114 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
115 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
116 #define STATUS_BUFF_EMPTY 0x00000001
118 #define SECTOR_BYTES 512
119 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
120 #define BCH4_BIT_PAD 4
122 /* GPMC ecc engine settings for read */
123 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
124 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
125 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
126 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
127 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
129 /* GPMC ecc engine settings for write */
130 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
132 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
134 #define BADBLOCK_MARKER_LENGTH 2
136 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
137 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
138 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
140 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
141 0xac, 0x6b, 0xff, 0x99, 0x7b};
142 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
144 struct omap_nand_info {
145 struct nand_chip nand;
146 struct platform_device *pdev;
150 enum nand_io xfer_type;
152 enum omap_ecc ecc_opt;
153 struct device_node *elm_of_node;
155 unsigned long phys_base;
156 struct completion comp;
157 struct dma_chan *dma;
161 OMAP_NAND_IO_READ = 0, /* read */
162 OMAP_NAND_IO_WRITE, /* write */
166 /* Interface to GPMC */
167 struct gpmc_nand_regs reg;
168 struct gpmc_nand_ops *ops;
170 /* fields specific for BCHx_HW ECC scheme */
171 struct device *elm_dev;
172 /* NAND ready gpio */
173 struct gpio_desc *ready_gpiod;
176 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
178 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
182 * omap_prefetch_enable - configures and starts prefetch transfer
183 * @cs: cs (chip select) number
184 * @fifo_th: fifo threshold to be used for read/ write
185 * @dma_mode: dma mode enable (1) or disable (0)
186 * @u32_count: number of bytes to be transferred
187 * @is_write: prefetch read(0) or write post(1) mode
188 * @info: NAND device structure containing platform data
190 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
191 unsigned int u32_count, int is_write, struct omap_nand_info *info)
195 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
198 if (readl(info->reg.gpmc_prefetch_control))
201 /* Set the amount of bytes to be prefetched */
202 writel(u32_count, info->reg.gpmc_prefetch_config2);
204 /* Set dma/mpu mode, the prefetch read / post write and
205 * enable the engine. Set which cs is has requested for.
207 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
208 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
209 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1));
210 writel(val, info->reg.gpmc_prefetch_config1);
212 /* Start the prefetch engine */
213 writel(0x1, info->reg.gpmc_prefetch_control);
219 * omap_prefetch_reset - disables and stops the prefetch engine
221 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
225 /* check if the same module/cs is trying to reset */
226 config1 = readl(info->reg.gpmc_prefetch_config1);
227 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
230 /* Stop the PFPW engine */
231 writel(0x0, info->reg.gpmc_prefetch_control);
233 /* Reset/disable the PFPW engine */
234 writel(0x0, info->reg.gpmc_prefetch_config1);
240 * omap_hwcontrol - hardware specific access to control-lines
241 * @chip: NAND chip object
242 * @cmd: command to device
244 * NAND_NCE: bit 0 -> don't care
245 * NAND_CLE: bit 1 -> Command Latch
246 * NAND_ALE: bit 2 -> Address Latch
248 * NOTE: boards may use different bits for these!!
250 static void omap_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl)
252 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
254 if (cmd != NAND_CMD_NONE) {
256 writeb(cmd, info->reg.gpmc_nand_command);
258 else if (ctrl & NAND_ALE)
259 writeb(cmd, info->reg.gpmc_nand_address);
262 writeb(cmd, info->reg.gpmc_nand_data);
267 * omap_read_buf8 - read data from NAND controller into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
272 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
274 struct nand_chip *nand = mtd_to_nand(mtd);
276 ioread8_rep(nand->legacy.IO_ADDR_R, buf, len);
280 * omap_write_buf8 - write buffer to NAND controller
281 * @mtd: MTD device structure
283 * @len: number of bytes to write
285 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
287 struct omap_nand_info *info = mtd_to_omap(mtd);
288 u_char *p = (u_char *)buf;
292 iowrite8(*p++, info->nand.legacy.IO_ADDR_W);
293 /* wait until buffer is available for write */
295 status = info->ops->nand_writebuffer_empty();
301 * omap_read_buf16 - read data from NAND controller into buffer
302 * @mtd: MTD device structure
303 * @buf: buffer to store date
304 * @len: number of bytes to read
306 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
308 struct nand_chip *nand = mtd_to_nand(mtd);
310 ioread16_rep(nand->legacy.IO_ADDR_R, buf, len / 2);
314 * omap_write_buf16 - write buffer to NAND controller
315 * @mtd: MTD device structure
317 * @len: number of bytes to write
319 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
321 struct omap_nand_info *info = mtd_to_omap(mtd);
322 u16 *p = (u16 *) buf;
324 /* FIXME try bursts of writesw() or DMA ... */
328 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
329 /* wait until buffer is available for write */
331 status = info->ops->nand_writebuffer_empty();
337 * omap_read_buf_pref - read data from NAND controller into buffer
338 * @chip: NAND chip object
339 * @buf: buffer to store date
340 * @len: number of bytes to read
342 static void omap_read_buf_pref(struct nand_chip *chip, u_char *buf, int len)
344 struct mtd_info *mtd = nand_to_mtd(chip);
345 struct omap_nand_info *info = mtd_to_omap(mtd);
346 uint32_t r_count = 0;
350 /* take care of subpage reads */
352 if (info->nand.options & NAND_BUSWIDTH_16)
353 omap_read_buf16(mtd, buf, len % 4);
355 omap_read_buf8(mtd, buf, len % 4);
356 p = (u32 *) (buf + len % 4);
360 /* configure and start prefetch transfer */
361 ret = omap_prefetch_enable(info->gpmc_cs,
362 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
364 /* PFPW engine is busy, use cpu copy method */
365 if (info->nand.options & NAND_BUSWIDTH_16)
366 omap_read_buf16(mtd, (u_char *)p, len);
368 omap_read_buf8(mtd, (u_char *)p, len);
371 r_count = readl(info->reg.gpmc_prefetch_status);
372 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
373 r_count = r_count >> 2;
374 ioread32_rep(info->nand.legacy.IO_ADDR_R, p, r_count);
378 /* disable and stop the PFPW engine */
379 omap_prefetch_reset(info->gpmc_cs, info);
384 * omap_write_buf_pref - write buffer to NAND controller
385 * @chip: NAND chip object
387 * @len: number of bytes to write
389 static void omap_write_buf_pref(struct nand_chip *chip, const u_char *buf,
392 struct mtd_info *mtd = nand_to_mtd(chip);
393 struct omap_nand_info *info = mtd_to_omap(mtd);
394 uint32_t w_count = 0;
397 unsigned long tim, limit;
400 /* take care of subpage writes */
402 writeb(*buf, info->nand.legacy.IO_ADDR_W);
403 p = (u16 *)(buf + 1);
407 /* configure and start prefetch transfer */
408 ret = omap_prefetch_enable(info->gpmc_cs,
409 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
411 /* PFPW engine is busy, use cpu copy method */
412 if (info->nand.options & NAND_BUSWIDTH_16)
413 omap_write_buf16(mtd, (u_char *)p, len);
415 omap_write_buf8(mtd, (u_char *)p, len);
418 w_count = readl(info->reg.gpmc_prefetch_status);
419 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
420 w_count = w_count >> 1;
421 for (i = 0; (i < w_count) && len; i++, len -= 2)
422 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
424 /* wait for data to flushed-out before reset the prefetch */
426 limit = (loops_per_jiffy *
427 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
430 val = readl(info->reg.gpmc_prefetch_status);
431 val = PREFETCH_STATUS_COUNT(val);
432 } while (val && (tim++ < limit));
434 /* disable and stop the PFPW engine */
435 omap_prefetch_reset(info->gpmc_cs, info);
440 * omap_nand_dma_callback: callback on the completion of dma transfer
441 * @data: pointer to completion data structure
443 static void omap_nand_dma_callback(void *data)
445 complete((struct completion *) data);
449 * omap_nand_dma_transfer: configure and start dma transfer
450 * @mtd: MTD device structure
451 * @addr: virtual address in RAM of source/destination
452 * @len: number of data bytes to be transferred
453 * @is_write: flag for read/write operation
455 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
456 unsigned int len, int is_write)
458 struct omap_nand_info *info = mtd_to_omap(mtd);
459 struct dma_async_tx_descriptor *tx;
460 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
462 struct scatterlist sg;
463 unsigned long tim, limit;
468 if (!virt_addr_valid(addr))
471 sg_init_one(&sg, addr, len);
472 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
474 dev_err(&info->pdev->dev,
475 "Couldn't DMA map a %d byte buffer\n", len);
479 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
480 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
481 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 tx->callback = omap_nand_dma_callback;
486 tx->callback_param = &info->comp;
487 dmaengine_submit(tx);
489 init_completion(&info->comp);
491 /* setup and start DMA using dma_addr */
492 dma_async_issue_pending(info->dma);
494 /* configure and start prefetch transfer */
495 ret = omap_prefetch_enable(info->gpmc_cs,
496 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
498 /* PFPW engine is busy, use cpu copy method */
501 wait_for_completion(&info->comp);
503 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
507 val = readl(info->reg.gpmc_prefetch_status);
508 val = PREFETCH_STATUS_COUNT(val);
509 } while (val && (tim++ < limit));
511 /* disable and stop the PFPW engine */
512 omap_prefetch_reset(info->gpmc_cs, info);
514 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
518 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
520 if (info->nand.options & NAND_BUSWIDTH_16)
521 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
522 : omap_write_buf16(mtd, (u_char *) addr, len);
524 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
525 : omap_write_buf8(mtd, (u_char *) addr, len);
530 * omap_read_buf_dma_pref - read data from NAND controller into buffer
531 * @chip: NAND chip object
532 * @buf: buffer to store date
533 * @len: number of bytes to read
535 static void omap_read_buf_dma_pref(struct nand_chip *chip, u_char *buf,
538 struct mtd_info *mtd = nand_to_mtd(chip);
540 if (len <= mtd->oobsize)
541 omap_read_buf_pref(chip, buf, len);
543 /* start transfer in DMA mode */
544 omap_nand_dma_transfer(mtd, buf, len, 0x0);
548 * omap_write_buf_dma_pref - write buffer to NAND controller
549 * @chip: NAND chip object
551 * @len: number of bytes to write
553 static void omap_write_buf_dma_pref(struct nand_chip *chip, const u_char *buf,
556 struct mtd_info *mtd = nand_to_mtd(chip);
558 if (len <= mtd->oobsize)
559 omap_write_buf_pref(chip, buf, len);
561 /* start transfer in DMA mode */
562 omap_nand_dma_transfer(mtd, (u_char *)buf, len, 0x1);
566 * omap_nand_irq - GPMC irq handler
567 * @this_irq: gpmc irq number
568 * @dev: omap_nand_info structure pointer is passed here
570 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
572 struct omap_nand_info *info = (struct omap_nand_info *) dev;
575 bytes = readl(info->reg.gpmc_prefetch_status);
576 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
577 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
578 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
579 if (this_irq == info->gpmc_irq_count)
582 if (info->buf_len && (info->buf_len < bytes))
583 bytes = info->buf_len;
584 else if (!info->buf_len)
586 iowrite32_rep(info->nand.legacy.IO_ADDR_W, (u32 *)info->buf,
588 info->buf = info->buf + bytes;
589 info->buf_len -= bytes;
592 ioread32_rep(info->nand.legacy.IO_ADDR_R, (u32 *)info->buf,
594 info->buf = info->buf + bytes;
596 if (this_irq == info->gpmc_irq_count)
603 complete(&info->comp);
605 disable_irq_nosync(info->gpmc_irq_fifo);
606 disable_irq_nosync(info->gpmc_irq_count);
612 * omap_read_buf_irq_pref - read data from NAND controller into buffer
613 * @chip: NAND chip object
614 * @buf: buffer to store date
615 * @len: number of bytes to read
617 static void omap_read_buf_irq_pref(struct nand_chip *chip, u_char *buf,
620 struct mtd_info *mtd = nand_to_mtd(chip);
621 struct omap_nand_info *info = mtd_to_omap(mtd);
624 if (len <= mtd->oobsize) {
625 omap_read_buf_pref(chip, buf, len);
629 info->iomode = OMAP_NAND_IO_READ;
631 init_completion(&info->comp);
633 /* configure and start prefetch transfer */
634 ret = omap_prefetch_enable(info->gpmc_cs,
635 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
637 /* PFPW engine is busy, use cpu copy method */
642 enable_irq(info->gpmc_irq_count);
643 enable_irq(info->gpmc_irq_fifo);
645 /* waiting for read to complete */
646 wait_for_completion(&info->comp);
648 /* disable and stop the PFPW engine */
649 omap_prefetch_reset(info->gpmc_cs, info);
653 if (info->nand.options & NAND_BUSWIDTH_16)
654 omap_read_buf16(mtd, buf, len);
656 omap_read_buf8(mtd, buf, len);
660 * omap_write_buf_irq_pref - write buffer to NAND controller
661 * @chip: NAND chip object
663 * @len: number of bytes to write
665 static void omap_write_buf_irq_pref(struct nand_chip *chip, const u_char *buf,
668 struct mtd_info *mtd = nand_to_mtd(chip);
669 struct omap_nand_info *info = mtd_to_omap(mtd);
671 unsigned long tim, limit;
674 if (len <= mtd->oobsize) {
675 omap_write_buf_pref(chip, buf, len);
679 info->iomode = OMAP_NAND_IO_WRITE;
680 info->buf = (u_char *) buf;
681 init_completion(&info->comp);
683 /* configure and start prefetch transfer : size=24 */
684 ret = omap_prefetch_enable(info->gpmc_cs,
685 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
687 /* PFPW engine is busy, use cpu copy method */
692 enable_irq(info->gpmc_irq_count);
693 enable_irq(info->gpmc_irq_fifo);
695 /* waiting for write to complete */
696 wait_for_completion(&info->comp);
698 /* wait for data to flushed-out before reset the prefetch */
700 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
702 val = readl(info->reg.gpmc_prefetch_status);
703 val = PREFETCH_STATUS_COUNT(val);
705 } while (val && (tim++ < limit));
707 /* disable and stop the PFPW engine */
708 omap_prefetch_reset(info->gpmc_cs, info);
712 if (info->nand.options & NAND_BUSWIDTH_16)
713 omap_write_buf16(mtd, buf, len);
715 omap_write_buf8(mtd, buf, len);
719 * gen_true_ecc - This function will generate true ECC value
720 * @ecc_buf: buffer to store ecc code
722 * This generated true ECC value can be used when correcting
723 * data read from NAND flash memory core
725 static void gen_true_ecc(u8 *ecc_buf)
727 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
728 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
730 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
731 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
732 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
733 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
734 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
735 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
739 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
740 * @ecc_data1: ecc code from nand spare area
741 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
742 * @page_data: page data
744 * This function compares two ECC's and indicates if there is an error.
745 * If the error can be corrected it will be corrected to the buffer.
746 * If there is no error, %0 is returned. If there is an error but it
747 * was corrected, %1 is returned. Otherwise, %-1 is returned.
749 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
750 u8 *ecc_data2, /* read from register */
754 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
755 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
762 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
764 gen_true_ecc(ecc_data1);
765 gen_true_ecc(ecc_data2);
767 for (i = 0; i <= 2; i++) {
768 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
769 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
772 for (i = 0; i < 8; i++) {
773 tmp0_bit[i] = *ecc_data1 % 2;
774 *ecc_data1 = *ecc_data1 / 2;
777 for (i = 0; i < 8; i++) {
778 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
779 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
782 for (i = 0; i < 8; i++) {
783 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
784 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
787 for (i = 0; i < 8; i++) {
788 comp0_bit[i] = *ecc_data2 % 2;
789 *ecc_data2 = *ecc_data2 / 2;
792 for (i = 0; i < 8; i++) {
793 comp1_bit[i] = *(ecc_data2 + 1) % 2;
794 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
797 for (i = 0; i < 8; i++) {
798 comp2_bit[i] = *(ecc_data2 + 2) % 2;
799 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
802 for (i = 0; i < 6; i++)
803 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
805 for (i = 0; i < 8; i++)
806 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
808 for (i = 0; i < 8; i++)
809 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
811 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
812 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
814 for (i = 0; i < 24; i++)
815 ecc_sum += ecc_bit[i];
819 /* Not reached because this function is not called if
820 * ECC values are equal
825 /* Uncorrectable error */
826 pr_debug("ECC UNCORRECTED_ERROR 1\n");
830 /* UN-Correctable error */
831 pr_debug("ECC UNCORRECTED_ERROR B\n");
835 /* Correctable error */
836 find_byte = (ecc_bit[23] << 8) +
846 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
848 pr_debug("Correcting single bit ECC error at offset: "
849 "%d, bit: %d\n", find_byte, find_bit);
851 page_data[find_byte] ^= (1 << find_bit);
856 if (ecc_data2[0] == 0 &&
861 pr_debug("UNCORRECTED_ERROR default\n");
867 * omap_correct_data - Compares the ECC read with HW generated ECC
868 * @chip: NAND chip object
870 * @read_ecc: ecc read from nand flash
871 * @calc_ecc: ecc read from HW ECC registers
873 * Compares the ecc read from nand spare area with ECC registers values
874 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
875 * detection and correction. If there are no errors, %0 is returned. If
876 * there were errors and all of the errors were corrected, the number of
877 * corrected errors is returned. If uncorrectable errors exist, %-1 is
880 static int omap_correct_data(struct nand_chip *chip, u_char *dat,
881 u_char *read_ecc, u_char *calc_ecc)
883 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
884 int blockCnt = 0, i = 0, ret = 0;
887 /* Ex NAND_ECC_HW12_2048 */
888 if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
889 info->nand.ecc.size == 2048)
894 for (i = 0; i < blockCnt; i++) {
895 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
896 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
899 /* keep track of the number of corrected errors */
910 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
911 * @chip: NAND chip object
912 * @dat: The pointer to data on which ecc is computed
913 * @ecc_code: The ecc_code buffer
915 * Using noninverted ECC can be considered ugly since writing a blank
916 * page ie. padding will clear the ECC bytes. This is no problem as long
917 * nobody is trying to write data on the seemingly unused page. Reading
918 * an erased page will produce an ECC mismatch between generated and read
919 * ECC bytes that has to be dealt with separately.
921 static int omap_calculate_ecc(struct nand_chip *chip, const u_char *dat,
924 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
927 val = readl(info->reg.gpmc_ecc_config);
928 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
931 /* read ecc result */
932 val = readl(info->reg.gpmc_ecc1_result);
933 *ecc_code++ = val; /* P128e, ..., P1e */
934 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
935 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
936 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
942 * omap_enable_hwecc - This function enables the hardware ecc functionality
943 * @chip: NAND chip object
944 * @mode: Read/Write mode
946 static void omap_enable_hwecc(struct nand_chip *chip, int mode)
948 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
949 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
952 /* clear ecc and enable bits */
953 val = ECCCLEAR | ECC1;
954 writel(val, info->reg.gpmc_ecc_control);
956 /* program ecc and result sizes */
957 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
959 writel(val, info->reg.gpmc_ecc_size_config);
964 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
966 case NAND_ECC_READSYN:
967 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
970 dev_info(&info->pdev->dev,
971 "error: unrecognized Mode[%d]!\n", mode);
975 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
976 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
977 writel(val, info->reg.gpmc_ecc_config);
981 * omap_wait - wait until the command is done
982 * @this: NAND Chip structure
984 * Wait function is called during Program and erase operations and
985 * the way it is called from MTD layer, we should wait till the NAND
986 * chip is ready after the programming/erase operation has completed.
988 * Erase can take up to 400ms and program up to 20ms according to
989 * general NAND and SmartMedia specs
991 static int omap_wait(struct nand_chip *this)
993 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
994 unsigned long timeo = jiffies;
997 timeo += msecs_to_jiffies(400);
999 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1000 while (time_before(jiffies, timeo)) {
1001 status = readb(info->reg.gpmc_nand_data);
1002 if (status & NAND_STATUS_READY)
1007 status = readb(info->reg.gpmc_nand_data);
1012 * omap_dev_ready - checks the NAND Ready GPIO line
1013 * @chip: NAND chip object
1015 * Returns true if ready and false if busy.
1017 static int omap_dev_ready(struct nand_chip *chip)
1019 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1021 return gpiod_get_value(info->ready_gpiod);
1025 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1026 * @chip: NAND chip object
1027 * @mode: Read/Write mode
1029 * When using BCH with SW correction (i.e. no ELM), sector size is set
1030 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1031 * for both reading and writing with:
1032 * eccsize0 = 0 (no additional protected byte in spare area)
1033 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1035 static void __maybe_unused omap_enable_hwecc_bch(struct nand_chip *chip,
1038 unsigned int bch_type;
1039 unsigned int dev_width, nsectors;
1040 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1041 enum omap_ecc ecc_opt = info->ecc_opt;
1043 unsigned int ecc_size1, ecc_size0;
1045 /* GPMC configurations for calculating ECC */
1047 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1050 wr_mode = BCH_WRAPMODE_6;
1051 ecc_size0 = BCH_ECC_SIZE0;
1052 ecc_size1 = BCH_ECC_SIZE1;
1054 case OMAP_ECC_BCH4_CODE_HW:
1056 nsectors = chip->ecc.steps;
1057 if (mode == NAND_ECC_READ) {
1058 wr_mode = BCH_WRAPMODE_1;
1059 ecc_size0 = BCH4R_ECC_SIZE0;
1060 ecc_size1 = BCH4R_ECC_SIZE1;
1062 wr_mode = BCH_WRAPMODE_6;
1063 ecc_size0 = BCH_ECC_SIZE0;
1064 ecc_size1 = BCH_ECC_SIZE1;
1067 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1070 wr_mode = BCH_WRAPMODE_6;
1071 ecc_size0 = BCH_ECC_SIZE0;
1072 ecc_size1 = BCH_ECC_SIZE1;
1074 case OMAP_ECC_BCH8_CODE_HW:
1076 nsectors = chip->ecc.steps;
1077 if (mode == NAND_ECC_READ) {
1078 wr_mode = BCH_WRAPMODE_1;
1079 ecc_size0 = BCH8R_ECC_SIZE0;
1080 ecc_size1 = BCH8R_ECC_SIZE1;
1082 wr_mode = BCH_WRAPMODE_6;
1083 ecc_size0 = BCH_ECC_SIZE0;
1084 ecc_size1 = BCH_ECC_SIZE1;
1087 case OMAP_ECC_BCH16_CODE_HW:
1089 nsectors = chip->ecc.steps;
1090 if (mode == NAND_ECC_READ) {
1092 ecc_size0 = 52; /* ECC bits in nibbles per sector */
1093 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
1096 ecc_size0 = 0; /* extra bits in nibbles per sector */
1097 ecc_size1 = 52; /* OOB bits in nibbles per sector */
1104 writel(ECC1, info->reg.gpmc_ecc_control);
1106 /* Configure ecc size for BCH */
1107 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1108 writel(val, info->reg.gpmc_ecc_size_config);
1110 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1112 /* BCH configuration */
1113 val = ((1 << 16) | /* enable BCH */
1114 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
1115 (wr_mode << 8) | /* wrap mode */
1116 (dev_width << 7) | /* bus width */
1117 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1118 (info->gpmc_cs << 1) | /* ECC CS */
1119 (0x1)); /* enable ECC */
1121 writel(val, info->reg.gpmc_ecc_config);
1123 /* Clear ecc and enable bits */
1124 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1127 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1128 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1129 0x97, 0x79, 0xe5, 0x24, 0xb5};
1132 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1133 * @mtd: MTD device structure
1134 * @dat: The pointer to data on which ecc is computed
1135 * @ecc_calc: The ecc_code buffer
1136 * @i: The sector number (for a multi sector page)
1138 * Support calculating of BCH4/8/16 ECC vectors for one sector
1139 * within a page. Sector number is in @i.
1141 static int _omap_calculate_ecc_bch(struct mtd_info *mtd,
1142 const u_char *dat, u_char *ecc_calc, int i)
1144 struct omap_nand_info *info = mtd_to_omap(mtd);
1145 int eccbytes = info->nand.ecc.bytes;
1146 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1148 unsigned long bch_val1, bch_val2, bch_val3, bch_val4;
1152 ecc_code = ecc_calc;
1153 switch (info->ecc_opt) {
1154 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1155 case OMAP_ECC_BCH8_CODE_HW:
1156 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1157 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1158 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1159 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1160 *ecc_code++ = (bch_val4 & 0xFF);
1161 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1162 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1163 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1164 *ecc_code++ = (bch_val3 & 0xFF);
1165 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1166 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1167 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1168 *ecc_code++ = (bch_val2 & 0xFF);
1169 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1170 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1171 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1172 *ecc_code++ = (bch_val1 & 0xFF);
1174 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1175 case OMAP_ECC_BCH4_CODE_HW:
1176 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1177 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1178 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1179 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1180 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1181 ((bch_val1 >> 28) & 0xF);
1182 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1183 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1184 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1185 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1187 case OMAP_ECC_BCH16_CODE_HW:
1188 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1189 ecc_code[0] = ((val >> 8) & 0xFF);
1190 ecc_code[1] = ((val >> 0) & 0xFF);
1191 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1192 ecc_code[2] = ((val >> 24) & 0xFF);
1193 ecc_code[3] = ((val >> 16) & 0xFF);
1194 ecc_code[4] = ((val >> 8) & 0xFF);
1195 ecc_code[5] = ((val >> 0) & 0xFF);
1196 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1197 ecc_code[6] = ((val >> 24) & 0xFF);
1198 ecc_code[7] = ((val >> 16) & 0xFF);
1199 ecc_code[8] = ((val >> 8) & 0xFF);
1200 ecc_code[9] = ((val >> 0) & 0xFF);
1201 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1202 ecc_code[10] = ((val >> 24) & 0xFF);
1203 ecc_code[11] = ((val >> 16) & 0xFF);
1204 ecc_code[12] = ((val >> 8) & 0xFF);
1205 ecc_code[13] = ((val >> 0) & 0xFF);
1206 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1207 ecc_code[14] = ((val >> 24) & 0xFF);
1208 ecc_code[15] = ((val >> 16) & 0xFF);
1209 ecc_code[16] = ((val >> 8) & 0xFF);
1210 ecc_code[17] = ((val >> 0) & 0xFF);
1211 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1212 ecc_code[18] = ((val >> 24) & 0xFF);
1213 ecc_code[19] = ((val >> 16) & 0xFF);
1214 ecc_code[20] = ((val >> 8) & 0xFF);
1215 ecc_code[21] = ((val >> 0) & 0xFF);
1216 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1217 ecc_code[22] = ((val >> 24) & 0xFF);
1218 ecc_code[23] = ((val >> 16) & 0xFF);
1219 ecc_code[24] = ((val >> 8) & 0xFF);
1220 ecc_code[25] = ((val >> 0) & 0xFF);
1226 /* ECC scheme specific syndrome customizations */
1227 switch (info->ecc_opt) {
1228 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1229 /* Add constant polynomial to remainder, so that
1230 * ECC of blank pages results in 0x0 on reading back
1232 for (j = 0; j < eccbytes; j++)
1233 ecc_calc[j] ^= bch4_polynomial[j];
1235 case OMAP_ECC_BCH4_CODE_HW:
1236 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1237 ecc_calc[eccbytes - 1] = 0x0;
1239 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1240 /* Add constant polynomial to remainder, so that
1241 * ECC of blank pages results in 0x0 on reading back
1243 for (j = 0; j < eccbytes; j++)
1244 ecc_calc[j] ^= bch8_polynomial[j];
1246 case OMAP_ECC_BCH8_CODE_HW:
1247 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1248 ecc_calc[eccbytes - 1] = 0x0;
1250 case OMAP_ECC_BCH16_CODE_HW:
1260 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1261 * @chip: NAND chip object
1262 * @dat: The pointer to data on which ecc is computed
1263 * @ecc_calc: Buffer storing the calculated ECC bytes
1265 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1266 * when SW based correction is required as ECC is required for one sector
1269 static int omap_calculate_ecc_bch_sw(struct nand_chip *chip,
1270 const u_char *dat, u_char *ecc_calc)
1272 return _omap_calculate_ecc_bch(nand_to_mtd(chip), dat, ecc_calc, 0);
1276 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1277 * @mtd: MTD device structure
1278 * @dat: The pointer to data on which ecc is computed
1279 * @ecc_calc: Buffer storing the calculated ECC bytes
1281 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1283 static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
1284 const u_char *dat, u_char *ecc_calc)
1286 struct omap_nand_info *info = mtd_to_omap(mtd);
1287 int eccbytes = info->nand.ecc.bytes;
1288 unsigned long nsectors;
1291 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1292 for (i = 0; i < nsectors; i++) {
1293 ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
1297 ecc_calc += eccbytes;
1304 * erased_sector_bitflips - count bit flips
1305 * @data: data sector buffer
1307 * @info: omap_nand_info
1309 * Check the bit flips in erased page falls below correctable level.
1310 * If falls below, report the page as erased with correctable bit
1311 * flip, else report as uncorrectable page.
1313 static int erased_sector_bitflips(u_char *data, u_char *oob,
1314 struct omap_nand_info *info)
1316 int flip_bits = 0, i;
1318 for (i = 0; i < info->nand.ecc.size; i++) {
1319 flip_bits += hweight8(~data[i]);
1320 if (flip_bits > info->nand.ecc.strength)
1324 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1325 flip_bits += hweight8(~oob[i]);
1326 if (flip_bits > info->nand.ecc.strength)
1331 * Bit flips falls in correctable level.
1332 * Fill data area with 0xFF
1335 memset(data, 0xFF, info->nand.ecc.size);
1336 memset(oob, 0xFF, info->nand.ecc.bytes);
1343 * omap_elm_correct_data - corrects page data area in case error reported
1344 * @chip: NAND chip object
1346 * @read_ecc: ecc read from nand flash
1347 * @calc_ecc: ecc read from HW ECC registers
1349 * Calculated ecc vector reported as zero in case of non-error pages.
1350 * In case of non-zero ecc vector, first filter out erased-pages, and
1351 * then process data via ELM to detect bit-flips.
1353 static int omap_elm_correct_data(struct nand_chip *chip, u_char *data,
1354 u_char *read_ecc, u_char *calc_ecc)
1356 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1357 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1358 int eccsteps = info->nand.ecc.steps;
1359 int i , j, stat = 0;
1360 int eccflag, actual_eccbytes;
1361 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1362 u_char *ecc_vec = calc_ecc;
1363 u_char *spare_ecc = read_ecc;
1364 u_char *erased_ecc_vec;
1367 bool is_error_reported = false;
1368 u32 bit_pos, byte_pos, error_max, pos;
1371 switch (info->ecc_opt) {
1372 case OMAP_ECC_BCH4_CODE_HW:
1373 /* omit 7th ECC byte reserved for ROM code compatibility */
1374 actual_eccbytes = ecc->bytes - 1;
1375 erased_ecc_vec = bch4_vector;
1377 case OMAP_ECC_BCH8_CODE_HW:
1378 /* omit 14th ECC byte reserved for ROM code compatibility */
1379 actual_eccbytes = ecc->bytes - 1;
1380 erased_ecc_vec = bch8_vector;
1382 case OMAP_ECC_BCH16_CODE_HW:
1383 actual_eccbytes = ecc->bytes;
1384 erased_ecc_vec = bch16_vector;
1387 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1391 /* Initialize elm error vector to zero */
1392 memset(err_vec, 0, sizeof(err_vec));
1394 for (i = 0; i < eccsteps ; i++) {
1395 eccflag = 0; /* initialize eccflag */
1398 * Check any error reported,
1399 * In case of error, non zero ecc reported.
1401 for (j = 0; j < actual_eccbytes; j++) {
1402 if (calc_ecc[j] != 0) {
1403 eccflag = 1; /* non zero ecc, error present */
1409 if (memcmp(calc_ecc, erased_ecc_vec,
1410 actual_eccbytes) == 0) {
1412 * calc_ecc[] matches pattern for ECC(all 0xff)
1413 * so this is definitely an erased-page
1416 buf = &data[info->nand.ecc.size * i];
1418 * count number of 0-bits in read_buf.
1419 * This check can be removed once a similar
1420 * check is introduced in generic NAND driver
1422 bitflip_count = erased_sector_bitflips(
1423 buf, read_ecc, info);
1424 if (bitflip_count) {
1426 * number of 0-bits within ECC limits
1427 * So this may be an erased-page
1429 stat += bitflip_count;
1432 * Too many 0-bits. It may be a
1433 * - programmed-page, OR
1434 * - erased-page with many bit-flips
1435 * So this page requires check by ELM
1437 err_vec[i].error_reported = true;
1438 is_error_reported = true;
1443 /* Update the ecc vector */
1444 calc_ecc += ecc->bytes;
1445 read_ecc += ecc->bytes;
1448 /* Check if any error reported */
1449 if (!is_error_reported)
1452 /* Decode BCH error using ELM module */
1453 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1456 for (i = 0; i < eccsteps; i++) {
1457 if (err_vec[i].error_uncorrectable) {
1458 dev_err(&info->pdev->dev,
1459 "uncorrectable bit-flips found\n");
1461 } else if (err_vec[i].error_reported) {
1462 for (j = 0; j < err_vec[i].error_count; j++) {
1463 switch (info->ecc_opt) {
1464 case OMAP_ECC_BCH4_CODE_HW:
1465 /* Add 4 bits to take care of padding */
1466 pos = err_vec[i].error_loc[j] +
1469 case OMAP_ECC_BCH8_CODE_HW:
1470 case OMAP_ECC_BCH16_CODE_HW:
1471 pos = err_vec[i].error_loc[j];
1476 error_max = (ecc->size + actual_eccbytes) * 8;
1477 /* Calculate bit position of error */
1480 /* Calculate byte position of error */
1481 byte_pos = (error_max - pos - 1) / 8;
1483 if (pos < error_max) {
1484 if (byte_pos < 512) {
1485 pr_debug("bitflip@dat[%d]=%x\n",
1486 byte_pos, data[byte_pos]);
1487 data[byte_pos] ^= 1 << bit_pos;
1489 pr_debug("bitflip@oob[%d]=%x\n",
1491 spare_ecc[byte_pos - 512]);
1492 spare_ecc[byte_pos - 512] ^=
1496 dev_err(&info->pdev->dev,
1497 "invalid bit-flip @ %d:%d\n",
1504 /* Update number of correctable errors */
1505 stat = max_t(unsigned int, stat, err_vec[i].error_count);
1507 /* Update page data with sector size */
1509 spare_ecc += ecc->bytes;
1512 return (err) ? err : stat;
1516 * omap_write_page_bch - BCH ecc based write page function for entire page
1517 * @chip: nand chip info structure
1519 * @oob_required: must write chip->oob_poi to OOB
1522 * Custom write page method evolved to support multi sector writing in one shot
1524 static int omap_write_page_bch(struct nand_chip *chip, const uint8_t *buf,
1525 int oob_required, int page)
1527 struct mtd_info *mtd = nand_to_mtd(chip);
1529 uint8_t *ecc_calc = chip->ecc.calc_buf;
1531 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1533 /* Enable GPMC ecc engine */
1534 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1537 chip->legacy.write_buf(chip, buf, mtd->writesize);
1539 /* Update ecc vector from GPMC result registers */
1540 omap_calculate_ecc_bch_multi(mtd, buf, &ecc_calc[0]);
1542 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1547 /* Write ecc vector to OOB area */
1548 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1550 return nand_prog_page_end_op(chip);
1554 * omap_write_subpage_bch - BCH hardware ECC based subpage write
1555 * @chip: nand chip info structure
1556 * @offset: column address of subpage within the page
1557 * @data_len: data length
1559 * @oob_required: must write chip->oob_poi to OOB
1560 * @page: page number to write
1562 * OMAP optimized subpage write method.
1564 static int omap_write_subpage_bch(struct nand_chip *chip, u32 offset,
1565 u32 data_len, const u8 *buf,
1566 int oob_required, int page)
1568 struct mtd_info *mtd = nand_to_mtd(chip);
1569 u8 *ecc_calc = chip->ecc.calc_buf;
1570 int ecc_size = chip->ecc.size;
1571 int ecc_bytes = chip->ecc.bytes;
1572 int ecc_steps = chip->ecc.steps;
1573 u32 start_step = offset / ecc_size;
1574 u32 end_step = (offset + data_len - 1) / ecc_size;
1578 * Write entire page at one go as it would be optimal
1579 * as ECC is calculated by hardware.
1580 * ECC is calculated for all subpages but we choose
1581 * only what we want.
1583 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1585 /* Enable GPMC ECC engine */
1586 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
1589 chip->legacy.write_buf(chip, buf, mtd->writesize);
1591 for (step = 0; step < ecc_steps; step++) {
1592 /* mask ECC of un-touched subpages by padding 0xFF */
1593 if (step < start_step || step > end_step)
1594 memset(ecc_calc, 0xff, ecc_bytes);
1596 ret = _omap_calculate_ecc_bch(mtd, buf, ecc_calc, step);
1602 ecc_calc += ecc_bytes;
1605 /* copy calculated ECC for whole page to chip->buffer->oob */
1606 /* this include masked-value(0xFF) for unwritten subpages */
1607 ecc_calc = chip->ecc.calc_buf;
1608 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
1613 /* write OOB buffer to NAND device */
1614 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
1616 return nand_prog_page_end_op(chip);
1620 * omap_read_page_bch - BCH ecc based page read function for entire page
1621 * @chip: nand chip info structure
1622 * @buf: buffer to store read data
1623 * @oob_required: caller requires OOB data read to chip->oob_poi
1624 * @page: page number to read
1626 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1627 * used for error correction.
1628 * Custom method evolved to support ELM error correction & multi sector
1629 * reading. On reading page data area is read along with OOB data with
1630 * ecc engine enabled. ecc vector updated after read of OOB data.
1631 * For non error pages ecc vector reported as zero.
1633 static int omap_read_page_bch(struct nand_chip *chip, uint8_t *buf,
1634 int oob_required, int page)
1636 struct mtd_info *mtd = nand_to_mtd(chip);
1637 uint8_t *ecc_calc = chip->ecc.calc_buf;
1638 uint8_t *ecc_code = chip->ecc.code_buf;
1640 unsigned int max_bitflips = 0;
1642 nand_read_page_op(chip, page, 0, NULL, 0);
1644 /* Enable GPMC ecc engine */
1645 chip->ecc.hwctl(chip, NAND_ECC_READ);
1648 chip->legacy.read_buf(chip, buf, mtd->writesize);
1650 /* Read oob bytes */
1651 nand_change_read_column_op(chip,
1652 mtd->writesize + BADBLOCK_MARKER_LENGTH,
1653 chip->oob_poi + BADBLOCK_MARKER_LENGTH,
1654 chip->ecc.total, false);
1656 /* Calculate ecc bytes */
1657 omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
1659 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1664 stat = chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1667 mtd->ecc_stats.failed++;
1669 mtd->ecc_stats.corrected += stat;
1670 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1673 return max_bitflips;
1677 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1678 * @info: NAND device structure containing platform data
1679 * @elm_node: ELM's DT node
1681 static bool is_elm_present(struct omap_nand_info *info,
1682 struct device_node *elm_node)
1684 struct platform_device *pdev;
1686 /* check whether elm-id is passed via DT */
1688 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1691 pdev = of_find_device_by_node(elm_node);
1692 /* check whether ELM device is registered */
1694 dev_err(&info->pdev->dev, "ELM device not found\n");
1697 /* ELM module available, now configure it */
1698 info->elm_dev = &pdev->dev;
1702 static bool omap2_nand_ecc_check(struct omap_nand_info *info)
1704 bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1706 switch (info->ecc_opt) {
1707 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1708 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1709 ecc_needs_omap_bch = false;
1710 ecc_needs_bch = true;
1711 ecc_needs_elm = false;
1713 case OMAP_ECC_BCH4_CODE_HW:
1714 case OMAP_ECC_BCH8_CODE_HW:
1715 case OMAP_ECC_BCH16_CODE_HW:
1716 ecc_needs_omap_bch = true;
1717 ecc_needs_bch = false;
1718 ecc_needs_elm = true;
1721 ecc_needs_omap_bch = false;
1722 ecc_needs_bch = false;
1723 ecc_needs_elm = false;
1727 if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
1728 dev_err(&info->pdev->dev,
1729 "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
1732 if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1733 dev_err(&info->pdev->dev,
1734 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1737 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1738 dev_err(&info->pdev->dev, "ELM not available\n");
1745 static const char * const nand_xfer_types[] = {
1746 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1747 [NAND_OMAP_POLLED] = "polled",
1748 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1749 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1752 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1754 struct device_node *child = dev->of_node;
1759 if (of_property_read_u32(child, "reg", &cs) < 0) {
1760 dev_err(dev, "reg not found in DT\n");
1766 /* detect availability of ELM module. Won't be present pre-OMAP4 */
1767 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1768 if (!info->elm_of_node) {
1769 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1770 if (!info->elm_of_node)
1771 dev_dbg(dev, "ti,elm-id not in DT\n");
1774 /* select ecc-scheme for NAND */
1775 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1776 dev_err(dev, "ti,nand-ecc-opt not found\n");
1780 if (!strcmp(s, "sw")) {
1781 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1782 } else if (!strcmp(s, "ham1") ||
1783 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1784 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1785 } else if (!strcmp(s, "bch4")) {
1786 if (info->elm_of_node)
1787 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1789 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1790 } else if (!strcmp(s, "bch8")) {
1791 if (info->elm_of_node)
1792 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1794 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1795 } else if (!strcmp(s, "bch16")) {
1796 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1798 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1802 /* select data transfer mode */
1803 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1804 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1805 if (!strcasecmp(s, nand_xfer_types[i])) {
1806 info->xfer_type = i;
1811 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1818 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section,
1819 struct mtd_oob_region *oobregion)
1821 struct omap_nand_info *info = mtd_to_omap(mtd);
1822 struct nand_chip *chip = &info->nand;
1823 int off = BADBLOCK_MARKER_LENGTH;
1825 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1826 !(chip->options & NAND_BUSWIDTH_16))
1832 oobregion->offset = off;
1833 oobregion->length = chip->ecc.total;
1838 static int omap_ooblayout_free(struct mtd_info *mtd, int section,
1839 struct mtd_oob_region *oobregion)
1841 struct omap_nand_info *info = mtd_to_omap(mtd);
1842 struct nand_chip *chip = &info->nand;
1843 int off = BADBLOCK_MARKER_LENGTH;
1845 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1846 !(chip->options & NAND_BUSWIDTH_16))
1852 off += chip->ecc.total;
1853 if (off >= mtd->oobsize)
1856 oobregion->offset = off;
1857 oobregion->length = mtd->oobsize - off;
1862 static const struct mtd_ooblayout_ops omap_ooblayout_ops = {
1863 .ecc = omap_ooblayout_ecc,
1864 .free = omap_ooblayout_free,
1867 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section,
1868 struct mtd_oob_region *oobregion)
1870 struct nand_device *nand = mtd_to_nanddev(mtd);
1871 unsigned int nsteps = nanddev_get_ecc_nsteps(nand);
1872 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand);
1873 int off = BADBLOCK_MARKER_LENGTH;
1875 if (section >= nsteps)
1879 * When SW correction is employed, one OMAP specific marker byte is
1880 * reserved after each ECC step.
1882 oobregion->offset = off + (section * (ecc_bytes + 1));
1883 oobregion->length = ecc_bytes;
1888 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section,
1889 struct mtd_oob_region *oobregion)
1891 struct nand_device *nand = mtd_to_nanddev(mtd);
1892 unsigned int nsteps = nanddev_get_ecc_nsteps(nand);
1893 unsigned int ecc_bytes = nanddev_get_ecc_bytes_per_step(nand);
1894 int off = BADBLOCK_MARKER_LENGTH;
1900 * When SW correction is employed, one OMAP specific marker byte is
1901 * reserved after each ECC step.
1903 off += ((ecc_bytes + 1) * nsteps);
1904 if (off >= mtd->oobsize)
1907 oobregion->offset = off;
1908 oobregion->length = mtd->oobsize - off;
1913 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
1914 .ecc = omap_sw_ooblayout_ecc,
1915 .free = omap_sw_ooblayout_free,
1918 static int omap_nand_attach_chip(struct nand_chip *chip)
1920 struct mtd_info *mtd = nand_to_mtd(chip);
1921 struct omap_nand_info *info = mtd_to_omap(mtd);
1922 struct device *dev = &info->pdev->dev;
1923 int min_oobbytes = BADBLOCK_MARKER_LENGTH;
1924 int oobbytes_per_step;
1925 dma_cap_mask_t mask;
1928 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1929 chip->bbt_options |= NAND_BBT_NO_OOB;
1931 chip->options |= NAND_SKIP_BBTSCAN;
1933 /* Re-populate low-level callbacks based on xfer modes */
1934 switch (info->xfer_type) {
1935 case NAND_OMAP_PREFETCH_POLLED:
1936 chip->legacy.read_buf = omap_read_buf_pref;
1937 chip->legacy.write_buf = omap_write_buf_pref;
1940 case NAND_OMAP_POLLED:
1941 /* Use nand_base defaults for {read,write}_buf */
1944 case NAND_OMAP_PREFETCH_DMA:
1946 dma_cap_set(DMA_SLAVE, mask);
1947 info->dma = dma_request_chan(dev->parent, "rxtx");
1949 if (IS_ERR(info->dma)) {
1950 dev_err(dev, "DMA engine request failed\n");
1951 return PTR_ERR(info->dma);
1953 struct dma_slave_config cfg;
1955 memset(&cfg, 0, sizeof(cfg));
1956 cfg.src_addr = info->phys_base;
1957 cfg.dst_addr = info->phys_base;
1958 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1959 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1960 cfg.src_maxburst = 16;
1961 cfg.dst_maxburst = 16;
1962 err = dmaengine_slave_config(info->dma, &cfg);
1965 "DMA engine slave config failed: %d\n",
1969 chip->legacy.read_buf = omap_read_buf_dma_pref;
1970 chip->legacy.write_buf = omap_write_buf_dma_pref;
1974 case NAND_OMAP_PREFETCH_IRQ:
1975 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);
1976 if (info->gpmc_irq_fifo <= 0)
1978 err = devm_request_irq(dev, info->gpmc_irq_fifo,
1979 omap_nand_irq, IRQF_SHARED,
1980 "gpmc-nand-fifo", info);
1982 dev_err(dev, "Requesting IRQ %d, error %d\n",
1983 info->gpmc_irq_fifo, err);
1984 info->gpmc_irq_fifo = 0;
1988 info->gpmc_irq_count = platform_get_irq(info->pdev, 1);
1989 if (info->gpmc_irq_count <= 0)
1991 err = devm_request_irq(dev, info->gpmc_irq_count,
1992 omap_nand_irq, IRQF_SHARED,
1993 "gpmc-nand-count", info);
1995 dev_err(dev, "Requesting IRQ %d, error %d\n",
1996 info->gpmc_irq_count, err);
1997 info->gpmc_irq_count = 0;
2001 chip->legacy.read_buf = omap_read_buf_irq_pref;
2002 chip->legacy.write_buf = omap_write_buf_irq_pref;
2007 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type);
2011 if (!omap2_nand_ecc_check(info))
2015 * Bail out earlier to let NAND_ECC_ENGINE_TYPE_SOFT code create its own
2016 * ooblayout instead of using ours.
2018 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2019 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
2020 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2024 /* Populate MTD interface based on ECC scheme */
2025 switch (info->ecc_opt) {
2026 case OMAP_ECC_HAM1_CODE_HW:
2027 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
2028 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2029 chip->ecc.bytes = 3;
2030 chip->ecc.size = 512;
2031 chip->ecc.strength = 1;
2032 chip->ecc.calculate = omap_calculate_ecc;
2033 chip->ecc.hwctl = omap_enable_hwecc;
2034 chip->ecc.correct = omap_correct_data;
2035 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2036 oobbytes_per_step = chip->ecc.bytes;
2038 if (!(chip->options & NAND_BUSWIDTH_16))
2043 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
2044 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2045 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2046 chip->ecc.size = 512;
2047 chip->ecc.bytes = 7;
2048 chip->ecc.strength = 4;
2049 chip->ecc.hwctl = omap_enable_hwecc_bch;
2050 chip->ecc.correct = rawnand_sw_bch_correct;
2051 chip->ecc.calculate = omap_calculate_ecc_bch_sw;
2052 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2053 /* Reserve one byte for the OMAP marker */
2054 oobbytes_per_step = chip->ecc.bytes + 1;
2055 /* Software BCH library is used for locating errors */
2056 err = rawnand_sw_bch_init(chip);
2058 dev_err(dev, "Unable to use BCH library\n");
2063 case OMAP_ECC_BCH4_CODE_HW:
2064 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2065 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2066 chip->ecc.size = 512;
2067 /* 14th bit is kept reserved for ROM-code compatibility */
2068 chip->ecc.bytes = 7 + 1;
2069 chip->ecc.strength = 4;
2070 chip->ecc.hwctl = omap_enable_hwecc_bch;
2071 chip->ecc.correct = omap_elm_correct_data;
2072 chip->ecc.read_page = omap_read_page_bch;
2073 chip->ecc.write_page = omap_write_page_bch;
2074 chip->ecc.write_subpage = omap_write_subpage_bch;
2075 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2076 oobbytes_per_step = chip->ecc.bytes;
2078 err = elm_config(info->elm_dev, BCH4_ECC,
2079 mtd->writesize / chip->ecc.size,
2080 chip->ecc.size, chip->ecc.bytes);
2085 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2086 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2087 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2088 chip->ecc.size = 512;
2089 chip->ecc.bytes = 13;
2090 chip->ecc.strength = 8;
2091 chip->ecc.hwctl = omap_enable_hwecc_bch;
2092 chip->ecc.correct = rawnand_sw_bch_correct;
2093 chip->ecc.calculate = omap_calculate_ecc_bch_sw;
2094 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
2095 /* Reserve one byte for the OMAP marker */
2096 oobbytes_per_step = chip->ecc.bytes + 1;
2097 /* Software BCH library is used for locating errors */
2098 err = rawnand_sw_bch_init(chip);
2100 dev_err(dev, "unable to use BCH library\n");
2105 case OMAP_ECC_BCH8_CODE_HW:
2106 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2107 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2108 chip->ecc.size = 512;
2109 /* 14th bit is kept reserved for ROM-code compatibility */
2110 chip->ecc.bytes = 13 + 1;
2111 chip->ecc.strength = 8;
2112 chip->ecc.hwctl = omap_enable_hwecc_bch;
2113 chip->ecc.correct = omap_elm_correct_data;
2114 chip->ecc.read_page = omap_read_page_bch;
2115 chip->ecc.write_page = omap_write_page_bch;
2116 chip->ecc.write_subpage = omap_write_subpage_bch;
2117 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2118 oobbytes_per_step = chip->ecc.bytes;
2120 err = elm_config(info->elm_dev, BCH8_ECC,
2121 mtd->writesize / chip->ecc.size,
2122 chip->ecc.size, chip->ecc.bytes);
2128 case OMAP_ECC_BCH16_CODE_HW:
2129 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2130 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2131 chip->ecc.size = 512;
2132 chip->ecc.bytes = 26;
2133 chip->ecc.strength = 16;
2134 chip->ecc.hwctl = omap_enable_hwecc_bch;
2135 chip->ecc.correct = omap_elm_correct_data;
2136 chip->ecc.read_page = omap_read_page_bch;
2137 chip->ecc.write_page = omap_write_page_bch;
2138 chip->ecc.write_subpage = omap_write_subpage_bch;
2139 mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
2140 oobbytes_per_step = chip->ecc.bytes;
2142 err = elm_config(info->elm_dev, BCH16_ECC,
2143 mtd->writesize / chip->ecc.size,
2144 chip->ecc.size, chip->ecc.bytes);
2150 dev_err(dev, "Invalid or unsupported ECC scheme\n");
2154 /* Check if NAND device's OOB is enough to store ECC signatures */
2155 min_oobbytes += (oobbytes_per_step *
2156 (mtd->writesize / chip->ecc.size));
2157 if (mtd->oobsize < min_oobbytes) {
2159 "Not enough OOB bytes: required = %d, available=%d\n",
2160 min_oobbytes, mtd->oobsize);
2167 static const struct nand_controller_ops omap_nand_controller_ops = {
2168 .attach_chip = omap_nand_attach_chip,
2171 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2172 static struct nand_controller omap_gpmc_controller;
2173 static bool omap_gpmc_controller_initialized;
2175 static int omap_nand_probe(struct platform_device *pdev)
2177 struct omap_nand_info *info;
2178 struct mtd_info *mtd;
2179 struct nand_chip *nand_chip;
2181 struct resource *res;
2182 struct device *dev = &pdev->dev;
2184 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
2191 err = omap_get_dt_info(dev, info);
2195 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
2197 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
2201 nand_chip = &info->nand;
2202 mtd = nand_to_mtd(nand_chip);
2203 mtd->dev.parent = &pdev->dev;
2204 nand_set_flash_node(nand_chip, dev->of_node);
2207 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
2208 "omap2-nand.%d", info->gpmc_cs);
2210 dev_err(&pdev->dev, "Failed to set MTD name\n");
2215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2216 nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
2217 if (IS_ERR(nand_chip->legacy.IO_ADDR_R))
2218 return PTR_ERR(nand_chip->legacy.IO_ADDR_R);
2220 info->phys_base = res->start;
2222 if (!omap_gpmc_controller_initialized) {
2223 omap_gpmc_controller.ops = &omap_nand_controller_ops;
2224 nand_controller_init(&omap_gpmc_controller);
2225 omap_gpmc_controller_initialized = true;
2228 nand_chip->controller = &omap_gpmc_controller;
2230 nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
2231 nand_chip->legacy.cmd_ctrl = omap_hwcontrol;
2233 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
2235 if (IS_ERR(info->ready_gpiod)) {
2236 dev_err(dev, "failed to get ready gpio\n");
2237 return PTR_ERR(info->ready_gpiod);
2241 * If RDY/BSY line is connected to OMAP then use the omap ready
2242 * function and the generic nand_wait function which reads the status
2243 * register after monitoring the RDY/BSY line. Otherwise use a standard
2244 * chip delay which is slightly more than tR (AC Timing) of the NAND
2245 * device and read status register until you get a failure or success
2247 if (info->ready_gpiod) {
2248 nand_chip->legacy.dev_ready = omap_dev_ready;
2249 nand_chip->legacy.chip_delay = 0;
2251 nand_chip->legacy.waitfunc = omap_wait;
2252 nand_chip->legacy.chip_delay = 50;
2255 if (info->flash_bbt)
2256 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2258 /* scan NAND device connected to chip controller */
2259 nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
2261 err = nand_scan(nand_chip, 1);
2265 err = mtd_device_register(mtd, NULL, 0);
2269 platform_set_drvdata(pdev, mtd);
2274 nand_cleanup(nand_chip);
2277 if (!IS_ERR_OR_NULL(info->dma))
2278 dma_release_channel(info->dma);
2280 rawnand_sw_bch_cleanup(nand_chip);
2285 static int omap_nand_remove(struct platform_device *pdev)
2287 struct mtd_info *mtd = platform_get_drvdata(pdev);
2288 struct nand_chip *nand_chip = mtd_to_nand(mtd);
2289 struct omap_nand_info *info = mtd_to_omap(mtd);
2292 rawnand_sw_bch_cleanup(nand_chip);
2295 dma_release_channel(info->dma);
2296 ret = mtd_device_unregister(mtd);
2298 nand_cleanup(nand_chip);
2302 static const struct of_device_id omap_nand_ids[] = {
2303 { .compatible = "ti,omap2-nand", },
2306 MODULE_DEVICE_TABLE(of, omap_nand_ids);
2308 static struct platform_driver omap_nand_driver = {
2309 .probe = omap_nand_probe,
2310 .remove = omap_nand_remove,
2312 .name = DRIVER_NAME,
2313 .of_match_table = of_match_ptr(omap_nand_ids),
2317 module_platform_driver(omap_nand_driver);
2319 MODULE_ALIAS("platform:" DRIVER_NAME);
2320 MODULE_LICENSE("GPL");
2321 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");