2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/rawnand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <linux/of_device.h>
38 #include <asm/mach/flash.h>
39 #include <linux/platform_data/mtd-mxc_nand.h>
41 #define DRIVER_NAME "mxc_nand"
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
56 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
57 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
58 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
59 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
60 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
61 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
62 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
63 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
64 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
65 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
68 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
69 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
70 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
71 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
72 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
73 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
74 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
75 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
76 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
81 * Operation modes for the NFC. Valid for v1, v2 and v3
84 #define NFC_CMD (1 << 0)
85 #define NFC_ADDR (1 << 1)
86 #define NFC_INPUT (1 << 2)
87 #define NFC_OUTPUT (1 << 3)
88 #define NFC_ID (1 << 4)
89 #define NFC_STATUS (1 << 5)
91 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
92 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
95 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
96 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
103 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
104 #define NFC_V3_WRPROT_LOCK (1 << 1)
105 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
106 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
111 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
112 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
113 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
114 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
115 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
116 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
118 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
119 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
121 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
122 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
123 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
126 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
127 #define NFC_V3_CONFIG3_FW8 (1 << 3)
128 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
130 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
131 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133 #define NFC_V3_IPC (host->regs_ip + 0x2C)
134 #define NFC_V3_IPC_CREQ (1 << 0)
135 #define NFC_V3_IPC_INT (1 << 31)
137 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139 struct mxc_nand_host;
141 struct mxc_nand_devtype_data {
142 void (*preset)(struct mtd_info *);
143 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
145 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
147 void (*send_page)(struct mtd_info *, unsigned int);
148 void (*send_read_id)(struct mxc_nand_host *);
149 uint16_t (*get_dev_status)(struct mxc_nand_host *);
150 int (*check_int)(struct mxc_nand_host *);
151 void (*irq_control)(struct mxc_nand_host *, int);
152 u32 (*get_ecc_status)(struct mxc_nand_host *);
153 const struct mtd_ooblayout_ops *ooblayout;
154 void (*select_chip)(struct mtd_info *mtd, int chip);
155 int (*setup_data_interface)(struct mtd_info *mtd, int csline,
156 const struct nand_data_interface *conf);
157 void (*enable_hwecc)(struct nand_chip *chip, bool enable);
160 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
161 * (CONFIG1:INT_MSK is set). To handle this the driver uses
162 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
164 int irqpending_quirk;
168 size_t spare0_offset;
177 struct mxc_nand_host {
178 struct nand_chip nand;
181 void __iomem *spare0;
182 void __iomem *main_area0;
186 void __iomem *regs_axi;
187 void __iomem *regs_ip;
196 struct completion op_completion;
199 unsigned int buf_start;
201 const struct mxc_nand_devtype_data *devtype_data;
202 struct mxc_nand_platform_data pdata;
205 static const char * const part_probes[] = {
206 "cmdlinepart", "RedBoot", "ofpart", NULL };
208 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
212 const __iomem u32 *s = src;
214 for (i = 0; i < (size >> 2); i++)
215 *t++ = __raw_readl(s++);
218 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
222 const __iomem u16 *s = src;
224 /* We assume that src (IO) is always 32bit aligned */
225 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
226 memcpy32_fromio(trg, src, size);
230 for (i = 0; i < (size >> 1); i++)
231 *t++ = __raw_readw(s++);
234 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
236 /* __iowrite32_copy use 32bit size values so divide by 4 */
237 __iowrite32_copy(trg, src, size / 4);
240 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
243 __iomem u16 *t = trg;
246 /* We assume that trg (IO) is always 32bit aligned */
247 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
248 memcpy32_toio(trg, src, size);
252 for (i = 0; i < (size >> 1); i++)
253 __raw_writew(*s++, t++);
257 * The controller splits a page into data chunks of 512 bytes + partial oob.
258 * There are writesize / 512 such chunks, the size of the partial oob parts is
259 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
260 * contains additionally the byte lost by rounding (if any).
261 * This function handles the needed shuffling between host->data_buf (which
262 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
263 * spare) and the NFC buffer.
265 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
267 struct nand_chip *this = mtd_to_nand(mtd);
268 struct mxc_nand_host *host = nand_get_controller_data(this);
269 u16 i, oob_chunk_size;
270 u16 num_chunks = mtd->writesize / 512;
273 u8 __iomem *s = host->spare0;
274 u16 sparebuf_size = host->devtype_data->spare_len;
276 /* size of oob chunk for all but possibly the last one */
277 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
280 for (i = 0; i < num_chunks - 1; i++)
281 memcpy16_fromio(d + i * oob_chunk_size,
282 s + i * sparebuf_size,
286 memcpy16_fromio(d + i * oob_chunk_size,
287 s + i * sparebuf_size,
288 host->used_oobsize - i * oob_chunk_size);
290 for (i = 0; i < num_chunks - 1; i++)
291 memcpy16_toio(&s[i * sparebuf_size],
292 &d[i * oob_chunk_size],
296 memcpy16_toio(&s[i * sparebuf_size],
297 &d[i * oob_chunk_size],
298 host->used_oobsize - i * oob_chunk_size);
303 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
304 * the upper layers perform a read/write buf operation, the saved column address
305 * is used to index into the full page. So usually this function is called with
306 * column == 0 (unless no column cycle is needed indicated by column == -1)
308 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
310 struct nand_chip *nand_chip = mtd_to_nand(mtd);
311 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
313 /* Write out column address, if necessary */
315 host->devtype_data->send_addr(host, column & 0xff,
317 if (mtd->writesize > 512)
318 /* another col addr cycle for 2k page */
319 host->devtype_data->send_addr(host,
320 (column >> 8) & 0xff,
324 /* Write out page address, if necessary */
325 if (page_addr != -1) {
326 /* paddr_0 - p_addr_7 */
327 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
329 if (mtd->writesize > 512) {
330 if (mtd->size >= 0x10000000) {
331 /* paddr_8 - paddr_15 */
332 host->devtype_data->send_addr(host,
333 (page_addr >> 8) & 0xff,
335 host->devtype_data->send_addr(host,
336 (page_addr >> 16) & 0xff,
339 /* paddr_8 - paddr_15 */
340 host->devtype_data->send_addr(host,
341 (page_addr >> 8) & 0xff, true);
343 if (nand_chip->options & NAND_ROW_ADDR_3) {
344 /* paddr_8 - paddr_15 */
345 host->devtype_data->send_addr(host,
346 (page_addr >> 8) & 0xff,
348 host->devtype_data->send_addr(host,
349 (page_addr >> 16) & 0xff,
352 /* paddr_8 - paddr_15 */
353 host->devtype_data->send_addr(host,
354 (page_addr >> 8) & 0xff, true);
359 static int check_int_v3(struct mxc_nand_host *host)
363 tmp = readl(NFC_V3_IPC);
364 if (!(tmp & NFC_V3_IPC_INT))
367 tmp &= ~NFC_V3_IPC_INT;
368 writel(tmp, NFC_V3_IPC);
373 static int check_int_v1_v2(struct mxc_nand_host *host)
377 tmp = readw(NFC_V1_V2_CONFIG2);
378 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
381 if (!host->devtype_data->irqpending_quirk)
382 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
387 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
391 tmp = readw(NFC_V1_V2_CONFIG1);
394 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
396 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
398 writew(tmp, NFC_V1_V2_CONFIG1);
401 static void irq_control_v3(struct mxc_nand_host *host, int activate)
405 tmp = readl(NFC_V3_CONFIG2);
408 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
410 tmp |= NFC_V3_CONFIG2_INT_MSK;
412 writel(tmp, NFC_V3_CONFIG2);
415 static void irq_control(struct mxc_nand_host *host, int activate)
417 if (host->devtype_data->irqpending_quirk) {
419 enable_irq(host->irq);
421 disable_irq_nosync(host->irq);
423 host->devtype_data->irq_control(host, activate);
427 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
429 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
432 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
434 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
437 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
439 return readl(NFC_V3_ECC_STATUS_RESULT);
442 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
444 struct mxc_nand_host *host = dev_id;
446 if (!host->devtype_data->check_int(host))
449 irq_control(host, 0);
451 complete(&host->op_completion);
456 /* This function polls the NANDFC to wait for the basic operation to
457 * complete by checking the INT bit of config2 register.
459 static int wait_op_done(struct mxc_nand_host *host, int useirq)
464 * If operation is already complete, don't bother to setup an irq or a
467 if (host->devtype_data->check_int(host))
471 unsigned long timeout;
473 reinit_completion(&host->op_completion);
475 irq_control(host, 1);
477 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
478 if (!timeout && !host->devtype_data->check_int(host)) {
479 dev_dbg(host->dev, "timeout waiting for irq\n");
483 int max_retries = 8000;
489 done = host->devtype_data->check_int(host);
493 } while (--max_retries);
496 dev_dbg(host->dev, "timeout polling for completion\n");
501 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
506 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
509 writel(cmd, NFC_V3_FLASH_CMD);
511 /* send out command */
512 writel(NFC_CMD, NFC_V3_LAUNCH);
514 /* Wait for operation to complete */
515 wait_op_done(host, useirq);
518 /* This function issues the specified command to the NAND device and
519 * waits for completion. */
520 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
522 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
524 writew(cmd, NFC_V1_V2_FLASH_CMD);
525 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
527 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
528 int max_retries = 100;
529 /* Reset completion is indicated by NFC_CONFIG2 */
531 while (max_retries-- > 0) {
532 if (readw(NFC_V1_V2_CONFIG2) == 0) {
538 dev_dbg(host->dev, "%s: RESET failed\n", __func__);
540 /* Wait for operation to complete */
541 wait_op_done(host, useirq);
545 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
548 writel(addr, NFC_V3_FLASH_ADDR0);
550 /* send out address */
551 writel(NFC_ADDR, NFC_V3_LAUNCH);
553 wait_op_done(host, 0);
556 /* This function sends an address (or partial address) to the
557 * NAND device. The address is used to select the source/destination for
559 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
561 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
563 writew(addr, NFC_V1_V2_FLASH_ADDR);
564 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
566 /* Wait for operation to complete */
567 wait_op_done(host, islast);
570 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
572 struct nand_chip *nand_chip = mtd_to_nand(mtd);
573 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
576 tmp = readl(NFC_V3_CONFIG1);
578 writel(tmp, NFC_V3_CONFIG1);
580 /* transfer data from NFC ram to nand */
581 writel(ops, NFC_V3_LAUNCH);
583 wait_op_done(host, false);
586 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
588 struct nand_chip *nand_chip = mtd_to_nand(mtd);
589 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
591 /* NANDFC buffer 0 is used for page read/write */
592 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
594 writew(ops, NFC_V1_V2_CONFIG2);
596 /* Wait for operation to complete */
597 wait_op_done(host, true);
600 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
602 struct nand_chip *nand_chip = mtd_to_nand(mtd);
603 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
606 if (mtd->writesize > 512)
611 for (i = 0; i < bufs; i++) {
613 /* NANDFC buffer 0 is used for page read/write */
614 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
616 writew(ops, NFC_V1_V2_CONFIG2);
618 /* Wait for operation to complete */
619 wait_op_done(host, true);
623 static void send_read_id_v3(struct mxc_nand_host *host)
625 /* Read ID into main buffer */
626 writel(NFC_ID, NFC_V3_LAUNCH);
628 wait_op_done(host, true);
630 memcpy32_fromio(host->data_buf, host->main_area0, 16);
633 /* Request the NANDFC to perform a read of the NAND device ID. */
634 static void send_read_id_v1_v2(struct mxc_nand_host *host)
636 /* NANDFC buffer 0 is used for device ID output */
637 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
639 writew(NFC_ID, NFC_V1_V2_CONFIG2);
641 /* Wait for operation to complete */
642 wait_op_done(host, true);
644 memcpy32_fromio(host->data_buf, host->main_area0, 16);
647 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
649 writew(NFC_STATUS, NFC_V3_LAUNCH);
650 wait_op_done(host, true);
652 return readl(NFC_V3_CONFIG1) >> 16;
655 /* This function requests the NANDFC to perform a read of the
656 * NAND device status and returns the current status. */
657 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
659 void __iomem *main_buf = host->main_area0;
663 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
666 * The device status is stored in main_area0. To
667 * prevent corruption of the buffer save the value
668 * and restore it afterwards.
670 store = readl(main_buf);
672 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
673 wait_op_done(host, true);
675 ret = readw(main_buf);
677 writel(store, main_buf);
682 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
684 struct mxc_nand_host *host = nand_get_controller_data(chip);
687 if (chip->ecc.mode != NAND_ECC_HW)
690 config1 = readw(NFC_V1_V2_CONFIG1);
693 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
695 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
697 writew(config1, NFC_V1_V2_CONFIG1);
700 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
702 struct mxc_nand_host *host = nand_get_controller_data(chip);
705 if (chip->ecc.mode != NAND_ECC_HW)
708 config2 = readl(NFC_V3_CONFIG2);
711 config2 |= NFC_V3_CONFIG2_ECC_EN;
713 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
715 writel(config2, NFC_V3_CONFIG2);
718 /* This functions is used by upper layer to checks if device is ready */
719 static int mxc_nand_dev_ready(struct mtd_info *mtd)
722 * NFC handles R/B internally. Therefore, this function
723 * always returns status as ready.
728 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
731 struct mtd_info *mtd = nand_to_mtd(chip);
732 struct mxc_nand_host *host = nand_get_controller_data(chip);
733 unsigned int bitflips_corrected = 0;
737 host->devtype_data->enable_hwecc(chip, ecc);
739 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
740 mxc_do_addr_cycle(mtd, 0, page);
742 if (mtd->writesize > 512)
743 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
745 no_subpages = mtd->writesize >> 9;
747 for (i = 0; i < no_subpages; i++) {
750 /* NANDFC buffer 0 is used for page read/write */
751 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
753 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
755 /* Wait for operation to complete */
756 wait_op_done(host, true);
758 ecc_stats = get_ecc_status_v1(host);
763 switch (ecc_stats & 0x3) {
768 mtd->ecc_stats.corrected++;
769 bitflips_corrected = 1;
772 mtd->ecc_stats.failed++;
779 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
781 copy_spare(mtd, true, oob);
783 return bitflips_corrected;
786 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
787 void *oob, bool ecc, int page)
789 struct mtd_info *mtd = nand_to_mtd(chip);
790 struct mxc_nand_host *host = nand_get_controller_data(chip);
791 unsigned int max_bitflips = 0;
794 u8 ecc_bit_mask, err_limit;
796 host->devtype_data->enable_hwecc(chip, ecc);
798 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
799 mxc_do_addr_cycle(mtd, 0, page);
801 if (mtd->writesize > 512)
802 host->devtype_data->send_cmd(host,
803 NAND_CMD_READSTART, true);
805 host->devtype_data->send_page(mtd, NFC_OUTPUT);
808 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
810 copy_spare(mtd, true, oob);
812 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
813 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
815 no_subpages = mtd->writesize >> 9;
817 ecc_stat = host->devtype_data->get_ecc_status(host);
820 err = ecc_stat & ecc_bit_mask;
821 if (err > err_limit) {
822 mtd->ecc_stats.failed++;
824 mtd->ecc_stats.corrected += err;
825 max_bitflips = max_t(unsigned int, max_bitflips, err);
829 } while (--no_subpages);
834 static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
835 uint8_t *buf, int oob_required, int page)
837 struct mxc_nand_host *host = nand_get_controller_data(chip);
841 oob_buf = chip->oob_poi;
845 return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
848 static int mxc_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
849 uint8_t *buf, int oob_required, int page)
851 struct mxc_nand_host *host = nand_get_controller_data(chip);
855 oob_buf = chip->oob_poi;
859 return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
862 static int mxc_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
865 struct mxc_nand_host *host = nand_get_controller_data(chip);
867 return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
871 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
874 struct mtd_info *mtd = nand_to_mtd(chip);
875 struct mxc_nand_host *host = nand_get_controller_data(chip);
877 host->devtype_data->enable_hwecc(chip, ecc);
879 host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
880 mxc_do_addr_cycle(mtd, 0, page);
882 memcpy32_toio(host->main_area0, buf, mtd->writesize);
883 copy_spare(mtd, false, chip->oob_poi);
885 host->devtype_data->send_page(mtd, NFC_INPUT);
886 host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
887 mxc_do_addr_cycle(mtd, 0, page);
892 static int mxc_nand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
893 const uint8_t *buf, int oob_required,
896 return mxc_nand_write_page(chip, buf, true, page);
899 static int mxc_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
900 const uint8_t *buf, int oob_required, int page)
902 return mxc_nand_write_page(chip, buf, false, page);
905 static int mxc_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
908 struct mxc_nand_host *host = nand_get_controller_data(chip);
910 memset(host->data_buf, 0xff, mtd->writesize);
912 return mxc_nand_write_page(chip, host->data_buf, false, page);
915 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
917 struct nand_chip *nand_chip = mtd_to_nand(mtd);
918 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
921 /* Check for status request */
922 if (host->status_request)
923 return host->devtype_data->get_dev_status(host) & 0xFF;
925 if (nand_chip->options & NAND_BUSWIDTH_16) {
926 /* only take the lower byte of each word */
927 ret = *(uint16_t *)(host->data_buf + host->buf_start);
929 host->buf_start += 2;
931 ret = *(uint8_t *)(host->data_buf + host->buf_start);
935 dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
939 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
941 struct nand_chip *nand_chip = mtd_to_nand(mtd);
942 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
945 ret = *(uint16_t *)(host->data_buf + host->buf_start);
946 host->buf_start += 2;
951 /* Write data of length len to buffer buf. The data to be
952 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
953 * Operation by the NFC, the data is written to NAND Flash */
954 static void mxc_nand_write_buf(struct mtd_info *mtd,
955 const u_char *buf, int len)
957 struct nand_chip *nand_chip = mtd_to_nand(mtd);
958 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
959 u16 col = host->buf_start;
960 int n = mtd->oobsize + mtd->writesize - col;
964 memcpy(host->data_buf + col, buf, n);
966 host->buf_start += n;
969 /* Read the data buffer from the NAND Flash. To read the data from NAND
970 * Flash first the data output cycle is initiated by the NFC, which copies
971 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
973 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
975 struct nand_chip *nand_chip = mtd_to_nand(mtd);
976 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
977 u16 col = host->buf_start;
978 int n = mtd->oobsize + mtd->writesize - col;
982 memcpy(buf, host->data_buf + col, n);
984 host->buf_start += n;
987 /* This function is used by upper layer for select and
988 * deselect of the NAND chip */
989 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
991 struct nand_chip *nand_chip = mtd_to_nand(mtd);
992 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
995 /* Disable the NFC clock */
997 clk_disable_unprepare(host->clk);
1003 if (!host->clk_act) {
1004 /* Enable the NFC clock */
1005 clk_prepare_enable(host->clk);
1010 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
1012 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1013 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1016 /* Disable the NFC clock */
1017 if (host->clk_act) {
1018 clk_disable_unprepare(host->clk);
1024 if (!host->clk_act) {
1025 /* Enable the NFC clock */
1026 clk_prepare_enable(host->clk);
1030 host->active_cs = chip;
1031 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
1034 #define MXC_V1_ECCBYTES 5
1036 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1037 struct mtd_oob_region *oobregion)
1039 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1041 if (section >= nand_chip->ecc.steps)
1044 oobregion->offset = (section * 16) + 6;
1045 oobregion->length = MXC_V1_ECCBYTES;
1050 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1051 struct mtd_oob_region *oobregion)
1053 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1055 if (section > nand_chip->ecc.steps)
1059 if (mtd->writesize <= 512) {
1060 oobregion->offset = 0;
1061 oobregion->length = 5;
1063 oobregion->offset = 2;
1064 oobregion->length = 4;
1067 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1068 if (section < nand_chip->ecc.steps)
1069 oobregion->length = (section * 16) + 6 -
1072 oobregion->length = mtd->oobsize - oobregion->offset;
1078 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1079 .ecc = mxc_v1_ooblayout_ecc,
1080 .free = mxc_v1_ooblayout_free,
1083 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1084 struct mtd_oob_region *oobregion)
1086 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1089 if (section >= nand_chip->ecc.steps)
1092 oobregion->offset = (section * stepsize) + 7;
1093 oobregion->length = nand_chip->ecc.bytes;
1098 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1099 struct mtd_oob_region *oobregion)
1101 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1102 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1104 if (section >= nand_chip->ecc.steps)
1108 if (mtd->writesize <= 512) {
1109 oobregion->offset = 0;
1110 oobregion->length = 5;
1112 oobregion->offset = 2;
1113 oobregion->length = 4;
1116 oobregion->offset = section * stepsize;
1117 oobregion->length = 7;
1123 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1124 .ecc = mxc_v2_ooblayout_ecc,
1125 .free = mxc_v2_ooblayout_free,
1129 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1130 * on how much oob the nand chip has. For 8bit ecc we need at least
1131 * 26 bytes of oob data per 512 byte block.
1133 static int get_eccsize(struct mtd_info *mtd)
1135 int oobbytes_per_512 = 0;
1137 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1139 if (oobbytes_per_512 < 26)
1145 static void preset_v1(struct mtd_info *mtd)
1147 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1148 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1149 uint16_t config1 = 0;
1151 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
1152 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1154 if (!host->devtype_data->irqpending_quirk)
1155 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1159 writew(config1, NFC_V1_V2_CONFIG1);
1160 /* preset operation */
1162 /* Unlock the internal RAM Buffer */
1163 writew(0x2, NFC_V1_V2_CONFIG);
1165 /* Blocks to be unlocked */
1166 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1167 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1169 /* Unlock Block Command for given address range */
1170 writew(0x4, NFC_V1_V2_WRPROT);
1173 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
1174 const struct nand_data_interface *conf)
1176 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1177 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1178 int tRC_min_ns, tRC_ps, ret;
1179 unsigned long rate, rate_round;
1180 const struct nand_sdr_timings *timings;
1183 timings = nand_get_sdr_timings(conf);
1184 if (IS_ERR(timings))
1187 config1 = readw(NFC_V1_V2_CONFIG1);
1189 tRC_min_ns = timings->tRC_min / 1000;
1190 rate = 1000000000 / tRC_min_ns;
1193 * For tRC < 30ns we have to use EDO mode. In this case the controller
1194 * does one access per clock cycle. Otherwise the controller does one
1195 * access in two clock cycles, thus we have to double the rate to the
1198 if (tRC_min_ns < 30) {
1199 rate_round = clk_round_rate(host->clk, rate);
1200 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1201 tRC_ps = 1000000000 / (rate_round / 1000);
1204 rate_round = clk_round_rate(host->clk, rate);
1205 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1206 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1210 * The timing values compared against are from the i.MX25 Automotive
1211 * datasheet, Table 50. NFC Timing Parameters
1213 if (timings->tCLS_min > tRC_ps - 1000 ||
1214 timings->tCLH_min > tRC_ps - 2000 ||
1215 timings->tCS_min > tRC_ps - 1000 ||
1216 timings->tCH_min > tRC_ps - 2000 ||
1217 timings->tWP_min > tRC_ps - 1500 ||
1218 timings->tALS_min > tRC_ps ||
1219 timings->tALH_min > tRC_ps - 3000 ||
1220 timings->tDS_min > tRC_ps ||
1221 timings->tDH_min > tRC_ps - 5000 ||
1222 timings->tWC_min > 2 * tRC_ps ||
1223 timings->tWH_min > tRC_ps - 2500 ||
1224 timings->tRR_min > 6 * tRC_ps ||
1225 timings->tRP_min > 3 * tRC_ps / 2 ||
1226 timings->tRC_min > 2 * tRC_ps ||
1227 timings->tREH_min > (tRC_ps / 2) - 2500) {
1228 dev_dbg(host->dev, "Timing out of bounds\n");
1232 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1235 ret = clk_set_rate(host->clk, rate);
1239 writew(config1, NFC_V1_V2_CONFIG1);
1241 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1242 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1248 static void preset_v2(struct mtd_info *mtd)
1250 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1251 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1252 uint16_t config1 = 0;
1254 config1 |= NFC_V2_CONFIG1_FP_INT;
1256 if (!host->devtype_data->irqpending_quirk)
1257 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1259 if (mtd->writesize) {
1260 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1262 if (nand_chip->ecc.mode == NAND_ECC_HW)
1263 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1265 host->eccsize = get_eccsize(mtd);
1266 if (host->eccsize == 4)
1267 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1269 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1274 writew(config1, NFC_V1_V2_CONFIG1);
1275 /* preset operation */
1277 /* spare area size in 16-bit half-words */
1278 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1280 /* Unlock the internal RAM Buffer */
1281 writew(0x2, NFC_V1_V2_CONFIG);
1283 /* Blocks to be unlocked */
1284 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1285 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1286 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1287 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1288 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1289 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1290 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1291 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1293 /* Unlock Block Command for given address range */
1294 writew(0x4, NFC_V1_V2_WRPROT);
1297 static void preset_v3(struct mtd_info *mtd)
1299 struct nand_chip *chip = mtd_to_nand(mtd);
1300 struct mxc_nand_host *host = nand_get_controller_data(chip);
1301 uint32_t config2, config3;
1304 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1305 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1307 /* Unlock the internal RAM Buffer */
1308 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1311 /* Blocks to be unlocked */
1312 for (i = 0; i < NAND_MAX_CHIPS; i++)
1313 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1315 writel(0, NFC_V3_IPC);
1317 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1318 NFC_V3_CONFIG2_2CMD_PHASES |
1319 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1320 NFC_V3_CONFIG2_ST_CMD(0x70) |
1321 NFC_V3_CONFIG2_INT_MSK |
1322 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1324 addr_phases = fls(chip->pagemask) >> 3;
1326 if (mtd->writesize == 2048) {
1327 config2 |= NFC_V3_CONFIG2_PS_2048;
1328 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1329 } else if (mtd->writesize == 4096) {
1330 config2 |= NFC_V3_CONFIG2_PS_4096;
1331 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1333 config2 |= NFC_V3_CONFIG2_PS_512;
1334 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1337 if (mtd->writesize) {
1338 if (chip->ecc.mode == NAND_ECC_HW)
1339 config2 |= NFC_V3_CONFIG2_ECC_EN;
1341 config2 |= NFC_V3_CONFIG2_PPB(
1342 ffs(mtd->erasesize / mtd->writesize) - 6,
1343 host->devtype_data->ppb_shift);
1344 host->eccsize = get_eccsize(mtd);
1345 if (host->eccsize == 8)
1346 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1349 writel(config2, NFC_V3_CONFIG2);
1351 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1352 NFC_V3_CONFIG3_NO_SDMA |
1353 NFC_V3_CONFIG3_RBB_MODE |
1354 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1355 NFC_V3_CONFIG3_ADD_OP(0);
1357 if (!(chip->options & NAND_BUSWIDTH_16))
1358 config3 |= NFC_V3_CONFIG3_FW8;
1360 writel(config3, NFC_V3_CONFIG3);
1362 writel(0, NFC_V3_DELAY_LINE);
1365 /* Used by the upper layer to write command to NAND Flash for
1366 * different operations to be carried out on NAND Flash */
1367 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1368 int column, int page_addr)
1370 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1371 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1373 dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1374 command, column, page_addr);
1376 /* Reset command state information */
1377 host->status_request = false;
1379 /* Command pre-processing step */
1381 case NAND_CMD_RESET:
1382 host->devtype_data->preset(mtd);
1383 host->devtype_data->send_cmd(host, command, false);
1386 case NAND_CMD_STATUS:
1387 host->buf_start = 0;
1388 host->status_request = true;
1390 host->devtype_data->send_cmd(host, command, true);
1391 WARN_ONCE(column != -1 || page_addr != -1,
1392 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1393 command, column, page_addr);
1394 mxc_do_addr_cycle(mtd, column, page_addr);
1397 case NAND_CMD_READID:
1398 host->devtype_data->send_cmd(host, command, true);
1399 mxc_do_addr_cycle(mtd, column, page_addr);
1400 host->devtype_data->send_read_id(host);
1401 host->buf_start = 0;
1404 case NAND_CMD_ERASE1:
1405 case NAND_CMD_ERASE2:
1406 host->devtype_data->send_cmd(host, command, false);
1407 WARN_ONCE(column != -1,
1408 "Unexpected column value (cmd=%u, col=%d)\n",
1410 mxc_do_addr_cycle(mtd, column, page_addr);
1413 case NAND_CMD_PARAM:
1414 host->devtype_data->send_cmd(host, command, false);
1415 mxc_do_addr_cycle(mtd, column, page_addr);
1416 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1417 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1418 host->buf_start = 0;
1421 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1427 static int mxc_nand_set_features(struct mtd_info *mtd, struct nand_chip *chip,
1428 int addr, u8 *subfeature_param)
1430 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1431 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1434 host->buf_start = 0;
1436 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1437 chip->write_byte(mtd, subfeature_param[i]);
1439 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1440 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1441 mxc_do_addr_cycle(mtd, addr, -1);
1442 host->devtype_data->send_page(mtd, NFC_INPUT);
1447 static int mxc_nand_get_features(struct mtd_info *mtd, struct nand_chip *chip,
1448 int addr, u8 *subfeature_param)
1450 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1451 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1454 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1455 mxc_do_addr_cycle(mtd, addr, -1);
1456 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1457 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1458 host->buf_start = 0;
1460 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1461 *subfeature_param++ = chip->read_byte(mtd);
1467 * The generic flash bbt decriptors overlap with our ecc
1468 * hardware, so define some i.MX specific ones.
1470 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1471 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1473 static struct nand_bbt_descr bbt_main_descr = {
1474 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1475 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1480 .pattern = bbt_pattern,
1483 static struct nand_bbt_descr bbt_mirror_descr = {
1484 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1485 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1490 .pattern = mirror_pattern,
1493 /* v1 + irqpending_quirk: i.MX21 */
1494 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1495 .preset = preset_v1,
1496 .read_page = mxc_nand_read_page_v1,
1497 .send_cmd = send_cmd_v1_v2,
1498 .send_addr = send_addr_v1_v2,
1499 .send_page = send_page_v1,
1500 .send_read_id = send_read_id_v1_v2,
1501 .get_dev_status = get_dev_status_v1_v2,
1502 .check_int = check_int_v1_v2,
1503 .irq_control = irq_control_v1_v2,
1504 .get_ecc_status = get_ecc_status_v1,
1505 .ooblayout = &mxc_v1_ooblayout_ops,
1506 .select_chip = mxc_nand_select_chip_v1_v3,
1507 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1508 .irqpending_quirk = 1,
1510 .regs_offset = 0xe00,
1511 .spare0_offset = 0x800,
1517 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1518 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1519 .preset = preset_v1,
1520 .read_page = mxc_nand_read_page_v1,
1521 .send_cmd = send_cmd_v1_v2,
1522 .send_addr = send_addr_v1_v2,
1523 .send_page = send_page_v1,
1524 .send_read_id = send_read_id_v1_v2,
1525 .get_dev_status = get_dev_status_v1_v2,
1526 .check_int = check_int_v1_v2,
1527 .irq_control = irq_control_v1_v2,
1528 .get_ecc_status = get_ecc_status_v1,
1529 .ooblayout = &mxc_v1_ooblayout_ops,
1530 .select_chip = mxc_nand_select_chip_v1_v3,
1531 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1532 .irqpending_quirk = 0,
1534 .regs_offset = 0xe00,
1535 .spare0_offset = 0x800,
1542 /* v21: i.MX25, i.MX35 */
1543 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1544 .preset = preset_v2,
1545 .read_page = mxc_nand_read_page_v2_v3,
1546 .send_cmd = send_cmd_v1_v2,
1547 .send_addr = send_addr_v1_v2,
1548 .send_page = send_page_v2,
1549 .send_read_id = send_read_id_v1_v2,
1550 .get_dev_status = get_dev_status_v1_v2,
1551 .check_int = check_int_v1_v2,
1552 .irq_control = irq_control_v1_v2,
1553 .get_ecc_status = get_ecc_status_v2,
1554 .ooblayout = &mxc_v2_ooblayout_ops,
1555 .select_chip = mxc_nand_select_chip_v2,
1556 .setup_data_interface = mxc_nand_v2_setup_data_interface,
1557 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1558 .irqpending_quirk = 0,
1560 .regs_offset = 0x1e00,
1561 .spare0_offset = 0x1000,
1569 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1570 .preset = preset_v3,
1571 .read_page = mxc_nand_read_page_v2_v3,
1572 .send_cmd = send_cmd_v3,
1573 .send_addr = send_addr_v3,
1574 .send_page = send_page_v3,
1575 .send_read_id = send_read_id_v3,
1576 .get_dev_status = get_dev_status_v3,
1577 .check_int = check_int_v3,
1578 .irq_control = irq_control_v3,
1579 .get_ecc_status = get_ecc_status_v3,
1580 .ooblayout = &mxc_v2_ooblayout_ops,
1581 .select_chip = mxc_nand_select_chip_v1_v3,
1582 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1583 .irqpending_quirk = 0,
1586 .spare0_offset = 0x1000,
1587 .axi_offset = 0x1e00,
1595 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1596 .preset = preset_v3,
1597 .read_page = mxc_nand_read_page_v2_v3,
1598 .send_cmd = send_cmd_v3,
1599 .send_addr = send_addr_v3,
1600 .send_page = send_page_v3,
1601 .send_read_id = send_read_id_v3,
1602 .get_dev_status = get_dev_status_v3,
1603 .check_int = check_int_v3,
1604 .irq_control = irq_control_v3,
1605 .get_ecc_status = get_ecc_status_v3,
1606 .ooblayout = &mxc_v2_ooblayout_ops,
1607 .select_chip = mxc_nand_select_chip_v1_v3,
1608 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1609 .irqpending_quirk = 0,
1612 .spare0_offset = 0x1000,
1613 .axi_offset = 0x1e00,
1620 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1622 return host->devtype_data == &imx21_nand_devtype_data;
1625 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1627 return host->devtype_data == &imx27_nand_devtype_data;
1630 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1632 return host->devtype_data == &imx25_nand_devtype_data;
1635 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1637 return host->devtype_data == &imx51_nand_devtype_data;
1640 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1642 return host->devtype_data == &imx53_nand_devtype_data;
1645 static const struct platform_device_id mxcnd_devtype[] = {
1647 .name = "imx21-nand",
1648 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1650 .name = "imx27-nand",
1651 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1653 .name = "imx25-nand",
1654 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1656 .name = "imx51-nand",
1657 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1659 .name = "imx53-nand",
1660 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1665 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1668 static const struct of_device_id mxcnd_dt_ids[] = {
1670 .compatible = "fsl,imx21-nand",
1671 .data = &imx21_nand_devtype_data,
1673 .compatible = "fsl,imx27-nand",
1674 .data = &imx27_nand_devtype_data,
1676 .compatible = "fsl,imx25-nand",
1677 .data = &imx25_nand_devtype_data,
1679 .compatible = "fsl,imx51-nand",
1680 .data = &imx51_nand_devtype_data,
1682 .compatible = "fsl,imx53-nand",
1683 .data = &imx53_nand_devtype_data,
1687 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1689 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1691 struct device_node *np = host->dev->of_node;
1692 const struct of_device_id *of_id =
1693 of_match_device(mxcnd_dt_ids, host->dev);
1698 host->devtype_data = of_id->data;
1703 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1709 static int mxcnd_probe(struct platform_device *pdev)
1711 struct nand_chip *this;
1712 struct mtd_info *mtd;
1713 struct mxc_nand_host *host;
1714 struct resource *res;
1717 /* Allocate memory for MTD device structure and private data */
1718 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1723 /* allocate a temporary buffer for the nand_scan_ident() */
1724 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1725 if (!host->data_buf)
1728 host->dev = &pdev->dev;
1729 /* structures must be linked */
1731 mtd = nand_to_mtd(this);
1732 mtd->dev.parent = &pdev->dev;
1733 mtd->name = DRIVER_NAME;
1735 /* 50 us command delay time */
1736 this->chip_delay = 5;
1738 nand_set_controller_data(this, host);
1739 nand_set_flash_node(this, pdev->dev.of_node),
1740 this->dev_ready = mxc_nand_dev_ready;
1741 this->cmdfunc = mxc_nand_command;
1742 this->read_byte = mxc_nand_read_byte;
1743 this->read_word = mxc_nand_read_word;
1744 this->write_buf = mxc_nand_write_buf;
1745 this->read_buf = mxc_nand_read_buf;
1746 this->set_features = mxc_nand_set_features;
1747 this->get_features = mxc_nand_get_features;
1749 host->clk = devm_clk_get(&pdev->dev, NULL);
1750 if (IS_ERR(host->clk))
1751 return PTR_ERR(host->clk);
1753 err = mxcnd_probe_dt(host);
1755 struct mxc_nand_platform_data *pdata =
1756 dev_get_platdata(&pdev->dev);
1758 host->pdata = *pdata;
1759 host->devtype_data = (struct mxc_nand_devtype_data *)
1760 pdev->id_entry->driver_data;
1768 this->setup_data_interface = host->devtype_data->setup_data_interface;
1770 if (host->devtype_data->needs_ip) {
1771 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1772 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1773 if (IS_ERR(host->regs_ip))
1774 return PTR_ERR(host->regs_ip);
1776 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1778 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1781 host->base = devm_ioremap_resource(&pdev->dev, res);
1782 if (IS_ERR(host->base))
1783 return PTR_ERR(host->base);
1785 host->main_area0 = host->base;
1787 if (host->devtype_data->regs_offset)
1788 host->regs = host->base + host->devtype_data->regs_offset;
1789 host->spare0 = host->base + host->devtype_data->spare0_offset;
1790 if (host->devtype_data->axi_offset)
1791 host->regs_axi = host->base + host->devtype_data->axi_offset;
1793 this->ecc.bytes = host->devtype_data->eccbytes;
1794 host->eccsize = host->devtype_data->eccsize;
1796 this->select_chip = host->devtype_data->select_chip;
1797 this->ecc.size = 512;
1798 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1800 if (host->pdata.hw_ecc) {
1801 this->ecc.mode = NAND_ECC_HW;
1803 this->ecc.mode = NAND_ECC_SOFT;
1804 this->ecc.algo = NAND_ECC_HAMMING;
1807 /* NAND bus width determines access functions used by upper layer */
1808 if (host->pdata.width == 2)
1809 this->options |= NAND_BUSWIDTH_16;
1811 /* update flash based bbt */
1812 if (host->pdata.flash_bbt)
1813 this->bbt_options |= NAND_BBT_USE_FLASH;
1815 init_completion(&host->op_completion);
1817 host->irq = platform_get_irq(pdev, 0);
1822 * Use host->devtype_data->irq_control() here instead of irq_control()
1823 * because we must not disable_irq_nosync without having requested the
1826 host->devtype_data->irq_control(host, 0);
1828 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1829 0, DRIVER_NAME, host);
1833 err = clk_prepare_enable(host->clk);
1839 * Now that we "own" the interrupt make sure the interrupt mask bit is
1840 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1843 if (host->devtype_data->irqpending_quirk) {
1844 disable_irq_nosync(host->irq);
1845 host->devtype_data->irq_control(host, 1);
1848 /* first scan to find the device and get the page size */
1849 err = nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL);
1853 switch (this->ecc.mode) {
1855 this->ecc.read_page = mxc_nand_read_page;
1856 this->ecc.read_page_raw = mxc_nand_read_page_raw;
1857 this->ecc.read_oob = mxc_nand_read_oob;
1858 this->ecc.write_page = mxc_nand_write_page_ecc;
1859 this->ecc.write_page_raw = mxc_nand_write_page_raw;
1860 this->ecc.write_oob = mxc_nand_write_oob;
1871 if (this->bbt_options & NAND_BBT_USE_FLASH) {
1872 this->bbt_td = &bbt_main_descr;
1873 this->bbt_md = &bbt_mirror_descr;
1876 /* allocate the right size buffer now */
1877 devm_kfree(&pdev->dev, (void *)host->data_buf);
1878 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1880 if (!host->data_buf) {
1885 /* Call preset again, with correct writesize this time */
1886 host->devtype_data->preset(mtd);
1888 if (!this->ecc.bytes) {
1889 if (host->eccsize == 8)
1890 this->ecc.bytes = 18;
1891 else if (host->eccsize == 4)
1892 this->ecc.bytes = 9;
1896 * Experimentation shows that i.MX NFC can only handle up to 218 oob
1897 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1898 * into copying invalid data to/from the spare IO buffer, as this
1899 * might cause ECC data corruption when doing sub-page write to a
1900 * partially written page.
1902 host->used_oobsize = min(mtd->oobsize, 218U);
1904 if (this->ecc.mode == NAND_ECC_HW) {
1905 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1906 this->ecc.strength = 1;
1908 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1911 /* second phase scan */
1912 err = nand_scan_tail(mtd);
1916 /* Register the partitions */
1917 err = mtd_device_parse_register(mtd, part_probes, NULL,
1919 host->pdata.nr_parts);
1923 platform_set_drvdata(pdev, host);
1931 clk_disable_unprepare(host->clk);
1936 static int mxcnd_remove(struct platform_device *pdev)
1938 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1940 nand_release(nand_to_mtd(&host->nand));
1942 clk_disable_unprepare(host->clk);
1947 static struct platform_driver mxcnd_driver = {
1949 .name = DRIVER_NAME,
1950 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1952 .id_table = mxcnd_devtype,
1953 .probe = mxcnd_probe,
1954 .remove = mxcnd_remove,
1956 module_platform_driver(mxcnd_driver);
1958 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1959 MODULE_DESCRIPTION("MXC NAND MTD driver");
1960 MODULE_LICENSE("GPL");