1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Amlogic Meson Nand Flash Controller Driver
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Liang Yang <liang.yang@amlogic.com>
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/iopoll.h>
22 #include <linux/sched/task_stack.h>
24 #define NFC_REG_CMD 0x00
25 #define NFC_CMD_IDLE (0xc << 14)
26 #define NFC_CMD_CLE (0x5 << 14)
27 #define NFC_CMD_ALE (0x6 << 14)
28 #define NFC_CMD_ADL ((0 << 16) | (3 << 20))
29 #define NFC_CMD_ADH ((1 << 16) | (3 << 20))
30 #define NFC_CMD_AIL ((2 << 16) | (3 << 20))
31 #define NFC_CMD_AIH ((3 << 16) | (3 << 20))
32 #define NFC_CMD_SEED ((8 << 16) | (3 << 20))
33 #define NFC_CMD_M2N ((0 << 17) | (2 << 20))
34 #define NFC_CMD_N2M ((1 << 17) | (2 << 20))
35 #define NFC_CMD_RB BIT(20)
36 #define NFC_CMD_SCRAMBLER_ENABLE BIT(19)
37 #define NFC_CMD_SCRAMBLER_DISABLE 0
38 #define NFC_CMD_SHORTMODE_DISABLE 0
39 #define NFC_CMD_RB_INT BIT(14)
40 #define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16))
42 #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))
44 #define NFC_REG_CFG 0x04
45 #define NFC_REG_DADR 0x08
46 #define NFC_REG_IADR 0x0c
47 #define NFC_REG_BUF 0x10
48 #define NFC_REG_INFO 0x14
49 #define NFC_REG_DC 0x18
50 #define NFC_REG_ADR 0x1c
51 #define NFC_REG_DL 0x20
52 #define NFC_REG_DH 0x24
53 #define NFC_REG_CADR 0x28
54 #define NFC_REG_SADR 0x2c
55 #define NFC_REG_PINS 0x30
56 #define NFC_REG_VER 0x38
58 #define NFC_RB_IRQ_EN BIT(21)
60 #define CLK_DIV_SHIFT 0
61 #define CLK_DIV_WIDTH 6
63 #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \
68 ((short_mode) << 13) | \
69 (((page_size) & 0x7f) << 6) | \
73 #define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff))
74 #define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff))
75 #define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff))
76 #define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff))
78 #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
79 #define DMA_ADDR_ALIGN 8
81 #define ECC_CHECK_RETURN_FF (-1)
83 #define NAND_CE0 (0xe << 10)
84 #define NAND_CE1 (0xd << 10)
86 #define DMA_BUSY_TIMEOUT 0x100000
87 #define CMD_FIFO_EMPTY_TIMEOUT 1000
91 /* eMMC clock register, misc control */
92 #define CLK_SELECT_NAND BIT(31)
94 #define NFC_CLK_CYCLE 6
96 /* nand flash controller delay 3 ns */
97 #define NFC_DEFAULT_DELAY 3000
99 #define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff)
100 #define MAX_CYCLE_ADDRS 5
104 #define ECC_PARITY_BCH8_512B 14
105 #define ECC_COMPLETE BIT(31)
106 #define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0))
107 #define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0))
108 #define ECC_UNCORRECTABLE 0x3f
110 #define PER_INFO_BYTE 8
112 #define NFC_CMD_RAW_LEN GENMASK(13, 0)
114 #define NFC_COLUMN_ADDR_0 0
115 #define NFC_COLUMN_ADDR_1 0
117 struct meson_nfc_nand_chip {
118 struct list_head node;
119 struct nand_chip nand;
120 unsigned long clk_rate;
121 unsigned long level1_divider;
131 u8 sels[] __counted_by(nsels);
134 struct meson_nand_ecc {
140 struct meson_nfc_data {
141 const struct nand_ecc_caps *ecc_caps;
144 struct meson_nfc_param {
151 u32 addrs[MAX_CYCLE_ADDRS];
162 struct nand_controller controller;
163 struct clk *core_clk;
164 struct clk *device_clk;
165 struct clk *nand_clk;
166 struct clk_divider nand_divider;
168 unsigned long clk_rate;
172 void __iomem *reg_base;
173 void __iomem *reg_clk;
174 struct completion completion;
175 struct list_head chips;
176 const struct meson_nfc_data *data;
177 struct meson_nfc_param param;
178 struct nand_timing timing;
181 struct nand_rw_cmd rw;
188 unsigned long assigned_cs;
193 NFC_ECC_BCH8_512 = 1,
202 #define MESON_ECC_DATA(b, s, sz) { .bch = (b), .strength = (s), .size = (sz) }
204 static struct meson_nand_ecc meson_ecc[] = {
205 MESON_ECC_DATA(NFC_ECC_BCH8_512, 8, 512),
206 MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8, 1024),
207 MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24, 1024),
208 MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30, 1024),
209 MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40, 1024),
210 MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50, 1024),
211 MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60, 1024),
214 static int meson_nand_calc_ecc_bytes(int step_size, int strength)
218 if (step_size == 512 && strength == 8)
219 return ECC_PARITY_BCH8_512B;
221 ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8);
222 ecc_bytes = ALIGN(ecc_bytes, 2);
227 NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps,
228 meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60);
230 static const int axg_stepinfo_strengths[] = { 8 };
232 static const struct nand_ecc_step_info axg_stepinfo[] = {
235 .strengths = axg_stepinfo_strengths,
236 .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths)
240 .strengths = axg_stepinfo_strengths,
241 .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths)
245 static const struct nand_ecc_caps meson_axg_ecc_caps = {
246 .stepinfos = axg_stepinfo,
247 .nstepinfos = ARRAY_SIZE(axg_stepinfo),
248 .calc_ecc_bytes = meson_nand_calc_ecc_bytes,
251 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand)
253 return container_of(nand, struct meson_nfc_nand_chip, nand);
256 static void meson_nfc_select_chip(struct nand_chip *nand, int chip)
258 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
259 struct meson_nfc *nfc = nand_get_controller_data(nand);
262 if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
265 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
266 nfc->param.rb_select = nfc->param.chip_select;
267 nfc->timing.twb = meson_chip->twb;
268 nfc->timing.tadl = meson_chip->tadl;
269 nfc->timing.tbers_max = meson_chip->tbers_max;
271 if (nfc->clk_rate != meson_chip->clk_rate) {
272 ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate);
274 dev_err(nfc->dev, "failed to set clock rate\n");
277 nfc->clk_rate = meson_chip->clk_rate;
279 if (nfc->bus_timing != meson_chip->bus_timing) {
280 value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
281 writel(value, nfc->reg_base + NFC_REG_CFG);
282 writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
283 nfc->bus_timing = meson_chip->bus_timing;
287 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
289 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
290 nfc->reg_base + NFC_REG_CMD);
293 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
295 writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
296 nfc->reg_base + NFC_REG_CMD);
299 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
302 struct mtd_info *mtd = nand_to_mtd(nand);
303 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
304 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
305 u32 bch = meson_chip->bch_mode, cmd;
306 int len = mtd->writesize, pagesize, pages;
308 pagesize = nand->ecc.size;
311 len = mtd->writesize + mtd->oobsize;
312 cmd = len | scrambler | DMA_DIR(dir);
313 writel(cmd, nfc->reg_base + NFC_REG_CMD);
317 pages = len / nand->ecc.size;
319 cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
320 NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
322 writel(cmd, nfc->reg_base + NFC_REG_CMD);
325 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
328 * Insert two commands to make sure all valid commands are finished.
330 * The Nand flash controller is designed as two stages pipleline -
331 * a) fetch and b) excute.
332 * There might be cases when the driver see command queue is empty,
333 * but the Nand flash controller still has two commands buffered,
334 * one is fetched into NFC request queue (ready to run), and another
335 * is actively executing. So pushing 2 "IDLE" commands guarantees that
336 * the pipeline is emptied.
338 meson_nfc_cmd_idle(nfc, 0);
339 meson_nfc_cmd_idle(nfc, 0);
342 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
343 unsigned int timeout_ms)
348 /* wait cmd fifo is empty */
349 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
350 !NFC_CMD_GET_SIZE(cmd_size),
351 10, timeout_ms * 1000);
353 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
358 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
360 meson_nfc_drain_cmd(nfc);
362 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
365 static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i)
367 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
370 len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i;
372 return meson_chip->data_buf + len;
375 static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i)
377 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
380 temp = nand->ecc.size + nand->ecc.bytes;
381 len = (temp + 2) * i;
383 return meson_chip->data_buf + len;
386 static void meson_nfc_get_data_oob(struct nand_chip *nand,
392 oob_len = nand->ecc.bytes + 2;
393 for (i = 0; i < nand->ecc.steps; i++) {
395 dsrc = meson_nfc_data_ptr(nand, i);
396 memcpy(buf, dsrc, nand->ecc.size);
397 buf += nand->ecc.size;
399 osrc = meson_nfc_oob_ptr(nand, i);
400 memcpy(oobbuf, osrc, oob_len);
405 static void meson_nfc_set_data_oob(struct nand_chip *nand,
406 const u8 *buf, u8 *oobbuf)
411 oob_len = nand->ecc.bytes + 2;
412 for (i = 0; i < nand->ecc.steps; i++) {
414 dsrc = meson_nfc_data_ptr(nand, i);
415 memcpy(dsrc, buf, nand->ecc.size);
416 buf += nand->ecc.size;
418 osrc = meson_nfc_oob_ptr(nand, i);
419 memcpy(osrc, oobbuf, oob_len);
424 static int meson_nfc_wait_no_rb_pin(struct nand_chip *nand, int timeout_ms,
427 struct meson_nfc *nfc = nand_get_controller_data(nand);
430 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
431 meson_nfc_drain_cmd(nfc);
432 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
434 cfg = readl(nfc->reg_base + NFC_REG_CFG);
435 cfg |= NFC_RB_IRQ_EN;
436 writel(cfg, nfc->reg_base + NFC_REG_CFG);
438 reinit_completion(&nfc->completion);
439 nand_status_op(nand, NULL);
441 /* use the max erase time as the maximum clock for waiting R/B */
442 cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max;
443 writel(cmd, nfc->reg_base + NFC_REG_CMD);
445 if (!wait_for_completion_timeout(&nfc->completion,
446 msecs_to_jiffies(timeout_ms)))
450 nand_exit_status_op(nand);
455 static int meson_nfc_wait_rb_pin(struct meson_nfc *nfc, int timeout_ms)
460 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
461 meson_nfc_drain_cmd(nfc);
462 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
464 cfg = readl(nfc->reg_base + NFC_REG_CFG);
465 cfg |= NFC_RB_IRQ_EN;
466 writel(cfg, nfc->reg_base + NFC_REG_CFG);
468 reinit_completion(&nfc->completion);
470 /* use the max erase time as the maximum clock for waiting R/B */
471 cmd = NFC_CMD_RB | NFC_CMD_RB_INT
472 | nfc->param.chip_select | nfc->timing.tbers_max;
473 writel(cmd, nfc->reg_base + NFC_REG_CMD);
475 ret = wait_for_completion_timeout(&nfc->completion,
476 msecs_to_jiffies(timeout_ms));
483 static int meson_nfc_queue_rb(struct nand_chip *nand, int timeout_ms,
486 struct meson_nfc *nfc = nand_get_controller_data(nand);
488 if (nfc->no_rb_pin) {
489 /* This mode is used when there is no wired R/B pin.
490 * It works like 'nand_soft_waitrdy()', but instead of
491 * polling NAND_CMD_STATUS bit in the software loop,
492 * it will wait for interrupt - controllers checks IO
493 * bus and when it detects NAND_CMD_STATUS on it, it
494 * raises interrupt. After interrupt, NAND_CMD_READ0 is
495 * sent as terminator of the ready waiting procedure if
496 * needed (for all cases except page programming - this
497 * is reason of 'need_cmd_read0' flag).
499 return meson_nfc_wait_no_rb_pin(nand, timeout_ms,
502 return meson_nfc_wait_rb_pin(nfc, timeout_ms);
506 static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
508 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
512 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
513 info = &meson_chip->info_buf[i];
514 *info |= oob_buf[count];
515 *info |= oob_buf[count + 1] << 8;
519 static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)
521 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
525 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
526 info = &meson_chip->info_buf[i];
527 oob_buf[count] = *info;
528 oob_buf[count + 1] = *info >> 8;
532 static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
535 struct mtd_info *mtd = nand_to_mtd(nand);
536 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
540 for (i = 0; i < nand->ecc.steps; i++) {
541 info = &meson_chip->info_buf[i];
542 if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
543 mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
544 *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
545 *correct_bitmap |= BIT_ULL(i);
548 if ((nand->options & NAND_NEED_SCRAMBLING) &&
549 ECC_ZERO_CNT(*info) < nand->ecc.strength) {
550 mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info);
551 *bitflips = max_t(u32, *bitflips,
552 ECC_ZERO_CNT(*info));
553 ret = ECC_CHECK_RETURN_FF;
561 static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf,
562 int datalen, void *infobuf, int infolen,
563 enum dma_data_direction dir)
565 struct meson_nfc *nfc = nand_get_controller_data(nand);
569 nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
570 ret = dma_mapping_error(nfc->dev, nfc->daddr);
572 dev_err(nfc->dev, "DMA mapping error\n");
575 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
576 writel(cmd, nfc->reg_base + NFC_REG_CMD);
578 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
579 writel(cmd, nfc->reg_base + NFC_REG_CMD);
582 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
583 ret = dma_mapping_error(nfc->dev, nfc->iaddr);
585 dev_err(nfc->dev, "DMA mapping error\n");
586 dma_unmap_single(nfc->dev,
587 nfc->daddr, datalen, dir);
590 nfc->info_bytes = infolen;
591 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
592 writel(cmd, nfc->reg_base + NFC_REG_CMD);
594 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
595 writel(cmd, nfc->reg_base + NFC_REG_CMD);
601 static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
602 int datalen, int infolen,
603 enum dma_data_direction dir)
605 struct meson_nfc *nfc = nand_get_controller_data(nand);
607 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
609 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
614 static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
616 struct meson_nfc *nfc = nand_get_controller_data(nand);
621 info = kzalloc(PER_INFO_BYTE, GFP_KERNEL);
625 ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
626 PER_INFO_BYTE, DMA_FROM_DEVICE);
630 cmd = NFC_CMD_N2M | len;
631 writel(cmd, nfc->reg_base + NFC_REG_CMD);
633 meson_nfc_drain_cmd(nfc);
634 meson_nfc_wait_cmd_finish(nfc, 1000);
635 meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE);
643 static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
645 struct meson_nfc *nfc = nand_get_controller_data(nand);
649 ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL,
654 cmd = NFC_CMD_M2N | len;
655 writel(cmd, nfc->reg_base + NFC_REG_CMD);
657 meson_nfc_drain_cmd(nfc);
658 meson_nfc_wait_cmd_finish(nfc, 1000);
659 meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE);
664 static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
667 const struct nand_sdr_timings *sdr =
668 nand_get_sdr_timings(nand_get_interface_config(nand));
669 struct mtd_info *mtd = nand_to_mtd(nand);
670 struct meson_nfc *nfc = nand_get_controller_data(nand);
671 u32 *addrs = nfc->cmdfifo.rw.addrs;
672 u32 cs = nfc->param.chip_select;
673 u32 cmd0, cmd_num, row_start;
676 cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int);
678 cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
679 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
681 addrs[0] = cs | NFC_CMD_ALE | NFC_COLUMN_ADDR_0;
682 if (mtd->writesize <= 512) {
686 addrs[1] = cs | NFC_CMD_ALE | NFC_COLUMN_ADDR_1;
690 addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0);
691 addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1);
693 if (nand->options & NAND_ROW_ADDR_3)
694 addrs[row_start + 2] =
695 cs | NFC_CMD_ALE | ROW_ADDER(page, 2);
702 for (i = 0; i < cmd_num; i++)
703 writel_relaxed(nfc->cmdfifo.cmd[i],
704 nfc->reg_base + NFC_REG_CMD);
707 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
708 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
709 meson_nfc_queue_rb(nand, PSEC_TO_MSEC(sdr->tR_max), true);
711 meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
717 static int meson_nfc_write_page_sub(struct nand_chip *nand,
720 const struct nand_sdr_timings *sdr =
721 nand_get_sdr_timings(nand_get_interface_config(nand));
722 struct mtd_info *mtd = nand_to_mtd(nand);
723 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
724 struct meson_nfc *nfc = nand_get_controller_data(nand);
725 int data_len, info_len;
729 meson_nfc_select_chip(nand, nand->cur_cs);
731 data_len = mtd->writesize + mtd->oobsize;
732 info_len = nand->ecc.steps * PER_INFO_BYTE;
734 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE);
738 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
739 data_len, meson_chip->info_buf,
740 info_len, DMA_TO_DEVICE);
744 if (nand->options & NAND_NEED_SCRAMBLING) {
745 meson_nfc_cmd_seed(nfc, page);
746 meson_nfc_cmd_access(nand, raw, DIRWRITE,
747 NFC_CMD_SCRAMBLER_ENABLE);
749 meson_nfc_cmd_access(nand, raw, DIRWRITE,
750 NFC_CMD_SCRAMBLER_DISABLE);
753 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
754 writel(cmd, nfc->reg_base + NFC_REG_CMD);
755 meson_nfc_queue_rb(nand, PSEC_TO_MSEC(sdr->tPROG_max), false);
757 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE);
762 static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf,
763 int oob_required, int page)
765 u8 *oob_buf = nand->oob_poi;
767 meson_nfc_set_data_oob(nand, buf, oob_buf);
769 return meson_nfc_write_page_sub(nand, page, 1);
772 static int meson_nfc_write_page_hwecc(struct nand_chip *nand,
773 const u8 *buf, int oob_required, int page)
775 struct mtd_info *mtd = nand_to_mtd(nand);
776 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
777 u8 *oob_buf = nand->oob_poi;
779 memcpy(meson_chip->data_buf, buf, mtd->writesize);
780 memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
781 meson_nfc_set_user_byte(nand, oob_buf);
783 return meson_nfc_write_page_sub(nand, page, 0);
786 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
787 struct nand_chip *nand, int raw)
789 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
794 neccpages = raw ? 1 : nand->ecc.steps;
795 info = &meson_chip->info_buf[neccpages - 1];
797 usleep_range(10, 15);
798 /* info is updated by nfc dma engine*/
800 dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,
802 ret = *info & ECC_COMPLETE;
806 static int meson_nfc_read_page_sub(struct nand_chip *nand,
809 struct mtd_info *mtd = nand_to_mtd(nand);
810 struct meson_nfc *nfc = nand_get_controller_data(nand);
811 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
812 int data_len, info_len;
815 meson_nfc_select_chip(nand, nand->cur_cs);
817 data_len = mtd->writesize + mtd->oobsize;
818 info_len = nand->ecc.steps * PER_INFO_BYTE;
820 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD);
824 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
825 data_len, meson_chip->info_buf,
826 info_len, DMA_FROM_DEVICE);
830 if (nand->options & NAND_NEED_SCRAMBLING) {
831 meson_nfc_cmd_seed(nfc, page);
832 meson_nfc_cmd_access(nand, raw, DIRREAD,
833 NFC_CMD_SCRAMBLER_ENABLE);
835 meson_nfc_cmd_access(nand, raw, DIRREAD,
836 NFC_CMD_SCRAMBLER_DISABLE);
839 ret = meson_nfc_wait_dma_finish(nfc);
840 meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
842 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE);
847 static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf,
848 int oob_required, int page)
850 u8 *oob_buf = nand->oob_poi;
853 ret = meson_nfc_read_page_sub(nand, page, 1);
857 meson_nfc_get_data_oob(nand, buf, oob_buf);
862 static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
863 int oob_required, int page)
865 struct mtd_info *mtd = nand_to_mtd(nand);
866 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
867 struct nand_ecc_ctrl *ecc = &nand->ecc;
868 u64 correct_bitmap = 0;
870 u8 *oob_buf = nand->oob_poi;
873 ret = meson_nfc_read_page_sub(nand, page, 0);
877 meson_nfc_get_user_byte(nand, oob_buf);
878 ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap);
879 if (ret == ECC_CHECK_RETURN_FF) {
881 memset(buf, 0xff, mtd->writesize);
882 memset(oob_buf, 0xff, mtd->oobsize);
883 } else if (ret < 0) {
884 if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) {
885 mtd->ecc_stats.failed++;
888 ret = meson_nfc_read_page_raw(nand, buf, 0, page);
892 for (i = 0; i < nand->ecc.steps ; i++) {
893 u8 *data = buf + i * ecc->size;
894 u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
896 if (correct_bitmap & BIT_ULL(i))
898 ret = nand_check_erased_ecc_chunk(data, ecc->size,
903 mtd->ecc_stats.failed++;
905 mtd->ecc_stats.corrected += ret;
906 bitflips = max_t(u32, bitflips, ret);
909 } else if (buf && buf != meson_chip->data_buf) {
910 memcpy(buf, meson_chip->data_buf, mtd->writesize);
916 static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page)
918 return meson_nfc_read_page_raw(nand, NULL, 1, page);
921 static int meson_nfc_read_oob(struct nand_chip *nand, int page)
923 return meson_nfc_read_page_hwecc(nand, NULL, 1, page);
926 static bool meson_nfc_is_buffer_dma_safe(const void *buffer)
928 if ((uintptr_t)buffer % DMA_ADDR_ALIGN)
931 if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer)))
937 meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr)
939 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR))
942 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in))
943 return instr->ctx.data.buf.in;
945 return kzalloc(instr->ctx.data.len, GFP_KERNEL);
949 meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr,
952 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) ||
956 if (buf == instr->ctx.data.buf.in)
959 memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len);
964 meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr)
966 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR))
969 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out))
970 return (void *)instr->ctx.data.buf.out;
972 return kmemdup(instr->ctx.data.buf.out,
973 instr->ctx.data.len, GFP_KERNEL);
977 meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
980 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) ||
984 if (buf != instr->ctx.data.buf.out)
988 static int meson_nfc_check_op(struct nand_chip *chip,
989 const struct nand_operation *op)
993 for (op_id = 0; op_id < op->ninstrs; op_id++) {
994 const struct nand_op_instr *instr;
996 instr = &op->instrs[op_id];
998 switch (instr->type) {
999 case NAND_OP_DATA_IN_INSTR:
1000 case NAND_OP_DATA_OUT_INSTR:
1001 if (instr->ctx.data.len > NFC_CMD_RAW_LEN)
1013 static int meson_nfc_exec_op(struct nand_chip *nand,
1014 const struct nand_operation *op, bool check_only)
1016 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1017 struct meson_nfc *nfc = nand_get_controller_data(nand);
1018 const struct nand_op_instr *instr = NULL;
1020 u32 op_id, delay_idle, cmd;
1024 err = meson_nfc_check_op(nand, op);
1031 meson_nfc_select_chip(nand, op->cs);
1032 for (op_id = 0; op_id < op->ninstrs; op_id++) {
1033 instr = &op->instrs[op_id];
1034 delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns),
1035 meson_chip->level1_divider *
1037 switch (instr->type) {
1038 case NAND_OP_CMD_INSTR:
1039 cmd = nfc->param.chip_select | NFC_CMD_CLE;
1040 cmd |= instr->ctx.cmd.opcode & 0xff;
1041 writel(cmd, nfc->reg_base + NFC_REG_CMD);
1042 meson_nfc_cmd_idle(nfc, delay_idle);
1045 case NAND_OP_ADDR_INSTR:
1046 for (i = 0; i < instr->ctx.addr.naddrs; i++) {
1047 cmd = nfc->param.chip_select | NFC_CMD_ALE;
1048 cmd |= instr->ctx.addr.addrs[i] & 0xff;
1049 writel(cmd, nfc->reg_base + NFC_REG_CMD);
1051 meson_nfc_cmd_idle(nfc, delay_idle);
1054 case NAND_OP_DATA_IN_INSTR:
1055 buf = meson_nand_op_get_dma_safe_input_buf(instr);
1058 meson_nfc_read_buf(nand, buf, instr->ctx.data.len);
1059 meson_nand_op_put_dma_safe_input_buf(instr, buf);
1062 case NAND_OP_DATA_OUT_INSTR:
1063 buf = meson_nand_op_get_dma_safe_output_buf(instr);
1066 meson_nfc_write_buf(nand, buf, instr->ctx.data.len);
1067 meson_nand_op_put_dma_safe_output_buf(instr, buf);
1070 case NAND_OP_WAITRDY_INSTR:
1071 meson_nfc_queue_rb(nand, instr->ctx.waitrdy.timeout_ms,
1073 if (instr->delay_ns)
1074 meson_nfc_cmd_idle(nfc, delay_idle);
1078 meson_nfc_wait_cmd_finish(nfc, 1000);
1082 static int meson_ooblayout_ecc(struct mtd_info *mtd, int section,
1083 struct mtd_oob_region *oobregion)
1085 struct nand_chip *nand = mtd_to_nand(mtd);
1087 if (section >= nand->ecc.steps)
1090 oobregion->offset = 2 + (section * (2 + nand->ecc.bytes));
1091 oobregion->length = nand->ecc.bytes;
1096 static int meson_ooblayout_free(struct mtd_info *mtd, int section,
1097 struct mtd_oob_region *oobregion)
1099 struct nand_chip *nand = mtd_to_nand(mtd);
1101 if (section >= nand->ecc.steps)
1104 oobregion->offset = section * (2 + nand->ecc.bytes);
1105 oobregion->length = 2;
1110 static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
1111 .ecc = meson_ooblayout_ecc,
1112 .free = meson_ooblayout_free,
1115 static int meson_nfc_clk_init(struct meson_nfc *nfc)
1117 struct clk_parent_data nfc_divider_parent_data[1] = {0};
1118 struct clk_init_data init = {0};
1121 /* request core clock */
1122 nfc->core_clk = devm_clk_get(nfc->dev, "core");
1123 if (IS_ERR(nfc->core_clk)) {
1124 dev_err(nfc->dev, "failed to get core clock\n");
1125 return PTR_ERR(nfc->core_clk);
1128 nfc->device_clk = devm_clk_get(nfc->dev, "device");
1129 if (IS_ERR(nfc->device_clk)) {
1130 dev_err(nfc->dev, "failed to get device clock\n");
1131 return PTR_ERR(nfc->device_clk);
1134 init.name = devm_kasprintf(nfc->dev,
1135 GFP_KERNEL, "%s#div",
1136 dev_name(nfc->dev));
1140 init.ops = &clk_divider_ops;
1141 nfc_divider_parent_data[0].fw_name = "device";
1142 init.parent_data = nfc_divider_parent_data;
1143 init.num_parents = 1;
1144 nfc->nand_divider.reg = nfc->reg_clk;
1145 nfc->nand_divider.shift = CLK_DIV_SHIFT;
1146 nfc->nand_divider.width = CLK_DIV_WIDTH;
1147 nfc->nand_divider.hw.init = &init;
1148 nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED |
1149 CLK_DIVIDER_ROUND_CLOSEST |
1150 CLK_DIVIDER_ALLOW_ZERO;
1152 nfc->nand_clk = devm_clk_register(nfc->dev, &nfc->nand_divider.hw);
1153 if (IS_ERR(nfc->nand_clk))
1154 return PTR_ERR(nfc->nand_clk);
1156 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
1157 writel(CLK_SELECT_NAND | readl(nfc->reg_clk),
1160 ret = clk_prepare_enable(nfc->core_clk);
1162 dev_err(nfc->dev, "failed to enable core clock\n");
1166 ret = clk_prepare_enable(nfc->device_clk);
1168 dev_err(nfc->dev, "failed to enable device clock\n");
1169 goto err_device_clk;
1172 ret = clk_prepare_enable(nfc->nand_clk);
1174 dev_err(nfc->dev, "pre enable NFC divider fail\n");
1178 ret = clk_set_rate(nfc->nand_clk, 24000000);
1180 goto err_disable_clk;
1185 clk_disable_unprepare(nfc->nand_clk);
1187 clk_disable_unprepare(nfc->device_clk);
1189 clk_disable_unprepare(nfc->core_clk);
1193 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1195 clk_disable_unprepare(nfc->nand_clk);
1196 clk_disable_unprepare(nfc->device_clk);
1197 clk_disable_unprepare(nfc->core_clk);
1200 static void meson_nfc_free_buffer(struct nand_chip *nand)
1202 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1204 kfree(meson_chip->info_buf);
1205 kfree(meson_chip->data_buf);
1208 static int meson_chip_buffer_init(struct nand_chip *nand)
1210 struct mtd_info *mtd = nand_to_mtd(nand);
1211 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1212 u32 page_bytes, info_bytes, nsectors;
1214 nsectors = mtd->writesize / nand->ecc.size;
1216 page_bytes = mtd->writesize + mtd->oobsize;
1217 info_bytes = nsectors * PER_INFO_BYTE;
1219 meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
1220 if (!meson_chip->data_buf)
1223 meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
1224 if (!meson_chip->info_buf) {
1225 kfree(meson_chip->data_buf);
1233 int meson_nfc_setup_interface(struct nand_chip *nand, int csline,
1234 const struct nand_interface_config *conf)
1236 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1237 const struct nand_sdr_timings *timings;
1238 u32 div, bt_min, bt_max, tbers_clocks;
1240 timings = nand_get_sdr_timings(conf);
1241 if (IS_ERR(timings))
1244 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1247 div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE);
1248 bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div;
1249 bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min +
1250 timings->tRC_min / 2) / div;
1252 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
1253 div * NFC_CLK_CYCLE);
1254 meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
1255 div * NFC_CLK_CYCLE);
1256 tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
1257 div * NFC_CLK_CYCLE);
1258 meson_chip->tbers_max = ilog2(tbers_clocks);
1259 if (!is_power_of_2(tbers_clocks))
1260 meson_chip->tbers_max++;
1262 bt_min = DIV_ROUND_UP(bt_min, 1000);
1263 bt_max = DIV_ROUND_UP(bt_max, 1000);
1265 if (bt_max < bt_min)
1268 meson_chip->level1_divider = div;
1269 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
1270 meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
1275 static int meson_nand_bch_mode(struct nand_chip *nand)
1277 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1280 if (nand->ecc.strength > 60 || nand->ecc.strength < 8)
1283 for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) {
1284 if (meson_ecc[i].strength == nand->ecc.strength &&
1285 meson_ecc[i].size == nand->ecc.size) {
1286 meson_chip->bch_mode = meson_ecc[i].bch;
1294 static void meson_nand_detach_chip(struct nand_chip *nand)
1296 meson_nfc_free_buffer(nand);
1299 static int meson_nand_attach_chip(struct nand_chip *nand)
1301 struct meson_nfc *nfc = nand_get_controller_data(nand);
1302 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
1303 struct mtd_info *mtd = nand_to_mtd(nand);
1308 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1311 meson_chip->sels[0]);
1316 raw_writesize = mtd->writesize + mtd->oobsize;
1317 if (raw_writesize > NFC_CMD_RAW_LEN) {
1318 dev_err(nfc->dev, "too big write size in raw mode: %d > %ld\n",
1319 raw_writesize, NFC_CMD_RAW_LEN);
1323 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1324 nand->bbt_options |= NAND_BBT_NO_OOB;
1326 nand->options |= NAND_NO_SUBPAGE_WRITE;
1328 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1331 dev_err(nfc->dev, "failed to ECC init\n");
1335 mtd_set_ooblayout(mtd, &meson_ooblayout_ops);
1337 ret = meson_nand_bch_mode(nand);
1341 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1342 nand->ecc.write_page_raw = meson_nfc_write_page_raw;
1343 nand->ecc.write_page = meson_nfc_write_page_hwecc;
1344 nand->ecc.write_oob_raw = nand_write_oob_std;
1345 nand->ecc.write_oob = nand_write_oob_std;
1347 nand->ecc.read_page_raw = meson_nfc_read_page_raw;
1348 nand->ecc.read_page = meson_nfc_read_page_hwecc;
1349 nand->ecc.read_oob_raw = meson_nfc_read_oob_raw;
1350 nand->ecc.read_oob = meson_nfc_read_oob;
1352 if (nand->options & NAND_BUSWIDTH_16) {
1353 dev_err(nfc->dev, "16bits bus width not supported");
1356 ret = meson_chip_buffer_init(nand);
1363 static const struct nand_controller_ops meson_nand_controller_ops = {
1364 .attach_chip = meson_nand_attach_chip,
1365 .detach_chip = meson_nand_detach_chip,
1366 .setup_interface = meson_nfc_setup_interface,
1367 .exec_op = meson_nfc_exec_op,
1371 meson_nfc_nand_chip_init(struct device *dev,
1372 struct meson_nfc *nfc, struct device_node *np)
1374 struct meson_nfc_nand_chip *meson_chip;
1375 struct nand_chip *nand;
1376 struct mtd_info *mtd;
1379 u32 nand_rb_val = 0;
1381 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
1382 if (!nsels || nsels > MAX_CE_NUM) {
1383 dev_err(dev, "invalid register property size\n");
1387 meson_chip = devm_kzalloc(dev, struct_size(meson_chip, sels, nsels),
1392 meson_chip->nsels = nsels;
1394 for (i = 0; i < nsels; i++) {
1395 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1397 dev_err(dev, "could not retrieve register property: %d\n",
1402 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1403 dev_err(dev, "CS %d already assigned\n", tmp);
1408 nand = &meson_chip->nand;
1409 nand->controller = &nfc->controller;
1410 nand->controller->ops = &meson_nand_controller_ops;
1411 nand_set_flash_node(nand, np);
1412 nand_set_controller_data(nand, nfc);
1414 nand->options |= NAND_USES_DMA;
1415 mtd = nand_to_mtd(nand);
1416 mtd->owner = THIS_MODULE;
1417 mtd->dev.parent = dev;
1419 ret = of_property_read_u32(np, "nand-rb", &nand_rb_val);
1421 nfc->no_rb_pin = true;
1428 ret = nand_scan(nand, nsels);
1432 ret = mtd_device_register(mtd, NULL, 0);
1434 dev_err(dev, "failed to register MTD device: %d\n", ret);
1439 list_add_tail(&meson_chip->node, &nfc->chips);
1444 static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1446 struct meson_nfc_nand_chip *meson_chip;
1447 struct mtd_info *mtd;
1449 while (!list_empty(&nfc->chips)) {
1450 meson_chip = list_first_entry(&nfc->chips,
1451 struct meson_nfc_nand_chip, node);
1452 mtd = nand_to_mtd(&meson_chip->nand);
1453 WARN_ON(mtd_device_unregister(mtd));
1455 nand_cleanup(&meson_chip->nand);
1456 list_del(&meson_chip->node);
1460 static int meson_nfc_nand_chips_init(struct device *dev,
1461 struct meson_nfc *nfc)
1463 struct device_node *np = dev->of_node;
1464 struct device_node *nand_np;
1467 for_each_child_of_node(np, nand_np) {
1468 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1470 meson_nfc_nand_chip_cleanup(nfc);
1471 of_node_put(nand_np);
1479 static irqreturn_t meson_nfc_irq(int irq, void *id)
1481 struct meson_nfc *nfc = id;
1484 cfg = readl(nfc->reg_base + NFC_REG_CFG);
1485 if (!(cfg & NFC_RB_IRQ_EN))
1488 cfg &= ~(NFC_RB_IRQ_EN);
1489 writel(cfg, nfc->reg_base + NFC_REG_CFG);
1491 complete(&nfc->completion);
1495 static const struct meson_nfc_data meson_gxl_data = {
1496 .ecc_caps = &meson_gxl_ecc_caps,
1499 static const struct meson_nfc_data meson_axg_data = {
1500 .ecc_caps = &meson_axg_ecc_caps,
1503 static const struct of_device_id meson_nfc_id_table[] = {
1505 .compatible = "amlogic,meson-gxl-nfc",
1506 .data = &meson_gxl_data,
1508 .compatible = "amlogic,meson-axg-nfc",
1509 .data = &meson_axg_data,
1513 MODULE_DEVICE_TABLE(of, meson_nfc_id_table);
1515 static int meson_nfc_probe(struct platform_device *pdev)
1517 struct device *dev = &pdev->dev;
1518 struct meson_nfc *nfc;
1521 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1525 nfc->data = of_device_get_match_data(&pdev->dev);
1529 nand_controller_init(&nfc->controller);
1530 INIT_LIST_HEAD(&nfc->chips);
1531 init_completion(&nfc->completion);
1535 nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc");
1536 if (IS_ERR(nfc->reg_base))
1537 return PTR_ERR(nfc->reg_base);
1539 nfc->reg_clk = devm_platform_ioremap_resource_byname(pdev, "emmc");
1540 if (IS_ERR(nfc->reg_clk))
1541 return PTR_ERR(nfc->reg_clk);
1543 irq = platform_get_irq(pdev, 0);
1547 ret = meson_nfc_clk_init(nfc);
1549 dev_err(dev, "failed to initialize NAND clock\n");
1553 writel(0, nfc->reg_base + NFC_REG_CFG);
1554 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1556 dev_err(dev, "failed to request NFC IRQ\n");
1561 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1563 dev_err(dev, "failed to set DMA mask\n");
1567 platform_set_drvdata(pdev, nfc);
1569 ret = meson_nfc_nand_chips_init(dev, nfc);
1571 dev_err(dev, "failed to init NAND chips\n");
1577 meson_nfc_disable_clk(nfc);
1581 static void meson_nfc_remove(struct platform_device *pdev)
1583 struct meson_nfc *nfc = platform_get_drvdata(pdev);
1585 meson_nfc_nand_chip_cleanup(nfc);
1587 meson_nfc_disable_clk(nfc);
1590 static struct platform_driver meson_nfc_driver = {
1591 .probe = meson_nfc_probe,
1592 .remove_new = meson_nfc_remove,
1594 .name = "meson-nand",
1595 .of_match_table = meson_nfc_id_table,
1598 module_platform_driver(meson_nfc_driver);
1600 MODULE_LICENSE("Dual MIT/GPL");
1601 MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>");
1602 MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver");