1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
5 * Copyright (C) 2017 Marvell
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
10 #include <linux/module.h>
11 #include <linux/clk.h>
12 #include <linux/mtd/rawnand.h>
13 #include <linux/of_platform.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
19 #include <asm/unaligned.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dma/pxa-dma.h>
24 #include <linux/platform_data/mtd-nand-pxa3xx.h>
26 /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */
28 #define FIFO_REP(x) (x / sizeof(u32))
29 #define BCH_SEQ_READS (32 / FIFO_DEPTH)
30 /* NFC does not support transfers of larger chunks at a time */
31 #define MAX_CHUNK_SIZE 2112
32 /* NFCv1 cannot read more that 7 bytes of ID */
33 #define NFCV1_READID_LEN 7
34 /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */
36 #define POLL_TIMEOUT 100000
37 /* Interrupt maximum wait period in ms */
38 #define IRQ_TIMEOUT 1000
39 /* Latency in clock cycles between SoC pins and NFC logic */
40 #define MIN_RD_DEL_CNT 3
41 /* Maximum number of contiguous address cycles */
42 #define MAX_ADDRESS_CYC_NFCV1 5
43 #define MAX_ADDRESS_CYC_NFCV2 7
44 /* System control registers/bits to enable the NAND controller on some SoCs */
45 #define GENCONF_SOC_DEVICE_MUX 0x208
46 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
47 #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20)
48 #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21)
49 #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25)
50 #define GENCONF_CLK_GATING_CTRL 0x220
51 #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2)
52 #define GENCONF_ND_CLK_CTRL 0x700
53 #define GENCONF_ND_CLK_CTRL_EN BIT(0)
55 /* NAND controller data flash control register */
57 #define NDCR_ALL_INT GENMASK(11, 0)
58 #define NDCR_CS1_CMDDM BIT(7)
59 #define NDCR_CS0_CMDDM BIT(8)
60 #define NDCR_RDYM BIT(11)
61 #define NDCR_ND_ARB_EN BIT(12)
62 #define NDCR_RA_START BIT(15)
63 #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16)
64 #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0)
65 #define NDCR_DWIDTH_M BIT(26)
66 #define NDCR_DWIDTH_C BIT(27)
67 #define NDCR_ND_RUN BIT(28)
68 #define NDCR_DMA_EN BIT(29)
69 #define NDCR_ECC_EN BIT(30)
70 #define NDCR_SPARE_EN BIT(31)
71 #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \
72 NDCR_DWIDTH_M | NDCR_DWIDTH_C))
74 /* NAND interface timing parameter 0 register */
76 #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0)
77 #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3)
78 #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3)
79 #define NDTR0_SEL_NRE_EDGE BIT(7)
80 #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8)
81 #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11)
82 #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16)
83 #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19)
84 #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22)
85 #define NDTR0_SELCNTR BIT(26)
86 #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27)
88 /* NAND interface timing parameter 1 register */
90 #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0)
91 #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4)
92 #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8)
93 #define NDTR1_PRESCALE BIT(14)
94 #define NDTR1_WAIT_MODE BIT(15)
95 #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16)
97 /* NAND controller status register */
99 #define NDSR_WRCMDREQ BIT(0)
100 #define NDSR_RDDREQ BIT(1)
101 #define NDSR_WRDREQ BIT(2)
102 #define NDSR_CORERR BIT(3)
103 #define NDSR_UNCERR BIT(4)
104 #define NDSR_CMDD(cs) BIT(8 - cs)
105 #define NDSR_RDY(rb) BIT(11 + rb)
106 #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F)
108 /* NAND ECC control register */
109 #define NDECCCTRL 0x28
110 #define NDECCCTRL_BCH_EN BIT(0)
112 /* NAND controller data buffer register */
115 /* NAND controller command buffer 0 register */
117 #define NDCB0_CMD1(x) ((x & 0xFF) << 0)
118 #define NDCB0_CMD2(x) ((x & 0xFF) << 8)
119 #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16)
120 #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7)
121 #define NDCB0_DBC BIT(19)
122 #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21)
123 #define NDCB0_CSEL BIT(24)
124 #define NDCB0_RDY_BYP BIT(27)
125 #define NDCB0_LEN_OVRD BIT(28)
126 #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29)
128 /* NAND controller command buffer 1 register */
130 #define NDCB1_COLS(x) ((x & 0xFFFF) << 0)
131 #define NDCB1_ADDRS_PAGE(x) (x << 16)
133 /* NAND controller command buffer 2 register */
135 #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0)
136 #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0)
138 /* NAND controller command buffer 3 register */
140 #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16)
141 #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24)
143 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
147 #define TYPE_READ_ID 3
148 #define TYPE_STATUS 4
150 #define TYPE_NAKED_CMD 6
151 #define TYPE_NAKED_ADDR 7
153 #define XTYPE_MONOLITHIC_RW 0
154 #define XTYPE_LAST_NAKED_RW 1
155 #define XTYPE_FINAL_COMMAND 3
157 #define XTYPE_WRITE_DISPATCH 4
158 #define XTYPE_NAKED_RW 5
159 #define XTYPE_COMMAND_DISPATCH 6
163 * Marvell ECC engine works differently than the others, in order to limit the
164 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
165 * per subpage, and depending on a the desired strength needed by the NAND chip,
166 * a particular layout mixing data/spare/ecc is defined, with a possible last
167 * chunk smaller that the others.
169 * @writesize: Full page size on which the layout applies
170 * @chunk: Desired ECC chunk size on which the layout applies
171 * @strength: Desired ECC strength (per chunk size bytes) on which the
173 * @nchunks: Total number of chunks
174 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
175 * repetitions of the pattern:
176 * (data_bytes + spare_bytes + ecc_bytes).
177 * @data_bytes: Number of data bytes per chunk
178 * @spare_bytes: Number of spare bytes per chunk
179 * @ecc_bytes: Number of ecc bytes per chunk
180 * @last_data_bytes: Number of data bytes in the last chunk
181 * @last_spare_bytes: Number of spare bytes in the last chunk
182 * @last_ecc_bytes: Number of ecc bytes in the last chunk
184 struct marvell_hw_ecc_layout {
189 /* Corresponding layout */
196 int last_spare_bytes;
200 #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \
206 .full_chunk_cnt = fcc, \
210 .last_data_bytes = ldb, \
211 .last_spare_bytes = lsb, \
212 .last_ecc_bytes = leb, \
215 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
216 static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
217 MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
218 MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
219 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
220 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
221 MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30),
225 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
226 * is made by a field in NDCB0 register, and in another field in NDCB2 register.
227 * The datasheet describes the logic with an error: ADDR5 field is once
228 * declared at the beginning of NDCB2, and another time at its end. Because the
229 * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical
230 * to use the last bit of this field instead of the first ones.
232 * @cs: Wanted CE lane.
233 * @ndcb0_csel: Value of the NDCB0 register with or without the flag
234 * selecting the wanted CE lane. This is set once when
235 * the Device Tree is probed.
236 * @rb: Ready/Busy pin for the flash chip
238 struct marvell_nand_chip_sel {
245 * NAND chip structure: stores NAND chip device related information
247 * @chip: Base NAND chip structure
248 * @node: Used to store NAND chips into a list
249 * @layout NAND layout when using hardware ECC
250 * @ndcr: Controller register value for this NAND chip
251 * @ndtr0: Timing registers 0 value for this NAND chip
252 * @ndtr1: Timing registers 1 value for this NAND chip
253 * @selected_die: Current active CS
254 * @nsels: Number of CS lines required by the NAND chip
255 * @sels: Array of CS lines descriptions
257 struct marvell_nand_chip {
258 struct nand_chip chip;
259 struct list_head node;
260 const struct marvell_hw_ecc_layout *layout;
267 struct marvell_nand_chip_sel sels[0];
270 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
272 return container_of(chip, struct marvell_nand_chip, chip);
275 static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
278 return &nand->sels[nand->selected_die];
282 * NAND controller capabilities for distinction between compatible strings
284 * @max_cs_nb: Number of Chip Select lines available
285 * @max_rb_nb: Number of Ready/Busy lines available
286 * @need_system_controller: Indicates if the SoC needs to have access to the
287 * system controller (ie. to enable the NAND controller)
288 * @legacy_of_bindings: Indicates if DT parsing must be done using the old
290 * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie.
291 * BCH error detection and correction algorithm,
292 * NDCB3 register has been added
293 * @use_dma: Use dma for data transfers
295 struct marvell_nfc_caps {
296 unsigned int max_cs_nb;
297 unsigned int max_rb_nb;
298 bool need_system_controller;
299 bool legacy_of_bindings;
305 * NAND controller structure: stores Marvell NAND controller information
307 * @controller: Base controller structure
308 * @dev: Parent device (used to print error messages)
309 * @regs: NAND controller registers
310 * @core_clk: Core clock
311 * @reg_clk: Regiters clock
312 * @complete: Completion object to wait for NAND controller events
313 * @assigned_cs: Bitmask describing already assigned CS lines
314 * @chips: List containing all the NAND chips attached to
315 * this NAND controller
316 * @caps: NAND controller capabilities for each compatible string
317 * @dma_chan: DMA channel (NFCv1 only)
318 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
321 struct nand_hw_control controller;
324 struct clk *core_clk;
326 struct completion complete;
327 unsigned long assigned_cs;
328 struct list_head chips;
329 struct nand_chip *selected_chip;
330 const struct marvell_nfc_caps *caps;
332 /* DMA (NFCv1 only) */
334 struct dma_chan *dma_chan;
338 static inline struct marvell_nfc *to_marvell_nfc(struct nand_hw_control *ctrl)
340 return container_of(ctrl, struct marvell_nfc, controller);
344 * NAND controller timings expressed in NAND Controller clock cycles
346 * @tRP: ND_nRE pulse width
347 * @tRH: ND_nRE high duration
348 * @tWP: ND_nWE pulse time
349 * @tWH: ND_nWE high duration
350 * @tCS: Enable signal setup time
351 * @tCH: Enable signal hold time
352 * @tADL: Address to write data delay
353 * @tAR: ND_ALE low to ND_nRE low delay
354 * @tWHR: ND_nWE high to ND_nRE low for status read
355 * @tRHW: ND_nRE high duration, read to write delay
356 * @tR: ND_nWE high to ND_nRE low for read
358 struct marvell_nfc_timings {
375 * Derives a duration in numbers of clock cycles.
377 * @ps: Duration in pico-seconds
378 * @period_ns: Clock period in nano-seconds
380 * Convert the duration in nano-seconds, then divide by the period and
381 * return the number of clock periods.
383 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
384 #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
388 * NAND driver structure filled during the parsing of the ->exec_op() subop
389 * subset of instructions.
391 * @ndcb: Array of values written to NDCBx registers
392 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle
393 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
394 * @rdy_delay_ns: Optional delay after waiting for the RB pin
395 * @data_delay_ns: Optional delay after the data xfer
396 * @data_instr_idx: Index of the data instruction in the subop
397 * @data_instr: Pointer to the data instruction in the subop
399 struct marvell_nfc_op {
401 unsigned int cle_ale_delay_ns;
402 unsigned int rdy_timeout_ms;
403 unsigned int rdy_delay_ns;
404 unsigned int data_delay_ns;
405 unsigned int data_instr_idx;
406 const struct nand_op_instr *data_instr;
410 * Internal helper to conditionnally apply a delay (from the above structure,
413 static void cond_delay(unsigned int ns)
421 udelay(DIV_ROUND_UP(ns, 1000));
425 * The controller has many flags that could generate interrupts, most of them
426 * are disabled and polling is used. For the very slow signals, using interrupts
427 * may relax the CPU charge.
429 static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask)
433 /* Writing 1 disables the interrupt */
434 reg = readl_relaxed(nfc->regs + NDCR);
435 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
438 static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask)
442 /* Writing 0 enables the interrupt */
443 reg = readl_relaxed(nfc->regs + NDCR);
444 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
447 static void marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask)
449 writel_relaxed(int_mask, nfc->regs + NDSR);
452 static void marvell_nfc_force_byte_access(struct nand_chip *chip,
455 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
459 * Callers of this function do not verify if the NAND is using a 16-bit
460 * an 8-bit bus for normal operations, so we need to take care of that
461 * here by leaving the configuration unchanged if the NAND does not have
462 * the NAND_BUSWIDTH_16 flag set.
464 if (!(chip->options & NAND_BUSWIDTH_16))
467 ndcr = readl_relaxed(nfc->regs + NDCR);
470 ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C);
472 ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
474 writel_relaxed(ndcr, nfc->regs + NDCR);
477 static int marvell_nfc_wait_ndrun(struct nand_chip *chip)
479 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
484 * The command is being processed, wait for the ND_RUN bit to be
485 * cleared by the NFC. If not, we must clear it by hand.
487 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
488 (val & NDCR_ND_RUN) == 0,
489 POLL_PERIOD, POLL_TIMEOUT);
491 dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
492 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
501 * Any time a command has to be sent to the controller, the following sequence
502 * has to be followed:
503 * - call marvell_nfc_prepare_cmd()
504 * -> activate the ND_RUN bit that will kind of 'start a job'
505 * -> wait the signal indicating the NFC is waiting for a command
506 * - send the command (cmd and address cycles)
507 * - enventually send or receive the data
508 * - call marvell_nfc_end_cmd() with the corresponding flag
509 * -> wait the flag to be triggered or cancel the job with a timeout
511 * The following helpers are here to factorize the code a bit so that
512 * specialized functions responsible for executing the actual NAND
513 * operations do not have to replicate the same code blocks.
515 static int marvell_nfc_prepare_cmd(struct nand_chip *chip)
517 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
521 /* Poll ND_RUN and clear NDSR before issuing any command */
522 ret = marvell_nfc_wait_ndrun(chip);
524 dev_err(nfc->dev, "Last operation did not succeed\n");
528 ndcr = readl_relaxed(nfc->regs + NDCR);
529 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
531 /* Assert ND_RUN bit and wait the NFC to be ready */
532 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
533 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
535 POLL_PERIOD, POLL_TIMEOUT);
537 dev_err(nfc->dev, "Timeout on WRCMDRE\n");
541 /* Command may be written, clear WRCMDREQ status bit */
542 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
547 static void marvell_nfc_send_cmd(struct nand_chip *chip,
548 struct marvell_nfc_op *nfc_op)
550 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
551 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
553 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n"
554 "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n",
555 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
556 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]);
558 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
560 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
561 writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
564 * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7
565 * fields are used (only available on NFCv2).
567 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD ||
568 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) {
569 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2))
570 writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
574 static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag,
577 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
581 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
583 POLL_PERIOD, POLL_TIMEOUT);
586 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n",
589 dmaengine_terminate_all(nfc->dma_chan);
594 * DMA function uses this helper to poll on CMDD bits without wanting
595 * them to be cleared.
597 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
600 writel_relaxed(flag, nfc->regs + NDSR);
605 static int marvell_nfc_wait_cmdd(struct nand_chip *chip)
607 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
608 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel);
610 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
613 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
615 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
618 /* Timeout is expressed in ms */
620 timeout_ms = IRQ_TIMEOUT;
622 init_completion(&nfc->complete);
624 marvell_nfc_enable_int(nfc, NDCR_RDYM);
625 ret = wait_for_completion_timeout(&nfc->complete,
626 msecs_to_jiffies(timeout_ms));
627 marvell_nfc_disable_int(nfc, NDCR_RDYM);
628 marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
630 dev_err(nfc->dev, "Timeout waiting for RB signal\n");
637 static void marvell_nfc_select_chip(struct mtd_info *mtd, int die_nr)
639 struct nand_chip *chip = mtd_to_nand(mtd);
640 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
641 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
644 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
647 if (die_nr < 0 || die_nr >= marvell_nand->nsels) {
648 nfc->selected_chip = NULL;
649 marvell_nand->selected_die = -1;
654 * Do not change the timing registers when using the DT property
655 * marvell,nand-keep-config; in that case ->ndtr0 and ->ndtr1 from the
656 * marvell_nand structure are supposedly empty.
658 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
659 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
662 * Reset the NDCR register to a clean state for this particular chip,
663 * also clear ND_RUN bit.
665 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
666 NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN;
667 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
669 /* Also reset the interrupt status register */
670 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
672 nfc->selected_chip = chip;
673 marvell_nand->selected_die = die_nr;
676 static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
678 struct marvell_nfc *nfc = dev_id;
679 u32 st = readl_relaxed(nfc->regs + NDSR);
680 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
683 * RDY interrupt mask is one bit in NDCR while there are two status
684 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
686 if (st & NDSR_RDY(1))
692 marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
694 if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ)))
695 complete(&nfc->complete);
700 /* HW ECC related functions */
701 static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
703 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
704 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
706 if (!(ndcr & NDCR_ECC_EN)) {
707 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
710 * When enabling BCH, set threshold to 0 to always know the
711 * number of corrected bitflips.
713 if (chip->ecc.algo == NAND_ECC_BCH)
714 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
718 static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
720 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
721 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
723 if (ndcr & NDCR_ECC_EN) {
724 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
725 if (chip->ecc.algo == NAND_ECC_BCH)
726 writel_relaxed(0, nfc->regs + NDECCCTRL);
730 /* DMA related helpers */
731 static void marvell_nfc_enable_dma(struct marvell_nfc *nfc)
735 reg = readl_relaxed(nfc->regs + NDCR);
736 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
739 static void marvell_nfc_disable_dma(struct marvell_nfc *nfc)
743 reg = readl_relaxed(nfc->regs + NDCR);
744 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
747 /* Read/write PIO/DMA accessors */
748 static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc,
749 enum dma_data_direction direction,
752 unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE);
753 struct dma_async_tx_descriptor *tx;
754 struct scatterlist sg;
758 marvell_nfc_enable_dma(nfc);
759 /* Prepare the DMA transfer */
760 sg_init_one(&sg, nfc->dma_buf, dma_len);
761 dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
762 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1,
763 direction == DMA_FROM_DEVICE ?
764 DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
767 dev_err(nfc->dev, "Could not prepare DMA S/G list\n");
771 /* Do the task and wait for it to finish */
772 cookie = dmaengine_submit(tx);
773 ret = dma_submit_error(cookie);
777 dma_async_issue_pending(nfc->dma_chan);
778 ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
779 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
780 marvell_nfc_disable_dma(nfc);
782 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n",
783 dmaengine_tx_status(nfc->dma_chan, cookie, NULL));
784 dmaengine_terminate_all(nfc->dma_chan);
791 static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
794 unsigned int last_len = len % FIFO_DEPTH;
795 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
798 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
799 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
802 u8 tmp_buf[FIFO_DEPTH];
804 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
805 memcpy(in + last_full_offset, tmp_buf, last_len);
811 static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out,
814 unsigned int last_len = len % FIFO_DEPTH;
815 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
818 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
819 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH));
822 u8 tmp_buf[FIFO_DEPTH];
824 memcpy(tmp_buf, out + last_full_offset, last_len);
825 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
831 static void marvell_nfc_check_empty_chunk(struct nand_chip *chip,
832 u8 *data, int data_len,
833 u8 *spare, int spare_len,
834 u8 *ecc, int ecc_len,
835 unsigned int *max_bitflips)
837 struct mtd_info *mtd = nand_to_mtd(chip);
841 * Blank pages (all 0xFF) that have not been written may be recognized
842 * as bad if bitflips occur, so whenever an uncorrectable error occurs,
843 * check if the entire page (with ECC bytes) is actually blank or not.
852 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
853 spare, spare_len, chip->ecc.strength);
855 mtd->ecc_stats.failed++;
859 /* Update the stats and max_bitflips */
860 mtd->ecc_stats.corrected += bf;
861 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
865 * Check a chunk is correct or not according to hardware ECC engine.
866 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
867 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
868 * value indicating that a check on the emptyness of the subpage must be
869 * performed before declaring the subpage corrupted.
871 static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip,
872 unsigned int *max_bitflips)
874 struct mtd_info *mtd = nand_to_mtd(chip);
875 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
879 ndsr = readl_relaxed(nfc->regs + NDSR);
881 /* Check uncorrectable error flag */
882 if (ndsr & NDSR_UNCERR) {
883 writel_relaxed(ndsr, nfc->regs + NDSR);
886 * Do not increment ->ecc_stats.failed now, instead, return a
887 * non-zero value to indicate that this chunk was apparently
888 * bad, and it should be check to see if it empty or not. If
889 * the chunk (with ECC bytes) is not declared empty, the calling
890 * function must increment the failure count.
895 /* Check correctable error flag */
896 if (ndsr & NDSR_CORERR) {
897 writel_relaxed(ndsr, nfc->regs + NDSR);
899 if (chip->ecc.algo == NAND_ECC_BCH)
900 bf = NDSR_ERRCNT(ndsr);
905 /* Update the stats and max_bitflips */
906 mtd->ecc_stats.corrected += bf;
907 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
912 /* Hamming read helpers */
913 static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip,
914 u8 *data_buf, u8 *oob_buf,
917 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
918 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
919 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
920 struct marvell_nfc_op nfc_op = {
921 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
922 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
924 NDCB0_CMD1(NAND_CMD_READ0) |
925 NDCB0_CMD2(NAND_CMD_READSTART),
926 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
927 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
929 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
932 /* NFCv2 needs more information about the operation being executed */
933 if (nfc->caps->is_nfcv2)
934 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
936 ret = marvell_nfc_prepare_cmd(chip);
940 marvell_nfc_send_cmd(chip, &nfc_op);
941 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
942 "RDDREQ while draining FIFO (data/oob)");
947 * Read the page then the OOB area. Unlike what is shown in current
948 * documentation, spare bytes are protected by the ECC engine, and must
949 * be at the beginning of the OOB area or running this driver on legacy
950 * systems will prevent the discovery of the BBM/BBT.
953 marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE,
954 lt->data_bytes + oob_bytes);
955 memcpy(data_buf, nfc->dma_buf, lt->data_bytes);
956 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes);
958 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes);
959 marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes);
962 ret = marvell_nfc_wait_cmdd(chip);
967 static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct mtd_info *mtd,
968 struct nand_chip *chip, u8 *buf,
969 int oob_required, int page)
971 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
975 static int marvell_nfc_hw_ecc_hmg_read_page(struct mtd_info *mtd,
976 struct nand_chip *chip,
977 u8 *buf, int oob_required,
980 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
981 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
982 int max_bitflips = 0, ret;
985 marvell_nfc_enable_hw_ecc(chip);
986 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
988 ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
989 marvell_nfc_disable_hw_ecc(chip);
995 * When ECC failures are detected, check if the full page has been
996 * written or not. Ignore the failure if it is actually empty.
998 raw_buf = kmalloc(full_sz, GFP_KERNEL);
1002 marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf +
1003 lt->data_bytes, true, page);
1004 marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0,
1008 return max_bitflips;
1012 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1013 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1014 * also stands for ->read_oob().
1016 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct mtd_info *mtd,
1017 struct nand_chip *chip, int page)
1019 /* Invalidate page cache */
1022 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf,
1023 chip->oob_poi, true, page);
1026 /* Hamming write helpers */
1027 static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
1029 const u8 *oob_buf, bool raw,
1032 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1033 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1034 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1035 struct marvell_nfc_op nfc_op = {
1036 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) |
1037 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1038 NDCB0_CMD1(NAND_CMD_SEQIN) |
1039 NDCB0_CMD2(NAND_CMD_PAGEPROG) |
1041 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1042 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1044 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1047 /* NFCv2 needs more information about the operation being executed */
1048 if (nfc->caps->is_nfcv2)
1049 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1051 ret = marvell_nfc_prepare_cmd(chip);
1055 marvell_nfc_send_cmd(chip, &nfc_op);
1056 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1057 "WRDREQ while loading FIFO (data)");
1061 /* Write the page then the OOB area */
1063 memcpy(nfc->dma_buf, data_buf, lt->data_bytes);
1064 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes);
1065 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes +
1066 lt->ecc_bytes + lt->spare_bytes);
1068 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes);
1069 marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes);
1072 ret = marvell_nfc_wait_cmdd(chip);
1076 ret = marvell_nfc_wait_op(chip,
1077 PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1081 static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct mtd_info *mtd,
1082 struct nand_chip *chip,
1084 int oob_required, int page)
1086 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1090 static int marvell_nfc_hw_ecc_hmg_write_page(struct mtd_info *mtd,
1091 struct nand_chip *chip,
1093 int oob_required, int page)
1097 marvell_nfc_enable_hw_ecc(chip);
1098 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1100 marvell_nfc_disable_hw_ecc(chip);
1106 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1107 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1108 * also stands for ->write_oob().
1110 static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct mtd_info *mtd,
1111 struct nand_chip *chip,
1114 /* Invalidate page cache */
1117 memset(chip->data_buf, 0xFF, mtd->writesize);
1119 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf,
1120 chip->oob_poi, true, page);
1123 /* BCH read helpers */
1124 static int marvell_nfc_hw_ecc_bch_read_page_raw(struct mtd_info *mtd,
1125 struct nand_chip *chip, u8 *buf,
1126 int oob_required, int page)
1128 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1129 u8 *oob = chip->oob_poi;
1130 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1131 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1132 lt->last_spare_bytes;
1133 int data_len = lt->data_bytes;
1134 int spare_len = lt->spare_bytes;
1135 int ecc_len = lt->ecc_bytes;
1139 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1141 nand_read_page_op(chip, page, 0, NULL, 0);
1143 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1144 /* Update last chunk length */
1145 if (chunk >= lt->full_chunk_cnt) {
1146 data_len = lt->last_data_bytes;
1147 spare_len = lt->last_spare_bytes;
1148 ecc_len = lt->last_ecc_bytes;
1151 /* Read data bytes*/
1152 nand_change_read_column_op(chip, chunk * chunk_size,
1153 buf + (lt->data_bytes * chunk),
1156 /* Read spare bytes */
1157 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
1160 /* Read ECC bytes */
1161 nand_read_data_op(chip, oob + ecc_offset +
1162 (ALIGN(lt->ecc_bytes, 32) * chunk),
1169 static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk,
1170 u8 *data, unsigned int data_len,
1171 u8 *spare, unsigned int spare_len,
1174 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1175 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1176 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1178 struct marvell_nfc_op nfc_op = {
1179 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1180 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1182 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1183 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1184 .ndcb[3] = data_len + spare_len,
1187 ret = marvell_nfc_prepare_cmd(chip);
1192 nfc_op.ndcb[0] |= NDCB0_DBC |
1193 NDCB0_CMD1(NAND_CMD_READ0) |
1194 NDCB0_CMD2(NAND_CMD_READSTART);
1197 * Trigger the monolithic read on the first chunk, then naked read on
1198 * intermediate chunks and finally a last naked read on the last chunk.
1201 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1202 else if (chunk < lt->nchunks - 1)
1203 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1205 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1207 marvell_nfc_send_cmd(chip, &nfc_op);
1210 * According to the datasheet, when reading from NDDB
1211 * with BCH enabled, after each 32 bytes reads, we
1212 * have to make sure that the NDSR.RDDREQ bit is set.
1214 * Drain the FIFO, 8 32-bit reads at a time, and skip
1215 * the polling on the last read.
1217 * Length is a multiple of 32 bytes, hence it is a multiple of 8 too.
1219 for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1220 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1221 "RDDREQ while draining FIFO (data)");
1222 marvell_nfc_xfer_data_in_pio(nfc, data,
1223 FIFO_DEPTH * BCH_SEQ_READS);
1224 data += FIFO_DEPTH * BCH_SEQ_READS;
1227 for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1228 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1229 "RDDREQ while draining FIFO (OOB)");
1230 marvell_nfc_xfer_data_in_pio(nfc, spare,
1231 FIFO_DEPTH * BCH_SEQ_READS);
1232 spare += FIFO_DEPTH * BCH_SEQ_READS;
1236 static int marvell_nfc_hw_ecc_bch_read_page(struct mtd_info *mtd,
1237 struct nand_chip *chip,
1238 u8 *buf, int oob_required,
1241 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1242 int data_len = lt->data_bytes, spare_len = lt->spare_bytes, ecc_len;
1243 u8 *data = buf, *spare = chip->oob_poi, *ecc;
1244 int max_bitflips = 0;
1245 u32 failure_mask = 0;
1246 int chunk, ecc_offset_in_page, ret;
1249 * With BCH, OOB is not fully used (and thus not read entirely), not
1250 * expected bytes could show up at the end of the OOB buffer if not
1251 * explicitly erased.
1254 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1256 marvell_nfc_enable_hw_ecc(chip);
1258 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1259 /* Update length for the last chunk */
1260 if (chunk >= lt->full_chunk_cnt) {
1261 data_len = lt->last_data_bytes;
1262 spare_len = lt->last_spare_bytes;
1265 /* Read the chunk and detect number of bitflips */
1266 marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
1267 spare, spare_len, page);
1268 ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
1270 failure_mask |= BIT(chunk);
1276 marvell_nfc_disable_hw_ecc(chip);
1279 return max_bitflips;
1282 * Please note that dumping the ECC bytes during a normal read with OOB
1283 * area would add a significant overhead as ECC bytes are "consumed" by
1284 * the controller in normal mode and must be re-read in raw mode. To
1285 * avoid dropping the performances, we prefer not to include them. The
1286 * user should re-read the page in raw mode if ECC bytes are required.
1288 * However, for any subpage read error reported by ->correct(), the ECC
1289 * bytes must be read in raw mode and the full subpage must be checked
1290 * to see if it is entirely empty of if there was an actual error.
1292 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1293 /* No failure reported for this chunk, move to the next one */
1294 if (!(failure_mask & BIT(chunk)))
1297 /* Derive ECC bytes positions (in page/buffer) and length */
1298 ecc = chip->oob_poi +
1299 (lt->full_chunk_cnt * lt->spare_bytes) +
1300 lt->last_spare_bytes +
1301 (chunk * ALIGN(lt->ecc_bytes, 32));
1302 ecc_offset_in_page =
1303 (chunk * (lt->data_bytes + lt->spare_bytes +
1305 (chunk < lt->full_chunk_cnt ?
1306 lt->data_bytes + lt->spare_bytes :
1307 lt->last_data_bytes + lt->last_spare_bytes);
1308 ecc_len = chunk < lt->full_chunk_cnt ?
1309 lt->ecc_bytes : lt->last_ecc_bytes;
1311 /* Do the actual raw read of the ECC bytes */
1312 nand_change_read_column_op(chip, ecc_offset_in_page,
1313 ecc, ecc_len, false);
1315 /* Derive data/spare bytes positions (in buffer) and length */
1316 data = buf + (chunk * lt->data_bytes);
1317 data_len = chunk < lt->full_chunk_cnt ?
1318 lt->data_bytes : lt->last_data_bytes;
1319 spare = chip->oob_poi + (chunk * (lt->spare_bytes +
1321 spare_len = chunk < lt->full_chunk_cnt ?
1322 lt->spare_bytes : lt->last_spare_bytes;
1324 /* Check the entire chunk (data + spare + ecc) for emptyness */
1325 marvell_nfc_check_empty_chunk(chip, data, data_len, spare,
1326 spare_len, ecc, ecc_len,
1330 return max_bitflips;
1333 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct mtd_info *mtd,
1334 struct nand_chip *chip, int page)
1336 /* Invalidate page cache */
1339 return chip->ecc.read_page_raw(mtd, chip, chip->data_buf, true, page);
1342 static int marvell_nfc_hw_ecc_bch_read_oob(struct mtd_info *mtd,
1343 struct nand_chip *chip, int page)
1345 /* Invalidate page cache */
1348 return chip->ecc.read_page(mtd, chip, chip->data_buf, true, page);
1351 /* BCH write helpers */
1352 static int marvell_nfc_hw_ecc_bch_write_page_raw(struct mtd_info *mtd,
1353 struct nand_chip *chip,
1355 int oob_required, int page)
1357 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1358 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1359 int data_len = lt->data_bytes;
1360 int spare_len = lt->spare_bytes;
1361 int ecc_len = lt->ecc_bytes;
1362 int spare_offset = 0;
1363 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1364 lt->last_spare_bytes;
1367 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1369 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1370 if (chunk >= lt->full_chunk_cnt) {
1371 data_len = lt->last_data_bytes;
1372 spare_len = lt->last_spare_bytes;
1373 ecc_len = lt->last_ecc_bytes;
1376 /* Point to the column of the next chunk */
1377 nand_change_write_column_op(chip, chunk * full_chunk_size,
1380 /* Write the data */
1381 nand_write_data_op(chip, buf + (chunk * lt->data_bytes),
1387 /* Write the spare bytes */
1389 nand_write_data_op(chip, chip->oob_poi + spare_offset,
1392 /* Write the ECC bytes */
1394 nand_write_data_op(chip, chip->oob_poi + ecc_offset,
1397 spare_offset += spare_len;
1398 ecc_offset += ALIGN(ecc_len, 32);
1401 return nand_prog_page_end_op(chip);
1405 marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
1406 const u8 *data, unsigned int data_len,
1407 const u8 *spare, unsigned int spare_len,
1410 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1411 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1412 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1415 struct marvell_nfc_op nfc_op = {
1416 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
1417 .ndcb[3] = data_len + spare_len,
1421 * First operation dispatches the CMD_SEQIN command, issue the address
1422 * cycles and asks for the first chunk of data.
1423 * All operations in the middle (if any) will issue a naked write and
1424 * also ask for data.
1425 * Last operation (if any) asks for the last chunk of data through a
1429 if (lt->nchunks == 1)
1430 xtype = XTYPE_MONOLITHIC_RW;
1432 xtype = XTYPE_WRITE_DISPATCH;
1434 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
1435 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1436 NDCB0_CMD1(NAND_CMD_SEQIN);
1437 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1438 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1439 } else if (chunk < lt->nchunks - 1) {
1440 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1442 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1445 /* Always dispatch the PAGEPROG command on the last chunk */
1446 if (chunk == lt->nchunks - 1)
1447 nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
1449 ret = marvell_nfc_prepare_cmd(chip);
1453 marvell_nfc_send_cmd(chip, &nfc_op);
1454 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1455 "WRDREQ while loading FIFO (data)");
1459 /* Transfer the contents */
1460 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len));
1461 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len));
1466 static int marvell_nfc_hw_ecc_bch_write_page(struct mtd_info *mtd,
1467 struct nand_chip *chip,
1469 int oob_required, int page)
1471 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1472 const u8 *data = buf;
1473 const u8 *spare = chip->oob_poi;
1474 int data_len = lt->data_bytes;
1475 int spare_len = lt->spare_bytes;
1478 /* Spare data will be written anyway, so clear it to avoid garbage */
1480 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1482 marvell_nfc_enable_hw_ecc(chip);
1484 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1485 if (chunk >= lt->full_chunk_cnt) {
1486 data_len = lt->last_data_bytes;
1487 spare_len = lt->last_spare_bytes;
1490 marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len,
1491 spare, spare_len, page);
1496 * Waiting only for CMDD or PAGED is not enough, ECC are
1497 * partially written. No flag is set once the operation is
1498 * really finished but the ND_RUN bit is cleared, so wait for it
1499 * before stepping into the next command.
1501 marvell_nfc_wait_ndrun(chip);
1504 ret = marvell_nfc_wait_op(chip,
1505 PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1507 marvell_nfc_disable_hw_ecc(chip);
1515 static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct mtd_info *mtd,
1516 struct nand_chip *chip,
1519 /* Invalidate page cache */
1522 memset(chip->data_buf, 0xFF, mtd->writesize);
1524 return chip->ecc.write_page_raw(mtd, chip, chip->data_buf, true, page);
1527 static int marvell_nfc_hw_ecc_bch_write_oob(struct mtd_info *mtd,
1528 struct nand_chip *chip, int page)
1530 /* Invalidate page cache */
1533 memset(chip->data_buf, 0xFF, mtd->writesize);
1535 return chip->ecc.write_page(mtd, chip, chip->data_buf, true, page);
1538 /* NAND framework ->exec_op() hooks and related helpers */
1539 static void marvell_nfc_parse_instructions(struct nand_chip *chip,
1540 const struct nand_subop *subop,
1541 struct marvell_nfc_op *nfc_op)
1543 const struct nand_op_instr *instr = NULL;
1544 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1545 bool first_cmd = true;
1549 /* Reset the input structure as most of its fields will be OR'ed */
1550 memset(nfc_op, 0, sizeof(struct marvell_nfc_op));
1552 for (op_id = 0; op_id < subop->ninstrs; op_id++) {
1553 unsigned int offset, naddrs;
1555 int len = nand_subop_get_data_len(subop, op_id);
1557 instr = &subop->instrs[op_id];
1559 switch (instr->type) {
1560 case NAND_OP_CMD_INSTR:
1563 NDCB0_CMD1(instr->ctx.cmd.opcode);
1566 NDCB0_CMD2(instr->ctx.cmd.opcode) |
1569 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1573 case NAND_OP_ADDR_INSTR:
1574 offset = nand_subop_get_addr_start_off(subop, op_id);
1575 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
1576 addrs = &instr->ctx.addr.addrs[offset];
1578 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs);
1580 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
1581 nfc_op->ndcb[1] |= addrs[i] << (8 * i);
1584 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]);
1586 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]);
1588 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]);
1590 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1593 case NAND_OP_DATA_IN_INSTR:
1594 nfc_op->data_instr = instr;
1595 nfc_op->data_instr_idx = op_id;
1596 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ);
1597 if (nfc->caps->is_nfcv2) {
1599 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1601 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1603 nfc_op->data_delay_ns = instr->delay_ns;
1606 case NAND_OP_DATA_OUT_INSTR:
1607 nfc_op->data_instr = instr;
1608 nfc_op->data_instr_idx = op_id;
1609 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE);
1610 if (nfc->caps->is_nfcv2) {
1612 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1614 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1616 nfc_op->data_delay_ns = instr->delay_ns;
1619 case NAND_OP_WAITRDY_INSTR:
1620 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
1621 nfc_op->rdy_delay_ns = instr->delay_ns;
1627 static int marvell_nfc_xfer_data_pio(struct nand_chip *chip,
1628 const struct nand_subop *subop,
1629 struct marvell_nfc_op *nfc_op)
1631 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1632 const struct nand_op_instr *instr = nfc_op->data_instr;
1633 unsigned int op_id = nfc_op->data_instr_idx;
1634 unsigned int len = nand_subop_get_data_len(subop, op_id);
1635 unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
1636 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
1639 if (instr->ctx.data.force_8bit)
1640 marvell_nfc_force_byte_access(chip, true);
1643 u8 *in = instr->ctx.data.buf.in + offset;
1645 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1647 const u8 *out = instr->ctx.data.buf.out + offset;
1649 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
1652 if (instr->ctx.data.force_8bit)
1653 marvell_nfc_force_byte_access(chip, false);
1658 static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip,
1659 const struct nand_subop *subop)
1661 struct marvell_nfc_op nfc_op;
1665 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1666 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
1668 ret = marvell_nfc_prepare_cmd(chip);
1672 marvell_nfc_send_cmd(chip, &nfc_op);
1673 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1674 "RDDREQ/WRDREQ while draining raw data");
1678 cond_delay(nfc_op.cle_ale_delay_ns);
1681 if (nfc_op.rdy_timeout_ms) {
1682 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1687 cond_delay(nfc_op.rdy_delay_ns);
1690 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1691 ret = marvell_nfc_wait_cmdd(chip);
1695 cond_delay(nfc_op.data_delay_ns);
1698 if (nfc_op.rdy_timeout_ms) {
1699 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1704 cond_delay(nfc_op.rdy_delay_ns);
1708 * NDCR ND_RUN bit should be cleared automatically at the end of each
1709 * operation but experience shows that the behavior is buggy when it
1710 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1713 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1715 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1722 static int marvell_nfc_naked_access_exec(struct nand_chip *chip,
1723 const struct nand_subop *subop)
1725 struct marvell_nfc_op nfc_op;
1728 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1731 * Naked access are different in that they need to be flagged as naked
1732 * by the controller. Reset the controller registers fields that inform
1733 * on the type and refill them according to the ongoing operation.
1735 nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) |
1736 NDCB0_CMD_XTYPE(XTYPE_MASK));
1737 switch (subop->instrs[0].type) {
1738 case NAND_OP_CMD_INSTR:
1739 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD);
1741 case NAND_OP_ADDR_INSTR:
1742 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR);
1744 case NAND_OP_DATA_IN_INSTR:
1745 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) |
1746 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1748 case NAND_OP_DATA_OUT_INSTR:
1749 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) |
1750 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1753 /* This should never happen */
1757 ret = marvell_nfc_prepare_cmd(chip);
1761 marvell_nfc_send_cmd(chip, &nfc_op);
1763 if (!nfc_op.data_instr) {
1764 ret = marvell_nfc_wait_cmdd(chip);
1765 cond_delay(nfc_op.cle_ale_delay_ns);
1769 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1770 "RDDREQ/WRDREQ while draining raw data");
1774 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1775 ret = marvell_nfc_wait_cmdd(chip);
1780 * NDCR ND_RUN bit should be cleared automatically at the end of each
1781 * operation but experience shows that the behavior is buggy when it
1782 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1784 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) {
1785 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1787 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1794 static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip,
1795 const struct nand_subop *subop)
1797 struct marvell_nfc_op nfc_op;
1800 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1802 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1803 cond_delay(nfc_op.rdy_delay_ns);
1808 static int marvell_nfc_read_id_type_exec(struct nand_chip *chip,
1809 const struct nand_subop *subop)
1811 struct marvell_nfc_op nfc_op;
1814 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1815 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1816 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID);
1818 ret = marvell_nfc_prepare_cmd(chip);
1822 marvell_nfc_send_cmd(chip, &nfc_op);
1823 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1824 "RDDREQ while reading ID");
1828 cond_delay(nfc_op.cle_ale_delay_ns);
1830 if (nfc_op.rdy_timeout_ms) {
1831 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1836 cond_delay(nfc_op.rdy_delay_ns);
1838 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1839 ret = marvell_nfc_wait_cmdd(chip);
1843 cond_delay(nfc_op.data_delay_ns);
1848 static int marvell_nfc_read_status_exec(struct nand_chip *chip,
1849 const struct nand_subop *subop)
1851 struct marvell_nfc_op nfc_op;
1854 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1855 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1856 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS);
1858 ret = marvell_nfc_prepare_cmd(chip);
1862 marvell_nfc_send_cmd(chip, &nfc_op);
1863 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1864 "RDDREQ while reading status");
1868 cond_delay(nfc_op.cle_ale_delay_ns);
1870 if (nfc_op.rdy_timeout_ms) {
1871 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1876 cond_delay(nfc_op.rdy_delay_ns);
1878 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1879 ret = marvell_nfc_wait_cmdd(chip);
1883 cond_delay(nfc_op.data_delay_ns);
1888 static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip,
1889 const struct nand_subop *subop)
1891 struct marvell_nfc_op nfc_op;
1894 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1895 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET);
1897 ret = marvell_nfc_prepare_cmd(chip);
1901 marvell_nfc_send_cmd(chip, &nfc_op);
1902 ret = marvell_nfc_wait_cmdd(chip);
1906 cond_delay(nfc_op.cle_ale_delay_ns);
1908 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1912 cond_delay(nfc_op.rdy_delay_ns);
1917 static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip,
1918 const struct nand_subop *subop)
1920 struct marvell_nfc_op nfc_op;
1923 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1924 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE);
1926 ret = marvell_nfc_prepare_cmd(chip);
1930 marvell_nfc_send_cmd(chip, &nfc_op);
1931 ret = marvell_nfc_wait_cmdd(chip);
1935 cond_delay(nfc_op.cle_ale_delay_ns);
1937 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1941 cond_delay(nfc_op.rdy_delay_ns);
1946 static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER(
1947 /* Monolithic reads/writes */
1948 NAND_OP_PARSER_PATTERN(
1949 marvell_nfc_monolithic_access_exec,
1950 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1951 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2),
1952 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1953 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
1954 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
1955 NAND_OP_PARSER_PATTERN(
1956 marvell_nfc_monolithic_access_exec,
1957 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1958 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2),
1959 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE),
1960 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1961 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1962 /* Naked commands */
1963 NAND_OP_PARSER_PATTERN(
1964 marvell_nfc_naked_access_exec,
1965 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
1966 NAND_OP_PARSER_PATTERN(
1967 marvell_nfc_naked_access_exec,
1968 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)),
1969 NAND_OP_PARSER_PATTERN(
1970 marvell_nfc_naked_access_exec,
1971 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
1972 NAND_OP_PARSER_PATTERN(
1973 marvell_nfc_naked_access_exec,
1974 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)),
1975 NAND_OP_PARSER_PATTERN(
1976 marvell_nfc_naked_waitrdy_exec,
1977 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1980 static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
1981 /* Naked commands not supported, use a function for each pattern */
1982 NAND_OP_PARSER_PATTERN(
1983 marvell_nfc_read_id_type_exec,
1984 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1985 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
1986 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
1987 NAND_OP_PARSER_PATTERN(
1988 marvell_nfc_erase_cmd_type_exec,
1989 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1990 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
1991 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1992 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1993 NAND_OP_PARSER_PATTERN(
1994 marvell_nfc_read_status_exec,
1995 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1996 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
1997 NAND_OP_PARSER_PATTERN(
1998 marvell_nfc_reset_cmd_type_exec,
1999 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2000 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2001 NAND_OP_PARSER_PATTERN(
2002 marvell_nfc_naked_waitrdy_exec,
2003 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2006 static int marvell_nfc_exec_op(struct nand_chip *chip,
2007 const struct nand_operation *op,
2010 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2012 if (nfc->caps->is_nfcv2)
2013 return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
2016 return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser,
2021 * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
2024 static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2025 struct mtd_oob_region *oobregion)
2027 struct nand_chip *chip = mtd_to_nand(mtd);
2028 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2033 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) +
2035 oobregion->offset = mtd->oobsize - oobregion->length;
2040 static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section,
2041 struct mtd_oob_region *oobregion)
2043 struct nand_chip *chip = mtd_to_nand(mtd);
2044 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2050 * Bootrom looks in bytes 0 & 5 for bad blocks for the
2051 * 4KB page / 4bit BCH combination.
2053 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)
2054 oobregion->offset = 6;
2056 oobregion->offset = 2;
2058 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) +
2059 lt->last_spare_bytes - oobregion->offset;
2064 static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = {
2065 .ecc = marvell_nand_ooblayout_ecc,
2066 .free = marvell_nand_ooblayout_free,
2069 static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
2070 struct nand_ecc_ctrl *ecc)
2072 struct nand_chip *chip = mtd_to_nand(mtd);
2073 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2074 const struct marvell_hw_ecc_layout *l;
2077 if (!nfc->caps->is_nfcv2 &&
2078 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) {
2080 "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n",
2081 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize);
2085 to_marvell_nand(chip)->layout = NULL;
2086 for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) {
2087 l = &marvell_nfc_layouts[i];
2088 if (mtd->writesize == l->writesize &&
2089 ecc->size == l->chunk && ecc->strength == l->strength) {
2090 to_marvell_nand(chip)->layout = l;
2095 if (!to_marvell_nand(chip)->layout ||
2096 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2098 "ECC strength %d at page size %d is not supported\n",
2099 ecc->strength, mtd->writesize);
2103 mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
2104 ecc->steps = l->nchunks;
2105 ecc->size = l->data_bytes;
2107 if (ecc->strength == 1) {
2108 chip->ecc.algo = NAND_ECC_HAMMING;
2109 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2110 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2111 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2112 ecc->read_oob = ecc->read_oob_raw;
2113 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2114 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2115 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2116 ecc->write_oob = ecc->write_oob_raw;
2118 chip->ecc.algo = NAND_ECC_BCH;
2120 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2121 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2122 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2123 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2124 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2125 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2126 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2127 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2133 static int marvell_nand_ecc_init(struct mtd_info *mtd,
2134 struct nand_ecc_ctrl *ecc)
2136 struct nand_chip *chip = mtd_to_nand(mtd);
2137 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2140 if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) {
2141 if (chip->ecc_step_ds && chip->ecc_strength_ds) {
2142 ecc->size = chip->ecc_step_ds;
2143 ecc->strength = chip->ecc_strength_ds;
2146 "No minimum ECC strength, using 1b/512B\n");
2152 switch (ecc->mode) {
2154 ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc);
2160 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
2161 mtd->writesize != SZ_2K) {
2162 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
2174 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
2175 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
2177 static struct nand_bbt_descr bbt_main_descr = {
2178 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2179 NAND_BBT_2BIT | NAND_BBT_VERSION,
2183 .maxblocks = 8, /* Last 8 blocks in each chip */
2184 .pattern = bbt_pattern
2187 static struct nand_bbt_descr bbt_mirror_descr = {
2188 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2189 NAND_BBT_2BIT | NAND_BBT_VERSION,
2193 .maxblocks = 8, /* Last 8 blocks in each chip */
2194 .pattern = bbt_mirror_pattern
2197 static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
2198 const struct nand_data_interface
2201 struct nand_chip *chip = mtd_to_nand(mtd);
2202 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2203 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2204 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
2205 const struct nand_sdr_timings *sdr;
2206 struct marvell_nfc_timings nfc_tmg;
2209 sdr = nand_get_sdr_timings(conf);
2211 return PTR_ERR(sdr);
2214 * SDR timings are given in pico-seconds while NFC timings must be
2215 * expressed in NAND controller clock cycles, which is half of the
2216 * frequency of the accessible ECC clock retrieved by clk_get_rate().
2217 * This is not written anywhere in the datasheet but was observed
2218 * with an oscilloscope.
2220 * NFC datasheet gives equations from which thoses calculations
2221 * are derived, they tend to be slightly more restrictives than the
2222 * given core timings and may improve the overall speed.
2224 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2225 nfc_tmg.tRH = nfc_tmg.tRP;
2226 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2227 nfc_tmg.tWH = nfc_tmg.tWP;
2228 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2229 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2230 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2232 * Read delay is the time of propagation from SoC pins to NFC internal
2233 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In
2234 * EDO mode, an additional delay of tRH must be taken into account so
2235 * the data is sampled on the falling edge instead of the rising edge.
2237 read_delay = sdr->tRC_min >= 30000 ?
2238 MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
2240 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2242 * tWHR and tRHW are supposed to be read to write delays (and vice
2243 * versa) but in some cases, ie. when doing a change column, they must
2244 * be greater than that to be sure tCCS delay is respected.
2246 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2248 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2252 * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays.
2253 * NFCv1: No WAIT_MODE, tR must be maximal.
2255 if (nfc->caps->is_nfcv2) {
2256 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2258 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,
2260 if (nfc_tmg.tR + 3 > nfc_tmg.tCH)
2261 nfc_tmg.tR = nfc_tmg.tCH - 3;
2269 marvell_nand->ndtr0 =
2270 NDTR0_TRP(nfc_tmg.tRP) |
2271 NDTR0_TRH(nfc_tmg.tRH) |
2272 NDTR0_ETRP(nfc_tmg.tRP) |
2273 NDTR0_TWP(nfc_tmg.tWP) |
2274 NDTR0_TWH(nfc_tmg.tWH) |
2275 NDTR0_TCS(nfc_tmg.tCS) |
2276 NDTR0_TCH(nfc_tmg.tCH);
2278 marvell_nand->ndtr1 =
2279 NDTR1_TAR(nfc_tmg.tAR) |
2280 NDTR1_TWHR(nfc_tmg.tWHR) |
2281 NDTR1_TR(nfc_tmg.tR);
2283 if (nfc->caps->is_nfcv2) {
2284 marvell_nand->ndtr0 |=
2285 NDTR0_RD_CNT_DEL(read_delay) |
2287 NDTR0_TADL(nfc_tmg.tADL);
2289 marvell_nand->ndtr1 |=
2290 NDTR1_TRHW(nfc_tmg.tRHW) |
2297 static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
2298 struct device_node *np)
2300 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev);
2301 struct marvell_nand_chip *marvell_nand;
2302 struct mtd_info *mtd;
2303 struct nand_chip *chip;
2308 * The legacy "num-cs" property indicates the number of CS on the only
2309 * chip connected to the controller (legacy bindings does not support
2310 * more than one chip). The CS and RB pins are always the #0.
2312 * When not using legacy bindings, a couple of "reg" and "nand-rb"
2313 * properties must be filled. For each chip, expressed as a subnode,
2314 * "reg" points to the CS lines and "nand-rb" to the RB line.
2316 if (pdata || nfc->caps->legacy_of_bindings) {
2319 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
2321 dev_err(dev, "missing/invalid reg property\n");
2326 /* Alloc the nand chip structure */
2327 marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) +
2329 sizeof(struct marvell_nand_chip_sel)),
2331 if (!marvell_nand) {
2332 dev_err(dev, "could not allocate chip structure\n");
2336 marvell_nand->nsels = nsels;
2337 marvell_nand->selected_die = -1;
2339 for (i = 0; i < nsels; i++) {
2340 if (pdata || nfc->caps->legacy_of_bindings) {
2342 * Legacy bindings use the CS lines in natural
2347 /* Retrieve CS id */
2348 ret = of_property_read_u32_index(np, "reg", i, &cs);
2350 dev_err(dev, "could not retrieve reg property: %d\n",
2356 if (cs >= nfc->caps->max_cs_nb) {
2357 dev_err(dev, "invalid reg value: %u (max CS = %d)\n",
2358 cs, nfc->caps->max_cs_nb);
2362 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
2363 dev_err(dev, "CS %d already assigned\n", cs);
2368 * The cs variable represents the chip select id, which must be
2369 * converted in bit fields for NDCB0 and NDCB2 to select the
2370 * right chip. Unfortunately, due to a lack of information on
2371 * the subject and incoherent documentation, the user should not
2372 * use CS1 and CS3 at all as asserting them is not supported in
2373 * a reliable way (due to multiplexing inside ADDR5 field).
2375 marvell_nand->sels[i].cs = cs;
2379 marvell_nand->sels[i].ndcb0_csel = 0;
2383 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL;
2389 /* Retrieve RB id */
2390 if (pdata || nfc->caps->legacy_of_bindings) {
2391 /* Legacy bindings always use RB #0 */
2394 ret = of_property_read_u32_index(np, "nand-rb", i,
2398 "could not retrieve RB property: %d\n",
2404 if (rb >= nfc->caps->max_rb_nb) {
2405 dev_err(dev, "invalid reg value: %u (max RB = %d)\n",
2406 rb, nfc->caps->max_rb_nb);
2410 marvell_nand->sels[i].rb = rb;
2413 chip = &marvell_nand->chip;
2414 chip->controller = &nfc->controller;
2415 nand_set_flash_node(chip, np);
2417 chip->exec_op = marvell_nfc_exec_op;
2418 chip->select_chip = marvell_nfc_select_chip;
2419 if (!of_property_read_bool(np, "marvell,nand-keep-config"))
2420 chip->setup_data_interface = marvell_nfc_setup_data_interface;
2422 mtd = nand_to_mtd(chip);
2423 mtd->dev.parent = dev;
2426 * Default to HW ECC engine mode. If the nand-ecc-mode property is given
2427 * in the DT node, this entry will be overwritten in nand_scan_ident().
2429 chip->ecc.mode = NAND_ECC_HW;
2432 * Save a reference value for timing registers before
2433 * ->setup_data_interface() is called.
2435 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
2436 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
2438 chip->options |= NAND_BUSWIDTH_AUTO;
2439 ret = nand_scan_ident(mtd, marvell_nand->nsels, NULL);
2441 dev_err(dev, "could not identify the nand chip\n");
2445 if (pdata && pdata->flash_bbt)
2446 chip->bbt_options |= NAND_BBT_USE_FLASH;
2448 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
2450 * We'll use a bad block table stored in-flash and don't
2451 * allow writing the bad block marker to the flash.
2453 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2454 chip->bbt_td = &bbt_main_descr;
2455 chip->bbt_md = &bbt_mirror_descr;
2458 /* Save the chip-specific fields of NDCR */
2459 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
2460 if (chip->options & NAND_BUSWIDTH_16)
2461 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
2464 * On small page NANDs, only one cycle is needed to pass the
2467 if (mtd->writesize <= 512) {
2468 marvell_nand->addr_cyc = 1;
2470 marvell_nand->addr_cyc = 2;
2471 marvell_nand->ndcr |= NDCR_RA_START;
2475 * Now add the number of cycles needed to pass the row
2478 * Addressing a chip using CS 2 or 3 should also need the third row
2479 * cycle but due to inconsistance in the documentation and lack of
2480 * hardware to test this situation, this case is not supported.
2482 if (chip->options & NAND_ROW_ADDR_3)
2483 marvell_nand->addr_cyc += 3;
2485 marvell_nand->addr_cyc += 2;
2488 chip->ecc.size = pdata->ecc_step_size;
2489 chip->ecc.strength = pdata->ecc_strength;
2492 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2494 dev_err(dev, "ECC init failed: %d\n", ret);
2498 if (chip->ecc.mode == NAND_ECC_HW) {
2500 * Subpage write not available with hardware ECC, prohibit also
2501 * subpage read as in userspace subpage access would still be
2502 * allowed and subpage write, if used, would lead to numerous
2503 * uncorrectable ECC errors.
2505 chip->options |= NAND_NO_SUBPAGE_WRITE;
2508 if (pdata || nfc->caps->legacy_of_bindings) {
2510 * We keep the MTD name unchanged to avoid breaking platforms
2511 * where the MTD cmdline parser is used and the bootloader
2512 * has not been updated to use the new naming scheme.
2514 mtd->name = "pxa3xx_nand-0";
2515 } else if (!mtd->name) {
2517 * If the new bindings are used and the bootloader has not been
2518 * updated to pass a new mtdparts parameter on the cmdline, you
2519 * should define the following property in your NAND node, ie:
2521 * label = "main-storage";
2523 * This way, mtd->name will be set by the core when
2524 * nand_set_flash_node() is called.
2526 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
2527 "%s:nand.%d", dev_name(nfc->dev),
2528 marvell_nand->sels[0].cs);
2530 dev_err(nfc->dev, "Failed to allocate mtd->name\n");
2535 ret = nand_scan_tail(mtd);
2537 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
2542 /* Legacy bindings support only one chip */
2543 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2545 ret = mtd_device_register(mtd, NULL, 0);
2547 dev_err(dev, "failed to register mtd device: %d\n", ret);
2552 list_add_tail(&marvell_nand->node, &nfc->chips);
2557 static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
2559 struct device_node *np = dev->of_node;
2560 struct device_node *nand_np;
2561 int max_cs = nfc->caps->max_cs_nb;
2568 nchips = of_get_child_count(np);
2570 if (nchips > max_cs) {
2571 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips,
2577 * Legacy bindings do not use child nodes to exhibit NAND chip
2578 * properties and layout. Instead, NAND properties are mixed with the
2579 * controller ones, and partitions are defined as direct subnodes of the
2580 * NAND controller node.
2582 if (nfc->caps->legacy_of_bindings) {
2583 ret = marvell_nand_chip_init(dev, nfc, np);
2587 for_each_child_of_node(np, nand_np) {
2588 ret = marvell_nand_chip_init(dev, nfc, nand_np);
2590 of_node_put(nand_np);
2598 static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
2600 struct marvell_nand_chip *entry, *temp;
2602 list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
2603 nand_release(nand_to_mtd(&entry->chip));
2604 list_del(&entry->node);
2608 static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
2610 struct platform_device *pdev = container_of(nfc->dev,
2611 struct platform_device,
2613 struct dma_slave_config config = {};
2615 dma_cap_mask_t mask;
2616 struct pxad_param param;
2619 if (!IS_ENABLED(CONFIG_PXA_DMA)) {
2621 "DMA not enabled in configuration\n");
2625 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
2629 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2631 dev_err(nfc->dev, "No resource defined for data DMA\n");
2635 param.drcmr = r->start;
2636 param.prio = PXAD_PRIO_LOWEST;
2638 dma_cap_set(DMA_SLAVE, mask);
2640 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2643 if (!nfc->dma_chan) {
2645 "Unable to request data DMA channel\n");
2649 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2653 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2654 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2655 config.src_addr = r->start + NDDB;
2656 config.dst_addr = r->start + NDDB;
2657 config.src_maxburst = 32;
2658 config.dst_maxburst = 32;
2659 ret = dmaengine_slave_config(nfc->dma_chan, &config);
2661 dev_err(nfc->dev, "Failed to configure DMA channel\n");
2666 * DMA must act on length multiple of 32 and this length may be
2667 * bigger than the destination buffer. Use this buffer instead
2668 * for DMA transfers and then copy the desired amount of data to
2669 * the provided buffer.
2671 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2675 nfc->use_dma = true;
2680 static int marvell_nfc_init(struct marvell_nfc *nfc)
2682 struct device_node *np = nfc->dev->of_node;
2685 * Some SoCs like A7k/A8k need to enable manually the NAND
2686 * controller, gated clocks and reset bits to avoid being bootloader
2687 * dependent. This is done through the use of the System Functions
2690 if (nfc->caps->need_system_controller) {
2691 struct regmap *sysctrl_base =
2692 syscon_regmap_lookup_by_phandle(np,
2693 "marvell,system-controller");
2696 if (IS_ERR(sysctrl_base))
2697 return PTR_ERR(sysctrl_base);
2699 reg = GENCONF_SOC_DEVICE_MUX_NFC_EN |
2700 GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
2701 GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
2702 GENCONF_SOC_DEVICE_MUX_NFC_INT_EN;
2703 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
2705 regmap_read(sysctrl_base, GENCONF_CLK_GATING_CTRL, ®);
2706 reg |= GENCONF_CLK_GATING_CTRL_ND_GATE;
2707 regmap_write(sysctrl_base, GENCONF_CLK_GATING_CTRL, reg);
2709 regmap_read(sysctrl_base, GENCONF_ND_CLK_CTRL, ®);
2710 reg |= GENCONF_ND_CLK_CTRL_EN;
2711 regmap_write(sysctrl_base, GENCONF_ND_CLK_CTRL, reg);
2714 /* Configure the DMA if appropriate */
2715 if (!nfc->caps->is_nfcv2)
2716 marvell_nfc_init_dma(nfc);
2719 * ECC operations and interruptions are only enabled when specifically
2720 * needed. ECC shall not be activated in the early stages (fails probe).
2721 * Arbiter flag, even if marked as "reserved", must be set (empirical).
2722 * SPARE_EN bit must always be set or ECC bytes will not be at the same
2723 * offset in the read page and this will fail the protection.
2725 writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
2726 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);
2727 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
2728 writel_relaxed(0, nfc->regs + NDECCCTRL);
2733 static int marvell_nfc_probe(struct platform_device *pdev)
2735 struct device *dev = &pdev->dev;
2737 struct marvell_nfc *nfc;
2741 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc),
2747 nand_hw_control_init(&nfc->controller);
2748 INIT_LIST_HEAD(&nfc->chips);
2750 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2751 nfc->regs = devm_ioremap_resource(dev, r);
2752 if (IS_ERR(nfc->regs))
2753 return PTR_ERR(nfc->regs);
2755 irq = platform_get_irq(pdev, 0);
2757 dev_err(dev, "failed to retrieve irq\n");
2761 nfc->core_clk = devm_clk_get(&pdev->dev, "core");
2763 /* Managed the legacy case (when the first clock was not named) */
2764 if (nfc->core_clk == ERR_PTR(-ENOENT))
2765 nfc->core_clk = devm_clk_get(&pdev->dev, NULL);
2767 if (IS_ERR(nfc->core_clk))
2768 return PTR_ERR(nfc->core_clk);
2770 ret = clk_prepare_enable(nfc->core_clk);
2774 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg");
2775 if (PTR_ERR(nfc->reg_clk) != -ENOENT) {
2776 if (!IS_ERR(nfc->reg_clk)) {
2777 ret = clk_prepare_enable(nfc->reg_clk);
2779 goto unprepare_core_clk;
2781 ret = PTR_ERR(nfc->reg_clk);
2782 goto unprepare_core_clk;
2786 marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
2787 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
2788 ret = devm_request_irq(dev, irq, marvell_nfc_isr,
2789 0, "marvell-nfc", nfc);
2791 goto unprepare_reg_clk;
2793 /* Get NAND controller capabilities */
2795 nfc->caps = (void *)pdev->id_entry->driver_data;
2797 nfc->caps = of_device_get_match_data(&pdev->dev);
2800 dev_err(dev, "Could not retrieve NFC caps\n");
2802 goto unprepare_reg_clk;
2805 /* Init the controller and then probe the chips */
2806 ret = marvell_nfc_init(nfc);
2808 goto unprepare_reg_clk;
2810 platform_set_drvdata(pdev, nfc);
2812 ret = marvell_nand_chips_init(dev, nfc);
2814 goto unprepare_reg_clk;
2819 clk_disable_unprepare(nfc->reg_clk);
2821 clk_disable_unprepare(nfc->core_clk);
2826 static int marvell_nfc_remove(struct platform_device *pdev)
2828 struct marvell_nfc *nfc = platform_get_drvdata(pdev);
2830 marvell_nand_chips_cleanup(nfc);
2833 dmaengine_terminate_all(nfc->dma_chan);
2834 dma_release_channel(nfc->dma_chan);
2837 clk_disable_unprepare(nfc->reg_clk);
2838 clk_disable_unprepare(nfc->core_clk);
2843 static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
2846 .need_system_controller = true,
2850 static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
2856 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = {
2862 static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = {
2865 .need_system_controller = true,
2866 .legacy_of_bindings = true,
2870 static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = {
2873 .legacy_of_bindings = true,
2877 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = {
2880 .legacy_of_bindings = true,
2884 static const struct platform_device_id marvell_nfc_platform_ids[] = {
2886 .name = "pxa3xx-nand",
2887 .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps,
2891 MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids);
2893 static const struct of_device_id marvell_nfc_of_ids[] = {
2895 .compatible = "marvell,armada-8k-nand-controller",
2896 .data = &marvell_armada_8k_nfc_caps,
2899 .compatible = "marvell,armada370-nand-controller",
2900 .data = &marvell_armada370_nfc_caps,
2903 .compatible = "marvell,pxa3xx-nand-controller",
2904 .data = &marvell_pxa3xx_nfc_caps,
2906 /* Support for old/deprecated bindings: */
2908 .compatible = "marvell,armada-8k-nand",
2909 .data = &marvell_armada_8k_nfc_legacy_caps,
2912 .compatible = "marvell,armada370-nand",
2913 .data = &marvell_armada370_nfc_legacy_caps,
2916 .compatible = "marvell,pxa3xx-nand",
2917 .data = &marvell_pxa3xx_nfc_legacy_caps,
2921 MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids);
2923 static struct platform_driver marvell_nfc_driver = {
2925 .name = "marvell-nfc",
2926 .of_match_table = marvell_nfc_of_ids,
2928 .id_table = marvell_nfc_platform_ids,
2929 .probe = marvell_nfc_probe,
2930 .remove = marvell_nfc_remove,
2932 module_platform_driver(marvell_nfc_driver);
2934 MODULE_LICENSE("GPL");
2935 MODULE_DESCRIPTION("Marvell NAND controller driver");